1 files changed, 26 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 0f8847f10..b15b383fc 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -746,6 +746,32 @@ static void stm32_stdclockconfig(void)
       while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
         {
         }
+
+#ifdef CONFIG_STM32_LTDC
+      /* Configure PLLSAI */
+
+      regval = getreg32(STM32_RCC_PLLSAICFGR);
+      regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
+                | STM32_RCC_PLLSAICFGR_PLLSAIR
+                | STM32_RCC_PLLSAICFGR_PLLSAIQ);
+      putreg32(regval, STM32_RCC_PLLSAICFGR);
+
+      regval = getreg32(STM32_RCC_DCKCFGR);
+      regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
+      putreg32(regval, STM32_RCC_DCKCFGR);
+
+      /* Enable PLLSAI */
+
+      regval = getreg32(STM32_RCC_CR);
+      regval |= RCC_CR_PLLSAION;
+      putreg32(regval, STM32_RCC_CR);
+
+      /* Wait until the PLLSAI is ready */
+
+      while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0)
+        {
+        }
+#endif
     }
 }
 #endif