path: root/nuttx/arch/arm/src/sama5/Kconfig

#
# For a description of the syntax of this configuration file,
# see misc/tools/kconfig-language.txt.
#

if ARCH_CHIP_SAMA5

comment "ATSAMA5 Configuration Options"

choice
	prompt "Atmel AT91SAMA5 Chip Selection"
	default ARCH_CHIP_ATSAMA5D33

config ARCH_CHIP_ATSAMA5D31
	bool "Atmel ATSAMA5D31"
	select ARCH_CHIP_SAMA5D3
	select SAMA5_HAVE_EMAC

config ARCH_CHIP_ATSAMA5D33
	bool "Atmel ATSAMA5D33"
	select ARCH_CHIP_SAMA5D3
	select SAMA5_HAVE_GMAC

config ARCH_CHIP_ATSAMA5D34
	bool "Atmel ATSAMA5D34"
	select ARCH_CHIP_SAMA5D3
	select SAMA5_HAVE_GMAC

config ARCH_CHIP_ATSAMA5D35
	bool "Atmel ATSAMA5D35"
	select ARCH_CHIP_SAMA5D3
	select SAMA5_HAVE_EMAC
	select SAMA5_HAVE_GMAC

endchoice # Atmel AT91SAMA5 Chip Selection

menu "ATSAMA5 Peripheral Support"

config SAMA5_DBGU
	bool "Debug Unit Interrupt (DBGU)"
	default n

config SAMA5_PIT
	bool "Periodic Interval Timer Interrupt (PIT)"
	default n

config SAMA5_WDT
	bool "Watchdog timer Interrupt (WDT)"
	default n

config SAMA5_HSMC
	bool "Static Memory Controller (HSMC)"
	default n

config SAMA5_SMD
	bool "SMD Soft Modem (SMD)"
	default n

config SAMA5_UART0
	bool "UART 0"
	default y
	select ARCH_HAVE_UART0

config SAMA5_UART1
	bool "UART 1"
	default n
	select ARCH_HAVE_UART1

config SAMA5_USART0
	bool "USART 0"
	default n
	select ARCH_HAVE_USART0

config SAMA5_USART1
	bool "USART 1"
	default n
	select ARCH_HAVE_USART1

config SAMA5_USART2
	bool "USART 2"
	default n
	select ARCH_HAVE_USART2

config SAMA5_USART3
	bool "USART 3"
	default n
	select ARCH_HAVE_USART3

config SAMA5_TWI0
	bool "Two-Wire Interface 0 (TWI0)"
	default n

config SAMA5_TWI1
	bool "Two-Wire Interface 1 (TWI1)"
	default n

config SAMA5_TWI2
	bool "Two-Wire Interface 2 (TWI2)"
	default n

config SAMA5_HSMCI0
	bool "High Speed Multimedia Card Interface 0 (HSMCI0)"
	default n
	select ARCH_HAVE_SDIO

config SAMA5_HSMCI1
	bool "High Speed Multimedia Card Interface 1 (HSMCI1)"
	default n
	select ARCH_HAVE_SDIO

config SAMA5_HSMCI2
	bool "High Speed Multimedia Card Interface 2 (HSMCI2)"
	default n
	select ARCH_HAVE_SDIO

config SAMA5_SPI0
	bool "Serial Peripheral Interface 0 (SPI0)"
	default n

config SAMA5_SPI1
	bool "Serial Peripheral Interface 1 (SPI1)"
	default n

config SAMA5_TC0
	bool "Timer Counter 0 (ch. 0, 1, 2) (TC0)"
	default n

config SAMA5_TC1
	bool "Timer Counter 1 (ch. 3, 4, 5) (TC1)"
	default n

config SAMA5_PWM
	bool "Pulse Width Modulation Controller (PWM)"
	default n

config SAMA5_ADC
	bool "Touch Screen ADC Controller (ADC)"
	default n

config SAMA5_DMAC0
	bool "DMA Controller 0 (DMAC0)"
	default n
	select ARCH_DMA

config SAMA5_DMAC1
	bool "DMA Controller 1 (DMAC1)"
	default n
	select ARCH_DMA

config SAMA5_UHPHS
	bool "USB Host High Speed (UHPHS)"
	default n

config SAMA5_UDPHS
	bool "USB Device High Speed (UDPHS)"
	default n
	depends on SAMA5_HAVE_GMAC

config SAMA5_GMAC
	bool "Gigabit Ethernet MAC (GMAC)"
	default n
	depends on SAMA5_HAVE_GMAC
	select NETDEVICES
	select ARCH_HAVE_PHY

config SAMA5_EMAC
	bool "10/100MBps Ethernet MAC (EMAC)"
	default n
	depends on SAMA5_HAVE_EMAC
	select NETDEVICES
	select ARCH_HAVE_PHY

config SAMA5_LCDC
	bool "LCD Controller (LCDC)"
	default n

config SAMA5_ISI
	bool "Image Sensor Interface (ISI)"
	default n

config SAMA5_SSC0
	bool "Synchronous Serial Controller 0 (SSC0)"
	default n

config SAMA5_SSC1
	bool "Synchronous Serial Controller 1 (SSC1)"
	default n

config SAMA5_CAN0
	bool "CAN controller 0 (CAN0)"
	default n

config SAMA5_CAN1
	bool "CAN controller 1 (CAN1)"
	default n

config SAMA5_SHA
	bool "Secure Hash Algorithm (SHA)"
	default n

config SAMA5_AES
	bool "Advanced Encryption Standard (AES)"
	default n

config SAMA5_TDES
	bool "Triple Data Encryption Standard (TDES)"
	default n

config SAMA5_TRNG
	bool "True Random Number Generator (TRNG)"
	default n

config SAMA5_ARM
	bool "Performance Monitor Unit (ARM)"
	default n

config SAMA5_FUSE
	bool "Fuse Controller (FUSE)"
	default n

config SAMA5_MPDDRC
	bool "MPDDR controller (MPDDRC)"
	default n

endmenu # ATSAMA5 Peripheral Support

config SAMA5_PIO_IRQ
	bool "PIO pin interrupts"
	---help---
		Enable support for interrupting PIO pins

if SAMA5_PIO_IRQ

config SAMA5_PIOA_IRQ
	bool "PIOA interrupts"
	default n

config SAMA5_PIOB_IRQ
	bool "PIOB interrupts"
	default n

config SAMA5_PIOC_IRQ
	bool "PIOC interrupts"
	default n

config SAMA5_PIOD_IRQ
	bool "PIOD interrupts"
	default n

config SAMA5_PIOE_IRQ
	bool "PIOE interrupts"
	default n

endif # PIO_IRQ

config SAMA5_HAVE_GMAC
	bool
	default n

config SAMA5_HAVE_EMAC
	bool
	default n

if SAMA5_GMAC

menu "GMAC device driver options"

if SAMA5_EMAC

config SAMA5_GMAC_ISETH0
    bool "GMAC is ETH0"
    default y

endif # SAMA5_EMAC
endmenu # GMAC device driver options
endif # SAMA5_GMAC

if SAMA5_EMAC

menu "EMAC device driver options"

config SAMA5_EMAC_NRXBUFFERS
	int "Number of RX buffers"
	default 16
	---help---
		EMAC buffer memory is segmented into 128 byte units (not
		configurable).  This setting provides the number of such 128 byte
		units used for reception.  This is also equal to the number of RX
		descriptors that will be allocated  The selected value must be an
		even power of 2.

config SAMA5_EMAC_NTXBUFFERS
	int "Number of TX buffers"
	default 1
	---help---
		EMAC buffer memory is segmented into full Ethernet packets (size
		NET_BUFSIZE bytes).  This setting provides the number of such packets
		that can be in flight.  This is also equal to the number of TX
		descriptors that will be allocated.

config SAMA5_EMAC_PREALLOCATE
	bool "Preallocate buffers"
	default n
	---help---
		Buffer an descriptor many may either be allocated from the memory
		pool or pre-allocated to lie in .bss.  This options selected pre-
		allocated buffer memory.

config SAMA5_EMAC_NBC
	bool "Disable Broadcast"
	default n
	---help---
		Select to disable receipt of broadcast packets.

config SAMA5_EMAC_PHYADDR
	int "PHY address"
	default 1
	---help---
		The 5-bit address of the PHY on the board.  Default: 1

config SAMA5_EMAC_PHYINIT
	bool "Board-specific PHY Initialization"
	default n
	---help---
		Some boards require specialized initialization of the PHY before it can be used.
		This may include such things as configuring GPIOs, resetting the PHY, etc.  If
		SAMA5_EMAC_PHYINIT is defined in the configuration then the board specific logic must
		provide sam_phyinitialize();  The SAMA5 EMAC driver will call this function
		one time before it first uses the PHY.

config SAMA5_EMAC_MII
	bool "Use MII interface"
	default n
	---help---
		Support Ethernet MII interface (vs RMII).

config SAMA5_EMAC_RMII
	bool
	default y if !SAMA5_EMAC_MII
	default n if SAMA5_EMAC_MII

config SAMA5_EMAC_AUTONEG
	bool "Use autonegotiation"
	default y
	---help---
		Use PHY autonegotiation to determine speed and mode

config SAMA5_EMAC_ETHFD
	bool "Full duplex"
	default n
	depends on !SAMA5_EMAC_AUTONEG
	---help---
		If SAMA5_EMAC_AUTONEG is not defined, then this may be defined to select full duplex
		mode. Default: half-duplex

config SAMA5_EMAC_ETH100MBPS
	bool "100 Mbps"
	default n
	depends on !SAMA5_EMAC_AUTONEG
	---help---
		If SAMA5_EMAC_AUTONEG is not defined, then this may be defined to select 100 MBps
		speed.  Default: 10 Mbps

config SAMA5_EMAC_PHYSR
	int "PHY Status Register Address (decimal)"
	depends on SAMA5_EMAC_AUTONEG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  The PHY status register
		address may diff from PHY to PHY.  This configuration sets the address of
		the PHY status register.

config SAMA5_EMAC_PHYSR_ALTCONFIG
	bool "PHY Status Alternate Bit Layout"
	default n
	depends on SAMA5_EMAC_AUTONEG
	---help---
		Different PHYs present speed and mode information in different ways.  Some
		will present separate information for speed and mode (this is the default).
		Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
		full/half duplex indication. This options selects an alternative representation
		where speed and mode information are combined.  This might mean, for example,
		separate bits for 10HD, 100HD, 10FD and 100FD.

config SAMA5_EMAC_PHYSR_SPEED
	hex "PHY Speed Mask"
	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provides bit mask
		for isolating the 10 or 100MBps speed indication.

config SAMA5_EMAC_PHYSR_100MBPS
	hex "PHY 100Mbps Speed Value"
	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provides the value
		of the speed bit(s) indicating 100MBps speed.

config SAMA5_EMAC_PHYSR_MODE
	hex "PHY Mode Mask"
	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provide bit mask
		for isolating the full or half duplex mode bits.

config SAMA5_EMAC_PHYSR_FULLDUPLEX
	hex "PHY Full Duplex Mode Value"
	depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provides the
		value of the mode bits indicating full duplex mode.

config SAMA5_EMAC_PHYSR_ALTMODE
	hex "PHY Mode Mask"
	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This provide bit mask
		for isolating the speed and full/half duplex mode bits.

config SAMA5_EMAC_PHYSR_10HD
	hex "10MBase-T Half Duplex Value"
	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
		under the bit mask that represents the 10Mbps, half duplex setting.

config SAMA5_EMAC_PHYSR_100HD
	hex "100Base-T Half Duplex Value"
	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
		under the bit mask that represents the 100Mbps, half duplex setting.

config SAMA5_EMAC_PHYSR_10FD
	hex "10Base-T Full Duplex Value"
	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
		under the bit mask that represents the 10Mbps, full duplex setting.

config SAMA5_EMAC_PHYSR_100FD
	hex "100Base-T Full Duplex Value"
	depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
	---help---
		This must be provided if SAMA5_EMAC_AUTONEG is defined.  This is the value
		under the bit mask that represents the 100Mbps, full duplex setting.

config SAMA5_EMAC_REGDEBUG
	bool "Register-Level Debug"
	default n
	depends on DEBUG
	---help---
		Enable very low-level register access debug.  Depends on DEBUG.

config SAMA5_EMAC_ISETH0
    bool
    default y if !SAMA5_EMAC || !SAMA5_GMAC_ISETH0
    default n if SAMA5_EMAC && SAMA5_GMAC_ISETH0

endmenu # EMAC device driver options
endif # SAMA5_EMAC

if SAMA5_SPI0 || SAMA5_SPI1

menu "SPI device driver options"

config SAMA5_SPI_DMA
	bool "SPI DMA"
	default n
	depends on (SAMA5_DMAC0 && SAMA5_SPI0) || (SAMA5_DMAC1 && SAMA5_SPI1)
	---help---
		Use DMA to improve SPI transfer performance.

config SAMA5_SPI_DMATHRESHOLD
	int "SPI DMA threshold"
	default 4
	depends on SAMA5_SPI_DMA
	---help---
		When SPI DMA is enabled, small DMA transfers will still be performed
		by polling logic.  But we need a threshold value to determine what
		is small.  That value is provided by SAMA5_SPI_DMATHRESHOLD.

config SAMA5_SPI_DMADEBUG
	bool "SPI DMA transfer debug"
	depends on SAMA5_SPI_DMA && DEBUG && DEBUG_DMA
	default n
	---help---
		Enable special debug instrumentation analyze SPI DMA data transfers.
		This logic is as non-invasive as possible:  It samples DMA
		registers at key points in the data transfer and then dumps all of
		the registers at the end of the transfer.

config SAMA5_SPI_REGDEBUG
	bool "SPI Register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level SPI device debug information.  Requires also DEBUG.

endmenu # SPI device driver options
endif # SAMA5_SPI0 || SAMA5_SPI1

if SAMA5_TWI0 || SAMA5_TWI1 || SAMA5_TWI2

menu "TWI device driver options"

config SAMA5_TWI0_FREQUENCY
	int "TWI0 Frequency"
	default 100000
	depends on SAMA5_TWI0

config SAMA5_TWI1_FREQUENCY
	int "TWI1 Frequency"
	default 100000
	depends on SAMA5_TWI1

config SAMA5_TWI2_FREQUENCY
	int "TWI2 Frequency"
	default 100000
	depends on SAMA5_TWI2

config SAMA5_TWI_REGDEBUG
	bool "TWI register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level TWI device debug information.
		Very invasive! Requires also DEBUG.

endmenu # TWI device driver options
endif # SAMA5_TWI0 || SAMA5_TWI1 || SAMA5_TWI2

if SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2
menu "HSMCI device driver options"

config SAMA5_HSMCI_RDPROOF
	bool "Read Proof Enable"
	default n
	---help---
		Enabling Read Proof allows to stop the HSMCI Clock during read
		access if the internal FIFO is full. This will guarantee data
		integrity, not bandwidth.

config SAMA5_HSMCI_WRPROOF
	bool "Write Proof Enable"
	default n
	---help---
		Enabling Write Proof allows to stop the HSMCI Clock during write
		access if the internal FIFO is full. This will guarantee data
		integrity, not bandwidth.

config SAMA5_HSMCI_XFRDEBUG
	bool "HSMCI transfer debug"
	depends on DEBUG_FS && DEBUG_VERBOSE
	default n
	---help---
		Enable special debug instrumentation analyze HSMCI data transfers.
		This logic is as non-invasive as possible:  It samples HSMCI
		registers at key points in the data transfer and then dumps all of
		the registers at the end of the transfer.  If DEBUG_DMA is also
		enabled, then DMA register will be collected as well.  Requires also
		DEBUG_FS and DEBUG_VERBOSE.

config SAMA5_HSMCI_CMDDEBUG
	bool "HSMCI command debug"
	depends on DEBUG_FS && DEBUG_VERBOSE
	default n
	---help---
		Enable special debug instrumentation analyze HSMCI commands. This
		logic is as non-invasive as possible:  It samples HSMCI registers at
		key points in the data transfer and then dumps all of the registers
		at the end of the transfer.  If DEBUG_DMA is also enabled, then DMA
		register will be collected as well.  Requires also DEBUG_FS and
		DEBUG_VERBOSE.

config SAMA5_HSMCI_REGDEBUG
	bool "HSMCI Register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level HSCMI device debug information.
		Very invasive! Requires also DEBUG.

endmenu # HSMCI device driver options
endif # SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2

if SAMA5_UDPHS
menu "USB High Speed Device Controller driver (DCD) options"

config UDPHS_SCATTERGATHER
	bool
	default n
	---help---
		Scatter gather DMA is not yet supported

config SAMA5_UDPHS_NDTDS
	int "Number of UDPHS DMA transfer descriptors"
	default 9
	depends on UDPHS_SCATTERGATHER
	---help---
		DMA tranfer descriptors are allocated in a pool at boot time.  This
		setting provides the number of DMA transfer descriptors to be
		allocated.

config SAMA5_UDPHS_PREALLOCATE
	bool "Pre-allocate DMA transfer descriptors"
	default y
	depends on UDPHS_SCATTERGATHER
	---help---
		If this option is selected then DMA tranfer descriptors will be
		pre-allocated in .bss.  Otherwise, the descriptors will be allocated
		at start-up time with kmalloc().  This might be important if a larger
		memory pool is available after startup.

config SAMA5_UDPHS_REGDEBUG
	bool "Enable low-level UPPHS register debug"
	default n
	depends on DEBUG

endmenu # USB High Speed Host Device driver (DCD) options
endif # SAMA5_UDPHS

if SAMA5_UHPHS
menu "USB High Speed Host Controller driver (HCD) options"

config SAMA5_OHCI
	bool "Full/low speed OHCI support"
	default n
	---help---
		Build support for the SAMA5 USB full speed Open Host Controller
		Interface (OHCI).

if SAMA5_OHCI
config SAMA5_OHCI_NEDS
	int "Number of endpoint descriptors"
	default 6

config SAMA5_OHCI_NTDS
	int "Number of transfer descriptors"
	default 9

config SAMA5_OHCI_TDBUFFERS
	int "Number of transfer descriptor buffers"
	default 6

config SAMA5_OHCI_TDBUFSIZE
	int "Size of one transfer descriptor buffer"
	default 128
	---help---
		The size of one transfer descriptor (TD) buffer in bytes.  The TD
		buffer size must be an even number of 32-bit words

config SAMA5_OHCI_REGDEBUG
	bool "Enable low-level OHCI register debug"
	default n
	depends on DEBUG

endif # SAMA5_OHCI

config SAMA5_EHCI
	bool "High speed EHCI support"
	default n
	---help---
		Build support for the SAMA5 USB high speed Enhanced Host Controller
		Interface (EHCI).  If low/full speed is needed too, then you must
		also enable the OHCI controller.

if SAMA5_EHCI

config SAMA5_EHCI_NQHS
	int "Number of Queue Head (QH) structures"
	default 4
	---help---
		Configurable number of Queue Head (QH) structures.  The default is
		one per Root hub port plus one for EP0 (4).

config SAMA5_EHCI_NQTDS
	int "Number of Queue Element Transfer Descriptor (qTDs)"
	default 6
	---help---
		Configurable number of Queue Element Transfer Descriptor (qTDs).
		The default is one per root hub plus three from EP0 (6).

config SAMA5_EHCI_BUFSIZE
	int "Size of one request/descriptor buffer"
	default 128
	---help---
		The size of one request/descriptor buffer in bytes.  The TD buffe
		size must be an even number of 32-bit words and must be large enough
		to hangle the largest transfer via a SETUP request.

config SAMA5_EHCI_PREALLOCATE
	bool "Preallocate descriptor pool"
	default y
	---help---
		Select this option to pre-allocate EHCI queue and descriptor
		structure pools in .bss.  Otherwise, these pools will be
		dynamically allocated using kmemalign().

config SAMA5_EHCI_REGDEBUG
	bool "Enable low-level EHCI register debug"
	default n
	depends on DEBUG

endif # SAMA5_EHCI

if SAMA5_OHCI || SAMA5_EHCI

config SAMA5_UHPHS_RHPORT1
	bool "Use Port A"
	default y
	depends on !SAMA5_UDPHS

config SAMA5_UHPHS_RHPORT2
	bool "Use Port B"
	default y

config SAMA5_UHPHS_RHPORT3
	bool "Use Port C"
	default y

endif # SAMA5_OHCI || SAMA5_EHCI

endmenu # USB High Speed Host Controller driver (HCD) options
endif # SAMA5_UHPHS

menu "External Memory Configuration"

config SAMA5_DDRCS
	bool "External DDR-SDRAM Memory"
	default n
	depends on SAMA5_MPDDRC
	---help---
		Build in support for DDR-SDRAM memory resources.

if SAMA5_DDRCS

config SAMA5_DDRCS_SIZE
	int "DDR-SDRAM Memory size"
	default 0
	---help---
		Mapped size of the DDR-SDRAM memory region.

choice
	prompt "DDR-SDRAM Memory Type"
	default SAMA5_DDRCS_LPDDR1
	---help---
		Select the type of DDR-SDRAM memory present

config SAMA5_DDRCS_LPDDR1
	bool "Low-power DDR1-SDRAM (LPDDR1)"

config SAMA5_DDRCS_LPDDR2
	bool "Low-power DDR2-SDRAM-S4 (LPDDR2)"

endchoice # DDR-SDRAM Memory Type
endif # SAMA5_DDRCS

config SAMA5_EBICS0
	bool "External CS0 Memory"
	default n
	depends on SAMA5_HSMC
	---help---
		Build in support for memory resources in the chip select 0 (CS0)
		memory region.

if SAMA5_EBICS0

config SAMA5_EBICS0_SIZE
	int "CS0 Memory size"
	default 0
	---help---
		Mapped size of the memory region at CS0.

choice
	prompt "CS0 Memory Type"
	default SAMA5_EBICS0_NOR
	---help---
		Select the type of memory present on CS0

config SAMA5_EBICS0_SRAM
	bool "SRAM"

config SAMA5_EBICS0_PSRAM
	bool "PSRAM"

config SAMA5_EBICS0_PROM
	bool "PROM"

config SAMA5_EBICS0_EEPROM
	bool "EEPROM"

config SAMA5_EBICS0_EPROM
	bool "EPROM"

config SAMA5_EBICS0_LCD
	bool "LCD"

config SAMA5_EBICS0_NOR
	bool "NOR Flash"

config SAMA5_EBICS0_NAND
	bool "NAND Flash"

endchoice # CS0 Memory Type
endif # SAMA5_EBICS0

config SAMA5_EBICS1
	bool "External CS1 Memory"
	default n
	depends on SAMA5_HSMC
	---help---
		Build in support for memory resources in the chip select 1 (CS1)
		memory region.

if SAMA5_EBICS1

config SAMA5_EBICS1_SIZE
	int "CS1 Memory size"
	default 0
	---help---
		Mapped size of the memory region at CS1.

choice
	prompt "CS1 Memory Type"
	default SAMA5_EBICS1_NOR
	---help---
		Select the type of memory present on CS1

config SAMA5_EBICS1_SRAM
	bool "SRAM"

config SAMA5_EBICS1_PSRAM
	bool "PSRAM"

config SAMA5_EBICS1_PROM
	bool "PROM"

config SAMA5_EBICS1_EEPROM
	bool "EEPROM"

config SAMA5_EBICS1_EPROM
	bool "EPROM"

config SAMA5_EBICS1_LCD
	bool "LCD"

config SAMA5_EBICS1_NOR
	bool "NOR Flash"

config SAMA5_EBICS1_NAND
	bool "NAND Flash"

endchoice # CS1 Memory Type
endif # SAMA5_EBICS1

config SAMA5_EBICS2
	bool "External CS2 Memory"
	depends on SAMA5_HSMC
	default n
	---help---
		Build in support for memory resources in the chip select 2 (CS2)
		memory region.

if SAMA5_EBICS2

config SAMA5_EBICS2_SIZE
	int "CS2 Memory size"
	default 0
	---help---
		Mapped size of the memory region at CS2.

choice
	prompt "CS2 Memory Type"
	default SAMA5_EBICS2_NOR
	---help---
		Select the type of memory present on CS2

config SAMA5_EBICS2_SRAM
	bool "SRAM"

config SAMA5_EBICS2_PSRAM
	bool "PSRAM"

config SAMA5_EBICS2_PROM
	bool "PROM"

config SAMA5_EBICS2_EEPROM
	bool "EEPROM"

config SAMA5_EBICS2_EPROM
	bool "EPROM"

config SAMA5_EBICS2_LCD
	bool "LCD"

config SAMA5_EBICS2_NOR
	bool "NOR Flash"

config SAMA5_EBICS2_NAND
	bool "NAND Flash"

endchoice # CS2 Memory Type
endif # SAMA5_EBICS2

config SAMA5_EBICS3
	bool "External CS3 Memory"
	default n
	depends on SAMA5_HSMC
	---help---
		Build in support for memory resources in the chip select 3 (CS3)
		memory region.

if SAMA5_EBICS3

config SAMA5_EBICS3_SIZE
	int "CS3 Memory size"
	default 0
	---help---
		Mapped size of the memory region at CS3.

choice
	prompt "CS3 Memory Type"
	default SAMA5_EBICS3_NOR
	---help---
		Select the type of memory present on CS3

config SAMA5_EBICS3_SRAM
	bool "SRAM"

config SAMA5_EBICS3_PSRAM
	bool "PSRAM"

config SAMA5_EBICS3_PROM
	bool "PROM"

config SAMA5_EBICS3_EEPROM
	bool "EEPROM"

config SAMA5_EBICS3_EPROM
	bool "EPROM"

config SAMA5_EBICS3_LCD
	bool "LCD"

config SAMA5_EBICS3_NOR
	bool "NOR Flash"

config SAMA5_EBICS3_NAND
	bool "NAND Flash"

endchoice # CS3 Memory Type
endif # SAMA5_EBICS3
endmenu # External Memory Configuration

choice
	prompt "SAMA5 Boot Configuration"
	default SAMA5_BOOT_ISRAM
	---help---
		The startup code needs to know if the code is running from internal SRAM,
		external SRAM, or CS0-3 in order to initialize properly.  Note that the
		boot device is not specified for cases where the code is copied into
		internal SRAM; those cases are all covered by SAMA5_BOOT_ISRAM.

config SAMA5_BOOT_ISRAM
	bool "Running from internal SRAM"

config SAMA5_BOOT_SDRAM
	bool "Running from external SDRAM"
	depends on SAMA5_DDRCS

config SAMA5_BOOT_CS0FLASH
	bool "Running in external FLASH CS0"
	depends on SAMA5_EBICS0_NOR

config SAMA5_BOOT_CS0SRAM
	bool "Running in external FLASH CS0"
	depends on SAMA5_EBICS0_SRAM || SAMA5_EBICS0_PSRAM

config SAMA5_BOOT_CS1FLASH
	bool "Running in external FLASH CS1"
	depends on SAMA5_EBICS1_NOR

config SAMA5_BOOT_CS1SRAM
	bool "Running in external FLASH CS1"
	depends on SAMA5_EBICS1_SRAM || SAMA5_EBICS1_PSRAM

config SAMA5_BOOT_CS2FLASH
	bool "Running in external FLASH CS2"
	depends on SAMA5_EBICS2_NOR

config SAMA5_BOOT_CS2SRAM
	bool "Running in external FLASH CS2"
	depends on SAMA5_EBICS2_SRAM || SAMA5_EBICS2_PSRAM

config SAMA5_BOOT_CS2FLASH
	bool "Running in external FLASH CS3"
	depends on SAMA5_EBICS3_NOR

config SAMA5_BOOT_CS3SRAM
	bool "Running in external FLASH CS3"
	depends on SAMA5_EBICS3_SRAM || SAMA5_EBICS3_PSRAM

endchoice # SAMA5 Boot Configuration

menu "Heap Configuration"

config SAMA5_ISRAM_HEAP
	bool "Include ISRAM in heap"
	default y
	depends on !SAMA5_BOOT_ISRAM
	---help---
		Include the internal SRAM memory in the heap.

		NOTE:  MM_REGIONS must also be set to indicate the total number of
		memory regions to be added to the heap.

		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM INTERNAL SRAM!!**
		In this case, the remaining ISRAM will automatically be added to the
		heap (using RAM_END).

config SAMA5_DDRCS_HEAP
	bool "Include DDR-SDRAM in heap"
	default y
	depends on SAMA5_DDRCS && !SAMA5_BOOT_SDRAM
	---help---
		Include the DDR-SDRAM memory in the heap.

		NOTE:  MM_REGIONS must also be set to indicate the total number of
		memory regions to be added to the heap.

		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM SDRAM!!**
		In this case, the remaining SDRAM will automatically be added to the
		heap (using RAM_END)

config SAMA5_EBICS0_HEAP
	bool "Include SRAM/PSRAM in heap"
	default y
	depends on (SAMA5_EBICS0_SRAM || SAMA5_EBICS0_PSRAM) && !SAMA5_BOOT_CS0SRAM
	---help---
		Include the CS0 SRAM/PSREAM memory in the heap.

		NOTE:  MM_REGIONS must also be set to indicate the total number of
		memory regions to be added to the heap.

		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS0 SRAM!!**
		In this case, the remaining SRAM will automatically be added to the
		heap (using RAM_END).

config SAMA5_EBICS1_HEAP
	bool "Include SRAM/PSRAM in heap"
	default y
	depends on (SAMA5_EBICS1_SRAM || SAMA5_EBICS1_PSRAM) && !SAMA5_BOOT_CS1SRAM
	---help---
		Include the CS1 SRAM/PSREAM memory in the heap.

		NOTE:  MM_REGIONS must also be set to indicate the total number of
		memory regions to be added to the heap.

		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS1 SRAM!!**
		In this case, the remaining SRAM will automatically be added to the
		heap (using RAM_END).

config SAMA5_EBICS2_HEAP
	bool "Include SRAM/PSRAM in heap"
	default y
	depends on (SAMA5_EBICS2_SRAM || SAMA5_EBICS2_PSRAM) && !SAMA5_BOOT_CS2SRAM
	---help---
		Include the CS2 SRAM/PSREAM memory in the heap.

		NOTE:  MM_REGIONS must also be set to indicate the total number of
		memory regions to be added to the heap.

		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS2 SRAM!!**
		In this case, the remaining SRAM will automatically be added to the
		heap (using RAM_END).

config SAMA5_EBICS3_HEAP
	bool "Include SRAM/PSRAM in heap"
	default y
	depends on (SAMA5_EBICS3_SRAM || SAMA5_EBICS3_PSRAM) && !SAMA5_BOOT_CS3SRAM
	---help---
		Include the CS3 SRAM/PSREAM memory in the heap.

		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS3 SRAM!!**
		In this case, the remaining SRAM will automatically be added to the
		heap (using RAM_END).

endmenu # Heap Configuration
endif # ARCH_CHIP_SAMA5