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author | Jason Zaugg <jzaugg@gmail.com> | 2015-08-21 14:00:46 +1000 |
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committer | Jason Zaugg <jzaugg@gmail.com> | 2015-10-08 14:09:59 +1000 |
commit | 571ed0312031a0826f65d40b27933d16b9617fbe (patch) | |
tree | dcd841aaa63b1b97d47eab76a5d3e2afc53ac75d /src/compiler/scala/tools/nsc/transform/Mixin.scala | |
parent | 5614baf08b2da56532b580c7e2f70cf357832970 (diff) | |
download | scala-571ed0312031a0826f65d40b27933d16b9617fbe.tar.gz scala-571ed0312031a0826f65d40b27933d16b9617fbe.tar.bz2 scala-571ed0312031a0826f65d40b27933d16b9617fbe.zip |
Desugar module var and accessor in refchecks/lazyvals
Rather than leaving it until mixin.
The broader motivation is to simplify the mixin phase of the
compiler before we get rid of implementatation classes in
favour of using JDK8 default interface methods.
The current code in mixin is used for both lazy val and modules,
and puts the "slow path" code that uses the monitor into a
dedicated method (`moduleName$lzyCompute`). I tracked this
back to a3d4d17b77. I can't tell from that commit whether the
performance sensititivity was related to modules or lazy vals,
from the commit message I'd say the latter.
As the initialization code for a module is just a constructor call,
rather than an arbitraryly large chunk of code for a lazy initializer,
this commit opts to inline the `lzycompute` method.
During refchecks, mixin module accessors are added to classes, so
that mixed in and defined modules are translated uniformly. Trait
owned modules get an accessor method with an empty body (that shares
the module symbol), but no module var.
Defer synthesis of the double checked locking idiom to the lazyvals
phase, which gets us a step closer to a unified translation of
modules and lazy vals.
I had to change the `atOwner` methods to to avoid using the
non-existent module class of a module accessor method as the
current owner. This fixes a latent bug. Without this change,
retypechecking of the module accessor method during erasure crashes
with an accessibility error selecting the module var.
In the process, I've tweaked a tree generation utility method
to wvoid synthesizing redundant blocks in module desugaring.
Diffstat (limited to 'src/compiler/scala/tools/nsc/transform/Mixin.scala')
-rw-r--r-- | src/compiler/scala/tools/nsc/transform/Mixin.scala | 35 |
1 files changed, 1 insertions, 34 deletions
diff --git a/src/compiler/scala/tools/nsc/transform/Mixin.scala b/src/compiler/scala/tools/nsc/transform/Mixin.scala index 00a994fe87..d6e4e1a727 100644 --- a/src/compiler/scala/tools/nsc/transform/Mixin.scala +++ b/src/compiler/scala/tools/nsc/transform/Mixin.scala @@ -861,16 +861,6 @@ abstract class Mixin extends InfoTransform with ast.TreeDSL { typedPos(init.head.pos)(mkFastPathLazyBody(clazz, lzyVal, cond, syncBody, nulls, retVal)) } - def mkInnerClassAccessorDoubleChecked(attrThis: Tree, rhs: Tree, moduleSym: Symbol, args: List[Tree]): Tree = - rhs match { - case Block(List(assign), returnTree) => - val Assign(moduleVarRef, _) = assign - val cond = Apply(Select(moduleVarRef, Object_eq), List(NULL)) - mkFastPathBody(clazz, moduleSym, cond, List(assign), List(NULL), returnTree, attrThis, args) - case _ => - abort(s"Invalid getter $rhs for module in $clazz") - } - def mkCheckedAccessor(clazz: Symbol, retVal: Tree, offset: Int, pos: Position, fieldSym: Symbol): Tree = { val sym = fieldSym.getterIn(fieldSym.owner) val bitmapSym = bitmapFor(clazz, offset, sym) @@ -926,18 +916,6 @@ abstract class Mixin extends InfoTransform with ast.TreeDSL { deriveDefDef(stat)(rhs => Block(List(rhs, localTyper.typed(mkSetFlag(clazz, fieldOffset(getter), getter, bitmapKind(getter)))), UNIT)) else stat } - else if (sym.isModule && (!clazz.isTrait || clazz.isImplClass) && !sym.isBridge) { - deriveDefDef(stat)(rhs => - typedPos(stat.pos)( - mkInnerClassAccessorDoubleChecked( - // Martin to Hubert: I think this can be replaced by selfRef(tree.pos) - // @PP: It does not seem so, it crashes for me trying to bootstrap. - if (clazz.isImplClass) gen.mkAttributedIdent(stat.vparamss.head.head.symbol) else gen.mkAttributedThis(clazz), - rhs, sym, stat.vparamss.head - ) - ) - ) - } else stat } stats map { @@ -1082,18 +1060,7 @@ abstract class Mixin extends InfoTransform with ast.TreeDSL { }) } else if (sym.isModule && !(sym hasFlag LIFTED | BRIDGE)) { - // add modules - val vsym = sym.owner.newModuleVarSymbol(sym) - addDef(position(sym), ValDef(vsym)) - - // !!! TODO - unravel the enormous duplication between this code and - // eliminateModuleDefs in RefChecks. - val rhs = gen.newModule(sym, vsym.tpe) - val assignAndRet = gen.mkAssignAndReturn(vsym, rhs) - val attrThis = gen.mkAttributedThis(clazz) - val rhs1 = mkInnerClassAccessorDoubleChecked(attrThis, assignAndRet, sym, List()) - - addDefDef(sym, rhs1) + // Moved to Refchecks } else if (!sym.isMethod) { // add fields |