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authorpaltherr <paltherr@epfl.ch>2003-07-10 12:59:58 +0000
committerpaltherr <paltherr@epfl.ch>2003-07-10 12:59:58 +0000
commit0e5eaf6fbd4e15a7d8fee50363d67a5bd1f81829 (patch)
treed685a0bd5431fbc357678083d1405b46612dec06 /test
parent808974e3492160faea5a0e085b4bb709e1457b65 (diff)
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- Removed some .apply
Diffstat (limited to 'test')
-rw-r--r--test/files/run/Course-2002-08.scala24
-rw-r--r--test/files/run/iq.scala2
2 files changed, 13 insertions, 13 deletions
diff --git a/test/files/run/Course-2002-08.scala b/test/files/run/Course-2002-08.scala
index ae39aeb90f..b821caa140 100644
--- a/test/files/run/Course-2002-08.scala
+++ b/test/files/run/Course-2002-08.scala
@@ -517,15 +517,15 @@ abstract class CircuitSimulator() extends BasicCircuitSimulator() {
val ctrlN = ctrl.map(w => { val iw = new Wire(); inverter(w,iw); iw});
val w0 = new Wire(), w1 = new Wire(), w2 = new Wire(), w3 = new Wire();
- andGate(in, ctrl.apply(1), w3);
- andGate(in, ctrl.apply(1), w2);
- andGate(in, ctrlN.apply(1), w1);
- andGate(in, ctrlN.apply(1), w0);
+ andGate(in, ctrl(1), w3);
+ andGate(in, ctrl(1), w2);
+ andGate(in, ctrlN(1), w1);
+ andGate(in, ctrlN(1), w0);
- andGate(w3, ctrl.apply(0), out.apply(3));
- andGate(w2, ctrlN.apply(0), out.apply(2));
- andGate(w1, ctrl.apply(0), out.apply(1));
- andGate(w0, ctrlN.apply(0), out.apply(0));
+ andGate(w3, ctrl(0), out(3));
+ andGate(w2, ctrlN(0), out(2));
+ andGate(w1, ctrl(0), out(1));
+ andGate(w0, ctrlN(0), out(0));
}
def connect(in: Wire, out: Wire) = {
@@ -566,13 +566,13 @@ class Main() extends CircuitSimulator() {
in.setSignal(true);
run;
- ctrl.apply(0).setSignal(true);
+ ctrl(0).setSignal(true);
run;
- ctrl.apply(1).setSignal(true);
+ ctrl(1).setSignal(true);
run;
- ctrl.apply(2).setSignal(true);
+ ctrl(2).setSignal(true);
run;
- ctrl.apply(0).setSignal(false);
+ ctrl(0).setSignal(false);
run;
}
}
diff --git a/test/files/run/iq.scala b/test/files/run/iq.scala
index a7f87409f3..f9c55476c7 100644
--- a/test/files/run/iq.scala
+++ b/test/files/run/iq.scala
@@ -41,7 +41,7 @@ object iq {
/* Test apply
* Expected: q5[5]: 5
*/
- java.lang.System.out.println("q5[5]: " + q5.apply(5));
+ java.lang.System.out.println("q5[5]: " + q5(5));
val q5c:Queue[char] = Queue.Empty.enqueue(0 as char, 1 as char,
2 as char, 3 as char,