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| author | px4dev <px4@purgatory.org> | 2012-08-13 23:56:52 -0700 |
|---|---|---|
| committer | px4dev <px4@purgatory.org> | 2012-08-13 23:56:52 -0700 |
| commit | 91d1524837b5c5302593ad8b415e9db9ca8f7680 (patch) | |
| tree | 100623c4dcf9eaa1a11e0a04dbd48357b4bfa088 | |
| parent | 165105bd93ce9a5f21b4739ed6643b44a8797f94 (diff) | |
| download | px4-firmware-91d1524837b5c5302593ad8b415e9db9ca8f7680.tar.gz px4-firmware-91d1524837b5c5302593ad8b415e9db9ca8f7680.tar.bz2 px4-firmware-91d1524837b5c5302593ad8b415e9db9ca8f7680.zip | |
Avoid reinitializing a SPI bus once it's been set up the first time.
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_spi.c | 54 |
1 files changed, 36 insertions, 18 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.c b/nuttx/arch/arm/src/stm32/stm32_spi.c index 06a994524..a65f1e1eb 100644 --- a/nuttx/arch/arm/src/stm32/stm32_spi.c +++ b/nuttx/arch/arm/src/stm32/stm32_spi.c @@ -1368,15 +1368,21 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv = &g_spi1dev; - /* Configure SPI1 pins: SCK, MISO, and MOSI */ + /* Only configure if the port is not already configured */ - stm32_configgpio(GPIO_SPI1_SCK); - stm32_configgpio(GPIO_SPI1_MISO); - stm32_configgpio(GPIO_SPI1_MOSI); + if (!(spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE)) + { + + /* Configure SPI1 pins: SCK, MISO, and MOSI */ + + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); - /* Set up default configuration: Master, 8-bit, etc. */ + /* Set up default configuration: Master, 8-bit, etc. */ - spi_portinitialize(priv); + spi_portinitialize(priv); + } } else #endif @@ -1387,15 +1393,21 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv = &g_spi2dev; - /* Configure SPI2 pins: SCK, MISO, and MOSI */ + /* Only configure if the port is not already configured */ + + if (!(spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE)) + { + + /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32_configgpio(GPIO_SPI2_SCK); - stm32_configgpio(GPIO_SPI2_MISO); - stm32_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); - /* Set up default configuration: Master, 8-bit, etc. */ + /* Set up default configuration: Master, 8-bit, etc. */ - spi_portinitialize(priv); + spi_portinitialize(priv); + } } else #endif @@ -1406,15 +1418,21 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv = &g_spi3dev; - /* Configure SPI3 pins: SCK, MISO, and MOSI */ + /* Only configure if the port is not already configured */ + + if (!(spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE)) + { + + /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32_configgpio(GPIO_SPI3_SCK); - stm32_configgpio(GPIO_SPI3_MISO); - stm32_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); - /* Set up default configuration: Master, 8-bit, etc. */ + /* Set up default configuration: Master, 8-bit, etc. */ - spi_portinitialize(priv); + spi_portinitialize(priv); + } } #endif |