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| author | px4dev <px4@purgatory.org> | 2013-07-29 23:13:46 -0700 |
|---|---|---|
| committer | px4dev <px4@purgatory.org> | 2013-07-29 23:13:46 -0700 |
| commit | 57cbf724f159cec88b21281a4ace415276df3a38 (patch) | |
| tree | c3dea3c546671702b0173619c9e8bc181c0e5179 | |
| parent | 1410625dea4204f758f42c1bdd06959f75a86ef9 (diff) | |
| download | px4-firmware-57cbf724f159cec88b21281a4ace415276df3a38.tar.gz px4-firmware-57cbf724f159cec88b21281a4ace415276df3a38.tar.bz2 px4-firmware-57cbf724f159cec88b21281a4ace415276df3a38.zip | |
Fix the clock enable register for FMUv2 PWM outputs 1-4.
Teach the stm32 pwm driver about the MOE bit on advanced timers.
| -rw-r--r-- | src/drivers/boards/px4fmuv2/px4fmu_pwm_servo.c | 2 | ||||
| -rw-r--r-- | src/drivers/stm32/drv_pwm_servo.c | 12 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/drivers/boards/px4fmuv2/px4fmu_pwm_servo.c b/src/drivers/boards/px4fmuv2/px4fmu_pwm_servo.c index d1656005b..bcbc0010c 100644 --- a/src/drivers/boards/px4fmuv2/px4fmu_pwm_servo.c +++ b/src/drivers/boards/px4fmuv2/px4fmu_pwm_servo.c @@ -53,7 +53,7 @@ __EXPORT const struct pwm_servo_timer pwm_timers[PWM_SERVO_MAX_TIMERS] = { { .base = STM32_TIM1_BASE, - .clock_register = STM32_RCC_APB1ENR, + .clock_register = STM32_RCC_APB2ENR, .clock_bit = RCC_APB2ENR_TIM1EN, .clock_freq = STM32_APB2_TIM1_CLKIN }, diff --git a/src/drivers/stm32/drv_pwm_servo.c b/src/drivers/stm32/drv_pwm_servo.c index 7b060412c..c85e83ddc 100644 --- a/src/drivers/stm32/drv_pwm_servo.c +++ b/src/drivers/stm32/drv_pwm_servo.c @@ -88,6 +88,7 @@ #define rCCR4(_tmr) REG(_tmr, STM32_GTIM_CCR4_OFFSET) #define rDCR(_tmr) REG(_tmr, STM32_GTIM_DCR_OFFSET) #define rDMAR(_tmr) REG(_tmr, STM32_GTIM_DMAR_OFFSET) +#define rBDTR(_tmr) REG(_tmr, STM32_ATIM_BDTR_OFFSET) static void pwm_timer_init(unsigned timer); static void pwm_timer_set_rate(unsigned timer, unsigned rate); @@ -110,6 +111,11 @@ pwm_timer_init(unsigned timer) rCCER(timer) = 0; rDCR(timer) = 0; + if ((pwm_timers[timer].base == STM32_TIM1_BASE) || (pwm_timers[timer].base == STM32_TIM8_BASE)) { + /* master output enable = on */ + rBDTR(timer) = ATIM_BDTR_MOE; + } + /* configure the timer to free-run at 1MHz */ rPSC(timer) = (pwm_timers[timer].clock_freq / 1000000) - 1; @@ -163,6 +169,9 @@ pwm_channel_init(unsigned channel) rCCER(timer) |= GTIM_CCER_CC4E; break; } + + /* generate an update event; reloads the counter and all registers */ + rEGR(timer) = GTIM_EGR_UG; } int @@ -203,6 +212,9 @@ up_pwm_servo_set(unsigned channel, servo_position_t value) return -1; } + /* generate an update event; reloads the counter and all registers */ + rEGR(timer) = GTIM_EGR_UG; + return 0; } |