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authorAndrew Tridgell <tridge@samba.org>2013-01-27 11:06:13 +1100
committerLorenz Meier <lm@inf.ethz.ch>2013-02-14 23:06:52 +0100
commit6eb69b07a8fd44fff1bfcf77bf4622f4dd044eef (patch)
treedae8be8b3b90dd58bc5f9d3f62981519a72709b7 /apps/px4io/i2c.c
parentbfecfbf5eef422e0ee069a17ff2482b352e29386 (diff)
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Merged debug level commits from Tridge
Diffstat (limited to 'apps/px4io/i2c.c')
-rw-r--r--apps/px4io/i2c.c41
1 files changed, 34 insertions, 7 deletions
diff --git a/apps/px4io/i2c.c b/apps/px4io/i2c.c
index 235f8affa..4485daa5b 100644
--- a/apps/px4io/i2c.c
+++ b/apps/px4io/i2c.c
@@ -65,10 +65,6 @@
#define rTRISE REG(STM32_I2C_TRISE_OFFSET)
static int i2c_interrupt(int irq, void *context);
-#ifdef DEBUG
-static void i2c_dump(void);
-#endif
-
static void i2c_rx_setup(void);
static void i2c_tx_setup(void);
static void i2c_rx_complete(void);
@@ -152,6 +148,39 @@ i2c_init(void)
#endif
}
+
+/*
+ reset the I2C bus
+ used to recover from lockups
+ */
+void i2c_reset(void)
+{
+ rCR1 |= I2C_CR1_SWRST;
+ rCR1 = 0;
+
+ /* set for DMA operation */
+ rCR2 |= I2C_CR2_ITEVFEN |I2C_CR2_ITERREN | I2C_CR2_DMAEN;
+
+ /* set the frequency value in CR2 */
+ rCR2 &= ~I2C_CR2_FREQ_MASK;
+ rCR2 |= STM32_PCLK1_FREQUENCY / 1000000;
+
+ /* set divisor and risetime for fast mode */
+ uint16_t result = STM32_PCLK1_FREQUENCY / (400000 * 25);
+ if (result < 1)
+ result = 1;
+ result = 3;
+ rCCR &= ~I2C_CCR_CCR_MASK;
+ rCCR |= I2C_CCR_DUTY | I2C_CCR_FS | result;
+ rTRISE = (uint16_t)((((STM32_PCLK1_FREQUENCY / 1000000) * 300) / 1000) + 1);
+
+ /* set our device address */
+ rOAR1 = 0x1a << 1;
+
+ /* and enable the I2C port */
+ rCR1 |= I2C_CR1_ACK | I2C_CR1_PE;
+}
+
static int
i2c_interrupt(int irq, FAR void *context)
{
@@ -301,8 +330,7 @@ i2c_tx_complete(void)
i2c_tx_setup();
}
-#ifdef DEBUG
-static void
+void
i2c_dump(void)
{
debug("CR1 0x%08x CR2 0x%08x", rCR1, rCR2);
@@ -310,4 +338,3 @@ i2c_dump(void)
debug("CCR 0x%08x TRISE 0x%08x", rCCR, rTRISE);
debug("SR1 0x%08x SR2 0x%08x", rSR1, rSR2);
}
-#endif \ No newline at end of file