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author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-02-21 23:23:18 +0000 |
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committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-02-21 23:23:18 +0000 |
commit | d8c42f1ed57b77cc7381ebd6408c2f0f969e97b3 (patch) | |
tree | 8f935c05e96bea2d1fb97dc3508507189e231675 /nuttx/arch | |
parent | 20b15f2d8c1fc7dd2926f473eb34f507f83df5cf (diff) | |
download | px4-firmware-d8c42f1ed57b77cc7381ebd6408c2f0f969e97b3.tar.gz px4-firmware-d8c42f1ed57b77cc7381ebd6408c2f0f969e97b3.tar.bz2 px4-firmware-d8c42f1ed57b77cc7381ebd6408c2f0f969e97b3.zip |
Misc fixes to quadrature encoder debug output
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4411 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx/arch')
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_qencoder.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_qencoder.c b/nuttx/arch/arm/src/stm32/stm32_qencoder.c index 97d7c4235..67ba1eabb 100644 --- a/nuttx/arch/arm/src/stm32/stm32_qencoder.c +++ b/nuttx/arch/arm/src/stm32/stm32_qencoder.c @@ -77,18 +77,18 @@ # ifdef CONFIG_DEBUG_VERBOSE # define qevdbg vdbg # define qellvdbg llvdbg -# define stm32_dumpgpio(p,m) stm32_dumpgpio(p,m) +# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) # else -# define qelldbg(x...) +# define qevdbg(x...) # define qellvdbg(x...) -# define stm32_dumpgpio(p,m) +# define qe_dumpgpio(p,m) # endif #else # define qedbg(x...) # define qelldbg(x...) # define qevdbg(x...) # define qellvdbg(x...) -# define stm32_dumpgpio(p,m) +# define qe_dumpgpio(p,m) #endif /************************************************************************************ @@ -604,6 +604,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) uint16_t ccmr1; uint16_t ccer; uint16_t cr1; + uint16_t regval; int ret; /* NOTE: Clocking should have been enabled in the low-level RCC logic at boot-up */ @@ -754,7 +755,12 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) cr1 &= ~GTIM_CR1_URS; stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - /* Enable the update interrupt */ + /* Clear any pending update interrupts */ + + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF) + + /* Then enable the update interrupt */ dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier |= GTIM_DIER_UIE; @@ -947,6 +953,7 @@ static int stm32_reset(FAR struct qe_lowerhalf_s *lower) FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower; irqstate_t flags; + qevdbg("Resetting position to zero\n"); DEBUGASSERT(lower && priv->inuse); /* Reset the timer and the counter. Interrupts are disabled to make this atomic |