Fresh import of the PX4 firmware sources.

80 files changed, 19219 insertions, 0 deletions

diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig
new file mode 100644
index 000000000..2f6595dbd
--- /dev/null
+++ b/nuttx/configs/Kconfig
@@ -0,0 +1,714 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+choice
+	prompt "Select target board"
+	default ARCH_BOARD_CUSTOM
+	---help---
+		Select the board hosting the architure.  You must first select the
+		exact MCU part number, then the boards supporting that part will
+		be available for selection.  Use ARCH_BOARD_CUSTOM to create a new
+		board configuration.
+
+config ARCH_BOARD_AMBER
+	bool "Amber Web Server"
+	depends on ARCH_CHIP_ATMEGA128
+	---help---
+		This is placeholder for the SoC Robotics Amber Web Server that is based
+		on the Atmel AVR ATMega128 MCU.  There is not much there yet and what is
+		there is untested due to tool-related issues.
+
+config ARCH_BOARD_AVR32DEV1
+	bool "Atmel AVR32DEV1 board"
+	depends on ARCH_CHIP_AT32UC3B0256
+	---help---
+		This is a port of NuttX to the Atmel AVR32DEV1 board.  That board is
+		based on the Atmel AT32UC3B0256 MCU and uses a specially patched
+		version of the GNU toolchain:  The patches provide support for the
+		AVR32 family.  That patched GNU toolchain is available only from the
+		Atmel website.  STATUS: This port is functional but very basic.  There
+		are configurations for NSH and the OS test.
+
+config ARCH_BOARD_C5471EVM
+	bool "Spectrum Digital C5471 evaluation board"
+	depends on ARCH_CHIP_C5471
+	---help---
+		This is a port to the Spectrum Digital C5471 evaluation board.  The
+		TMS320C5471 is a dual core processor from TI with an ARM7TDMI general
+		purpose processor and a c54 DSP.  It is also known as TMS320DA180 or just DA180. 
+		NuttX runs on the ARM core and is built with a GNU arm-elf toolchain*.
+		This port is complete and verified.
+
+config ARCH_BOARD_COMPALE88
+	bool "Compal e88 phone"
+	depends on ARCH_CHIP_CALYPSO
+	---help---
+		These directories contain the board support for compal e88 and e99 phones.
+		These ports are based on patches contributed by Denis Carikli for both the
+		compal e99 and e88.  The patches were made by Alan Carvalho de Assis and
+		Denis Carikli using the Stefan Richter's Osmocom-bb patches.
+
+config ARCH_BOARD_COMPALE99
+	bool "Compal e99 phone"
+	depends on ARCH_CHIP_CALYPSO
+	---help---
+		These directories contain the board support for compal e88 and e99 phones.
+		These ports are based on patches contributed by Denis Carikli for both the
+		compal e99 and e88.  The patches were made by Alan Carvalho de Assis and
+		Denis Carikli using the Stefan Richter's Osmocom-bb patches.
+
+config ARCH_BOARD_DEMOS92S12NEC64
+	bool "Freescale DMO9S12NE64 board"
+	depends on ARCH_CHIP_MCS92S12NEC64
+	---help---
+	Freescale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu.  This
+	port uses the m9s12x GCC toolchain.  STATUS:  (Still) under development; it
+	is code complete but has not yet been verified.
+
+config ARCH_BOARD_EA3131
+	bool "Embedded Artists EA3131 Development board"
+	depends on ARCH_CHIP_LPC3131
+	---help---
+		Embedded Artists EA3131 Development board.  This board is based on the 
+		an NXP LPC3131 MCU. This OS is built with the arm-elf toolchain*.
+		STATUS:  This port is complete and mature.
+
+config ARCH_BOARD_EA3152
+	bool "Embedded Artists EA3152 Development board"
+	depends on ARCH_CHIP_LPC3152
+	---help---
+		Embedded Artists EA3152 Development board.  This board is based on the 
+		an NXP LPC3152 MCU. This OS is built with the arm-elf toolchain*.
+		STATUS:  This port is has not be exercised well, but since it is
+		a simple derivative of the ea3131, it should be fully functional.
+
+config ARCH_BOARD_EAGLE100
+	bool "Micromint Eagle-100 Development board"
+	depends on ARCH_CHIP_LM3S6918
+	---help---
+		Micromint Eagle-100 Development board.  This board is based on the 
+		an ARM Cortex-M3 MCU, the Luminary LM3S6918. This OS is built with the
+		arm-elf toolchain*.  STATUS:  This port is complete and mature.
+
+config ARCH_BOARD_EKK_LM3S9B96
+	bool "TI/Stellaris EKK-LM3S9B96"
+	depends on ARCH_CHIP_LM3S9B96
+	---help---
+		TI/Stellaris EKK-LM3S9B96 board.  This board is based on the 
+		an EKK-LM3S9B96 which is a Cortex-M3.
+
+config ARCH_BOARD_EZ80F910200KITG
+	bool "ZiLOG ez80f0910200kitg development kit"
+	depends on ARCH_CHIP_EZ80F91
+	---help---
+		ez80Acclaim! Microcontroller.  This port use the ZiLOG ez80f0910200kitg
+		development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line
+		tools.  The development environment is Cygwin under WinXP.
+
+config ARCH_BOARD_EZ80F910200ZCO
+	bool "ZiLOG ez80f0910200zco development kit"
+	depends on ARCH_CHIP_EZ80F91
+	---help---
+		ez80Acclaim! Microcontroller.  This port use the Zilog ez80f0910200zco
+		development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line
+		tools.  The development environment is Cygwin under WinXP.
+
+config ARCH_BOARD_HYMINI_STM32V
+	bool "HY-Mini STM32v board"
+	depends on ARCH_CHIP_STM32F103VCT
+	---help---
+		A configuration for the HY-Mini STM32v board.  This board is based on the
+		STM32F103VCT chip.
+
+config ARCH_BOARD_LINCOLN60
+	bool "Micromint Lincoln 60 board"
+	depends on ARCH_CHIP_LPC1769
+	---help---
+		Micromint Lincoln 60 board using the NXP LPC1769 MCU.
+
+config ARCH_BOARD_KWIKSTIK_K40
+	bool "FreeScale KwikStik-K40 development board"
+	depends on ARCH_CHIP_MK40X256VLQ100
+	---help---
+		Kinetis K40 Cortex-M4 MCU.  This port uses the FreeScale KwikStik-K40
+		development board.
+
+config ARCH_BOARD_LM3S6432S2E
+	bool "Stellaris RDK-S2E Reference Design Kit"
+	depends on ARCH_CHIP_LM3S6432
+	---help---
+		Stellaris RDK-S2E Reference Design Kit and the MDL-S2E Ethernet to
+		Serial module.
+
+config ARCH_BOARD_LM3S6965EK
+	bool "Stellaris LM3S6965 Evaluation Kit"
+	depends on ARCH_CHIP_LM3S6965
+	---help---
+		Stellaris LM3S6965 Evaluation Kit.  This board is based on the 
+		an ARM Cortex-M3 MCU, the Luminary/TI LM3S6965. This OS is built with the
+		arm-elf toolchain*.  STATUS:  This port is complete and mature.
+
+config ARCH_BOARD_LM3S8962EK
+	bool "Stellaris LMS38962 Evaluation Kit"
+	depends on ARCH_CHIP_LM3S8962
+	---help---
+		Stellaris LMS38962 Evaluation Kit.
+
+config ARCH_BOARD_LPCXPRESSO
+	bool "NXP LPCExpresso LPC1768"
+	depends on ARCH_CHIP_LPC1768
+	---help---
+		Embedded Artists base board with NXP LPCExpresso LPC1768.  This board
+		is based on the NXP LPC1768.  The Code Red toolchain is used by default.
+
+config ARCH_BOARD_LPC4330_XPLORER
+	bool "NXG LPC4330-Xplorer"
+	depends on ARCH_CHIP_LPC4330FET100
+	---help---
+		NXG Technologoies LPC4330 Xplorer board.  This board is based on the
+		LPC4330FET100.  The Code Red toolchain is used by default.
+
+config ARCH_BOARD_M68332EVB
+	bool "Motoroloa M68332EVB"
+	depends on ARCH_M68332
+	---help---
+		This is a work in progress for the venerable m68322evb board from
+		Motorola. This OS is also built with the arm-elf toolchain.  STATUS:
+		This port was never completed.
+
+config ARCH_BOARD_MBED
+	bool "mbed LCP1768"
+	depends on ARCH_CHIP_LPC1768
+	---help---
+		The configurations in this directory support the mbed board (http://mbed.org)
+		that features the NXP LPC1768 microcontroller. This OS is also built
+		with the arm-elf toolchain*.  STATUS:  Contributed.
+
+config ARCH_BOARD_MCU123
+	bool "mcu123.com LPC2148 Development Board"
+	depends on ARCH_CHIP_LPC2148
+	---help---
+		This port is for the NXP LPC2148 as provided on the mcu123.com
+		lpc214x development board. This OS is also built with the arm-elf
+		toolchain*.  The port supports serial, timer0, spi, and usb.
+
+config ARCH_BOARD_MICROPENDOUS
+	bool "Opendous Micropendous 3 board"
+	depends on ARCH_CHIP_AT90USB646 || ARCH_CHIP_AT90USB647 || ARCH_CHIP_AT90USB1286 || ARCH_CHIP_AT90USB1287
+	---help---
+		This is a port to the Opendous Micropendous 3 board. This board may
+		be populated with either an AVR AT90USB646, 647, 1286, or 1287 MCU.
+		Support is configured for the AT90USB647.
+
+config ARCH_BOARD_MX1ADS
+	bool "Motorola MX1ADS development board"
+	depends on ARCH_CHIP_IMX1
+	---help---
+		This is a port to the Motorola MX1ADS development board.  That board
+		is based on the Freescale i.MX1 processor.  The i.MX1 is an ARM920T.
+		STATUS:  This port is nearly code complete but was never fully
+		integrated due to tool-related issues.
+
+config ARCH_BOARD_NE64BADGE
+	bool "FEG NE64 /PoE Badge board"
+	depends on ARCH_CHIP_MCS92S12NEC64
+	---help---
+		Future Electronics Group NE64 /PoE Badge board based on the
+		MC9S12NE64 hcs12 cpu.  This port uses the m9s12x GCC toolchain.
+		STATUS:  Under development.  The port is code-complete but has
+		not yet been fully tested.
+
+config ARCH_BOARD_NTOSD_DM320
+	bool "Neuros OSD v1.0 Dev Board"
+	depends on ARCH_CHIP_DM320
+	---help---
+		This port uses the Neuros OSD v1.0 Dev Board with a GNU arm-elf
+		toolchain*: see
+
+			http://wiki.neurostechnology.com/index.php/OSD_1.0_Developer_Home
+ 
+		There are some differences between the Dev Board and the currently
+		available commercial v1.0 Boards.  See
+
+			http://wiki.neurostechnology.com/index.php/OSD_Developer_Board_v1
+
+		NuttX operates on the ARM9EJS of this dual core processor.
+		STATUS: This port is code complete, verified, and included in the
+		NuttX 0.2.1 release.
+
+config  ARCH_BOARD_NUCLEUS2G
+	bool "Nucleus 2G board"
+	depends on ARCH_CHIP_LPC1768
+	---help---
+		This port uses the Nucleus 2G board (with Babel CAN board).  This board
+		features an NXP LPC1768 processor.  See the 2G website (http://www.2g-eng.com/)
+		for more information about the Nucleus 2G.
+
+config ARCH_BOARD_LPC1766STK
+	bool "Olimex LPC1766-STK board"
+	depends on ARCH_CHIP_LPC1766
+	---help---
+		This port uses the Olimex LPC1766-STK board and a GNU GCC toolchain* under
+		Linux or Cygwin.  STATUS: Complete and mature.
+
+config ARCH_BOARD_MIRTOO
+	bool "Mirtoo PIC32 Module from Dimitech"
+	depends on ARCH_CHIP_PIC32MX250F128D
+	---help---
+		This is the port to the DTX1-4000L "Mirtoo" module.  This module uses MicroChip
+		PIC32MX250F128D.  See http://www.dimitech.com/ for further information.
+
+config ARCH_BOARD_OLIMEXLPC2378
+	bool "Olimex-lpc2378 board"
+	depends on ARCH_CHIP_LPC2378
+	---help---
+		This port uses the Olimex-lpc2378 board and a GNU arm-elf toolchain* under
+		Linux or Cygwin.  STATUS: ostest and NSH configurations available.
+		This port for the NXP LPC2378 was contributed by Rommel Marcelo.
+
+config ARCH_BOARD_OLIMEX_STRP711
+	bool "Olimex STR-P711 board"
+	depends on ARCH_CHIP_STR71X
+	---help---
+		This port uses the Olimex STR-P711 board and a GNU arm-elf toolchain* under
+		Linux or Cygwin. See the http://www.olimex.com/dev/str-p711.html" for
+		further information.  STATUS: Configurations for the basic OS test and NSH
+		are complete and verified.
+
+config ARCH_BOARD_PCBLOGICPIC32MX
+	bool "PIC32MX board from PCB Logic Design Co"
+	depends on ARCH_CHIP_PIC32MX460F512L
+	---help---
+		This is the port of NuttX to the PIC32MX board from PCB Logic Design Co.
+		This board features the MicroChip PIC32MX460F512L.
+		The board is a very simple -- little more than a carrier for the PIC32
+		MCU plus voltage regulation, debug interface, and an OTG connector.
+		STATUS:  Code complete but testing has been stalled due to tool related problems
+		(PICkit 2 does not work with the PIC32).
+
+config ARCH_BOARD_PIC32_STARTERKIT
+	bool "Microchip PIC32 Ethernet Starter Kit (DM320004)"
+	depends on ARCH_CHIP_PIC32MX795F512L
+	---help---
+		This is the port of NuttX to the Microchip PIC32 Ethernet Starter Kit
+		(DM320004) with the Multimedia Expansion Board (MEB, DM320005).
+		See www.microchip.com for further information.
+
+config ARCH_BOARD_PIC32_PIC32MX7MMB
+	bool "Mikroelektronika PIC32MX7 MMB"
+	depends on ARCH_CHIP_PIC32MX795F512L
+	---help---
+		This is the port NuttX to the Mikroelektronika PIC32MX7 Multimedia Board
+		(MMB).  See http://www.mikroe.com/ for further information.
+
+config ARCH_BOARD_PJRC_87C52
+	bool "PJRC 87C52 development system"
+	depends on ARCH_CHIP_8052
+	---help---
+		8051 Microcontroller.  This port uses the PJRC 87C52 development system
+		and the SDCC toolchain.   This port is not quite ready for prime time.
+
+config ARCH_BOARD_QEMU_I486
+	bool "Qemu i486 Mode"
+	depends on ARCH_QEMU
+	---help---
+		Port of NuttX to QEMU in i486 mode.  This port will also run on real i486
+		hardwared (Google the Bifferboard).
+
+config ARCH_BOARD_RGMP
+	bool "RGMP"
+	depends on ARCH_RGMP
+	---help---
+		RGMP stands for RTOS and GPOS on Multi-Processor.  RGMP is a project for 
+		running GPOS and RTOS simultaneously on multi-processor platforms. You can
+		port your favorite RTOS to RGMP together with an unmodified Linux to form a
+		hybrid operating system. This makes your application able to use both RTOS
+		and GPOS features.
+
+		See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further information
+		about RGMP.
+
+config ARCH_BOARD_SAM3UEK
+	bool "Atmel SAM3U-EK development board"
+	depends on ARCH_CHIP_AT91SAM3U4E
+	---help---
+		The port of NuttX to the Atmel SAM3U-EK development board.
+
+config ARCH_BOARD_SKP16C26
+	bool "Renesas SKP16C26 StarterKit"
+	depends on ARCH_CHIP_M30262F8
+	---help---
+		Renesas M16C processor on the Renesas SKP16C26 StarterKit.  This port
+		uses the GNU m32c toolchain.  STATUS:  The port is complete but untested
+		due to issues with compiler internal errors.
+
+config ARCH_BOARD_STM3210E_EVAL
+	bool "STMicro STM3210E-EVAL development board"
+	depends on ARCH_CHIP_STM32F103ZET6
+	---help---
+		STMicro STM3210E-EVAL development board based on the STMicro STM32F103ZET6
+		microcontroller (ARM Cortex-M3).  This port uses the GNU Cortex-M3
+		toolchain.
+
+config ARCH_BOARD_STM3220G_EVAL
+	bool "STMicro STM3220G-EVAL development board"
+	depends on ARCH_CHIP_STM32F207IG
+	---help---
+		STMicro STM3220G-EVAL development board based on the STMicro STM32F407IG
+		microcontroller (ARM Cortex-M3).
+
+config ARCH_BOARD_STM3240G_EVAL
+	bool "STMicro STM3240G-EVAL development board"
+	depends on ARCH_CHIP_STM32F407IG
+	---help---
+		STMicro STM3240G-EVAL development board based on the STMicro STM32F103ZET6
+		microcontroller (ARM Cortex-M4 with FPU).  This port uses a GNU Cortex-M4
+		toolchain (such as CodeSourcery).
+
+config ARCH_BOARD_STM32F4_DISCOVERY
+	bool "STMicro STM32F4-Discovery board"
+	depends on ARCH_CHIP_STM32F407VG
+	---help---
+		STMicro STM32F4-Discovery board boased on the STMIcro STM32F407VGT6 MCU.
+
+config ARCH_BOARD_SUREPIC32MX
+	bool "Sure PIC32MX boards"
+	depends on ARCH_CHIP_PIC32MX440F512H
+	---help---
+		The "Advanced USB Storage Demo Board," Model DB-DP11215, from Sure
+		Electronics (http://www.sureelectronics.net/).  This board features
+		the MicroChip PIC32MX440F512H.  See also
+		http://www.sureelectronics.net/goods.php?id=1168 for further
+		information about the Sure DB-DP11215 board.
+
+config ARCH_BOARD_TEENSY
+	bool "PJRC Teensy++ 2.0 board"
+	depends on ARCH_CHIP_AT90USB1286
+	---help---
+		This is the port of NuttX to the PJRC Teensy++ 2.0 board.  This board is
+		developed by http://pjrc.com/teensy/.  The Teensy++ 2.0 is based
+		on an Atmel AT90USB1286 MCU.
+
+config ARCH_BOARD_TWR_K60N512
+	bool "FreeScale TWR-K60N512d evelopment board"
+	depends on ARCH_CHIP_MK60N512VMD100
+	---help---
+		Kinetis K60 Cortex-M4 MCU.  This port uses the FreeScale TWR-K60N512
+		development board.
+
+config ARCH_BOARD_UBW32
+	bool "UBW32 v2.4 board from Sparkfun"
+	depends on ARCH_CHIP_PIC32MX460F512L
+	---help---
+		This is the port to the Sparkfun UBW32 board.  This port uses the original v2.4
+		board which is based on the MicroChip PIC32MX460F512L.  See
+		http://www.sparkfun.com/products/8971.  This older version has been replaced
+		with this board http://www.sparkfun.com/products/9713. See also
+		http://www.schmalzhaus.com/UBW32/.
+
+config ARCH_BOARD_US7032EVB1
+	bool "Hitachi SH-1/US7032EVB1 board"
+	depends on ARCH_CHIP_SH7032
+	---help---
+		This is a port of the Hitachi SH-1 on the Hitachi SH-1/US7032EVB1 board.
+		STATUS:  Work has just began on this port.
+
+config ARCH_BOARD_VSN
+	bool "SOTEL NetClamps VSN sensor network platform"
+	depends on ARCH_CHIP_STM32F103RET6
+	---help---
+		ISOTEL NetClamps VSN V1.2 ready2go sensor network platform based on the
+		STMicro STM32F103RET6.  Contributed by Uros Platise.  See
+		http://isotel.eu/NetClamps/
+
+config ARCH_BOARD_XTRS
+	bool "XTRS TRS80 Model 3 emulation"
+	depends on ARCH_CHIP_Z80
+	---help---
+		TRS80 Model 3.  This port uses a vintage computer based on the Z80.
+		An emulator for this computer is available to run TRS80 programs on a 
+		linux platform (http://www.tim-mann.org/xtrs.html).
+
+config ARCH_BOARD_Z16F2800100ZCOG
+	bool "Zilog Z16F2800100ZCOG Development Kit"
+	depends on ARCH_CHIP_Z16F281
+	---help---
+		z16f Microcontroller.  This port use the ZiLIG z16f2800100zcog
+		development kit and the Zilog ZDS-II Windows command line tools.  The
+		development environment is Cygwin under WinXP.
+
+config ARCH_BOARD_Z80SIM
+	bool "Z80 Instruction Set Simulator"
+	depends on ARCH_CHIP_Z80
+	---help---
+		z80 Microcontroller.  This port uses a Z80 instruction set simulator.
+		That simulator can be found in the NuttX SVN at
+		http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/misc/sims/z80sim.
+		This port also uses the SDCC toolchain (http://sdcc.sourceforge.net/")
+		(verified with version 2.6.0).
+
+config ARCH_BOARD_Z8ENCORE000ZCO
+	bool "ZiLOG z8encore000zco Development Kit"
+	depends on ARCH_CHIP_Z8F6403
+	---help---
+		z8Encore! Microcontroller.  This port use the ZiLOG z8encore000zco
+		development kit, Z8F6403 part, and the Zilog ZDS-II Windows command line
+		tools.  The development environment is Cygwin under WinXP.
+
+config ARCH_BOARD_Z8F64200100KI
+	bool "ZiLOG Z8F64200100KIT Development Kit"
+	depends on ARCH_CHIP_Z8F642X
+	---help---
+		z8Encore! Microcontroller.  This port use the Zilog z8f64200100kit
+		development kit, Z8F6423 part, and the Zilog ZDS-II Windows command line
+		tools.  The development environment is Cygwin under WinXP.
+
+config ARCH_BOARD_SIM
+	bool "User mode simulation"
+	depends on ARCH_SIM
+	---help---
+		A user-mode port of NuttX to the x86 Linux/Cygwin platform is available.
+		The purpose of this port is primarily to support OS feature development.
+		This port does not support interrupts or a real timer (and hence no
+		round robin scheduler)  Otherwise, it is complete.
+
+config ARCH_BOARD_CUSTOM
+	bool "Custom development board"
+	---help---
+		Select this option if there is no directory for the board under configs/.
+
+		Don't see the board you want?  You must first select the exact MCU part
+		number, then the boards supporting that part will be available for selection.
+
+endchoice
+
+config ARCH_BOARD
+	string
+	default "amber"              if ARCH_BOARD_AMBER
+	default "avr32dev1"          if ARCH_BOARD_AVR32DEV1
+	default "c5471evm"           if ARCH_BOARD_C5471EVM
+	default "compal_e88"         if ARCH_BOARD_COMPALE88
+	default "compal_e99"         if ARCH_BOARD_COMPALE99
+	default "demo9s12ne64"       if ARCH_BOARD_DEMOS92S12NEC64
+	default "ea3131"             if ARCH_BOARD_EA3131
+	default "ea3152"             if ARCH_BOARD_EA3152
+	default "eagle100"           if ARCH_BOARD_EAGLE100
+	default "ekk-lm3s9b96"       if ARCH_BOARD_EKK_LM3S9B96
+	default "ez80f0910200kitg"   if ARCH_BOARD_EZ80F910200KITG
+	default "ez80f0910200zco"    if ARCH_BOARD_EZ80F910200ZCO
+	default "hymini-stm32v"      if ARCH_BOARD_HYMINI_STM32V
+	default "kwikstik-k40"       if ARCH_BOARD_KWIKSTIK_K40
+	default "lincoln60"          if ARCH_BOARD_LINCOLN60
+	default "lm3s6432-s2e"       if ARCH_BOARD_LM3S6432S2E
+	default "lm3s6965-ek"        if ARCH_BOARD_LM3S6965EK
+	default "lm3s8962-ek"        if ARCH_BOARD_LM3S8962EK
+	default "lpc4330-xplorer"    if ARCH_BOARD_LPC4330_XPLORER
+	default "lpcxpresso-lpc1768" if ARCH_BOARD_LPCXPRESSO
+	default "m68322evb"          if ARCH_BOARD_M68332EVB
+	default "mbed"               if ARCH_BOARD_MBED
+	default "mcu123-lpc214x"     if ARCH_BOARD_MCU123
+	default "micropendous3"      if ARCH_BOARD_MICROPENDOUS
+	default "mirtoo"             if ARCH_BOARD_MIRTOO
+	default "mx1ads"             if ARCH_BOARD_MX1ADS
+	default "ne64badge"          if ARCH_BOARD_NE64BADGE
+	default "ntosd-dm320"        if ARCH_BOARD_NTOSD_DM320
+	default "nucleus2g"          if ARCH_BOARD_NUCLEUS2G
+	default "olimex-lpc1766stk"  if ARCH_BOARD_LPC1766STK
+	default "olimex-lpc2378"     if ARCH_BOARD_OLIMEXLPC2378
+	default "olimex-strp711"     if ARCH_BOARD_OLIMEX_STRP711
+	default "pcblogic-pic32mx"   if ARCH_BOARD_PCBLOGICPIC32MX
+	default "pic32-starterkit"   if ARCH_BOARD_PIC32_STARTERKIT
+	default "pic32mx7mmb"        if ARCH_BOARD_PIC32_PIC32MX7MMB
+	default "pjrc-8051"          if ARCH_BOARD_PJRC_87C52
+	default "qemu-i486"          if ARCH_BOARD_QEMU_I486
+	default "rgmp"               if ARCH_BOARD_RGMP
+	default "sam3u-ek"           if ARCH_BOARD_SAM3UEK
+	default "skp16c26"           if ARCH_BOARD_SKP16C26
+	default "stm3210e-eval"      if ARCH_BOARD_STM3210E_EVAL
+	default "stm3220g-eval"      if ARCH_BOARD_STM3220G_EVAL
+	default "stm3240g-eval"      if ARCH_BOARD_STM3240G_EVAL
+	default "stm32f4discovery"   if ARCH_BOARD_STM32F4_DISCOVERY
+	default "sure-pic32mx"       if ARCH_BOARD_SUREPIC32MX
+	default "teensy"             if ARCH_BOARD_TEENSY
+	default "twr-k60n512"        if ARCH_BOARD_TWR_K60N512
+	default "ubw32"              if ARCH_BOARD_UBW32
+	default "us7032evb1"         if ARCH_BOARD_US7032EVB1
+	default "vsn"                if ARCH_BOARD_VSN
+	default "xtrs"               if ARCH_BOARD_XTRS
+	default "z16f2800100zcog"    if ARCH_BOARD_Z16F2800100ZCOG
+	default "z80sim"             if ARCH_BOARD_Z80SIM
+	default "z8encore000zco"     if ARCH_BOARD_Z8ENCORE000ZCO
+	default "z8f64200100kit"     if ARCH_BOARD_Z8F64200100KI
+	default "sim"                if ARCH_BOARD_SIM
+	default ""                   if ARCH_BOARD_CUSTOM
+
+if ARCH_BOARD_AMBER
+source "configs/amber/Kconfig"
+endif
+if ARCH_BOARD_AVR32DEV1
+source "configs/avr32dev1/Kconfig"
+endif
+if ARCH_BOARD_C5471EVM
+source "configs/c5471evm/Kconfig"
+endif
+if ARCH_BOARD_COMPALE88
+source "configs/compal_e88/Kconfig"
+endif
+if ARCH_BOARD_COMPALE99
+source "configs/compal_e99/Kconfig"
+endif
+if ARCH_BOARD_DEMOS92S12NEC64
+source "configs/demo9s12ne64/Kconfig"
+endif
+if ARCH_BOARD_EA3131
+source "configs/ea3131/Kconfig"
+endif
+if ARCH_BOARD_EA3152
+source "configs/ea3152/Kconfig"
+endif
+if ARCH_BOARD_EAGLE100
+source "configs/eagle100/Kconfig"
+endif
+if ARCH_BOARD_EKK_LM3S9B96
+source "configs/ekk-lm3s9b96/Kconfig"
+endif
+if ARCH_BOARD_EZ80F910200KITG
+source "configs/ez80f910200kitg/Kconfig"
+endif
+if ARCH_BOARD_EZ80F910200ZCO
+source "configs/ez80f910200zco/Kconfig"
+endif
+if ARCH_BOARD_HYMINI_STM32V
+source "configs/hymini-stm32v/Kconfig"
+endif
+if ARCH_BOARD_KWIKSTIK_K40
+source "configs/kwikstik-k40/Kconfig"
+endif
+if ARCH_BOARD_LINCOLN60
+source "configs/lincoln60/Kconfig"
+endif
+if ARCH_BOARD_LM3S6432S2E
+source "configs/lm3s6432-s2e/Kconfig"
+endif
+if ARCH_BOARD_LM3S6965EK
+source "configs/lm3s6965-ek/Kconfig"
+endif
+if ARCH_BOARD_LM3S8962EK
+source "configs/lm3s8962-ek/Kconfig"
+endif
+if ARCH_BOARD_LPC4330_XPLORER
+source "configs/lpc4330-xplorer/Kconfig"
+endif
+if ARCH_BOARD_LPCXPRESSO
+source "configs/lpcxpresso-lpc1768/Kconfig"
+endif
+if ARCH_BOARD_M68332EVB
+source "configs/m68332evb/Kconfig"
+endif
+if ARCH_BOARD_MBED
+source "configs/mbed/Kconfig"
+endif
+if ARCH_BOARD_MCU123
+source "configs/mcu123-lpc214x/Kconfig"
+endif
+if ARCH_BOARD_MICROPENDOUS
+source "configs/micropendous3/Kconfig"
+endif
+if ARCH_BOARD_MIRTOO
+source "configs/mirtoo/Kconfig"
+endif
+if ARCH_BOARD_MX1ADS
+source "configs/mx1ads/Kconfig"
+endif
+if ARCH_BOARD_NE64BADGE
+source "configs/ne64badge/Kconfig"
+endif
+if ARCH_BOARD_NTOSD_DM320
+source "configs/ntosd-dm320/Kconfig"
+endif
+if ARCH_BOARD_NUCLEUS2G
+source "configs/nucleus2g/Kconfig"
+endif
+if ARCH_BOARD_LPC1766STK
+source "configs/olimex-lpc1766stk/Kconfig"
+endif
+if ARCH_BOARD_OLIMEXLPC2378
+source "configs/olimex-lpc2378/Kconfig"
+endif
+if ARCH_BOARD_OLIMEX_STRP711
+source "configs/olimex-strp711/Kconfig"
+endif
+if ARCH_BOARD_PCBLOGICPIC32MX
+source "configs/pcblogic-pic32mx/Kconfig"
+endif
+if ARCH_BOARD_PIC32_STARTERKIT
+source "configs/pic32-starterkit/Kconfig"
+endif
+if ARCH_BOARD_PIC32_PIC32MX7MMB
+source "configs/pic32mx7mmb/Kconfig"
+endif
+if ARCH_BOARD_PJRC_87C52
+source "configs/pjrc-8051/Kconfig"
+endif
+if ARCH_BOARD_QEMU_I486
+source "configs/qemu-i486/Kconfig"
+endif
+if ARCH_BOARD_RGMP
+source "configs/rgmp/Kconfig"
+endif
+if ARCH_BOARD_SAM3UEK
+source "configs/sam3u-ek/Kconfig"
+endif
+if ARCH_BOARD_SKP16C26
+source "configs/skp16c26/Kconfig"
+endif
+if ARCH_BOARD_STM3210E_EVAL
+source "configs/stm3210e-eval/Kconfig"
+endif
+if ARCH_BOARD_STM3220G_EVAL
+source "configs/stm3220g-eval/Kconfig"
+endif
+if ARCH_BOARD_STM3240G_EVAL
+source "configs/stm3240g-eval/Kconfig"
+endif
+if ARCH_BOARD_STM32F4_DISCOVERY
+source "configs/stm32f4discovery/Kconfig"
+endif
+if ARCH_BOARD_SUREPIC32MX
+source "configs/sure-pic32mx/Kconfig"
+endif
+if ARCH_BOARD_TEENSY
+source "configs/teensy/Kconfig"
+endif
+if ARCH_BOARD_TWR_K60N512
+source "configs/twr-k60n512/Kconfig"
+endif
+if ARCH_BOARD_UBW32
+source "configs/ubw32/Kconfig"
+endif
+if ARCH_BOARD_US7032EVB1
+source "configs/us7032evb1/Kconfig"
+endif
+if ARCH_BOARD_VSN
+source "configs/vsn/Kconfig"
+endif
+if ARCH_BOARD_XTRS
+source "configs/xtrs/Kconfig"
+endif
+if ARCH_BOARD_Z16F2800100ZCOG
+source "configs/z16f2800100zcog/Kconfig"
+endif
+if ARCH_BOARD_Z80SIM
+source "configs/z80sim/Kconfig"
+endif
+if ARCH_BOARD_Z8ENCORE000ZCO
+source "configs/z8encore000zco/Kconfig"
+endif
+if ARCH_BOARD_Z8F64200100KI
+source "configs/z8f64200100kit/Kconfig"
+endif
+if ARCH_BOARD_SIM
+source "configs/sim/Kconfig"
+endif
diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt
new file mode 100644
index 000000000..db341dfe3
--- /dev/null
+++ b/nuttx/configs/README.txt
@@ -0,0 +1,1774 @@
+Board-Specific Configurations
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Table of Contents
+^^^^^^^^^^^^^^^^^
+
+  o Board-Specific Configurations
+  o Summary of Files
+  o Supported Architectures
+  o Configuring NuttX
+
+Board-Specific Configurations
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The NuttX configuration consists of:
+
+o Processor architecture specific files.  These are the files contained
+  in the arch/<arch-name>/ directory.
+
+o Chip/SoC specific files.  Each processor processor architecture
+  is embedded in chip or System-on-a-Chip (SoC) architecture.  The
+  full chip architecture includes the processor architecture plus
+  chip-specific interrupt logic, general purpose I/O (GIO) logic, and
+  specialized, internal peripherals (such as UARTs, USB, etc.).
+
+  These chip-specific files are contained within chip-specific
+  sub-directories in the arch/<arch-name>/ directory and are selected
+  via the CONFIG_ARCH_name selection
+
+o Board specific files.  In order to be usable, the chip must be
+  contained in a board environment.  The board configuration defines
+  additional properties of the board including such things as
+  peripheral LEDs, external peripherals (such as network, USB, etc.).
+
+  These board-specific configuration files can be found in the
+  configs/<board-name>/ sub-directories and are discussed in this
+  README.  Additional configuration information maybe available in
+  board-specific configs/<board-name>/README.txt files.
+
+The configs/ subdirectory contains configuration data for each board.  These
+board-specific configurations plus the architecture-specific configurations in
+the arch/ subdirectory completely define a customized port of NuttX.
+
+Directory Structure
+^^^^^^^^^^^^^^^^^^^
+
+The configs directory contains board specific configurationlogic.  Each
+board must provide a subdirectory <board-name> under configs/ with the
+following characteristics:
+
+
+  <board-name>
+  |-- README.txt
+  |-- include/
+  |   `-- (board-specific header files)
+  |-- src/
+  |   |-- Makefile
+  |   `-- (board-specific source files)
+  |-- <config1-dir>
+  |   |-- Make.defs
+  |   |-- defconfig
+  |   |-- appconfig*
+  |   `-- setenv.sh
+  |-- <config2-dir>
+  |   |-- Make.defs
+  |   |-- defconfig
+  |   |-- appconfig*
+  |   `-- setenv.sh
+  ...
+
+  *optional
+
+Summary of Files
+^^^^^^^^^^^^^^^^
+
+README.txt -- This text file provides additional information unique to
+  each board configuration sub-directory.
+
+include/ -- This directory contains board specific header files.  This
+  directory will be linked as include/arch/board at configuration time and
+  can be included via '#include <arch/board/header.h>'.  These header file
+  can only be included by files in arch/<arch-name>include/ and
+  arch/<arch-name>/src
+
+src/ -- This directory contains board specific drivers.  This
+  directory will be linked as arch/<arch-name>/src/board at configuration
+  time and will be integrated into the build system.
+
+src/Makefile -- This makefile will be invoked to build the board specific
+  drivers.  It must support the following targets:  libext$(LIBEXT), clean,
+  and distclean.
+
+A board may have various different configurations using these common source
+files.  Each board configuration is described by three files:  Make.defs,
+defconfig, and setenv.sh.  Typically, each set of configuration files is
+retained in a separate configuration sub-directory (<config1-dir>,
+<config2-dir>, .. in the above diagram).
+
+Make.defs -- This makefile fragment provides architecture and
+  tool-specific build options.  It will be included by all other
+  makefiles in the build (once it is installed).  This make fragment
+  should define:
+
+    Tools: CC, LD, AR, NM, OBJCOPY, OBJDUMP
+    Tool options: CFLAGS, LDFLAGS
+    COMPILE, ASSEMBLE, ARCHIVE, CLEAN, and MKDEP macros
+
+  When this makefile fragment runs, it will be passed TOPDIR which
+  is the path to the root directory of the build.  This makefile
+  fragment may include ${TOPDIR}/.config to perform configuration
+  specific settings.  For example, the CFLAGS will most likely be
+  different if CONFIG_DEBUG=y.
+
+defconfig -- This is a configuration file similar to the Linux
+  configuration file.  In contains variable/value pairs like:
+
+  CONFIG_VARIABLE=value
+
+  This configuration file will be used at build time:
+
+    (1) as a makefile fragment included in other makefiles, and
+    (2) to generate include/nuttx/config.h which is included by
+        most C files in the system.
+
+  The following variables are recognized by the build (you may
+  also include architecture/board-specific settings).
+
+  Architecture selection:
+
+    CONFIG_ARCH - Identifies the arch/ subdirectory
+    CONFIG_ARCH_name - For use in C code
+    CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+    CONFIG_ARCH_CHIP_name - For use in C code
+    CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
+       hence, the board that supports the particular chip or SoC.
+    CONFIG_ARCH_BOARD_name - For use in C code
+    CONFIG_ENDIAN_BIG - define if big endian (default is little
+       endian)
+    CONFIG_ARCH_NOINTC - define if the architecture does not
+      support an interrupt controller or otherwise cannot support
+      APIs like up_enable_irq() and up_disable_irq().
+    CONFIG_ARCH_VECNOTIRQ - Usually the interrupt vector number provided
+      to interfaces like irq_attach() and irq_detach are the same as IRQ
+      numbers that are provied to IRQ management functions like
+      up_enable_irq() and up_disable_irq().  But that is not true for all
+      interrupt controller implementations.  For example, the PIC32MX
+      interrupt controller manages interrupt sources that have a many-to-one
+      relationship to interrupt vectors. In such cases, CONFIG_ARCH_VECNOTIRQ
+      must defined so that the OS logic will know not to assume it can use
+      a vector number to enable or disable interrupts.
+    CONFIG_ARCH_IRQPRIO
+      Define if the architecture suports prioritizaton of interrupts
+      and the up_prioritize_irq() API.
+
+  Some architectures require a description of the RAM configuration:
+
+    CONFIG_DRAM_SIZE - Describes the installed DRAM.
+    CONFIG_DRAM_START - The start address of DRAM (physical)
+    CONFIG_DRAM_VSTART - The start address of DRAM (virtual)
+
+  General build options:
+
+    CONFIG_RRLOAD_BINARY - make the rrload binary format used with
+      BSPs from www.ridgerun.com using the tools/mkimage.sh script.
+    CONFIG_INTELHEX_BINARY - make the Intel HEX binary format
+      used with many different loaders using the GNU objcopy program
+      Should not be selected if you are not using the GNU toolchain.
+    CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format
+      used with many different loaders using the GNU objcopy program
+      Should not be selected if you are not using the GNU toolchain.
+    CONFIG_RAW_BINARY - make a raw binary format file used with many
+      different loaders using the GNU objcopy program.  This option
+      should not be selected if you are not using the GNU toolchain.
+    CONFIG_HAVE_LIBM - toolchain supports libm.a
+    CONFIG_HAVE_CXX - toolchain supports C++ and CXX, CXXFLAGS, and
+      COMPILEXX have been defined in the configurations Make.defs
+      file.
+    CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support
+      for initialization of static C++ instances for this architecture
+      and for the selected toolchain (via up_cxxinitialize()).
+
+  Building application code:
+
+    CONFIG_APPS_DIR - Identifies the directory that builds the
+      application to link with NuttX.  Default: ../apps This symbol must be assigned
+      to the path to the application build directory *relative* to
+      the NuttX top build direcory. If you had an application
+      directory and the NuttX directory each in separate directory
+      trees like this:
+
+      build
+       |-nuttx
+       |  |
+       |  `- Makefile
+       `-application
+       |
+       `- Makefile
+
+      Then you would set CONFIG_APPS_DIR=../application.
+
+      The application direction must contain Makefile and this make
+      file must support the following targets:
+
+      - libapps$(LIBEXT) (usually libapps.a). libapps.a is a static
+      library ( an archive) that contains all of application object
+      files.
+      - clean. Do whatever is appropriate to clean the application
+      directories for a fresh build.
+      - distclean. Clean everthing -- auto-generated files, symbolic
+      links etc. -- so that the directory contents are the same as
+      the contents in your configuration management system.
+      This is only done when you change the NuttX configuration.
+      - depend. Make or update the application build dependencies.
+
+      When this application is invoked it will receive the setting TOPDIR like:
+
+      $(MAKE) -C $(CONFIG_APPS_DIR) TOPDIR="$(TOPDIR)" <target>
+
+      TOPDIR is the full path to the NuttX directory. It can be used, for
+      example, to include makefile fragments (e.g., .config or Make.defs)
+      or to set up include file paths.
+
+  Two-pass build options.  If the 2 pass build option is selected, then these
+  options configure the make system build a extra link object. This link object
+  is assumed to be an incremental (relative) link object, but could be a static
+  library (archive) (some modification to this Makefile would be required if
+  CONFIG_PASS1_TARGET generates an archive). Pass 1 1ncremental (relative) link
+  objects should be put into the processor-specific source directory (where other
+  link objects will be created).  If the pass1 obect is an archive, it could
+  go anywhere.
+
+    CONFIG_BUILD_2PASS - Enables the two pass build options.
+
+  When the two pass build option is enabled, the following also apply:
+
+    CONFIG_PASS1_TARGET - The name of the first pass build target.  This
+      can be specific build target, a special build target (all, default, etc.)
+      or may just be left undefined.
+    CONFIG_PASS1_BUILDIR - The path, relative to the top NuttX build
+      directory to directory that contains the Makefile to build the
+      first pass object.  The Makefile must support the following targets:
+      - The special target CONFIG_PASS1_TARGET (if defined)
+      - and the usual depend, clean, and distclean targets.
+    CONFIG_PASS1_OBJECT - May be used to include an extra, pass1 object
+      into the final link.  This would probably be the object generated
+      from the CONFIG_PASS1_TARGET.  It may be available at link time
+      in the arch/<architecture>/src directory.
+
+  General OS setup
+
+    CONFIG_DEBUG - enables built-in debug options
+    CONFIG_DEBUG_VERBOSE - enables verbose debug output
+    CCONFIG_DEBUG_ENABLE - Support an interface to enable or disable debug output.
+    CONFIG_DEBUG_SYMBOLS - build without optimization and with
+      debug symbols (needed for use with a debugger).
+    CONFIG_DEBUG_SCHED - enable OS debug output (disabled by
+      default)
+    CONFIG_DEBUG_MM - enable memory management debug output
+      (disabled by default)
+    CONFIG_DEBUG_NET - enable network debug output (disabled
+      by default)
+    CONFIG_DEBUG_USB - enable usb debug output (disabled by
+      default)
+    CONFIG_DEBUG_FS - enable filesystem debug output (disabled
+      by default)
+    CONFIG_DEBUG_LIB - enable C library debug output (disabled
+      by default)
+    CONFIG_DEBUG_BINFMT - enable binary loader debug output (disabled
+      by default)
+    CONFIG_DEBUG_GRAPHICS - enable NX graphics debug output
+      (disabled by default)
+    CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot
+      time console output
+    CONFIG_MM_REGIONS - If the architecture includes multiple
+      regions of memory to allocate from, this specifies the
+      number of memory regions that the memory manager must
+      handle and enables the API mm_addregion(start, end);
+    CONFIG_MM_SMALL - Each memory allocation has a small allocation
+      overhead.  The size of that overhead is normally determined by
+      the "width" of the address support by the MCU.  MCUs that support
+      16-bit addressability have smaller overhead than devices that
+      support 32-bit addressability.  However, there are many MCUs
+      that support 32-bit addressability *but* have internal SRAM
+      of size less than or equal to 64Kb.  In this case, CONFIG_MM_SMALL
+      can be defined so that those MCUs will also benefit from the
+      smaller, 16-bit-based allocation overhead.
+    CONFIG_MSEC_PER_TICK - The default system timer is 100Hz
+      or MSEC_PER_TICK=10.  This setting may be defined to
+      inform NuttX that the processor hardware is providing
+      system timer interrupts at some interrupt interval other
+      than 10 msec.
+    CONFIG_RR_INTERVAL - The round robin timeslice will be set
+      this number of milliseconds;  Round robin scheduling can
+      be disabled by setting this value to zero.
+    CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in 
+      scheduler to monitor system performance
+    CONFIG_TASK_NAME_SIZE - Specifies that maximum size of a
+      task name to save in the TCB.  Useful if scheduler
+      instrumentation is selected.  Set to zero to disable.
+    CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY -
+      Used to initialize the internal time logic.
+    CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions.
+      You would only need this if you are concerned about accurate
+      time conversions in the past or in the distant future.
+    CONFIG_JULIAN_TIME - Enables Julian time conversions. You
+      would only need this if you are concerned about accurate
+      time conversion in the distand past.  You must also define
+      CONFIG_GREGORIAN_TIME in order to use Julian time.
+    CONFIG_DEV_CONSOLE - Set if architecture-specific logic
+      provides /dev/console.  Enables stdout, stderr, stdin.
+      This implies the "normal" serial driver provides the
+      console unless another console device is specified
+      (See CONFIG_DEV_LOWCONSOLE).
+    CONFIG_MUTEX_TYPES - Set to enable support for recursive and
+      errorcheck mutexes.  Enables pthread_mutexattr_settype().
+    CONFIG_PRIORITY_INHERITANCE - Set to enable support for
+      priority inheritance on mutexes and semaphores.
+      Priority inheritance is a strategy for addressing priority
+      inversion.
+    CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority
+      inheritance is enabled.  It defines the maximum number of
+      different threads (minus one) that can take counts on a
+      semaphore with priority inheritance support.  This may be 
+      set to zero if priority inheritance is disabled OR if you
+      are only using semaphores as mutexes (only one holder) OR
+      if no more than two threads participate using a counting
+      semaphore.
+    CONFIG_SEM_NNESTPRIO.  If priority inheritance is enabled,
+      then this setting is the maximum number of higher priority
+      threads (minus 1) than can be waiting for another thread
+      to release a count on a semaphore.  This value may be set
+      to zero if no more than one thread is expected to wait for
+      a semaphore.
+    CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors
+      by task_create() when a new task is started.  If set, all
+        files/drivers will appear to be closed in the new task.
+    CONFIG_FDCLONE_STDIO. Disable cloning of all but the first
+      three file descriptors (stdin, stdout, stderr) by task_create()
+      when a new task is started. If set, all files/drivers will
+      appear to be closed in the new task except for stdin, stdout,
+      and stderr.
+    CONFIG_SDCLONE_DISABLE. Disable cloning of all socket
+      desciptors by task_create() when a new task is started. If
+      set, all sockets will appear to be closed in the new task.
+    CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
+      This format will support execution of NuttX binaries located
+      in a ROMFS filesystem (see examples/nxflat).
+    CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+      handle delayed processing from interrupt handlers.  This feature
+      is required for some drivers but, if there are not complaints,
+      can be safely disabled.  The worker thread also performs
+      garbage collection -- completing any delayed memory deallocations
+      from interrupt handlers.  If the worker thread is disabled,
+      then that clean will be performed by the IDLE thread instead
+      (which runs at the lowest of priority and may not be appropriate
+      if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+      is enabled, then the following options can also be used:
+    CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+      thread.  Default: 50
+    CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+      work in units of microseconds.  Default: 50*1000 (50 MS).
+    CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+      thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+    CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+      the worker thread.  Default: 4
+    CONFIG_SCHED_WAITPID - Enables the waitpid() API
+    CONFIG_SCHED_ATEXIT -  Enables the atexit() API
+    CONFIG_SCHED_ATEXIT_MAX -  By default if CONFIG_SCHED_ATEXIT is
+      selected, only a single atexit() function is supported. That number
+      can be increased by defined this setting to the number that you require.
+    CONFIG_SCHED_ONEXIT -  Enables the on_exit() API
+    CONFIG_SCHED_ONEXIT_MAX -  By default if CONFIG_SCHED_ONEXIT is selected,
+      only a single on_exit() function is supported. That number can be
+      increased by defined this setting to the number that you require.
+
+  System Logging:
+    CONFIG_SYSLOG enables general system logging support.
+    CONFIG_SYSLOG_DEVPATH - The full path to the system logging device.  Default
+      "/dev/ramlog" (RAMLOG) or "dev/ttyS1" (character device)
+
+    At present, there are two system loggins devices available. If CONFIG_SYSLOG
+    is selected, then these options are also available.
+
+    CONFIG_SYSLOG_CHAR - Enable the generic character device for the SYSLOG.
+      A disadvantage of using the generic character device for the SYSLOG is that
+      it cannot handle debug output generated from interrupt level handlers.
+      NOTE:  No more than one SYSLOG device should be configured.
+
+    CONFIG_RAMLOG - Enables the RAM logging feature. The RAM log is a circular
+      buffer in RAM. NOTE:  No more than one SYSLOG device should be configured.
+    CONFIG_RAMLOG_CONSOLE - Use the RAM logging device as a system console.
+      If this feature is enabled (along with CONFIG_DEV_CONSOLE), then all
+      console output will be re-directed to a circular buffer in RAM.  This
+      is useful, for example, if the only console is a Telnet console.  Then
+      in that case, console output from non-Telnet threads will go to the
+      circular buffer and can be viewed using the NSH 'dmesg' command.
+    CONFIG_RAMLOG_SYSLOG - Use the RAM logging device for the syslogging
+      interface.  If this feature is enabled (along with CONFIG_SYSLOG),
+      then all debug output (only) will be re-directed to the circular
+      buffer in RAM.  This RAM log can be view from NSH using the 'dmesg'
+      command.  NOTE:  Unlike the limited, generic character driver SYSLOG
+      device, the RAMLOG *can* be used to generate debug output from interrupt
+      level handlers.
+    CONFIG_RAMLOG_NPOLLWAITERS - The number of threads than can be waiting
+     for this driver on poll().  Default: 4
+
+    If CONFIG_RAMLOG_CONSOLE or CONFIG_RAMLOG_SYSLOG is selected, then the
+    following may also be provided:
+
+    CONFIG_RAMLOG_CONSOLE_BUFSIZE - Size of the console RAM log.  Default: 1024
+
+  Kernel build options:
+    CONFIG_NUTTX_KERNEL - Builds NuttX as a separately compiled kernel.
+    CONFIG_SYS_RESERVED - Reserved system call values for use
+      by architecture-specific logic.
+
+  OS setup related to on-demand paging:
+
+    CONFIG_PAGING - If set =y in your configation file, this setting will
+      enable the on-demand paging feature as described in
+      http://www.nuttx.org/NuttXDemandPaging.html.
+
+  If CONFIG_PAGING is selected, then you will probabaly need CONFIG_BUILD_2PASS to
+  correctly position the code and the following configuration options also apply:
+
+    CONFIG_PAGING_PAGESIZE - The size of one managed page.  This must
+      be a value supported by the processor's memory management unit.
+    CONFIG_PAGING_NLOCKED - This is the number of locked pages in the
+      memory map.  The locked address region will then be from
+      CONFIG_DRAM_VSTART through (CONFIG_DRAM_VSTART +
+      CONFIG_PAGING_PAGESIZE*CONFIG_PAGING_NLOCKED)
+    CONFIG_PAGING_LOCKED_PBASE and CONFIG_PAGING_LOCKED_VBASE - These
+      may be defined to determine the base address of the locked page
+      regions.  If neither are defined, the logic will be set the bases
+      to CONFIG_DRAM_START and CONFIG_DRAM_VSTART (i.e., it assumes
+      that the base address of the locked region is at the beginning
+      of RAM).
+      NOTE:  In some architectures, it may be necessary to take some
+      memory from the beginning of this region for vectors or for a
+      page table. In such cases, CONFIG_PAGING_LOCKED_P/VBASE should
+      take that into consideration to prevent overlapping the locked
+      memory region and the system data at the beginning of SRAM.
+    CONFIG_PAGING_NPPAGED - This is the number of physical pages
+      available to support the paged text region.  This paged region
+      begins at (CONFIG_PAGING_LOCKED_PBASE + CONFIG_PAGING_PAGESIZE*CONFIG_PAGING_NPPAGED)
+      and continues until (CONFIG_PAGING_LOCKED_PBASE + CONFIG_PAGING_PAGESIZE*(CONFIG_PAGING_NLOCKED +
+      CONFIG_PAGING_NPPAGED)
+    CONFIG_PAGING_NVPAGED - This actual size of the paged text region
+      (in pages).  This is also the number of virtual pages required to
+      support the entire paged region. The on-demand paging feature is
+      intended to support only the case where the virtual paged text
+      area is much larger the available physical pages.  Otherwise, why
+      would you enable on-demand paging?
+    CONFIG_PAGING_NDATA - This is the number of data pages in the memory
+      map.  The data region will extend to the end of RAM unless overridden
+      by a setting in the configuration file.
+      NOTE:  In some architectures, it may be necessary to take some memory
+      from the end of RAM for page tables or other system usage.  The
+      configuration settings and linker directives must be cognizant of that:
+      CONFIG_PAGING_NDATA should be defined to prevent the data region from
+      extending all the way to the end of memory. 
+    CONFIG_PAGING_DEFPRIO - The default, minimum priority of the page fill
+      worker thread.  The priority of the page fill work thread will be boosted
+      boosted dynmically so that it matches the priority of the task on behalf
+      of which it peforms the fill.  This defines the minimum priority that
+      will be used. Default: 50.
+    CONFIG_PAGING_STACKSIZE - Defines the size of the allocated stack
+      for the page fill worker thread. Default: 1024.
+    CONFIG_PAGING_BLOCKINGFILL - The architecture specific up_fillpage()
+      function may be blocking or non-blocking.  If defined, this setting
+      indicates that the up_fillpage() implementation will block until the
+      transfer is completed. Default:  Undefined (non-blocking).
+    CONFIG_PAGING_WORKPERIOD - The page fill worker thread will wake periodically
+      even if there is no mapping to do.  This selection controls that wake-up
+      period (in microseconds).  This wake-up a failsafe that will handle any 
+      cases where a single is lost (that would really be a bug and shouldn't
+      happen!) and also supports timeouts for case of non-blocking, asynchronous
+      fills (see CONFIG_PAGING_TIMEOUT_TICKS).
+    CONFIG_PAGING_TIMEOUT_TICKS - If defined, the implementation will monitor
+      the (asynchronous) page fill logic.  If the fill takes longer than this
+      number if microseconds, then a fatal error will be declared.
+      Default: No timeouts monitored.
+
+    Some architecture-specific settings.  Defaults are architecture specific.
+    If you don't know what you are doing, it is best to leave these undefined
+    and try the system defaults:
+ 
+    CONFIG_PAGING_VECPPAGE - This the physical address of the page in
+      memory to be mapped to the vector address.
+    CONFIG_PAGING_VECL2PADDR - This is the physical address of the L2
+      page table entry to use for the vector mapping.
+    CONFIG_PAGING_VECL2VADDR - This is the virtual address of the L2
+      page table entry to use for the vector mapping.
+    CONFIG_PAGING_BINPATH - If CONFIG_PAGING_BINPATH is defined, then it
+      is the full path to a file on a mounted file system that contains
+      a binary image of the NuttX executable.  Pages will be filled by
+      reading from offsets into this file that correspond to virtual
+      fault addresses.
+    CONFIG_PAGING_MOUNTPT - If CONFIG_PAGING_BINPATH is defined, additional
+      options may be provided to control the initialization of underlying
+      devices. CONFIG_PAGING_MOUNTPT identifies the mountpoint to be used
+      if a device is mounted.
+    CONFIG_PAGING_MINOR - Some mount operations require a "minor" number
+      to identify the specific device instance. Default: 0
+    CONFIG_PAGING_SDSLOT - If CONFIG_PAGING_BINPATH is defined, additional
+      options may be provided to control the initialization of underlying
+      devices. CONFIG_PAGING_SDSLOT identifies the slot number of the SD
+      device to initialize. This must be undefined if SD is not being used.
+      This should be defined to be zero for the typical device that has
+      only a single slot (See CONFIG_MMCSD_NSLOTS). If defined, 
+      CONFIG_PAGING_SDSLOT will instruct certain board-specific logic to
+      initialize the media in this SD slot.
+    CONFIG_PAGING_M25PX - Use the m25px.c FLASH driver.  If this is selected,
+      then the MTD interface to the M25Px device will be used to support
+      paging.
+    CONFIG_PAGING_AT45DB - Use the at45db.c FLASH driver.  If this is selected,
+      then the MTD interface to the Atmel AT45DB device will be used to support
+      paging.
+    CONFIG_PAGING_BINOFFSET - If CONFIG_PAGING_M25PX or is CONFIG_PAGING_AT45DB
+      defined then CONFIG_PAGING_BINOFFSET will be used to specify the offset
+      in bytes into the FLASH device where the NuttX binary image is located.
+      Default: 0
+    CONFIG_PAGING_SPIPORT - If CONFIG_PAGING_M25PX CONFIG_PAGING_AT45DB is
+       defined and the device has multiple SPI busses (ports), then this
+      configuration should be set to indicate which SPI port the device is
+      connected. Default: 0
+
+  The following can be used to disable categories of APIs supported
+  by the OS.  If the compiler supports weak functions, then it
+  should not be necessary to disable functions unless you want to
+  restrict usage of those APIs.
+
+  There are certain dependency relationships in these features.
+
+    o mq_notify logic depends on signals to awaken tasks
+      waiting for queues to become full or empty.
+    o pthread_condtimedwait() depends on signals to wake
+      up waiting tasks.
+
+    CONFIG_DISABLE_CLOCK, CONFIG_DISABLE_POSIX_TIMERS, CONFIG_DISABLE_PTHREAD.
+    CONFIG_DISABLE_SIGNALS, CONFIG_DISABLE_MQUEUE, CONFIG_DISABLE_MOUNTPOUNT,
+    CONFIG_DISABLE_ENVIRON, CONFIG_DISABLE_POLL
+
+  Misc libc settings
+
+    CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a
+       little smaller if we do not support fieldwidthes
+    CONFIG_LIBC_FLOATINGPOINT - By default, floating point
+      support in printf, sscanf, etc. is disabled.
+
+  Allow for architecture optimized implementations
+
+    The architecture can provide optimized versions of the
+    following to improve system performance
+
+      CONFIG_ARCH_MEMCPY, CONFIG_ARCH_MEMCMP, CONFIG_ARCH_MEMMOVE
+      CONFIG_ARCH_MEMSET, CONFIG_ARCH_STRCMP, CONFIG_ARCH_STRCPY
+      CONFIG_ARCH_STRNCPY, CONFIG_ARCH_STRLEN, CONFIG_ARCH_STRNLEN
+      CONFIG_ARCH_BZERO
+
+  The architecture may provide custom versions of certain standard header
+  files:
+
+    CONFIG_ARCH_STDBOOL_H - The stdbool.h header file can be found at
+      nuttx/include/stdbool.h. However, that header includes logic to redirect
+      the inclusion of an architecture specific header file like:
+
+        #ifdef CONFIG_ARCH_STDBOOL_H
+        #  include <arch/stdbool.h>
+        #else
+        ...
+        #endif
+
+      Recall that that include path, include/arch, is a symbolic link and
+      will refer to a version of stdbool.h at nuttx/arch/<architecture>/include/stdbool.h.
+
+    CONFIG_ARCH_STDINT_H - Similar logic exists for the stdint.h header
+      file can also be found at nuttx/include/stdint.h.
+
+        #ifdef CONFIG_ARCH_STDBOOL_H
+        #  include <arch/stdinit.h>
+        #else
+        ...
+        #endif
+
+    CONFIG_ARCH_MATH_H - There is also a re-directing version of math.h in
+      the source tree. However, it resides out-of-the-way at include/nuttx/math.h
+      because it conflicts too often with the system math.h. If CONFIG_ARCH_MATH_H=y
+      is  defined, however, the top-level makefile will copy the redirecting
+      math.h header file from include/nuttx/math.h to include/math.h. math.h
+      will then include the architecture-specific version of math.h that you
+      must provide at nuttx/arch/>architecture</include/math.h.
+
+        #ifdef CONFIG_ARCH_MATH_H
+        #  include <arch/math.h>
+        #endif
+
+      So for the architectures that define CONFIG_ARCH_MATH_H=y, include/math.h
+      will be the redirecting math.h header file; for the architectures that
+      don't select CONFIG_ARCH_MATH_H, the redirecting math.h header file will
+      stay out-of-the-way in include/nuttx/.
+
+    CONFIG_ARCH_STDARG_H - There is also a redirecting version of stdarg.h in
+      the source tree as well. It also resides out-of-the-way at include/nuttx/stdarg.h.
+      This is because you should normally use your toolchain's stdarg.h file. But
+      sometimes, your toolchain's stdarg.h file may have other header file
+      dependencies and so may not be usable in the NuttX build environment. In
+      those cases, you may have to create a architecture-specific stdarg.h header
+      file at nuttx/arch/>architecture</include/stdarg.h
+
+      If CONFIG_ARCH_STDARG_H=y is defined, the top-level makefile will copy the
+      re-directing stdarg.h header file from include/nuttx/stdarg.h to
+      include/stdarg.h. So for the architectures that cannot use their toolchain's
+      stdarg.h file, they can use this alternative by defining CONFIG_ARCH_STDARG_H=y
+      and providing. If CONFIG_ARCH_STDARG_H, is not defined, then the stdarg.h
+      header file will stay out-of-the-way in include/nuttx/.
+
+    CONFIG_ARCH_ROMGETC - In Harvard architectures, data accesses and
+      instruction accesses occur on different busses, perhaps
+      concurrently.  All data accesses are performed on the data bus
+      unless special machine instructions are used to read data
+      from the instruction address space.  Also, in the typical
+      MCU, the available SRAM data memory is much smaller that the
+      non-volatile FLASH instruction memory.  So if the application
+      requires many constant strings, the only practical solution may
+      be to store those constant strings in FLASH memory where they
+      can only be accessed using architecture-specific machine
+      instructions.
+
+      If CONFIG_ARCH_ROMGETC is defined, then the architecture logic
+      must export the function up_romgetc().  up_romgetc() will simply
+      read one byte of data from the instruction space.
+ 
+      If CONFIG_ARCH_ROMGETC, certain C stdio functions are effected:
+      (1) All format strings in printf, fprintf, sprintf, etc. are
+      assumed to lie in FLASH (string arguments for %s are still assumed
+      to reside in SRAM). And (2), the string argument to puts and fputs
+      is assumed to reside in FLASH.  Clearly, these assumptions may have
+      to modified for the particular needs of your environment.  There
+      is no "one-size-fits-all" solution for this problem.
+
+  Sizes of configurable things (0 disables)
+
+    CONFIG_MAX_TASKS - The maximum number of simultaneously
+      active tasks.  This value must be a power of two.
+    CONFIG_NPTHREAD_KEYS - The number of items of thread-
+      specific data that can be retained
+    CONFIG_NFILE_DESCRIPTORS - The maximum number of file
+      descriptors (one for each open)
+    CONFIG_NFILE_STREAMS - The maximum number of streams that
+      can be fopen'ed
+    CONFIG_NAME_MAX - Maximum number of bytes in a filename (not including
+      terminating null).  Default: 32
+    CONFIG_PATH_MAX - Maximum number of bytes in a pathname, including the
+      terminating null character.  Default: MIN(256,(4*CONFIG_NAME_MAX+1))
+    CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate
+      on fopen. (Only if CONFIG_NFILE_STREAMS > 0)
+    CONFIG_STDIO_LINEBUFFER - If standard C buffered I/O is enabled
+      (CONFIG_STDIO_BUFFER_SIZE > 0), then this option may be added
+      to force automatic, line-oriented flushing the output buffer
+      for putc(), fputc(), putchar(), puts(), fputs(), printf(),
+      fprintf(), and vfprintf().  When a newline is encountered in
+      the output string, the output buffer will be flushed.  This
+      (slightly) increases the NuttX footprint but supports the kind
+      of behavior that people expect for printf().
+    CONFIG_NUNGET_CHARS - Number of characters that can be
+      buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0)
+    CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message
+      structures.  The system manages a pool of preallocated
+      message structures to minimize dynamic allocations
+    CONFIG_PREALLOC_IGMPGROUPS - Pre-allocated IGMP groups are used
+      only if needed from interrupt level group created (by the IGMP server).
+      Default: 4.
+    CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with
+      a fixed payload size given by this settin (does not include
+      other message structure overhead.
+    CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog
+      structures.  The system manages a pool of preallocated
+      watchdog structures to minimize dynamic allocations
+    CONFIG_DEV_PIPE_SIZE - Size, in bytes, of the buffer to allocated
+      for pipe and FIFO support
+
+  Filesystem configuration
+
+    CONFIG_FS_FAT - Enable FAT filesystem support
+    CONFIG_FAT_SECTORSIZE - Max supported sector size
+    CONFIG_FAT_LCNAMES - Enable use of the NT-style upper/lower case 8.3
+      file name support.
+    CONFIG_FAT_LFN - Enable FAT long file names.  NOTE:  Microsoft claims
+      patents on FAT long file name technology.  Please read the
+      disclaimer in the top-level COPYING file and only enable this
+      feature if you understand these issues.
+    CONFIG_FAT_MAXFNAME - If CONFIG_FAT_LFN is defined, then the
+      default, maximum long file name is 255 bytes.  This can eat up
+      a lot of memory (especially stack space).  If you are willing
+      to live with some non-standard, short long file names, then
+      define this value.  A good choice would be the same value as
+      selected for CONFIG_NAME_MAX which will limit the visibility
+      of longer file names anyway.
+    CONFIG_FS_FATTIME: Support FAT date and time. NOTE:  There is not
+      much sense in supporting FAT date and time unless you have a
+      hardware RTC or other way to get the time and date.
+    CONFIG_FS_NXFFS: Enable NuttX FLASH file system (NXFF) support.
+    CONFIG_NXFFS_ERASEDSTATE: The erased state of FLASH. 
+      This must have one of the values of 0xff or 0x00.
+      Default: 0xff.
+    CONFIG_NXFFS_PACKTHRESHOLD: When packing flash file data,
+      don't both with file chunks smaller than this number of data bytes.
+      Default: 32.
+    CONFIG_NXFFS_MAXNAMLEN: The maximum size of an NXFFS file name.
+      Default: 255.
+    CONFIG_NXFFS_PACKTHRESHOLD: When packing flash file data,
+      don't both with file chunks smaller than this number of data bytes.
+      Default: 32.
+    CONFIG_NXFFS_TAILTHRESHOLD: clean-up can either mean
+      packing files together toward the end of the file or, if file are
+      deleted at the end of the file, clean up can simply mean erasing
+      the end of FLASH memory so that it can be re-used again.  However,
+      doing this can also harm the life of the FLASH part because it can
+      mean that the tail end of the FLASH is re-used too often. This
+      threshold determines if/when it is worth erased the tail end of FLASH
+      and making it available for re-use (and possible over-wear).
+      Default: 8192.
+    CONFIG_FS_ROMFS - Enable ROMFS filesystem support
+    CONFIG_NFS - Enable Network File System (NFS) client file system support.
+      Provided support is version 3 using UDP.  In addition to common
+      prerequisites for mount-able file systems in general, this option
+      requires UDP networking support; this would include CONFIG_NETand
+      CONFIG_NET_UDP at a minimum.
+    CONFIG_FS_RAMMAP - For file systems that do not support XIP, this
+      option will enable a limited form of memory mapping that is
+      implemented by copying whole files into memory.
+
+  RTC
+
+    CONFIG_RTC - Enables general support for a hardware RTC.  Specific
+      architectures may require other specific settings.
+    CONFIG_RTC_DATETIME - There are two general types of RTC:  (1) A simple
+      battery backed counter that keeps the time when power is down, and (2)
+       A full date / time RTC the provides the date and time information, often
+      in BCD format.  If CONFIG_RTC_DATETIME is selected, it specifies this
+      second kind of RTC. In this case, the RTC is used to "seed" the normal
+      NuttX timer and the NuttX system timer provides for higher resoution
+      time.
+    CONFIG_RTC_HIRES - If CONFIG_RTC_DATETIME not selected, then the simple,
+      battery backed counter is used.  There are two different implementations
+      of such simple counters based on the time resolution of the counter:
+      The typical RTC keeps time to resolution of 1 second, usually
+      supporting a 32-bit time_t value.  In this case, the RTC is used to
+      "seed" the normal NuttX timer and the NuttX timer provides for higher
+      resoution time. If CONFIG_RTC_HIRES is enabled in the NuttX configuration,
+      then the RTC provides higher resolution time and completely replaces the
+      system timer for purpose of date and time.
+    CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the frequency
+      of the high resolution RTC must be provided.  If CONFIG_RTC_HIRES is
+      not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
+    CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an
+      alarm.  A callback function will be executed when the alarm goes off
+
+  CAN driver
+
+    CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+      CONFIG_STM32_CAN2 must also be defined)
+    CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID.  Default
+      Standard 11-bit IDs.
+    CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+      Default: 8
+    CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+      Default: 4
+    CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+      mode for testing. If the driver does support loopback mode, the setting
+      will enable it. (If the driver does not, this setting will have no effect).
+
+  SPI driver
+
+    CONFIG_SPI_OWNBUS - Set if there is only one active device
+      on the SPI bus.  No locking or SPI configuration will be performed.
+      It is not necessary for clients to lock, re-configure, etc..
+    CONFIG_SPI_EXCHANGE - Driver supports a single exchange method
+      (vs a recvblock() and sndblock ()methods)
+
+  SPI-based MMC/SD driver
+
+    CONFIG_MMCSD_NSLOTS - Number of MMC/SD slots supported by the
+      driver. Default is one.
+    CONFIG_MMCSD_READONLY -  Provide read-only access.  Default is
+      Read/Write
+    CONFIG_MMCSD_SPICLOCK - Maximum SPI clock to drive MMC/SD card.
+      Default is 20MHz.
+
+  SDIO/SDHC driver:
+
+    CONFIG_SDIO_DMA - SDIO driver supports DMA
+    CONFIG_SDIO_MUXBUS - Set this SDIO interface if the SDIO interface
+      or hardware resources are shared with other drivers.
+    CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode.  Default:
+      4-bit transfer mode.
+    CONFIG_MMCSD_MULTIBLOCK_DISABLE - Use only the single block transfer method.
+      This setting is used to work around buggy SDIO drivers that cannot handle
+      multiple block transfers.
+
+  SDIO-based MMC/SD driver
+
+    CONFIG_FS_READAHEAD - Enable read-ahead buffering
+    CONFIG_FS_WRITEBUFFER - Enable write buffering
+    CONFIG_MMCSD_MMCSUPPORT - Enable support for MMC cards
+    CONFIG_MMCSD_HAVECARDDETECT - SDIO driver card detection is
+      100% accurate
+
+  RiT P14201 OLED driver
+
+    CONFIG_LCD_P14201 - Enable P14201 support
+    CONFIG_P14201_SPIMODE - Controls the SPI mode
+    CONFIG_P14201_FREQUENCY - Define to use a different bus frequency
+    CONFIG_P14201_NINTERFACES - Specifies the number of physical P14201
+      devices that will be supported.
+    CONFIG_P14201_FRAMEBUFFER - If defined, accesses will be performed
+      using an in-memory copy of the OLEDs GDDRAM.  This cost of this
+      buffer is 128 * 96 / 2 = 6Kb.  If this is defined, then the driver
+      will be fully functional. If not, then it will have the following
+      limitations:
+      - Reading graphics memory cannot be supported, and
+      - All pixel writes must be aligned to byte boundaries.
+      The latter limitation effectively reduces the 128x96 disply to 64x96.
+
+  Nokia 6100 Configuration Settings:
+
+    CONFIG_NOKIA6100_SPIMODE - Controls the SPI mode
+    CONFIG_NOKIA6100_FREQUENCY - Define to use a different bus frequency
+    CONFIG_NOKIA6100_NINTERFACES - Specifies the number of physical Nokia
+      6100 devices that will be supported.
+    CONFIG_NOKIA6100_BPP - Device supports 8, 12, and 16 bits per pixel.
+    CONFIG_NOKIA6100_S1D15G10 - Selects the Epson S1D15G10 display controller
+    CONFIG_NOKIA6100_PCF8833 - Selects the Phillips PCF8833 display controller
+    CONFIG_NOKIA6100_BLINIT - Initial backlight setting
+
+    The following may need to be tuned for your hardware:
+    CONFIG_NOKIA6100_INVERT - Display inversion, 0 or 1, Default: 1
+    CONFIG_NOKIA6100_MY - Display row direction, 0 or 1, Default: 0
+    CONFIG_NOKIA6100_MX - Display column direction, 0 or 1, Default: 1
+    CONFIG_NOKIA6100_V - Display address direction, 0 or 1, Default: 0
+    CONFIG_NOKIA6100_ML - Display scan direction, 0 or 1, Default: 0
+    CONFIG_NOKIA6100_RGBORD - Display RGB order, 0 or 1, Default: 0
+
+    Required LCD driver settings:
+    CONFIG_LCD_NOKIA6100 - Enable Nokia 6100 support
+    CONFIG_LCD_MAXCONTRAST - must be 63 with the Epson controller and 127 with
+      the Phillips controller.
+    CONFIG_LCD_MAXPOWER - Maximum value of backlight setting.  The backlight
+      control is managed outside of the 6100 driver so this value has no
+      meaning to the driver.  Board-specific logic may place restrictions on
+      this value.
+
+  Input Devices
+
+    CONFIG_INPUT
+      Enables general support for input devices
+ 
+    CONFIG_INPUT_TSC2007
+      If CONFIG_INPUT is selected, then this setting will enable building
+      of the TI TSC2007 touchscreen driver.
+    CONFIG_TSC2007_MULTIPLE
+      Normally only a single TI TSC2007 touchscreen is used.  But if
+      there are multiple TSC2007 touchscreens, this setting will enable
+      multiple touchscreens with the same driver.
+
+    CONFIG_INPUT_STMPE811
+      Enables support for the STMPE811 driver (Needs CONFIG_INPUT)
+    CONFIG_STMPE811_SPI
+      Enables support for the SPI interface (not currenly supported)
+    CONFIG_STMPE811_I2C
+      Enables support for the I2C interface
+    CONFIG_STMPE811_MULTIPLE 
+      Can be defined to support multiple STMPE811 devices on board.
+    CONFIG_STMPE811_ACTIVELOW
+      Interrupt is generated by an active low signal (or falling edge).
+    CONFIG_STMPE811_EDGE
+      Interrupt is generated on an edge (vs. on the active level)
+    CONFIG_STMPE811_NPOLLWAITERS
+      Maximum number of threads that can be waiting on poll() (ignored if 
+      CONFIG_DISABLE_POLL is set).
+    CONFIG_STMPE811_TSC_DISABLE
+      Disable driver touchscreen functionality.
+    CONFIG_STMPE811_ADC_DISABLE
+      Disable driver ADC functionality.
+    CONFIG_STMPE811_GPIO_DISABLE
+      Disable driver GPIO functionlaity.
+    CONFIG_STMPE811_GPIOINT_DISABLE
+      Disable driver GPIO interrupt functionality (ignored if GPIO
+      functionality is disabled).
+    CONFIG_STMPE811_SWAPXY
+      Reverse the meaning of X and Y to handle different LCD orientations.
+    CONFIG_STMPE811_TEMP_DISABLE
+      Disable driver temperature sensor functionality.
+    CONFIG_STMPE811_REGDEBUG
+      Enabled very low register-level debug output.  Requires CONFIG_DEBUG.
+    CONFIG_STMPE811_THRESHX and CONFIG_STMPE811_THRESHY
+      STMPE811 touchscreen data comes in a a very high rate.  New touch positions
+      will only be reported when the X or Y data changes by these thresholds.
+      This trades reduces data rate for some loss in dragging accuracy.  The
+      STMPE811 is configure for 12-bit values so the raw ranges are 0-4095. So
+      for example, if your display is 320x240, then THRESHX=13 and THRESHY=17
+      would correspond to one pixel.  Default: 12
+
+  Analog Devices
+
+    CONFIG_DAC
+      Enables general support for Digital-to-Analog conversion devices.
+    CONFIG_ADC
+      Enables general support for Analog-to-Digital conversion devices.
+    CONFIG_ADC_ADS125X
+      Adds support for the TI ADS 125x ADC.
+
+  ENC28J60 Ethernet Driver Configuration Settings:
+
+    CONFIG_NET_ENC28J60 - Enabled ENC28J60 support
+    CONFIG_ENC28J60_SPIMODE - Controls the SPI mode
+    CONFIG_ENC28J60_FREQUENCY - Define to use a different bus frequency
+    CONFIG_ENC28J60_NINTERFACES - Specifies the number of physical ENC28J60
+      devices that will be supported.
+    CONFIG_ENC28J60_STATS - Collect network statistics
+    CONFIG_ENC28J60_HALFDUPPLEX - Default is full duplex
+
+  Networking support via uIP
+
+    CONFIG_NET - Enable or disable all network features
+    CONFIG_NET_NOINTS --  CONFIG_NET_NOINT indicates that uIP not called from
+      the interrupt level.  If CONFIG_NET_NOINTS is defined, critical sections
+      will be managed with semaphores; Otherwise, it assumed that uIP will be
+      called from interrupt level handling and critical sections will be
+      managed by enabling and disabling interrupts.
+    CONFIG_NET_MULTIBUFFER - Traditionally, uIP has used a single buffer
+      for all incoming and outgoing traffic.  If this configuration is
+      selected, then the driver can manage multiple I/O buffers and can,
+      for example, be filling one input buffer while sending another
+      output buffer.  Or, as another example, the driver may support
+      queuing of concurrent input/ouput and output transfers for better
+      performance.
+    CONFIG_NET_IPv6 - Build in support for IPv6
+    CONFIG_NSOCKET_DESCRIPTORS - Maximum number of socket descriptors
+    per task/thread.
+    CONFIG_NET_NACTIVESOCKETS - Maximum number of concurrent socket
+      operations (recv, send, etc.).  Default: CONFIG_NET_TCP_CONNS+CONFIG_NET_UDP_CONNS
+    CONFIG_NET_SOCKOPTS - Enable or disable support for socket options
+
+    CONFIG_NET_BUFSIZE - uIP buffer size
+    CONFIG_NET_TCPURGDATA - Determines if support for TCP urgent data
+      notification should be compiled in. Urgent data (out-of-band data)
+      is a rarely used TCP feature that is very seldom would be required.
+    CONFIG_NET_TCP - TCP support on or off
+    CONFIG_NET_TCP_CONNS - Maximum number of TCP connections (all tasks)
+    CONFIG_NET_MAX_LISTENPORTS - Maximum number of listening TCP ports (all tasks)
+    CONFIG_NET_TCP_READAHEAD_BUFSIZE - Size of TCP read-ahead buffers
+    CONFIG_NET_NTCP_READAHEAD_BUFFERS - Number of TCP read-ahead buffers
+      (may be zero)
+    CONFIG_NET_TCPBACKLOG - Incoming connections pend in a backlog until
+      accept() is called. The size of the backlog is selected when listen()
+      is called.
+    CONFIG_NET_UDP - UDP support on or off
+    CONFIG_NET_UDP_CHECKSUMS - UDP checksums on or off
+    CONFIG_NET_UDP_CONNS - The maximum amount of concurrent UDP
+      connections
+    CONFIG_NET_ICMP - Enable minimal ICMP support. Includes built-in support
+      for sending replies to received ECHO (ping) requests.
+    CONFIG_NET_ICMP_PING - Provide interfaces to support application level
+      support for sending ECHO (ping) requests and associating ECHO
+      replies.
+    CONFIG_NET_IGMP - Enable IGMPv2 client support.
+    CONFIG_PREALLOC_IGMPGROUPS - Pre-allocated IGMP groups are used
+      only if needed from interrupt level group created (by the IGMP server).
+      Default: 4.
+    CONFIG_NET_PINGADDRCONF - Use "ping" packet for setting IP address
+    CONFIG_NET_STATISTICS - uIP statistics on or off
+    CONFIG_NET_RECEIVE_WINDOW - The size of the advertised receiver's
+      window
+    CONFIG_NET_ARPTAB_SIZE - The size of the ARP table
+    CONFIG_NET_ARP_IPIN - Harvest IP/MAC address mappings from the ARP table
+      from incoming IP packets.
+    CONFIG_NET_BROADCAST - Incoming UDP broadcast support
+    CONFIG_NET_MULTICAST - Outgoing multi-cast address support
+    CONFIG_NET_FWCACHE_SIZE - number of packets to remember when
+      looking for duplicates
+
+  SLIP Driver.  SLIP supports point-to-point IP communications over a serial
+    port.  The default data link layer for uIP is Ethernet. If CONFIG_NET_SLIP
+    is defined in the NuttX configuration file, then SLIP will be supported.
+    The basic differences between the SLIP and Ethernet configurations is that
+    when SLIP is selected: 
+
+    * The link level header (that comes before the IP header) is omitted. 
+    * All MAC address processing is suppressed. 
+    * ARP is disabled.
+
+    If CONFIG_NET_SLIP is not selected, then Ethernet will be used (there is
+    no need to define anything special in the configuration file to use
+    Ethernet -- it is the default). 
+
+    CONFIG_NET_SLIP -- Enables building of the SLIP driver. SLIP requires
+      at least one IP protocols selected and the following additional
+      network settings: CONFIG_NET_NOINTS and CONFIG_NET_MULTIBUFFER.
+      CONFIG_NET_BUFSIZE *must* be set to 296.  Other optional configuration
+      settings that affect the SLIP driver: CONFIG_NET_STATISTICS. 
+      Default: Ethernet
+
+    If SLIP is selected, then the following SLIP options are available:
+
+    CONFIG_CLIP_NINTERFACES -- Selects the number of physical SLIP
+      interfaces to support.  Default: 1
+    CONFIG_SLIP_STACKSIZE -- Select the stack size of the SLIP RX and
+      TX tasks.  Default: 2048
+    CONFIG_SLIP_DEFPRIO - The priority of the SLIP RX and TX tasks.
+      Default: 128
+
+  UIP Network Utilities
+
+    CONFIG_NET_DHCP_LIGHT - Reduces size of DHCP
+    CONFIG_NET_RESOLV_ENTRIES - Number of resolver entries
+
+  THTTPD
+
+    CONFIG_THTTPD_PORT - THTTPD Server port number
+    CONFIG_THTTPD_IPADDR - Server IP address (no host name)
+    CONFIG_THTTPD_SERVER_ADDRESS - SERVER_ADDRESS: response
+    CONFIG_THTTPD_SERVER_SOFTWARE - SERVER_SOFTWARE: response
+    CONFIG_THTTPD_PATH - Server working directory
+    CONFIG_THTTPD_CGI_PATH - Path to CGI executables
+    CONFIG_THTTPD_CGI_PATTERN - Only CGI programs matching this
+      pattern will be executed.  In fact, if this value is not defined
+      then no CGI logic will be built.
+    CONFIG_THTTPD_CGI_PRIORITY - Provides the priority of CGI child tasks
+    CONFIG_THTTPD_CGI_STACKSIZE - Provides the initial stack size of
+      CGI child task (will be overridden by the stack size in the NXFLAT
+      header)
+    CONFIG_THTTPD_CGI_BYTECOUNT - Byte output limit for CGI tasks.
+    CONFIG_THTTPD_CGI_TIMELIMIT - How many seconds to allow CGI programs
+      to run before killing them.
+    CONFIG_THTTPD_CHARSET- The default character set name to use with
+      text MIME types.
+    CONFIG_THTTPD_IOBUFFERSIZE - 
+    CONFIG_THTTPD_INDEX_NAMES - A list of index filenames to check. The
+      files are searched for in this order.
+    CONFIG_AUTH_FILE - The file to use for authentication. If this is
+      defined then thttpd checks for this file in the local directory
+      before every fetch. If the file exists then authentication is done,
+      otherwise the fetch proceeds as usual. If you leave this undefined
+      then thttpd will not implement authentication at all and will not
+      check for auth files, which saves a bit of CPU time. A typical
+      value is ".htpasswd"
+    CONFIG_THTTPD_LISTEN_BACKLOG - The listen() backlog queue length.
+    CONFIG_THTTPD_LINGER_MSEC - How many milliseconds to leave a connection
+      open while doing a lingering close.
+    CONFIG_THTTPD_OCCASIONAL_MSEC - How often to run the occasional
+      cleanup job.
+    CONFIG_THTTPD_IDLE_READ_LIMIT_SEC - How many seconds to allow for
+     reading the initial request on a new connection.
+    CONFIG_THTTPD_IDLE_SEND_LIMIT_SEC - How many seconds before an
+      idle connection gets closed.
+    CONFIG_THTTPD_TILDE_MAP1 and CONFIG_THTTPD_TILDE_MAP2 - Tilde mapping.
+      Many URLs use ~username to indicate a user's home directory. thttpd
+       provides two options for mapping this construct to an  actual filename.
+      1) Map ~username to <prefix>/username. This is the recommended choice.
+        Each user gets a subdirectory in the main web tree, and the tilde
+        construct points there. The prefix could be something like "users",
+        or it could be empty.
+      2) Map ~username to <user's homedir>/<postfix>. The postfix would be
+        the name of a subdirectory off of the user's actual home dir,
+        something like "public_html".
+      You can also leave both options undefined, and thttpd will not do
+      anything special about tildes. Enabling both options is an error.
+      Typical values, if they're defined, are "users" for
+      CONFIG_THTTPD_TILDE_MAP1 and "public_html"forCONFIG_THTTPD_TILDE_MAP2. 
+    CONFIG_THTTPD_GENERATE_INDICES
+    CONFIG_THTTPD_URLPATTERN - If defined, then it will be used to match
+      and verify referrers.
+
+  FTP Server
+
+    CONFIG_FTPD_VENDORID - The vendor name to use in FTP communications.
+      Default: "NuttX"
+    CONFIG_FTPD_SERVERID - The server name to use in FTP communications.
+      Default: "NuttX FTP Server"
+    CONFIG_FTPD_CMDBUFFERSIZE - The maximum size of one command.  Default:
+      128 bytes.
+    CONFIG_FTPD_DATABUFFERSIZE - The size of the I/O buffer for data
+      transfers.  Default: 512 bytes.
+    CONFIG_FTPD_WORKERSTACKSIZE - The stacksize to allocate for each
+      FTP daemon worker thread.  Default:  2048 bytes.
+
+    Other required configuration settings:  Of course TCP networking support
+    is required.  But here are a couple that are less obvious:
+
+      CONFIG_DISABLE_PTHREAD - pthread support is required
+      CONFIG_DISABLE_POLL - poll() support is required
+
+  USB device controller driver
+
+    CONFIG_USBDEV - Enables USB device support
+    CONFIG_USBDEV_COMPOSITE
+      Enables USB composite device support
+    CONFIG_USBDEV_ISOCHRONOUS - Build in extra support for isochronous
+      endpoints
+    CONFIG_USBDEV_DUALSPEED -Hardware handles high and full speed
+      operation (USB 2.0)
+    CONFIG_USBDEV_SELFPOWERED - Will cause USB features to indicate
+      that the device is self-powered
+    CONFIG_USBDEV_MAXPOWER - Maximum power consumption in mA
+    CONFIG_USBDEV_TRACE - Enables USB tracing for debug
+    CONFIG_USBDEV_TRACE_NRECORDS - Number of trace entries to remember
+
+  USB host controller driver
+
+    CONFIG_USBHOST
+      Enables USB host support
+    CONFIG_USBHOST_NPREALLOC
+      Number of pre-allocated class instances
+    CONFIG_USBHOST_BULK_DISABLE
+      On some architectures, selecting this setting will reduce driver size
+      by disabling bulk endpoint support
+    CONFIG_USBHOST_INT_DISABLE
+      On some architectures, selecting this setting will reduce driver size
+      by disabling interrupt endpoint support
+    CONFIG_USBHOST_ISOC_DISABLE
+      On some architectures, selecting this setting will reduce driver size
+      by disabling isochronous endpoint support
+
+  USB host HID class driver. Requires CONFIG_USBHOST=y,
+    CONFIG_USBHOST_INT_DISABLE=n, CONFIG_NFILE_DESCRIPTORS > 0,
+    CONFIG_SCHED_WORKQUEUE=y, and CONFIG_DISABLE_SIGNALS=n.
+ 
+    CONFIG_HIDKBD_POLLUSEC
+      Device poll rate in microseconds. Default: 100 milliseconds.
+    CONFIG_HIDKBD_DEFPRIO
+      Priority of the polling thread.  Default: 50.
+    CONFIG_HIDKBD_STACKSIZE
+      Stack size for polling thread.  Default: 1024
+    CONFIG_HIDKBD_BUFSIZE
+      Scancode buffer size.  Default: 64.
+    CONFIG_HIDKBD_NPOLLWAITERS
+      If the poll() method is enabled, this defines the maximum number
+      of threads that can be waiting for keyboard events.  Default: 2.
+    CONFIG_HIDKBD_RAWSCANCODES
+      If set to y no conversion will be made on the raw keyboard scan
+      codes.  Default: ASCII conversion.
+    CONFIG_HIDKBD_ALLSCANCODES'
+      If set to y all 231 possible scancodes will be converted to
+      something.  Default:  104 key US keyboard.
+    CONFIG_HIDKBD_NODEBOUNCE
+      If set to y normal debouncing is disabled.  Default: 
+      Debounce enabled (No repeat keys).
+
+  USB host mass storage class driver. Requires CONFIG_USBHOST=y,
+    CONFIG_USBHOST_BULK_DISABLE=n, CONFIG_NFILE_DESCRIPTORS > 0,
+    and CONFIG_SCHED_WORKQUEUE=y
+
+  USB serial device class driver (Prolific PL2303 Emulation)
+
+    CONFIG_PL2303
+      Enable compilation of the USB serial driver
+    CONFIG_PL2303_EPINTIN
+      The logical 7-bit address of a hardware endpoint that supports
+      interrupt IN operation
+    CONFIG_PL2303_EPBULKOUT
+      The logical 7-bit address of a hardware endpoint that supports
+      bulk OUT operation
+    CONFIG_PL2303_EPBULKIN
+      The logical 7-bit address of a hardware endpoint that supports
+      bulk IN operation
+    CONFIG_PL2303_NWRREQS and CONFIG_PL2303_NRDREQS
+      The number of write/read requests that can be in flight
+    CONFIG_PL2303_VENDORID and CONFIG_PL2303_VENDORSTR
+      The vendor ID code/string
+    CONFIG_PL2303_PRODUCTID and CONFIG_PL2303_PRODUCTSTR
+      The product ID code/string
+    CONFIG_PL2303_RXBUFSIZE and CONFIG_PL2303_TXBUFSIZE
+      Size of the serial receive/transmit buffers
+
+  USB serial device class driver (Standard CDC ACM class)
+
+    CONFIG_CDCACM
+      Enable compilation of the USB serial driver
+    CONFIG_CDCACM_COMPOSITE
+      Configure the CDC serial driver as part of a composite driver
+      (only if CONFIG_USBDEV_COMPOSITE is also defined)
+    CONFIG_CDCACM_IFNOBASE
+       If the CDC driver is part of a composite device, then this may need to 
+      be defined to offset the CDC/ACM interface numbers so that they are
+      unique and contiguous.  When used with the Mass Storage driver, the
+      correct value for this offset is zero.
+    CONFIG_CDCACM_STRBASE
+      If the CDC driver is part of a composite device, then this may need to 
+      be defined to offset the CDC/ACM string numbers so that they are
+      unique and contiguous.  When used with the Mass Storage driver, the
+      correct value for this offset is four (this value actuallly only needs
+      to be defined if names are provided for the Notification interface,
+      CONFIG_CDCACM_NOTIFSTR, or the data interface, CONFIG_CDCACM_DATAIFSTR).
+    CONFIG_CDCACM_EP0MAXPACKET
+      Endpoint 0 max packet size. Default 64.
+    CONFIG_CDCACM_EPINTIN
+      The logical 7-bit address of a hardware endpoint that supports
+      interrupt IN operation.  Default 2.
+    CONFIG_CDCACM_EPINTIN_FSSIZE
+      Max package size for the interrupt IN endpoint if full speed mode.
+      Default 64.
+    CONFIG_CDCACM_EPINTIN_HSSIZE
+      Max package size for the interrupt IN endpoint if high speed mode.
+      Default 64.
+    CONFIG_CDCACM_EPBULKOUT
+      The logical 7-bit address of a hardware endpoint that supports
+      bulk OUT operation
+    CONFIG_CDCACM_EPBULKOUT_FSSIZE
+      Max package size for the bulk OUT endpoint if full speed mode.
+      Default 64.
+    CONFIG_CDCACM_EPBULKOUT_HSSIZE
+      Max package size for the bulk OUT endpoint if high speed mode.
+      Default 512.
+    CONFIG_CDCACM_EPBULKIN
+      The logical 7-bit address of a hardware endpoint that supports
+      bulk IN operation
+    CONFIG_CDCACM_EPBULKIN_FSSIZE
+      Max package size for the bulk IN endpoint if full speed mode.
+      Default 64.
+    CONFIG_CDCACM_EPBULKIN_HSSIZE
+      Max package size for the bulk IN endpoint if high speed mode.
+      Default 512.
+    CONFIG_CDCACM_NWRREQS and CONFIG_CDCACM_NRDREQS
+      The number of write/read requests that can be in flight.
+      CONFIG_CDCACM_NWRREQS includes write requests used for both the
+      interrupt and bulk IN endpoints.  Default 4.
+    CONFIG_CDCACM_VENDORID and CONFIG_CDCACM_VENDORSTR
+      The vendor ID code/string.  Default 0x0525 and "NuttX"
+      0x0525 is the Netchip vendor and should not be used in any
+      products.  This default VID was selected for compatibility with
+      the Linux CDC ACM default VID.
+    CONFIG_CDCACM_PRODUCTID and CONFIG_CDCACM_PRODUCTSTR
+      The product ID code/string. Default 0xa4a7 and "CDC/ACM Serial"
+      0xa4a7 was selected for compatibility with the Linux CDC ACM
+      default PID.
+    CONFIG_CDCACM_RXBUFSIZE and CONFIG_CDCACM_TXBUFSIZE
+      Size of the serial receive/transmit buffers. Default 256.
+
+  USB Storage Device Configuration
+
+    CONFIG_USBMSC
+      Enable compilation of the USB storage driver
+    CONFIG_USBMSC_COMPOSITE
+      Configure the mass storage driver as part of a composite driver
+      (only if CONFIG_USBDEV_COMPOSITE is also defined)
+    CONFIG_USBMSC_IFNOBASE
+      If the CDC driver is part of a composite device, then this may need to 
+      be defined to offset the mass storage interface number so that it is
+      unique and contiguous.  When used with the CDC/ACM driver, the
+      correct value for this offset is two (because of the two CDC/ACM
+      interfaces that will precede it).
+    CONFIG_USBMSC_STRBASE
+      If the CDC driver is part of a composite device, then this may need to 
+      be defined to offset the mass storage string numbers so that they are
+      unique and contiguous.  When used with the CDC/ACM driver, the
+      correct value for this offset is four (or perhaps 5 or 6, depending
+      on if CONFIG_CDCACM_NOTIFSTR or CONFIG_CDCACM_DATAIFSTR are defined).
+    CONFIG_USBMSC_EP0MAXPACKET
+      Max packet size for endpoint 0
+    CONFIG_USBMSCEPBULKOUT and CONFIG_USBMSC_EPBULKIN
+      The logical 7-bit address of a hardware endpoints that support
+      bulk OUT and IN operations
+    CONFIG_USBMSC_NWRREQS and CONFIG_USBMSC_NRDREQS
+      The number of write/read requests that can be in flight
+    CONFIG_USBMSC_BULKINREQLEN and CONFIG_USBMSC_BULKOUTREQLEN
+      The size of the buffer in each write/read request.  This
+      value needs to be at least as large as the endpoint
+      maxpacket and ideally as large as a block device sector.
+    CONFIG_USBMSC_VENDORID and CONFIG_USBMSC_VENDORSTR
+      The vendor ID code/string
+    CONFIG_USBMSC_PRODUCTID and CONFIG_USBMSC_PRODUCTSTR
+      The product ID code/string
+    CONFIG_USBMSC_REMOVABLE
+      Select if the media is removable
+
+  USB Composite Device Configuration
+
+    CONFIG_USBDEV_COMPOSITE
+      Enables USB composite device support
+    CONFIG_CDCACM_COMPOSITE
+      Configure the CDC serial driver as part of a composite driver
+      (only if CONFIG_USBDEV_COMPOSITE is also defined)
+    CONFIG_USBMSC_COMPOSITE
+      Configure the mass storage driver as part of a composite driver
+      (only if CONFIG_USBDEV_COMPOSITE is also defined)
+    CONFIG_COMPOSITE_IAD
+      If one of the members of the composite has multiple interfaces
+      (such as CDC/ACM), then an Interface Association Descriptor (IAD)
+      will be necessary.  Default:  IAD will be used automatically if
+      needed.  It should not be necessary to set this.
+    CONFIG_COMPOSITE_EP0MAXPACKET
+      Max packet size for endpoint 0
+    CONFIG_COMPOSITE_VENDORID and CONFIG_COMPOSITE_VENDORSTR
+      The vendor ID code/string
+    CONFIG_COMPOSITE_PRODUCTID and CONFIG_COMPOSITE_PRODUCTSTR
+      The product ID code/string
+    CONFIG_COMPOSITE_SERIALSTR
+      Device serial number string
+    CONFIG_COMPOSITE_CONFIGSTR
+      Configuration string
+    CONFIG_COMPOSITE_VERSIONNO
+      Interface version number.
+
+  Graphics related configuration settings
+
+    CONFIG_NX
+      Enables overall support for graphics library and NX
+    CONFIG_NX_MULTIUSER
+      Configures NX in multi-user mode
+    CONFIG_NX_NPLANES
+      Some YUV color formats requires support for multiple planes,
+      one for each color component.  Unless you have such special
+      hardware, this value should be undefined or set to 1.
+    CONFIG_NX_DISABLE_1BPP, CONFIG_NX_DISABLE_2BPP,
+    CONFIG_NX_DISABLE_4BPP, CONFIG_NX_DISABLE_8BPP,
+    CONFIG_NX_DISABLE_16BPP, CONFIG_NX_DISABLE_24BPP, and
+    CONFIG_NX_DISABLE_32BPP
+      NX supports a variety of pixel depths.  You can save some
+      memory by disabling support for unused color depths.
+    CONFIG_NX_PACKEDMSFIRST
+      If a pixel depth of less than 8-bits is used, then NX needs
+      to know if the pixels pack from the MS to LS or from LS to MS
+    CONFIG_NX_LCDDRIVER
+      By default, NX builds to use a framebuffer driver (see
+      include/nuttx/fb.h). If this option is defined, NX will
+      build to use an LCD driver (see include/nuttx/lcd/lcd.h).
+    CONFIG_LCD_MAXPOWER - The full-on power setting for an LCD
+      device.
+    CONFIG_LCD_MAXCONTRAST - The maximum contrast value for an
+      LCD device.
+    CONFIG_LCD_LANDSCAPE, CONFIG_LCD_PORTRAIT, CONFIG_LCD_RLANDSCAPE,
+      and CONFIG_LCD_RPORTRAIT - Some LCD drivers may support
+      these options to present the display in landscape, portrait,
+      reverse landscape, or reverse portrait orientations.  Check
+      the README.txt file in each board configuration directory to
+      see if any of these are supported by the board LCD logic.
+    CONFIG_NX_MOUSE
+      Build in support for mouse input.
+    CONFIG_NX_KBD
+      Build in support of keypad/keyboard input.
+    CONFIG_NXTK_BORDERWIDTH
+      Specifies with with of the border (in pixels) used with
+      framed windows.   The default is 4.
+    CONFIG_NXTK_BORDERCOLOR1 and CONFIG_NXTK_BORDERCOLOR2
+      Specify the colors of the border used with framed windows.
+      CONFIG_NXTK_BORDERCOLOR2 is the shadow side color and so
+      is normally darker.  The default is medium and dark grey,
+      respectively
+    CONFIG_NXTK_AUTORAISE
+      If set, a window will be raised to the top if the mouse position
+      is over a visible portion of the window.  Default: A mouse
+      button must be clicked over a visible portion of the window.
+    CONFIG_NXFONTS_CHARBITS
+      The number of bits in the character set.  Current options are
+      only 7 and 8.  The default is 7.
+
+    CONFIG_NXFONT_SANS23X27
+      This option enables support for a tiny, 23x27 san serif font
+      (font ID FONTID_SANS23X27 == 1).
+    CONFIG_NXFONT_SANS22X29
+      This option enables support for a small, 22x29 san serif font
+      (font ID FONTID_SANS22X29 == 2).
+    CONFIG_NXFONT_SANS28X37
+      This option enables support for a medium, 28x37 san serif font
+      (font ID FONTID_SANS28X37 == 3).
+    CONFIG_NXFONT_SANS39X48
+      This option enables support for a large, 39x48 san serif font
+      (font ID FONTID_SANS39X48 == 4).
+    CONFIG_NXFONT_SANS22X29B
+      This option enables support for a small, 22x29 san serif bold font
+      (font ID FONTID_SANS22X29B == 5).
+    CONFIG_NXFONT_SANS28X37B
+      This option enables support for a medium, 28x37 san serif bold font
+      (font ID FONTID_SANS28X37B == 6).
+    CONFIG_NXFONT_SANS40X49B
+      This option enables support for a large, 40x49 san serif bold font
+      (font ID FONTID_SANS40X49B == 7).
+    CONFIG_NXFONT_SERIF22X29
+      This option enables support for a small, 22x29 font (with serifs)
+      (font ID FONTID_SERIF22X29 == 8).
+    CONFIG_NXFONT_SERIF29X37
+      This option enables support for a medium, 29x37 font (with serifs)
+      (font ID FONTID_SERIF29X37 == 9).
+    CONFIG_NXFONT_SERIF38X48
+      This option enables support for a large, 38x48 font (with serifs)
+      (font ID FONTID_SERIF38X48 == 10).
+    CONFIG_NXFONT_SERIF22X28B
+      This option enables support for a small, 27x38 bold font (with serifs)
+      (font ID FONTID_SERIF22X28B == 11).
+    CONFIG_NXFONT_SERIF27X38B
+      This option enables support for a medium, 27x38 bold font (with serifs)
+      (font ID FONTID_SERIF27X38B == 12).
+    CONFIG_NXFONT_SERIF38X49B
+      This option enables support for a large, 38x49 bold font (with serifs)
+      (font ID FONTID_SERIF38X49B == 13).
+
+  NX Multi-user only options:
+
+    CONFIG_NX_BLOCKING
+      Open the client message queues in blocking mode.  In this case,
+      nx_eventhandler() will never return.
+    CONFIG_NX_MXSERVERMSGS and CONFIG_NX_MXCLIENTMSGS
+      Specifies the maximum number of messages that can fit in
+      the message queues.  No additional resources are allocated, but
+      this can be set to prevent flooding of the client or server with
+      too many messages (CONFIG_PREALLOC_MQ_MSGS controls how many
+      messages are pre-allocated).
+
+  Stack and heap information
+
+    CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP
+      operation from FLASH but must copy initialized .data sections to RAM.
+    CONFIG_BOOT_COPYTORAM -  Some configurations boot in FLASH
+      but copy themselves entirely into RAM for better performance.
+    CONFIG_BOOT_RAMFUNCS - Other configurations may copy just some functions
+      into RAM, either for better performance or for errata workarounds.
+    CONFIG_STACK_POINTER - The initial stack pointer (may not be supported
+      in all architectures).
+    CONFIG_STACK_ALIGNMENT - Set if the your application has specific
+      stack alignment requirements (may not be supported
+      in all architectures).
+    CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack.
+      This is the thread that (1) performs the inital boot of the system up
+      to the point where user_start() is spawned, and (2) there after is the
+      IDLE thread that executes only when there is no other thread ready to
+      run.
+    CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate
+      for the main user thread that begins at the user_start() entry point.
+    CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size
+    CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size
+    CONFIG_HEAP_BASE - The beginning of the heap
+    CONFIG_HEAP_SIZE - The size of the heap
+
+appconfig -- This is another configuration file that is specific to the
+  application.  This file is copied into the application build directory
+  when NuttX is configured.  See ../apps/README.txt for further details.
+
+setenv.sh -- This is a script that you can include that will be installed at
+  the toplevel of the directory structure and can be sourced to set any
+  necessary environment variables.  You will most likely have to customize the
+  default setenv.sh script in order for it to work correctly in your
+  environment.
+
+Supported Boards
+^^^^^^^^^^^^^^^^
+
+configs/amber
+  This is placeholder for the SoC Robotics Amber Web Server that is based
+  on the Atmel AVR ATMega128 MCU.  There is not much there yet and what is
+  there is untested due to tool-related issues.
+
+configs/avr32dev1
+  This is a port of NuttX to the Atmel AVR32DEV1 board.  That board is
+  based on the Atmel AT32UC3B0256 MCU and uses a specially patched
+  version of the GNU toolchain:  The patches provide support for the
+  AVR32 family.  That patched GNU toolchain is available only from the
+  Atmel website.  STATUS: This port is functional but very basic.  There
+  are configurations for NSH and the OS test.
+
+configs/c5471evm
+  This is a port to the Spectrum Digital C5471 evaluation board.  The
+  TMS320C5471 is a dual core processor from TI with an ARM7TDMI general
+  purpose processor and a c54 DSP.  It is also known as TMS320DA180 or just DA180. 
+  NuttX runs on the ARM core and is built with a GNU arm-elf toolchain*.
+  This port is complete and verified.
+
+configs/compal_e88 and compal_e99
+  These directories contain the board support for compal e88 and e99 phones.
+  These ports are based on patches contributed by Denis Carikli for both the
+  compal e99 and e88.  The patches were made by Alan Carvalho de Assis and
+  Denis Carikli using the Stefan Richter's Osmocom-bb patches.
+
+configs/demo9s12ne64
+  Freescale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu.  This
+  port uses the m9s12x GCC toolchain.  STATUS:  (Still) under development; it
+  is code complete but has not yet been verified.
+
+configs/ea3131
+  Embedded Artists EA3131 Development board.  This board is based on the 
+  an NXP LPC3131 MCU. This OS is built with the arm-elf toolchain*.
+  STATUS:  This port is complete and mature.
+
+configs/ea3152
+  Embedded Artists EA3152 Development board.  This board is based on the 
+  an NXP LPC3152 MCU. This OS is built with the arm-elf toolchain*.
+  STATUS:  This port is has not be exercised well, but since it is
+  a simple derivative of the ea3131, it should be fully functional.
+
+configs/eagle100
+  Micromint Eagle-100 Development board.  This board is based on the 
+  an ARM Cortex-M3 MCU, the Luminary LM3S6918. This OS is built with the
+  arm-elf toolchain*.  STATUS:  This port is complete and mature.
+
+configs/ekk-lm3s9b96
+  TI/Stellaris EKK-LM3S9B96 board.  This board is based on the 
+  an EKK-LM3S9B96 which is a Cortex-M3.
+
+configs/ez80f0910200kitg
+  ez80Acclaim! Microcontroller.  This port use the Zilog ez80f0910200kitg
+  development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line
+  tools.  The development environment is Cygwin under WinXP.
+
+configs/ez80f0910200zco
+  ez80Acclaim! Microcontroller.  This port use the Zilog ez80f0910200zco
+  development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line
+  tools.  The development environment is Cygwin under WinXP.
+
+configs/hymini-stm32v
+  A configuration for the HY-Mini STM32v board.  This board is based on the
+  STM32F103VCT chip.
+
+configs/kwikstik-k40.
+  Kinetis K40 Cortex-M4 MCU.  This port uses the FreeScale KwikStik-K40
+  development board.
+
+configs/lincoln60
+   NuttX port to the Micromint Lincoln 60 board.
+  
+configs/lm3s6432-s2e
+  Stellaris RDK-S2E Reference Design Kit and the MDL-S2E Ethernet to
+  Serial module.
+
+configs/lm3s6965-ek
+  Stellaris LM3S6965 Evaluation Kit.  This board is based on the 
+  an ARM Cortex-M3 MCU, the Luminary/TI LM3S6965. This OS is built with the
+  arm-elf toolchain*.  STATUS:  This port is complete and mature.
+
+configs/lm3s8962-ek
+  Stellaris LMS38962 Evaluation Kit.
+
+configs/lpcxpresso-lpc1768
+  Embedded Artists base board with NXP LPCExpresso LPC1768.  This board
+  is based on the NXP LPC1768.  The Code Red toolchain is used by default.
+  STATUS:  Under development.
+
+configs/lpc4330-xplorer
+  NuttX port to the LPC4330-Xplorer board from NGX Technologies featuring
+  the NXP LPC4330FET100 MCU
+
+configs/m68322evb
+  This is a work in progress for the venerable m68322evb board from
+  Motorola. This OS is also built with the arm-elf toolchain*.  STATUS:
+  This port was never completed.
+
+configs/mbed
+  The configurations in this directory support the mbed board (http://mbed.org)
+  that features the NXP LPC1768 microcontroller. This OS is also built
+  with the arm-elf toolchain*.  STATUS:  Contributed.
+
+configs/mcu123-lpc214x
+  This port is for the NXP LPC2148 as provided on the mcu123.com
+  lpc214x development board. This OS is also built with the arm-elf
+  toolchain*.  The port supports serial, timer0, spi, and usb.
+
+configs/micropendous3
+  This is a port to the Opendous Micropendous 3 board. This board may
+  be populated with either an AVR AT90USB646, 647, 1286, or 1287 MCU.
+  Support is configured for the AT90USB647.
+
+configs/mirtoo
+  This is the port to the DTX1-4000L "Mirtoo" module.  This module uses MicroChip
+  PIC32MX250F128D.  See http://www.dimitech.com/ for further information.
+
+configs/mx1ads
+  This is a port to the Motorola MX1ADS development board.  That board
+  is based on the Freescale i.MX1 processor.  The i.MX1 is an ARM920T.
+  STATUS:  This port is nearly code complete but was never fully
+  integrated due to tool-related issues.
+
+configs/ne64badge
+  Future Electronics Group NE64 /PoE Badge board based on the
+  MC9S12NE64 hcs12 cpu.  This port uses the m9s12x GCC toolchain.
+  STATUS:  Under development.  The port is code-complete but has
+  not yet been fully tested.
+
+configs/ntosd-dm320
+  This port uses the Neuros OSD v1.0 Dev Board with a GNU arm-elf
+  toolchain*: see
+
+    http://wiki.neurostechnology.com/index.php/OSD_1.0_Developer_Home
+ 
+  There are some differences between the Dev Board and the currently
+  available commercial v1.0 Boards.  See
+
+    http://wiki.neurostechnology.com/index.php/OSD_Developer_Board_v1
+
+  NuttX operates on the ARM9EJS of this dual core processor.
+  STATUS: This port is code complete, verified, and included in the
+  NuttX 0.2.1 release.
+
+configs/nucleus2g
+  This port uses the Nucleus 2G board (with Babel CAN board).  This board
+  features an NXP LPC1768 processor.  See the 2G website (http://www.2g-eng.com/)
+  for more information about the Nucleus 2G.
+
+configs/olimex-lpc1766stk
+  This port uses the Olimex LPC1766-STK board and a GNU GCC toolchain* under
+  Linux or Cygwin.  STATUS: Complete and mature.
+
+configs/olimex-lpc2378
+  This port uses the Olimex-lpc2378 board and a GNU arm-elf toolchain* under
+  Linux or Cygwin.  STATUS: ostest and NSH configurations available.
+  This port for the NXP LPC2378 was contributed by Rommel Marcelo.
+
+configs/olimex-strp711
+  This port uses the Olimex STR-P711 board and a GNU arm-elf toolchain* under
+  Linux or Cygwin. See the http://www.olimex.com/dev/str-p711.html" for
+  further information.  STATUS: Configurations for the basic OS test and NSH
+  are complete and verified.
+
+configs/pcblogic-pic32mx
+  This is the port of NuttX to the PIC32MX board from PCB Logic Design Co.
+  This board features the MicroChip PIC32MX460F512L.
+  The board is a very simple -- little more than a carrier for the PIC32
+  MCU plus voltage regulation, debug interface, and an OTG connector.
+  STATUS:  Code complete but testing has been stalled due to tool related problems
+  (PICkit 2 does not work with the PIC32).
+
+configs/pic32-starterkit
+
+  This directory contains the port of NuttX to the Microchip PIC32 Ethernet
+  Starter Kit (DM320004) with the Multimedia Expansion Board (MEB, DM320005).
+  See www.microchip.com for further information.
+
+configs/pic32mx7mmb
+
+  This directory will (eventually) contain the port of NuttX to the
+  Mikroelektronika PIC32MX7 Multimedia Board (MMB).  See
+  http://www.mikroe.com/ for further information.
+
+  STATUS:  Basic OS test configuration is in place, but the board does not boot.
+  It looks like I will need an ICD3 in order to debug the code (PICkit3
+  doesn't work for debug with this board).  This effort is temporarily stalled.
+
+configs/pjrc-8051
+  8051 Microcontroller.  This port uses the PJRC 87C52 development system
+  and the SDCC toolchain.   This port is not quite ready for prime time.
+
+configs/qemu-i486
+
+  Port of NuttX to QEMU in i486 mode.  This port will also run on real i486
+  hardwared (Google the Bifferboard).
+
+configs/rgmp
+  RGMP stands for RTOS and GPOS on Multi-Processor.  RGMP is a project for 
+  running GPOS and RTOS simultaneously on multi-processor platforms. You can
+  port your favorite RTOS to RGMP together with an unmodified Linux to form a
+  hybrid operating system. This makes your application able to use both RTOS
+  and GPOS features.
+
+  See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further information
+  about RGMP.
+
+configs/sam3u-ek
+  The port of NuttX to the Atmel SAM3U-EK development board.
+
+configs/sim
+  A user-mode port of NuttX to the x86 Linux platform is available.
+  The purpose of this port is primarily to support OS feature development.
+  This port does not support interrupts or a real timer (and hence no
+  round robin scheduler)  Otherwise, it is complete.
+
+configs/skp16c26
+  Renesas M16C processor on the Renesas SKP16C26 StarterKit.  This port
+  uses the GNU m32c toolchain.  STATUS:  The port is complete but untested
+  due to issues with compiler internal errors.
+
+configs/stm3210e-eval
+  STMicro STM3210E-EVAL development board based on the STMicro STM32F103ZET6
+  microcontroller (ARM Cortex-M3).  This port uses the GNU Cortex-M3
+  toolchain.
+
+configs/stm3220g-eval
+  STMicro STM3220G-EVAL development board based on the STMicro STM32F407IG
+  microcontroller (ARM Cortex-M3).
+
+configs/stm3240g-eval
+  STMicro STM3240G-EVAL development board based on the STMicro STM32F103ZET6
+  microcontroller (ARM Cortex-M4 with FPU).  This port uses a GNU Cortex-M4
+  toolchain (such as CodeSourcery).
+
+configs/stm32f4discovery
+  STMicro STM32F4-Discovery board boased on the STMIcro STM32F407VGT6 MCU.
+
+configs/sure-pic32mx
+  The "Advanced USB Storage Demo Board," Model DB-DP11215, from Sure
+  Electronics (http://www.sureelectronics.net/).  This board features
+  the MicroChip PIC32MX440F512H.  See also
+  http://www.sureelectronics.net/goods.php?id=1168 for further
+  information about the Sure DB-DP11215 board.
+
+configs/teensy
+  This is the port of NuttX to the PJRC Teensy++ 2.0 board.  This board is
+  developed by http://pjrc.com/teensy/.  The Teensy++ 2.0 is based
+  on an Atmel AT90USB1286 MCU.
+
+configs/twr-k60n512
+  Kinetis K60 Cortex-M4 MCU.  This port uses the FreeScale TWR-K60N512
+  development board.
+
+configs/ubw32
+
+  This is the port to the Sparkfun UBW32 board.  This port uses the original v2.4
+  board which is based on the MicroChip PIC32MX460F512L.  See
+  http://www.sparkfun.com/products/8971.  This older version has been replaced
+  with this board http://www.sparkfun.com/products/9713. See also
+  http://www.schmalzhaus.com/UBW32/.
+
+configs/us7032evb1
+  This is a port of the Hitachi SH-1 on the Hitachi SH-1/US7032EVB1 board.
+  STATUS:  Work has just began on this port.
+
+configs/vsn
+  ISOTEL NetClamps VSN V1.2 ready2go sensor network platform based on the
+  STMicro STM32F103RET6.  Contributed by Uros Platise.  See
+  http://isotel.eu/NetClamps/
+
+configs/xtrs
+  TRS80 Model 3.  This port uses a vintage computer based on the Z80.
+  An emulator for this computer is available to run TRS80 programs on a 
+  linux platform (http://www.tim-mann.org/xtrs.html).
+
+configs/z16f2800100zcog
+  z16f Microcontroller.  This port use the Zilog z16f2800100zcog
+  development kit and the Zilog ZDS-II Windows command line tools.  The
+  development environment is Cygwin under WinXP.
+
+configs/z80sim
+  z80 Microcontroller.  This port uses a Z80 instruction set simulator.
+  That simulator can be found in the NuttX SVN at
+  http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/misc/sims/z80sim.
+  This port also uses the SDCC toolchain (http://sdcc.sourceforge.net/")
+  (verified with version 2.6.0).
+
+configs/z8encore000zco
+  z8Encore! Microcontroller.  This port use the Zilog z8encore000zco
+  development kit, Z8F6403 part, and the Zilog ZDS-II Windows command line
+  tools.  The development environment is Cygwin under WinXP.
+
+configs/z8f64200100kit
+  z8Encore! Microcontroller.  This port use the Zilog z8f64200100kit
+  development kit, Z8F6423 part, and the Zilog ZDS-II Windows command line
+  tools.  The development environment is Cygwin under WinXP.
+
+Configuring NuttX
+^^^^^^^^^^^^^^^^^
+
+Configuring NuttX requires only copying
+
+  configs/<board-name>/<config-dir>/Make.def to ${TOPDIR}/Make.defs
+  configs/<board-name>/<config-dir>/setenv.sh to ${TOPDIR}/setenv.sh
+  configs/<board-name>/<config-dir>/defconfig to ${TOPDIR}/.config
+
+And if configs/<board-name>/<config-dir>/appconfig exists in the board
+configuration directory:
+
+  Copy configs/<board-name>/<config-dir>/appconfig to <app-dir>/.config
+  echo "APPS_LOC=\"<app-dir>\"" >> "${TOPDIR}/.config"
+
+tools/configure.sh
+  There is a script that automates these steps.  The following steps will
+  accomplish the same configuration:
+
+  cd tools
+  ./configure.sh <board-name>/<config-dir>
+
+And if configs/<board-name>/<config-dir>/appconfig exists and your
+application directory is not in the standard loction (../apps), then
+you should also specify the location of the application directory on the
+command line like:
+  
+  cd tools
+  ./configure.sh -a <app-dir> <board-name>/<config-dir>
diff --git a/nuttx/configs/px4fmu/README.txt b/nuttx/configs/px4fmu/README.txt
new file mode 100755
index 000000000..c92169206
--- /dev/null
+++ b/nuttx/configs/px4fmu/README.txt
@@ -0,0 +1,601 @@
+README
+======
+
+This README discusses issues unique to NuttX configurations for the
+PX4FMU development board.
+
+Or, it will once those are established.  For now, this is a copy of the file
+as presented for the STMicro STM32F407 evaluation board.  Read with caution.
+
+Contents
+========
+
+  - Development Environment
+  - GNU Toolchain Options
+  - IDEs
+  - NuttX buildroot Toolchain
+  - STM3240G-EVAL-specific Configuration Options
+  - LEDs
+  - Ethernet
+  - PWM
+  - CAN
+  - Configurations
+
+Development Environment
+=======================
+
+  Either Linux or Cygwin on Windows can be used for the development environment.
+  The source has been built only using the GNU toolchain (see below).  Other
+  toolchains will likely cause problems. Testing was performed using the Cygwin
+  environment because the Raisonance R-Link emulatator and some RIDE7 development tools
+  were used and those tools works only under Windows.
+
+GNU Toolchain Options
+=====================
+
+  The NuttX make system has been modified to support the following different
+  toolchain options.
+
+  1. The CodeSourcery GNU toolchain,
+  2. The devkitARM GNU toolchain,
+  3. Raisonance GNU toolchain, or
+  4. The NuttX buildroot Toolchain (see below).
+
+  All testing has been conducted using the CodeSourcery toolchain for Windows.  To use
+  the devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to
+  add one of the following configuration options to your .config (or defconfig)
+  file:
+
+    CONFIG_STM32_CODESOURCERYW=y  : CodeSourcery under Windows
+    CONFIG_STM32_CODESOURCERYL=y  : CodeSourcery under Linux
+    CONFIG_STM32_DEVKITARM=y      : devkitARM under Windows
+    CONFIG_STM32_RAISONANCE=y     : Raisonance RIDE7 under Windows
+    CONFIG_STM32_BUILDROOT=y      : NuttX buildroot under Linux or Cygwin (default)
+
+  If you change the default toolchain, then you may also have to modify the PATH in
+  the setenv.h file if your make cannot find the tools.
+
+  NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are
+  Windows native toolchains.  The CodeSourcey (for Linux) and NuttX buildroot
+  toolchains are Cygwin and/or Linux native toolchains. There are several limitations
+  to using a Windows based toolchain in a Cygwin environment.  The three biggest are:
+
+  1. The Windows toolchain cannot follow Cygwin paths.  Path conversions are
+     performed automatically in the Cygwin makefiles using the 'cygpath' utility
+     but you might easily find some new path problems.  If so, check out 'cygpath -w'
+
+  2. Windows toolchains cannot follow Cygwin symbolic links.  Many symbolic links
+     are used in Nuttx (e.g., include/arch).  The make system works around these
+     problems for the Windows tools by copying directories instead of linking them.
+     But this can also cause some confusion for you:  For example, you may edit
+     a file in a "linked" directory and find that your changes had no effect.
+     That is because you are building the copy of the file in the "fake" symbolic
+     directory.  If you use a Windows toolchain, you should get in the habit of
+     making like this:
+
+       make clean_context all
+
+     An alias in your .bashrc file might make that less painful.
+
+  3. Dependencies are not made when using Windows versions of the GCC.  This is
+     because the dependencies are generated using Windows pathes which do not
+     work with the Cygwin make.
+
+     Support has been added for making dependencies with the windows-native toolchains.
+     That support can be enabled by modifying your Make.defs file as follows:
+
+    -  MKDEP                = $(TOPDIR)/tools/mknulldeps.sh
+    +  MKDEP                = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
+
+     If you have problems with the dependency build (for example, if you are not
+     building on C:), then you may need to modify tools/mkdeps.sh
+
+  NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
+  level of -Os (See Make.defs).  It will work with -O0, -O1, or -O2, but not with
+  -Os.
+
+  NOTE 2: The devkitARM toolchain includes a version of MSYS make.  Make sure that
+  the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
+  path or will get the wrong version of make.
+
+IDEs
+====
+
+  NuttX is built using command-line make.  It can be used with an IDE, but some
+  effort will be required to create the project.
+  
+  Makefile Build
+  --------------
+  Under Eclipse, it is pretty easy to set up an "empty makefile project" and
+  simply use the NuttX makefile to build the system.  That is almost for free
+  under Linux.  Under Windows, you will need to set up the "Cygwin GCC" empty
+  makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
+  there is a lot of help on the internet).
+
+  Native Build
+  ------------
+  Here are a few tips before you start that effort:
+
+  1) Select the toolchain that you will be using in your .config file
+  2) Start the NuttX build at least one time from the Cygwin command line
+     before trying to create your project.  This is necessary to create
+     certain auto-generated files and directories that will be needed.
+  3) Set up include pathes:  You will need include/, arch/arm/src/stm32,
+     arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
+  4) All assembly files need to have the definition option -D __ASSEMBLY__
+     on the command line.
+
+  Startup files will probably cause you some headaches.  The NuttX startup file
+  is arch/arm/src/stm32/stm32_vectors.S.  With RIDE, I have to build NuttX
+  one time from the Cygwin command line in order to obtain the pre-built
+  startup object needed by RIDE.
+
+NuttX buildroot Toolchain
+=========================
+
+  A GNU GCC-based toolchain is assumed.  The files */setenv.sh should
+  be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
+  different from the default in your PATH variable).
+
+  If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
+  SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
+  This GNU toolchain builds and executes in the Linux or Cygwin environment.
+
+  1. You must have already configured Nuttx in <some-dir>/nuttx.
+
+     cd tools
+     ./configure.sh stm3240g-eval/<sub-dir>
+
+  2. Download the latest buildroot package into <some-dir>
+
+  3. unpack the buildroot tarball.  The resulting directory may
+     have versioning information on it like buildroot-x.y.z.  If so,
+     rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
+
+  4. cd <some-dir>/buildroot
+
+  5. cp configs/cortexm3-defconfig-4.3.3 .config
+
+  6. make oldconfig
+
+  7. make
+
+  8. Edit setenv.h, if necessary, so that the PATH variable includes
+     the path to the newly built binaries.
+
+  See the file configs/README.txt in the buildroot source tree.  That has more
+  detailed PLUS some special instructions that you will need to follow if you are
+  building a Cortex-M3 toolchain for Cygwin under Windows.
+
+Ethernet
+========
+
+The Ethernet driver is configured to use the MII interface:
+
+  Board Jumper Settings:
+
+    Jumper  Description
+    JP8     To enable MII, JP8 should not be fitted.
+    JP6     2-3: Enable MII interface mode
+    JP5     2-3: Provide 25 MHz clock for MII or 50 MHz clock for RMII by MCO at PA8
+    SB1     Not used with MII
+
+LEDs
+====
+
+The STM3240G-EVAL board has four LEDs labeled LD1, LD2, LD3 and LD4 on the
+board.. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined.  In that case, the usage by the board port is defined in
+include/board.h and src/up_leds.c. The LEDs are used to encode OS-related\
+events as follows:
+
+	SYMBOL				Meaning					LED1*	LED2	LED3	LED4
+	-------------------	-----------------------	-------	-------	-------	------
+	LED_STARTED			NuttX has been started	ON		OFF		OFF		OFF
+	LED_HEAPALLOCATE	Heap has been allocated	OFF		ON		OFF		OFF
+	LED_IRQSENABLED		Interrupts enabled		ON		ON		OFF		OFF
+	LED_STACKCREATED	Idle stack created		OFF		OFF		ON		OFF
+	LED_INIRQ			In an interrupt**		ON		N/C		N/C		OFF
+	LED_SIGNAL			In a signal handler***  N/C		ON		N/C		OFF
+	LED_ASSERTION		An assertion failed		ON		ON		N/C		OFF
+	LED_PANIC			The system has crashed	N/C		N/C		N/C		ON
+    LED_IDLE            STM32 is is sleep mode  (Optional, not used)
+
+  * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
+    and these LEDs will give you some indication of where the failure was
+ ** The normal state is LED3 ON and LED1 faintly glowing.  This faint glow
+    is because of timer interupts that result in the LED being illuminated
+    on a small proportion of the time.
+*** LED2 may also flicker normally if signals are processed.
+
+PWM
+===
+
+The STM3240G-Eval has no real on-board PWM devices, but the board can be
+configured to output a pulse train using TIM4 CH2.  This pin is used by
+FSMC is but is also connected to the Motor Control Connector (CN5) just
+for this purpose:
+
+  PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB)
+
+FSMC must be disabled in this case!  PD13 is available at:
+
+  Daughterboard Extension Connector, CN3, pin 32 - available
+  TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
+  Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14.
+
+CAN
+===
+
+Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2.
+
+  JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver
+  JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver
+
+CAN signals are then available on CN10 pins:
+
+  CN10 Pin 7 = CANH
+  CN10 Pin 2 = CANL
+
+Mapping to STM32 GPIO pins:
+
+  PD0   = FSMC_D2 & CAN1_RX   
+  PD1   = FSMC_D3 & CAN1_TX   
+  PB13  = ULPI_D6 & CAN2_TX
+  PB5   = ULPI_D7 & CAN2_RX
+
+Configuration Options:
+
+  CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+    CONFIG_STM32_CAN2 must also be defined)
+  CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+    Default: 8
+  CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+    Default: 4
+
+  CONFIG_STM32_CAN1 - Enable support for CAN1
+  CONFIG_CAN1_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN1 is defined.
+  CONFIG_STM32_CAN2 - Enable support for CAN1
+  CONFIG_CAN2_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN2 is defined.
+  CONFIG_CAN_REGDEBUG - If CONFIG_DEBUG is set, this will generate an
+    dump of all CAN registers.
+
+STM3240G-EVAL-specific Configuration Options
+============================================
+
+	CONFIG_ARCH - Identifies the arch/ subdirectory.  This should
+	   be set to:
+
+	   CONFIG_ARCH=arm
+
+	CONFIG_ARCH_family - For use in C code:
+
+	   CONFIG_ARCH_ARM=y
+
+	CONFIG_ARCH_architecture - For use in C code:
+
+	   CONFIG_ARCH_CORTEXM4=y
+
+	CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+	   CONFIG_ARCH_CHIP=stm32
+
+	CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+	   chip:
+
+	   CONFIG_ARCH_CHIP_STM32F407IG=y
+
+    CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+       configuration features.
+
+       CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+ 
+	CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
+	   hence, the board that supports the particular chip or SoC.
+
+	   CONFIG_ARCH_BOARD=stm3240g_eval (for the STM3240G-EVAL development board)
+
+	CONFIG_ARCH_BOARD_name - For use in C code
+
+	   CONFIG_ARCH_BOARD_STM3240G_EVAL=y
+
+	CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+	   of delay loops
+
+	CONFIG_ENDIAN_BIG - define if big endian (default is little
+	   endian)
+
+	CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+	   CONFIG_DRAM_SIZE=0x00010000 (64Kb)
+
+	CONFIG_DRAM_START - The start address of installed DRAM
+
+	   CONFIG_DRAM_START=0x20000000
+
+	CONFIG_DRAM_END - Last address+1 of installed RAM
+
+	   CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+
+	CONFIG_ARCH_IRQPRIO - The STM3240xxx supports interrupt prioritization
+
+	   CONFIG_ARCH_IRQPRIO=y
+
+	CONFIG_ARCH_FPU - The STM3240xxx supports a floating point unit (FPU)
+
+	   CONFIG_ARCH_FPU=y
+
+	CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+	   have LEDs
+
+	CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+	   stack. If defined, this symbol is the size of the interrupt
+	    stack in bytes.  If not defined, the user task stacks will be
+	  used during interrupt handling.
+
+	CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+	CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+
+	CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+	   cause a 100 second delay during boot-up.  This 100 second delay
+	   serves no purpose other than it allows you to calibratre
+	   CONFIG_ARCH_LOOPSPERMSEC.  You simply use a stop watch to measure
+	   the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
+	   the delay actually is 100 seconds.
+
+  Individual subsystems can be enabled:
+
+	AHB1
+	----
+	CONFIG_STM32_CRC
+	CONFIG_STM32_BKPSRAM
+	CONFIG_STM32_CCMDATARAM
+	CONFIG_STM32_DMA1
+	CONFIG_STM32_DMA2
+	CONFIG_STM32_ETHMAC
+	CONFIG_STM32_OTGHS
+
+	AHB2
+	----
+	CONFIG_STM32_DCMI
+	CONFIG_STM32_CRYP
+	CONFIG_STM32_HASH
+	CONFIG_STM32_RNG
+	CONFIG_STM32_OTGFS
+
+	AHB3
+	----
+	CONFIG_STM32_FSMC
+
+	APB1
+	----
+	CONFIG_STM32_TIM2
+	CONFIG_STM32_TIM3
+	CONFIG_STM32_TIM4
+	CONFIG_STM32_TIM5
+	CONFIG_STM32_TIM6
+	CONFIG_STM32_TIM7
+	CONFIG_STM32_TIM12
+	CONFIG_STM32_TIM13
+	CONFIG_STM32_TIM14
+	CONFIG_STM32_WWDG
+	CONFIG_STM32_SPI2
+	CONFIG_STM32_SPI3
+	CONFIG_STM32_USART2
+	CONFIG_STM32_USART3
+	CONFIG_STM32_UART4
+	CONFIG_STM32_UART5
+	CONFIG_STM32_I2C1
+	CONFIG_STM32_I2C2
+	CONFIG_STM32_I2C3
+	CONFIG_STM32_CAN1
+	CONFIG_STM32_CAN2
+	CONFIG_STM32_DAC1
+	CONFIG_STM32_DAC2
+	CONFIG_STM32_PWR -- Required for RTC
+
+	APB2
+	----
+	CONFIG_STM32_TIM1
+	CONFIG_STM32_TIM8
+	CONFIG_STM32_USART1
+	CONFIG_STM32_USART6
+	CONFIG_STM32_ADC1
+	CONFIG_STM32_ADC2
+	CONFIG_STM32_ADC3
+	CONFIG_STM32_SDIO
+	CONFIG_STM32_SPI1
+	CONFIG_STM32_SYSCFG
+	CONFIG_STM32_TIM9
+	CONFIG_STM32_TIM10
+	CONFIG_STM32_TIM11
+
+  Timer and I2C devices may need to the following to force power to be applied
+  unconditionally at power up.  (Otherwise, the device is powered when it is
+  initialized).
+
+    CONFIG_STM32_FORCEPOWER
+
+  Timer devices may be used for different purposes.  One special purpose is
+  to generate modulated outputs for such things as motor control.  If CONFIG_STM32_TIMn
+  is defined (as above) then the following may also be defined to indicate that
+  the timer is intended to be used for pulsed output modulation, ADC conversion,
+  or DAC conversion.
+
+	CONFIG_STM32_TIM1_PWM
+	CONFIG_STM32_TIM2_PWM
+	CONFIG_STM32_TIM3_PWM
+	CONFIG_STM32_TIM4_PWM
+	CONFIG_STM32_TIM5_PWM
+	CONFIG_STM32_TIM8_PWM
+	CONFIG_STM32_TIM9_PWM
+	CONFIG_STM32_TIM10_PWM
+	CONFIG_STM32_TIM11_PWM
+	CONFIG_STM32_TIM12_PWM
+	CONFIG_STM32_TIM13_PWM
+	CONFIG_STM32_TIM14_PWM
+
+	CONFIG_STM32_TIM1_ADC
+	CONFIG_STM32_TIM2_ADC
+	CONFIG_STM32_TIM3_ADC
+	CONFIG_STM32_TIM4_ADC
+	CONFIG_STM32_TIM5_ADC
+	CONFIG_STM32_TIM6_ADC
+	CONFIG_STM32_TIM7_ADC
+	CONFIG_STM32_TIM8_ADC
+
+	CONFIG_STM32_TIM1_DAC
+	CONFIG_STM32_TIM2_DAC
+	CONFIG_STM32_TIM3_DAC
+	CONFIG_STM32_TIM4_DAC
+	CONFIG_STM32_TIM5_DAC
+	CONFIG_STM32_TIM6_DAC
+	CONFIG_STM32_TIM7_DAC
+	CONFIG_STM32_TIM8_DAC
+
+  For each timer that is enabled for PWM usage, we need the following additional
+  configuration settings:
+
+	CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+ 
+  NOTE: The STM32 timers are each capable of generating different signals on
+  each of the four channels with different duty cycles.  That capability is
+  not supported by this driver:  Only one output channel per timer.
+
+  JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+
+	CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+	CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+	  but without JNTRST.
+	CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+  STM3240xxx specific device driver settings
+
+	CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+           m (m=4,5) for the console and ttys0 (default is the USART1).
+	CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+	   This specific the size of the receive buffer
+	CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+	   being sent.  This specific the size of the transmit buffer
+	CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART.  Must be
+	CONFIG_U[S]ARTn_BITS - The number of bits.  Must be either 7 or 8.
+	CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+	CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+	CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+	  support. Non-interrupt-driven, poll-waiting is recommended if the
+	  interrupt rate would be to high in the interrupt driven case.
+	CONFIG_STM32_SPI_DMA - Use DMA to improve SPI transfer performance.
+	  Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+	CONFIG_SDIO_DMA - Support DMA data transfers.  Requires CONFIG_STM32_SDIO
+	  and CONFIG_STM32_DMA2.
+	CONFIG_SDIO_PRI - Select SDIO interrupt prority.  Default: 128
+	CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. 
+	  Default:  Medium
+	CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode.  Default:
+	  4-bit transfer mode.
+
+	CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
+	CONFIG_STM32_MII - Support Ethernet MII interface
+	CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
+	CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
+	CONFIG_STM32_RMII - Support Ethernet RMII interface
+	CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
+	CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
+	  may be defined to select full duplex mode. Default: half-duplex
+	CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
+	  may be defined to select 100 MBps speed.  Default: 10 Mbps
+	CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  The PHY status register address may diff from PHY to PHY.  This
+	  configuration sets the address of the PHY status register.
+	CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provides bit mask indicating 10 or 100MBps speed.
+	CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provides the value of the speed bit(s) indicating 100MBps speed.
+	CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provide bit mask indicating full or half duplex modes.
+	CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
+	  defined.  This provides the value of the mode bits indicating full duplex mode.
+	CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP).  Not supported
+	  but some hooks are indicated with this condition.
+
+  STM3240G-EVAL CAN Configuration
+
+	CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+	  CONFIG_STM32_CAN2 must also be defined)
+	CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+	  Default: 8
+	CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+	  Default: 4
+	CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+	  mode for testing. The STM32 CAN driver does support loopback mode.
+	CONFIG_CAN1_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN1 is defined.
+	CONFIG_CAN2_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN2 is defined.
+	CONFIG_CAN_REGDEBUG - If CONFIG_DEBUG is set, this will generate an
+	  dump of all CAN registers.
+
+  STM3240G-EVAL LCD Hardware Configuration
+
+Configurations
+==============
+
+Each STM3240G-EVAL configuration is maintained in a sudirectory and
+can be selected as follow:
+
+	cd tools
+	./configure.sh stm3240g-eval/<subdir>
+	cd -
+	. ./setenv.sh
+
+Where <subdir> is one of the following:
+
+  dhcpd:
+  -----
+
+    This builds the DCHP server using the apps/examples/dhcpd application
+    (for execution from FLASH.) See apps/examples/README.txt for information
+    about the dhcpd example.  The server address is 10.0.0.1 and it serves
+    IP addresses in the range 10.0.0.2 through 10.0.0.17 (all of which, of
+    course, are configurable).
+
+    CONFIG_STM32_CODESOURCERYW=y  : CodeSourcery under Windows
+
+  nettest:
+  -------
+
+    This configuration directory may be used to verify networking performance
+    using the STM32's Ethernet controller. It uses apps/examples/nettest to excercise the
+    TCP/IP network.
+
+    CONFIG_EXAMPLE_NETTEST_SERVER=n                       : Target is configured as the client
+    CONFIG_EXAMPLE_NETTEST_PERFORMANCE=y                  : Only network performance is verified.
+    CONFIG_EXAMPLE_NETTEST_IPADDR=(10<<24|0<<16|0<<8|2)   : Target side is IP: 10.0.0.2
+    CONFIG_EXAMPLE_NETTEST_DRIPADDR=(10<<24|0<<16|0<<8|1) : Host side is IP: 10.0.0.1
+    CONFIG_EXAMPLE_NETTEST_CLIENTIP=(10<<24|0<<16|0<<8|1) : Server address used by which ever is client.
+
+  ostest:
+  ------
+    This configuration directory, performs a simple OS test using
+    examples/ostest.  By default, this project assumes that you are
+    using the DFU bootloader.
+
+    CONFIG_STM32_CODESOURCERYW=y  : CodeSourcery under Windows
+
+  nsh:
+  ---
+    Configures the NuttShell (nsh) located at apps/examples/nsh.  The
+    Configuration enables both the serial and telnet NSH interfaces.
+
+    CONFIG_STM32_CODESOURCERYW=y              : CodeSourcery under Windows
+    CONFIG_NSH_DHCPC=n                        : DHCP is disabled
+    CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2)   : Target IP address 10.0.0.2
+    CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1) : Host IP address 10.0.0.1
+
+    NOTE:  This example assumes that a network is connected.  During its
+    initialization, it will try to negotiate the link speed.  If you have
+    no network connected when you reset the board, there will be a long
+    delay (maybe 30 seconds?) before anything happens.  That is the timeout
+    before the networking finally gives up and decides that no network is
+    available.
diff --git a/nuttx/configs/px4fmu/common/Make.defs b/nuttx/configs/px4fmu/common/Make.defs
new file mode 100644
index 000000000..00a489eab
--- /dev/null
+++ b/nuttx/configs/px4fmu/common/Make.defs
@@ -0,0 +1,216 @@
+############################################################################
+# configs/px4fmu/common/Make.defs
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+#
+# Generic Make.defs for the PX4FMU
+# Do not specify/use this file directly - it is included by config-specific
+# Make.defs in the per-config directories.
+#
+
+#
+# We only support building with the ARM bare-metal toolchain from
+# https://launchpad.net/gcc-arm-embedded on Windows, Linux or Mac OS.
+#
+
+CROSSDEV		 = arm-none-eabi-
+
+CC			 = $(CROSSDEV)gcc
+CXX			 = $(CROSSDEV)g++
+CPP			 = $(CROSSDEV)gcc -E
+LD			 = $(CROSSDEV)ld
+AR			 = $(CROSSDEV)ar rcs
+NM			 = $(CROSSDEV)nm
+OBJCOPY			 = $(CROSSDEV)objcopy
+OBJDUMP			 = $(CROSSDEV)objdump
+
+MAXOPTIMIZATION		 = -O3
+ARCHCPUFLAGS		 = -mcpu=cortex-m4 \
+			   -mthumb \
+			   -march=armv7e-m \
+			   -mfpu=fpv4-sp-d16 \
+			   -mfloat-abi=hard
+
+
+# enable precise stack overflow tracking
+INSTRUMENTATIONDEFINES	 = -finstrument-functions \
+			   -ffixed-r10
+
+# pull in *just* libm from the toolchain ... this is grody
+LIBM			 = "${shell $(CC) $(ARCHCPUFLAGS) -print-file-name=libm.a}"
+EXTRA_LIBS		+= $(LIBM)
+
+# use our linker script
+LDSCRIPT		 = ld.script
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK		 = $(TOPDIR)/tools/winlink.sh
+  DIRUNLINK		 = $(TOPDIR)/tools/unlink.sh
+  MKDEP			 = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES		 = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES	 = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT		 = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)}"
+else
+  ifeq ($(PX4_WINTOOL),y)
+    # Windows-native toolchains (MSYS)
+    DIRLINK		 = $(TOPDIR)/tools/winlink.sh
+    DIRUNLINK		 = $(TOPDIR)/tools/unlink.sh
+    MKDEP		 = $(TOPDIR)/tools/mknulldeps.sh
+    ARCHINCLUDES	 = -I. -isystem $(TOPDIR)/include
+    ARCHXXINCLUDES	 = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+    ARCHSCRIPT		 = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)
+  else
+    # Linux/Cygwin-native toolchain 
+    MKDEP		 = $(TOPDIR)/tools/mkdeps.sh
+    ARCHINCLUDES	 = -I. -isystem $(TOPDIR)/include
+    ARCHXXINCLUDES	 = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+    ARCHSCRIPT		 = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)
+  endif
+endif
+
+# tool versions
+ARCHCCVERSION		 = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR		 = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+# optimisation flags
+ARCHOPTIMIZATION	 = $(MAXOPTIMIZATION) \
+			   -fno-strict-aliasing \
+			   -fno-strength-reduce \
+			   -fomit-frame-pointer \
+   			   -funsafe-math-optimizations \
+   			   -fno-builtin-printf \
+   			   -ffunction-sections \
+   			   -fdata-sections
+
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
+ARCHOPTIMIZATION	+= -g
+ARCHSCRIPT		+= -g
+endif
+
+ARCHCFLAGS		 = -std=gnu99
+ARCHCXXFLAGS		 = -fno-exceptions -fno-rtti -std=gnu++0x
+ARCHWARNINGS		 = -Wall \
+			   -Wextra \
+			   -Wdouble-promotion \
+			   -Wshadow \
+			   -Wfloat-equal \
+			   -Wframe-larger-than=1024 \
+			   -Wpointer-arith \
+			   -Wlogical-op \
+			   -Wmissing-declarations \
+			   -Wpacked \
+			   -Wno-unused-parameter
+#   -Wcast-qual  - generates spurious noreturn attribute warnings, try again later
+#   -Wconversion - would be nice, but too many "risky-but-safe" conversions in the code
+#   -Wcast-align - would help catch bad casts in some cases, but generates too many false positives
+
+ARCHCWARNINGS		 = $(ARCHWARNINGS) \
+			   -Wbad-function-cast \
+			   -Wstrict-prototypes \
+			   -Wold-style-declaration \
+			   -Wmissing-parameter-type \
+			   -Wmissing-prototypes \
+			   -Wnested-externs \
+			   -Wunsuffixed-float-constants
+ARCHWARNINGSXX		 = $(ARCHWARNINGS)
+ARCHDEFINES		 = 
+ARCHPICFLAGS		 = -fpic -msingle-pic-base -mpic-register=r10
+
+# this seems to be the only way to add linker flags
+ARCHSCRIPT		+= --warn-common \
+			   --gc-sections
+
+CFLAGS			 = $(ARCHCFLAGS) $(ARCHCWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -fno-common
+CPICFLAGS		 = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS		 = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS		 = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS		 = $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS			 = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1		 = -r -d -warn-common
+NXFLATLDFLAGS2		 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections
+LDNXFLATFLAGS		 = -e main -s 2048
+
+OBJEXT			 = .o
+LIBEXT			 = .a
+EXEEXT			 =
+
+# If VERBOSE is set, don't hide the compiler invocations.
+ifeq ($(VERBOSE),YES)
+_v				 =
+else
+_v				 = @
+endif
+
+define PREPROCESS
+	@echo "CPP: $1->$2"
+	@$(CPP) $(CPPFLAGS) $(abspath $1) -o $2
+endef
+
+define COMPILE
+	@echo "CC: $1"
+	$(_v)$(CC) -c $(CFLAGS) $(abspath $1) -o $2
+endef
+
+define COMPILEXX
+	@echo "CXX: $1"
+	$(_v)$(CXX) -c $(CXXFLAGS) $(abspath $1) -o $2
+endef
+
+define ASSEMBLE
+	@echo "AS: $1"
+	$(_v)$(CC) -c $(AFLAGS) $(abspath $1) -o $2
+endef
+
+# produce partially-linked $1 from files in $2
+define PRELINK
+	@echo "PRELINK: $1"
+	@$(LD) -Ur -o $1 $2 && $(OBJCOPY) --localize-hidden $1
+endef
+
+define ARCHIVE
+	echo "AR: $2"; \
+	$(AR) $1 $2 || { echo "$(AR) $1 $2 FAILED!" ; exit 1 ; }
+endef
+
+define CLEAN
+	@rm -f *.o *.a
+endef
+
+HOSTCC			 = gcc
+HOSTINCLUDES		 = -I.
+HOSTCFLAGS		 = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS		 =
+
diff --git a/nuttx/configs/px4fmu/common/ld.script b/nuttx/configs/px4fmu/common/ld.script
new file mode 100644
index 000000000..e3ca771b1
--- /dev/null
+++ b/nuttx/configs/px4fmu/common/ld.script
@@ -0,0 +1,133 @@
+/****************************************************************************
+ * configs/px4fmu/common/ld.script
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F405 has 1024Kb of FLASH beginning at address 0x0800:0000 and
+ * 192Kb of SRAM. SRAM is split up into three blocks:
+ *
+ * 1) 112Kb of SRAM beginning at address 0x2000:0000
+ * 2)  16Kb of SRAM beginning at address 0x2001:c000
+ * 3)  64Kb of TCM SRAM beginning at address 0x1000:0000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ *
+ * The first 0x4000 of flash is reserved for the bootloader.
+ */
+
+MEMORY
+{
+    flash (rx)   : ORIGIN = 0x08004000, LENGTH = 1008K
+    sram (rwx)   : ORIGIN = 0x20000000, LENGTH = 128K
+    ccsram (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+}
+
+OUTPUT_ARCH(arm)
+
+ENTRY(__start)		/* treat __start as the anchor for dead code stripping */
+EXTERN(_vectors)	/* force the vectors to be included in the output */
+
+/* 
+ * Ensure that abort() is present in the final object.  The exception handling
+ * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).
+ */
+EXTERN(abort)
+
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)        
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)        
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+
+		/* 
+		 * This is a hack to make the newlib libm __errno() call
+		 * use the NuttX get_errno_ptr() function.
+		 */
+		__errno = get_errno_ptr;
+	} > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/nuttx/configs/px4fmu/include/board.h b/nuttx/configs/px4fmu/include/board.h
new file mode 100755
index 000000000..0db8580ba
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/board.h
@@ -0,0 +1,392 @@
+/************************************************************************************
+ * configs/px4fmu/include/board.h
+ * include/arch/board/board.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_BOARD_BOARD_H
+#define __ARCH_BOARD_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+//#include "stm32_rcc.h"
+//#include "stm32_sdio.h"
+//#include "stm32_internal.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+/* The PX4FMU uses a 24MHz crystal connected to the HSE.
+ *
+ * This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
+ *   System Clock source           : PLL (HSE)
+ *   SYSCLK(Hz)                    : 168000000    Determined by PLL configuration
+ *   HCLK(Hz)                      : 168000000    (STM32_RCC_CFGR_HPRE)
+ *   AHB Prescaler                 : 1            (STM32_RCC_CFGR_HPRE)
+ *   APB1 Prescaler                : 4            (STM32_RCC_CFGR_PPRE1)
+ *   APB2 Prescaler                : 2            (STM32_RCC_CFGR_PPRE2)
+ *   HSE Frequency(Hz)             : 24000000     (STM32_BOARD_XTAL)
+ *   PLLM                          : 24           (STM32_PLLCFG_PLLM)
+ *   PLLN                          : 336          (STM32_PLLCFG_PLLN)
+ *   PLLP                          : 2            (STM32_PLLCFG_PLLP)
+ *   PLLQ                          : 7            (STM32_PLLCFG_PPQ)
+ *   Main regulator output voltage : Scale1 mode  Needed for high speed SYSCLK
+ *   Flash Latency(WS)             : 5
+ *   Prefetch Buffer               : OFF
+ *   Instruction cache             : ON
+ *   Data cache                    : ON
+ *   Require 48MHz for USB OTG FS, : Enabled
+ *   SDIO and RNG clock
+ */
+
+/* HSI - 16 MHz RC factory-trimmed
+ * LSI - 32 KHz RC
+ * HSE - On-board crystal frequency is 24MHz
+ * LSE - not installed
+ */
+
+#define STM32_BOARD_XTAL        24000000ul
+
+#define STM32_HSI_FREQUENCY     16000000ul
+#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+//#define STM32_LSE_FREQUENCY     32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ *         = (25,000,000 / 25) * 336
+ *         = 336,000,000
+ * SYSCLK  = PLL_VCO / PLLP
+ *         = 336,000,000 / 2 = 168,000,000
+ * USB OTG FS, SDIO and RNG Clock
+ *         =  PLL_VCO / PLLQ
+ *         = 48,000,000
+ */
+
+#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(24)
+#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(336)
+#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PPQ        RCC_PLLCFG_PLLQ(7)
+
+#define STM32_SYSCLK_FREQUENCY  168000000ul
+
+/* AHB clock (HCLK) is SYSCLK (168MHz) */
+
+#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK  /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
+
+/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
+
+/* Timers driven from APB1 will be twice PCLK1 */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
+/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
+
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+
+/* Timers driven from APB2 will be twice PCLK2 */
+
+#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
+/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
+ * otherwise frequency is 2xAPBx. 
+ * Note: TIM1,8 are on APB2, others on APB1
+ */
+
+#define STM32_TIM18_FREQUENCY   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_TIM27_FREQUENCY   (2*STM32_PCLK1_FREQUENCY)
+
+/* SDIO dividers.  Note that slower clocking is required when DMA is disabled 
+ * in order to avoid RX overrun/TX underrun errors due to delayed responses
+ * to service FIFOs in interrupt driven mode.  These values have not been
+ * tuned!!!
+ *
+ * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
+ */
+  
+#define SDIO_INIT_CLKDIV        (178 << SDIO_CLKCR_CLKDIV_SHIFT)
+
+/* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
+ * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_MMCXFR_CLKDIV    (2 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#else
+#  define SDIO_MMCXFR_CLKDIV    (3 << SDIO_CLKCR_CLKDIV_SHIFT) 
+#endif
+
+/* DMA ON:  HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
+ * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_SDXFR_CLKDIV     (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#else
+#  define SDIO_SDXFR_CLKDIV     (3 << SDIO_CLKCR_CLKDIV_SHIFT)
+#endif
+
+/* High-resolution timer
+ */
+#ifdef CONFIG_HRT_TIMER
+# define HRT_TIMER		1	/* use timer1 for the HRT */
+# define HRT_TIMER_CHANNEL	1	/* use capture/compare channel */
+#endif
+
+/* LED definitions ******************************************************************/
+/* PX4 has two LEDs that we will encode as: */
+
+#define LED_STARTED       0  /* LED? */
+#define LED_HEAPALLOCATE  1  /* LED? */
+#define LED_IRQSENABLED   2  /* LED? + LED? */
+#define LED_STACKCREATED  3  /* LED? */
+#define LED_INIRQ         4  /* LED? + LED? */
+#define LED_SIGNAL        5  /* LED? + LED? */
+#define LED_ASSERTION     6  /* LED? + LED? + LED? */
+#define LED_PANIC         7  /* N/C  + N/C  + N/C + LED? */
+
+/* Alternate function pin selections ************************************************/
+
+/*
+ * UARTs.
+ *
+ * Note that UART5 has no optional pinout.
+ */
+#define GPIO_USART1_RX	GPIO_USART1_RX_2
+#define GPIO_USART1_TX	GPIO_USART1_TX_2
+
+#define GPIO_USART2_RX	GPIO_USART2_RX_1
+#define GPIO_USART2_TX	GPIO_USART2_TX_1
+#define GPIO_USART2_RTS	GPIO_USART2_RTS_1
+#define GPIO_USART2_CTS	GPIO_USART2_CTS_1
+
+#define GPIO_USART6_RX	GPIO_USART6_RX_1
+#define GPIO_USART6_TX	GPIO_USART6_TX_1
+
+/* UART DMA configuration for USART1/6 */
+#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
+#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
+
+/*
+ * PWM
+ *
+ * Four PWM outputs can be configured on pins otherwise shared with
+ * USART2; two can take the flow control pins if they are not being used.
+ *
+ * Pins:
+ *
+ * CTS - PA0 - TIM2CH1
+ * RTS - PA1 - TIM2CH2
+ * TX  - PA2 - TIM2CH3
+ * RX  - PA3 - TIM2CH4
+ *
+ */
+#define GPIO_TIM2_CH1OUT	GPIO_TIM2_CH1OUT_1
+#define GPIO_TIM2_CH2OUT	GPIO_TIM2_CH2OUT_1
+#define GPIO_TIM2_CH3OUT	GPIO_TIM2_CH3OUT_1
+#define GPIO_TIM2_CH4OUT	GPIO_TIM2_CH4OUT_1
+
+/*
+ * PPM
+ *
+ * PPM input is handled by the HRT timer.
+ */
+#if defined(CONFIG_HRT_TIMER) && defined (CONFIG_HRT_PPM)
+# define HRT_PPM_CHANNEL	3	/* use capture/compare channel 3 */
+# define GPIO_PPM_IN	(GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN10)
+#endif
+
+/* 
+ * CAN
+ *
+ * CAN2 is routed to the expansion connector.
+ */
+
+#define GPIO_CAN2_RX	GPIO_CAN2_RX_2
+#define GPIO_CAN2_TX	GPIO_CAN2_TX_2
+
+/*
+ * I2C
+ */
+#define GPIO_I2C1_SCL	GPIO_I2C1_SCL_2
+#define GPIO_I2C1_SDA	GPIO_I2C1_SDA_2
+
+#define GPIO_I2C2_SCL	GPIO_I2C2_SCL_1
+#define GPIO_I2C2_SDA	GPIO_I2C2_SDA_1
+
+#define GPIO_I2C3_SCL	GPIO_I2C3_SCL_1
+#define GPIO_I2C3_SDA	GPIO_I2C3_SDA_1
+
+/*
+ * I2C busses
+ */
+#define PX4_I2C_BUS_ESC		1
+#define PX4_I2C_BUS_ONBOARD	2
+#define PX4_I2C_BUS_EXPANSION	3
+
+/*
+ * Devices on the onboard bus.
+ *
+ * Note that these are unshifted addresses.
+ */
+#define PX4_I2C_OBDEV_HMC5883	0x1e
+#define PX4_I2C_OBDEV_MS5611	NOTDEFINED
+#define PX4_I2C_OBDEV_EEPROM	0x50
+
+#define PX4_I2C_OBDEV_PX4IO_BL	0x18
+#define PX4_I2C_OBDEV_PX4IO	0x19
+
+/*
+ * SPI
+ */
+#define GPIO_SPI1_MISO	GPIO_SPI1_MISO_1
+#define GPIO_SPI1_MOSI	GPIO_SPI1_MOSI_1
+#define GPIO_SPI1_SCK	GPIO_SPI1_SCK_1
+
+#define GPIO_SPI3_MISO	GPIO_SPI3_MISO_2
+#define GPIO_SPI3_MOSI	GPIO_SPI3_MOSI_1
+#define GPIO_SPI3_SCK	GPIO_SPI3_SCK_2
+#define GPIO_SPI3_NSS	GPIO_SPI3_NSS_2
+
+/*
+ * Use these in place of the spi_dev_e enumeration to
+ * select a specific SPI device on SPI1
+ */
+#define PX4_SPIDEV_GYRO		1
+#define PX4_SPIDEV_ACCEL	2
+#define PX4_SPIDEV_MPU		3
+
+/*
+ * Tone alarm output
+ */
+#ifdef CONFIG_TONE_ALARM
+# define TONE_ALARM_TIMER	3	/* timer 3 */
+# define TONE_ALARM_CHANNEL	3	/* channel 3 */
+# define GPIO_TONE_ALARM	(GPIO_ALT|GPIO_AF2|GPIO_SPEED_2MHz|GPIO_FLOAT|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
+#endif
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the intitialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+EXTERN void stm32_boardinitialize(void);
+
+/************************************************************************************
+ * Button support.
+ *
+ * Description:
+ *   up_buttoninit() must be called to initialize button resources.  After
+ *   that, up_buttons() may be called to collect the current state of all
+ *   buttons or up_irqbutton() may be called to register button interrupt
+ *   handlers.
+ *
+ *   After up_buttoninit() has been called, up_buttons() may be called to
+ *   collect the state of all buttons.  up_buttons() returns an 8-bit bit set
+ *   with each bit associated with a button.  See the BUTTON_*_BIT
+ *   definitions in board.h for the meaning of each bit.
+ *
+ *   up_irqbutton() may be called to register an interrupt handler that will
+ *   be called when a button is depressed or released.  The ID value is a
+ *   button enumeration value that uniquely identifies a button resource. See the
+ *   BUTTON_* definitions in board.h for the meaning of enumeration
+ *   value.  The previous interrupt handler address is returned (so that it may
+ *   restored, if so desired).
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_BUTTONS
+EXTERN void up_buttoninit(void);
+EXTERN uint8_t up_buttons(void);
+#ifdef CONFIG_ARCH_IRQBUTTONS
+EXTERN xcpt_t up_irqbutton(int id, xcpt_t irqhandler);
+#endif
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif  /* __ARCH_BOARD_BOARD_H */
diff --git a/nuttx/configs/px4fmu/include/drv_bma180.h b/nuttx/configs/px4fmu/include/drv_bma180.h
new file mode 100644
index 000000000..a403415e4
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_bma180.h
@@ -0,0 +1,99 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the BOSCH BMA180 MEMS accelerometer
+ */
+
+/* IMPORTANT NOTES:
+ *
+ * SPI max. clock frequency: 25 Mhz
+ * CS has to be high before transfer,
+ * go low right before transfer and
+ * go high again right after transfer
+ *
+ */
+
+#include <sys/ioctl.h>
+
+#define _BMA180BASE	0x6300
+#define BMA180C(_x)	_IOC(_BMA180BASE, _x)
+
+/* 
+ * Sets the sensor internal sampling rate, and if a buffer
+ * has been configured, the rate at which entries will be
+ * added to the buffer.
+ */
+#define BMA180_SETRATE		BMA180C(1)
+
+#define BMA180_RATE_LP_10HZ		(0<<4)
+#define BMA180_RATE_LP_20HZ		(1<<4)
+#define BMA180_RATE_LP_40HZ		(2<<4)
+#define BMA180_RATE_LP_75HZ		(3<<4)
+#define BMA180_RATE_LP_150HZ	(4<<4)
+#define BMA180_RATE_LP_300HZ	(5<<4)
+#define BMA180_RATE_LP_600HZ	(6<<4)
+#define BMA180_RATE_LP_1200HZ	(7<<4)
+
+/*
+ * Sets the sensor internal range.
+ */
+#define BMA180_SETRANGE		BMA180C(2)
+
+#define BMA180_RANGE_1G			(0<<1)
+#define BMA180_RANGE_1_5G		(1<<1)
+#define BMA180_RANGE_2G			(2<<1)
+#define BMA180_RANGE_3G			(3<<1)
+#define BMA180_RANGE_4G			(4<<1)
+#define BMA180_RANGE_8G			(5<<1)
+#define BMA180_RANGE_16G		(6<<1)
+
+/*
+ * Sets the address of a shared BMA180_buffer
+ * structure that is maintained by the driver.
+ *
+ * If zero is passed as the address, disables
+ * the buffer updating.
+ */
+#define BMA180_SETBUFFER	BMA180C(3)
+
+struct bma180_buffer {
+	uint32_t	size;		/* number of entries in the samples[] array */
+	uint32_t	next;		/* the next entry that will be populated */
+	struct {
+		uint16_t	x;
+		uint16_t	y;
+		uint16_t	z;
+		uint8_t		temp;
+	} samples[];
+};
+
+extern int	bma180_attach(struct spi_dev_s *spi, int spi_id);
diff --git a/nuttx/configs/px4fmu/include/drv_eeprom.h b/nuttx/configs/px4fmu/include/drv_eeprom.h
new file mode 100644
index 000000000..e6801f6c4
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_eeprom.h
@@ -0,0 +1,73 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Driver for the ST MS5611 gyroscope
+ */
+
+/* IMPORTANT NOTES:
+ *
+ * SPI max. clock frequency: 10 Mhz
+ * CS has to be high before transfer,
+ * go low right before transfer and
+ * go high again right after transfer
+ *
+ */
+
+/* IMPORTANT: Adjust this number! */
+#define MAX_EEPROMS									2
+
+/* FMU onboard */
+#define FMU_ONBOARD_EEPROM_ADDRESS					0x50
+#define FMU_ONBOARD_EEPROM_TOTAL_SIZE_BYTES			16000
+#define FMU_ONBOARD_EEPROM_PAGE_SIZE_BYTES			64
+#define FMU_ONBOARD_EEPROM_PAGE_WRITE_TIME_US		5500
+#define FMU_ONBOARD_EEPROM_BUS_CLOCK				1000000   ///< 1 Mhz max. clock
+
+#define FMU_BASEBOARD_EEPROM_ADDRESS				0x57
+#define FMU_BASEBOARD_EEPROM_TOTAL_SIZE_BYTES		128
+#define FMU_BASEBOARD_EEPROM_PAGE_SIZE_BYTES		8
+#define FMU_BASEBOARD_EEPROM_PAGE_WRITE_TIME_US		3300
+#define FMU_BASEBOARD_EEPROM_BUS_CLOCK				400000    ///< 400 KHz max. clock
+
+/**
+ * @brief i2c I2C bus struct
+ * @brief device_address The device address as stated in the datasheet, e.g. for a Microchip 24XX128 0x50 with all ID pins tied to GND
+ * @brief total_size_bytes The total size in bytes, e.g. 16K = 16000 bytes for the Microchip 24XX128
+ * @brief page_size_bytes The size of one page, e.g. 64 bytes for the Microchip 24XX128
+ * @brief device_name The device name to register this device to, e.g. /dev/eeprom
+ * @brief fail_if_missing Returns error if the EEPROM was not found. This is helpful if the EEPROM might be attached later when the board is running
+ */
+extern int
+eeprom_attach(struct i2c_dev_s *i2c, uint8_t device_address, uint16_t total_size_bytes, uint16_t page_size_bytes, uint16_t page_write_time_us, const char* device_name, uint8_t fail_if_missing);
+
diff --git a/nuttx/configs/px4fmu/include/drv_gpio.h b/nuttx/configs/px4fmu/include/drv_gpio.h
new file mode 100644
index 000000000..22f80d038
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_gpio.h
@@ -0,0 +1,107 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file GPIO driver interface.
+ *
+ * This header defines the basic interface to platform-specific GPIOs.
+ */
+
+#ifndef _BOARD_DRV_GPIO_H
+#define _BOARD_DRV_GPIO_H
+
+/*
+ * PX4FMU GPIO numbers.
+ *
+ * For shared pins, alternate function 1 selects the non-GPIO mode 
+ * (USART2, CAN2, etc.)
+ */
+#define GPIO_EXT_1		(1<<0)		/**< high-power GPIO 1 */
+#define GPIO_EXT_2		(1<<1)		/**< high-power GPIO 1 */
+#define GPIO_MULTI_1		(1<<2)		/**< USART2 CTS */
+#define GPIO_MULTI_2		(1<<3)		/**< USART2 RTS */
+#define GPIO_MULTI_3		(1<<4)		/**< USART2 TX */
+#define GPIO_MULTI_4		(1<<5)		/**< USART2 RX */
+#define GPIO_CAN_TX		(1<<6)		/**< CAN2 TX */
+#define GPIO_CAN_RX		(1<<7)		/**< CAN2 RX */
+
+/**
+ * Default GPIO device - other devices may also support this protocol if
+ * they also export GPIO-like things.  This is always the GPIOs on the
+ * main board.
+ */
+#define GPIO_DEVICE_PATH	"/dev/gpio"
+
+/*
+ * IOCTL definitions.
+ *
+ * For all ioctls, the (arg) argument is a bitmask of GPIOs to be affected
+ * by the operation, with the LSB being the lowest-numbered GPIO.
+ *
+ * Note that there may be board-specific relationships between GPIOs;
+ * applications using GPIOs should be aware of this.
+ */
+#define _GPIOCBASE	0x6700
+#define GPIOC(_x)	_IOC(_GPIOCBASE, _x)
+
+/** reset all board GPIOs to their default state */
+#define GPIO_RESET	GPIOC(0)
+
+/** configure the board GPIOs in (arg) as outputs */
+#define GPIO_SET_OUTPUT	GPIOC(1)
+
+/** configure the board GPIOs in (arg) as inputs */
+#define GPIO_SET_INPUT	GPIOC(2)
+
+/** configure the board GPIOs in (arg) for the first alternate function (if supported) */
+#define GPIO_SET_ALT_1	GPIOC(3)
+
+/** configure the board GPIO (arg) for the second alternate function (if supported) */
+#define GPIO_SET_ALT_2	GPIOC(4)
+
+/** configure the board GPIO (arg) for the third alternate function (if supported) */
+#define GPIO_SET_ALT_3	GPIOC(5)
+
+/** configure the board GPIO (arg) for the fourth alternate function (if supported) */
+#define GPIO_SET_ALT_4	GPIOC(6)
+
+/** set the GPIOs in (arg) */
+#define GPIO_SET	GPIOC(10)
+
+/** clear the GPIOs in (arg) */
+#define GPIO_CLEAR	GPIOC(11)
+
+/** read all the GPIOs and return their values in *(uint32_t *)arg */
+#define GPIO_GET	GPIOC(12)
+
+#endif /* _DRV_GPIO_H */
diff --git a/nuttx/configs/px4fmu/include/drv_hmc5883l.h b/nuttx/configs/px4fmu/include/drv_hmc5883l.h
new file mode 100644
index 000000000..8dc9b8a93
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_hmc5883l.h
@@ -0,0 +1,100 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Driver for the ST HMC5883L gyroscope
+ */
+
+/* IMPORTANT NOTES:
+ *
+ * SPI max. clock frequency: 10 Mhz
+ * CS has to be high before transfer,
+ * go low right before transfer and
+ * go high again right after transfer
+ *
+ */
+
+#include <sys/ioctl.h>
+
+#define _HMC5883LBASE	0x6100
+#define HMC5883LC(_x)	_IOC(_HMC5883LBASE, _x)
+
+/* 
+ * Sets the sensor internal sampling rate, and if a buffer
+ * has been configured, the rate at which entries will be
+ * added to the buffer.
+ */
+#define HMC5883L_SETRATE		HMC5883LC(1)
+
+/* set rate (configuration A register */
+#define HMC5883L_RATE_0_75HZ		(0 << 2) /* 0.75 Hz */
+#define HMC5883L_RATE_1_50HZ		(1 << 2) /* 1.5 Hz */
+#define HMC5883L_RATE_3_00HZ		(2 << 2) /* 3 Hz */
+#define HMC5883L_RATE_7_50HZ		(3 << 2) /* 7.5 Hz */
+#define HMC5883L_RATE_15HZ			(4 << 2) /* 15 Hz (default) */
+#define HMC5883L_RATE_30HZ			(5 << 2) /* 30 Hz */
+#define HMC5883L_RATE_75HZ			(6 << 2) /* 75 Hz */
+
+/*
+ * Sets the sensor internal range.
+ */
+#define HMC5883L_SETRANGE		HMC5883LC(2)
+
+#define HMC5883L_RANGE_0_88GA			(0 << 5)
+#define HMC5883L_RANGE_1_33GA			(1 << 5)
+#define HMC5883L_RANGE_1_90GA			(2 << 5)
+#define HMC5883L_RANGE_2_50GA			(3 << 5)
+#define HMC5883L_RANGE_4_00GA			(4 << 5)
+
+/*
+ * Sets the address of a shared HMC5883L_buffer
+ * structure that is maintained by the driver.
+ *
+ * If zero is passed as the address, disables
+ * the buffer updating.
+ */
+#define HMC5883L_SETBUFFER	HMC5883LC(3)
+
+struct hmc5883l_buffer {
+	uint32_t	size;		/* number of entries in the samples[] array */
+	uint32_t	next;		/* the next entry that will be populated */
+	struct {
+		int16_t	x;
+		int16_t	y;
+		int16_t	z;
+	} samples[];
+};
+
+#define HMC5883L_RESET		HMC5883LC(4)
+
+extern int	hmc5883l_attach(struct i2c_dev_s *i2c);
diff --git a/nuttx/configs/px4fmu/include/drv_l3gd20.h b/nuttx/configs/px4fmu/include/drv_l3gd20.h
new file mode 100644
index 000000000..3b284d60d
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_l3gd20.h
@@ -0,0 +1,108 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/*
+ * Driver for the ST L3GD20 gyroscope
+ */
+
+/* IMPORTANT NOTES:
+ *
+ * SPI max. clock frequency: 10 Mhz
+ * CS has to be high before transfer,
+ * go low right before transfer and
+ * go high again right after transfer
+ *
+ */
+
+#include <sys/ioctl.h>
+
+#define _L3GD20BASE	0x6200
+#define L3GD20C(_x)	_IOC(_L3GD20BASE, _x)
+
+/* 
+ * Sets the sensor internal sampling rate, and if a buffer
+ * has been configured, the rate at which entries will be
+ * added to the buffer.
+ */
+#define L3GD20_SETRATE		L3GD20C(1)
+
+#define L3GD20_RATE_95HZ_LP_12_5HZ		((0<<7) | (0<<6) | (0<<5) | (0<<4))
+#define L3GD20_RATE_95HZ_LP_25HZ		((0<<7) | (0<<6) | (0<<5) | (1<<4))
+#define L3GD20_RATE_190HZ_LP_12_5HZ		((0<<7) | (1<<6) | (0<<5) | (0<<4))
+#define L3GD20_RATE_190HZ_LP_25HZ		((0<<7) | (1<<6) | (0<<5) | (1<<4))
+#define L3GD20_RATE_190HZ_LP_50HZ		((0<<7) | (1<<6) | (1<<5) | (0<<4))
+#define L3GD20_RATE_190HZ_LP_70HZ		((0<<7) | (1<<6) | (1<<5) | (1<<4))
+#define L3GD20_RATE_380HZ_LP_20HZ		((1<<7) | (0<<6) | (0<<5) | (0<<4))
+#define L3GD20_RATE_380HZ_LP_25HZ		((1<<7) | (0<<6) | (0<<5) | (1<<4))
+#define L3GD20_RATE_380HZ_LP_50HZ		((1<<7) | (0<<6) | (1<<5) | (0<<4))
+#define L3GD20_RATE_380HZ_LP_100HZ		((1<<7) | (0<<6) | (1<<5) | (1<<4))
+#define L3GD20_RATE_760HZ_LP_30HZ		((1<<7) | (1<<6) | (0<<5) | (0<<4))
+#define L3GD20_RATE_760HZ_LP_35HZ		((1<<7) | (1<<6) | (0<<5) | (1<<4))
+#define L3GD20_RATE_760HZ_LP_50HZ		((1<<7) | (1<<6) | (1<<5) | (0<<4))
+#define L3GD20_RATE_760HZ_LP_100HZ		((1<<7) | (1<<6) | (1<<5) | (1<<4))
+
+/*
+ * Sets the sensor internal range.
+ */
+#define L3GD20_SETRANGE		L3GD20C(2)
+
+#define L3GD20_RANGE_250DPS			(0<<4)
+#define L3GD20_RANGE_500DPS			(1<<4)
+#define L3GD20_RANGE_2000DPS		(3<<4)
+
+#define L3GD20_RATE_95HZ			((0<<6) | (0<<4))
+#define L3GD20_RATE_190HZ			((1<<6) | (0<<4))
+#define L3GD20_RATE_380HZ			((2<<6) | (1<<4))
+#define L3GD20_RATE_760HZ			((3<<6) | (2<<4))
+
+
+
+/*
+ * Sets the address of a shared l3gd20_buffer
+ * structure that is maintained by the driver.
+ *
+ * If zero is passed as the address, disables
+ * the buffer updating.
+ */
+#define L3GD20_SETBUFFER	L3GD20C(3)
+
+struct l3gd20_buffer {
+	uint32_t	size;		/* number of entries in the samples[] array */
+	uint32_t	next;		/* the next entry that will be populated */
+	struct {
+		int16_t	x;
+		int16_t	y;
+		int16_t	z;
+	} samples[];
+};
+
+extern int	l3gd20_attach(struct spi_dev_s *spi, int spi_id);
diff --git a/nuttx/configs/px4fmu/include/drv_led.h b/nuttx/configs/px4fmu/include/drv_led.h
new file mode 100644
index 000000000..4b7093346
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_led.h
@@ -0,0 +1,51 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#include <sys/ioctl.h>
+
+#define _LEDCBASE	0x6800
+#define LEDC(_x)	_IOC(_LEDCBASE, _x)
+
+/* set the LED identified by the argument */
+#define LED_ON	LEDC(1)
+
+/* clear the LED identified by the argument */
+#define LED_OFF	LEDC(2)
+
+///* toggle the LED identified by the argument */
+//#define LED_TOGGLE	LEDC(3)
+
+#define LED_BLUE		  0  /* Led on first port */
+#define LED_AMBER		  1  /* Led on second port */
+
+extern int	px4fmu_led_init(void);
diff --git a/nuttx/configs/px4fmu/include/drv_lis331.h b/nuttx/configs/px4fmu/include/drv_lis331.h
new file mode 100644
index 000000000..f4699cda0
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_lis331.h
@@ -0,0 +1,83 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Driver for the ST LIS331 MEMS accelerometer
+ */
+
+#include <sys/ioctl.h>
+
+#define _LIS331BASE	0x6900
+#define LIS331C(_x)	_IOC(_LIS331BASE, _x)
+
+/* 
+ * Sets the sensor internal sampling rate, and if a buffer
+ * has been configured, the rate at which entries will be
+ * added to the buffer.
+ */
+#define LIS331_SETRATE		LIS331C(1)
+
+#define LIS331_RATE_50Hz		(0<<3)
+#define LIS331_RATE_100Hz		(1<<3)
+#define LIS331_RATE_400Hz		(2<<3)
+#define LIS331_RATE_1000Hz		(3<<3)
+
+/*
+ * Sets the sensor internal range.
+ */
+#define LIS331_SETRANGE		LIS331C(2)
+
+#define LIS331_RANGE_2G			(0<<4)
+#define LIS331_RANGE_4G			(1<<4)
+#define LIS331_RANGE_8G			(3<<4)
+
+/*
+ * Sets the address of a shared lis331_buffer
+ * structure that is maintained by the driver.
+ *
+ * If zero is passed as the address, disables
+ * the buffer updating.
+ */
+#define LIS331_SETBUFFER	LIS331C(3)
+
+struct lis331_buffer {
+	uint32_t	size;		/* number of entries in the samples[] array */
+	uint32_t	next;		/* the next entry that will be populated */
+	struct {
+		uint16_t	x;
+		uint16_t	y;
+		uint16_t	z;
+	} samples[];
+};
+
+extern int	lis331_attach(struct spi_dev_s *spi, int spi_id);
diff --git a/nuttx/configs/px4fmu/include/drv_mpu6000.h b/nuttx/configs/px4fmu/include/drv_mpu6000.h
new file mode 100644
index 000000000..0a5a48b70
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_mpu6000.h
@@ -0,0 +1,92 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the Invense MPU-6000 gyroscope
+ */
+
+/* IMPORTANT NOTES:
+ *
+ * SPI max. clock frequency: 10 Mhz
+ * CS has to be high before transfer,
+ * go low right before transfer and
+ * go high again right after transfer
+ *
+ */
+
+#include <sys/ioctl.h>
+
+#define _MPU6000BASE	0x7600
+#define MPU6000C(_x)	_IOC(_MPU6000BASE, _x)
+
+/* 
+ * Sets the sensor internal sampling rate, and if a buffer
+ * has been configured, the rate at which entries will be
+ * added to the buffer.
+ */
+#define MPU6000_SETRATE		MPU6000C(1)
+
+#define MPU6000_RATE_95HZ_LP_12_5HZ		((0<<7) | (0<<6) | (0<<5) | (0<<4))
+
+/*
+ * Sets the sensor internal range.
+ */
+#define MPU6000_SETRANGE		MPU6000C(2)
+
+#define MPU6000_RANGE_250DPS			(0<<4)
+
+#define MPU6000_RATE_95HZ			((0<<6) | (0<<4))
+
+
+
+/*
+ * Sets the address of a shared MPU6000_buffer
+ * structure that is maintained by the driver.
+ *
+ * If zero is passed as the address, disables
+ * the buffer updating.
+ */
+#define MPU6000_SETBUFFER	MPU6000C(3)
+
+struct MPU6000_buffer {
+	uint32_t	size;		/* number of entries in the samples[] array */
+	uint32_t	next;		/* the next entry that will be populated */
+	struct {
+		uint16_t	x;
+		uint16_t	y;
+		uint16_t	z;
+		uint16_t	roll;
+		uint16_t	pitch;
+		uint16_t	yaw;
+	} samples[];
+};
+
+extern int	mpu6000_attach(struct spi_dev_s *spi, int spi_id);
diff --git a/nuttx/configs/px4fmu/include/drv_ms5611.h b/nuttx/configs/px4fmu/include/drv_ms5611.h
new file mode 100644
index 000000000..922a11219
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_ms5611.h
@@ -0,0 +1,76 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the Meas Spec MS5611 barometric pressure sensor
+ */
+
+#include <sys/ioctl.h>
+
+#define _MS5611BASE	0x6A00
+#define MS5611C(_x)	_IOC(_MS5611BASE, _x)
+
+/* 
+ * Sets the sensor internal sampling rate, and if a buffer
+ * has been configured, the rate at which entries will be
+ * added to the buffer.
+ */
+#define MS5611_SETRATE		MS5611C(1)
+
+/* set rate (configuration A register */
+#define MS5611_RATE_0_75HZ		(0 << 2) /* 0.75 Hz */
+
+/*
+ * Sets the sensor internal range.
+ */
+#define MS5611_SETRANGE		MS5611C(2)
+
+#define MS5611_RANGE_0_88GA			(0 << 5)
+
+/*
+ * Sets the address of a shared MS5611_buffer
+ * structure that is maintained by the driver.
+ *
+ * If zero is passed as the address, disables
+ * the buffer updating.
+ */
+#define MS5611_SETBUFFER	MS5611C(3)
+
+struct ms5611_buffer {
+	uint32_t	size;		/* number of entries in the samples[] array */
+	uint32_t	next;		/* the next entry that will be populated */
+	struct {
+		uint32_t	pressure;
+		uint16_t temperature;
+	} samples[];
+};
+
+extern int	ms5611_attach(struct i2c_dev_s *i2c);
diff --git a/nuttx/configs/px4fmu/include/drv_tone_alarm.h b/nuttx/configs/px4fmu/include/drv_tone_alarm.h
new file mode 100644
index 000000000..b24c85c8d
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/drv_tone_alarm.h
@@ -0,0 +1,130 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Driver for the PX4 audio alarm port, /dev/tone_alarm.
+ *
+ * The tone_alarm driver supports a set of predefined "alarm" 
+ * patterns and one user-supplied pattern.  Patterns are ordered by 
+ * priority, with a higher-priority pattern interrupting any
+ * lower-priority pattern that might be playing.
+ *
+ * The TONE_SET_ALARM ioctl can be used to select a predefined
+ * alarm pattern, from 1 - <TBD>.  Selecting pattern zero silences
+ * the alarm.
+ *
+ * To supply a custom pattern, write an array of 1 - <TBD> tone_note
+ * structures to /dev/tone_alarm.  The custom pattern has a priority
+ * of zero.
+ *
+ * Patterns will normally play once and then silence (if a pattern
+ * was overridden it will not resume).  A pattern may be made to
+ * repeat by inserting a note with the duration set to
+ * DURATION_REPEAT.  This pattern will loop until either a
+ * higher-priority pattern is started or pattern zero is requested
+ * via the ioctl.
+ */
+
+#ifndef DRV_TONE_ALARM_H_
+#define DRV_TONE_ALARM_H_
+
+#include <sys/ioctl.h>
+
+#define _TONE_ALARM_BASE	0x7400
+#define TONE_SET_ALARM		_IOC(_TONE_ALARM_BASE, 1)
+
+extern int	tone_alarm_init(void);
+
+/* structure describing one note in a tone pattern */
+struct tone_note {
+	uint8_t		pitch;
+	uint8_t		duration;	/* duration in multiples of 10ms */
+#define DURATION_END		0	/* ends the pattern */
+#define DURATION_REPEAT		255	/* resets the note counter to zero */
+};
+
+enum tone_pitch {
+	TONE_NOTE_E4,   /* E4 */
+	TONE_NOTE_F4,   /* F4 */
+	TONE_NOTE_F4S,  /* F#4/Gb4 */
+	TONE_NOTE_G4,   /* G4 */
+	TONE_NOTE_G4S,  /* G#4/Ab4 */
+	TONE_NOTE_A4,   /* A4 */
+	TONE_NOTE_A4S,  /* A#4/Bb4 */
+	TONE_NOTE_B4,   /* B4 */
+	TONE_NOTE_C5,   /* C5 */
+	TONE_NOTE_C5S,  /* C#5/Db5 */
+	TONE_NOTE_D5,   /* D5 */
+	TONE_NOTE_D5S,  /* D#5/Eb5 */
+	TONE_NOTE_E5,   /* E5 */
+	TONE_NOTE_F5,   /* F5 */
+	TONE_NOTE_F5S,  /* F#5/Gb5 */
+	TONE_NOTE_G5,   /* G5 */
+	TONE_NOTE_G5S,  /* G#5/Ab5 */
+	TONE_NOTE_A5,   /* A5 */
+	TONE_NOTE_A5S,  /* A#5/Bb5 */
+	TONE_NOTE_B5,   /* B5 */
+	TONE_NOTE_C6,   /* C6 */
+	TONE_NOTE_C6S,  /* C#6/Db6 */
+	TONE_NOTE_D6,   /* D6 */
+	TONE_NOTE_D6S,  /* D#6/Eb6 */
+	TONE_NOTE_E6,   /* E6 */
+	TONE_NOTE_F6,   /* F6 */
+	TONE_NOTE_F6S,  /* F#6/Gb6 */
+	TONE_NOTE_G6,   /* G6 */
+	TONE_NOTE_G6S,  /* G#6/Ab6 */
+	TONE_NOTE_A6,   /* A6 */
+	TONE_NOTE_A6S,  /* A#6/Bb6 */
+	TONE_NOTE_B6,   /* B6 */
+	TONE_NOTE_C7,   /* C7 */
+	TONE_NOTE_C7S,  /* C#7/Db7 */
+	TONE_NOTE_D7,   /* D7 */
+	TONE_NOTE_D7S,  /* D#7/Eb7 */
+	TONE_NOTE_E7,   /* E7 */
+	TONE_NOTE_F7,   /* F7 */
+	TONE_NOTE_F7S,  /* F#7/Gb7 */
+	TONE_NOTE_G7,   /* G7 */
+	TONE_NOTE_G7S,  /* G#7/Ab7 */
+	TONE_NOTE_A7,   /* A7 */
+	TONE_NOTE_A7S,  /* A#7/Bb7 */
+	TONE_NOTE_B7,   /* B7 */
+	TONE_NOTE_C8,   /* C8 */
+	TONE_NOTE_C8S,  /* C#8/Db8 */
+	TONE_NOTE_D8,   /* D8 */
+	TONE_NOTE_D8S,  /* D#8/Eb8 */
+
+	TONE_NOTE_SILENCE,
+	TONE_NOTE_MAX
+};
+
+#endif /* DRV_TONE_ALARM_H_ */
\ No newline at end of file
diff --git a/nuttx/configs/px4fmu/include/nsh_romfsimg.h b/nuttx/configs/px4fmu/include/nsh_romfsimg.h
new file mode 100644
index 000000000..799670c4d
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/nsh_romfsimg.h
@@ -0,0 +1,601 @@
+unsigned char romfs_img[] = {
+  0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x18, 0x90,
+  0xc0, 0x84, 0x3c, 0x72, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56,
+  0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49,
+  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97,
+  0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20,
+  0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,
+  0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0,
+  0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x00,
+  0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x20,
+  0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x20, 0x2e, 0x2e, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x01, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
+  0xaf, 0xce, 0x68, 0x4d, 0x72, 0x63, 0x2e, 0x6c, 0x6f, 0x67, 0x67, 0x69,
+  0x6e, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x21, 0x6e, 0x73,
+  0x68, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x49, 0x6e, 0x69, 0x74, 0x69, 0x61,
+  0x6c, 0x69, 0x73, 0x65, 0x20, 0x6c, 0x6f, 0x67, 0x67, 0x69, 0x6e, 0x67,
+  0x20, 0x73, 0x65, 0x72, 0x76, 0x69, 0x63, 0x65, 0x73, 0x2e, 0x0a, 0x23,
+  0x0a, 0x0a, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x2d, 0x64, 0x20, 0x2f, 0x66,
+  0x73, 0x2f, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x73, 0x64, 0x20, 0x5d, 0x0a,
+  0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x23, 0x20, 0x58, 0x58, 0x58, 0x20,
+  0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20,
+  0x62, 0x65, 0x20, 0x27, 0x3c, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64,
+  0x3e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27, 0x2e, 0x0a, 0x09, 0x23,
+  0x20, 0x73, 0x64, 0x6c, 0x6f, 0x67, 0x20, 0x26, 0x0a, 0x66, 0x69, 0x0a,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x72, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x03, 0xe9, 0x35, 0x68, 0x7f, 0x06, 0x72, 0x63, 0x2e, 0x50,
+  0x58, 0x34, 0x49, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x23, 0x21, 0x6e, 0x73, 0x68, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x46, 0x6c,
+  0x69, 0x67, 0x68, 0x74, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70,
+  0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x66, 0x6f, 0x72, 0x20,
+  0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x20, 0x77, 0x69, 0x74, 0x68, 0x20,
+  0x50, 0x58, 0x34, 0x49, 0x4f, 0x20, 0x63, 0x61, 0x72, 0x72, 0x69, 0x65,
+  0x72, 0x20, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x2e, 0x0a, 0x23, 0x0a, 0x0a,
+  0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d,
+  0x20, 0x64, 0x6f, 0x69, 0x6e, 0x67, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f,
+  0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x2e, 0x2e, 0x2e, 0x22,
+  0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20,
+  0x74, 0x68, 0x65, 0x20, 0x4f, 0x52, 0x42, 0x0a, 0x23, 0x0a, 0x75, 0x6f,
+  0x72, 0x62, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x0a, 0x0a, 0x23, 0x0a,
+  0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20,
+  0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x73, 0x2e, 0x0a, 0x23, 0x0a, 0x73,
+  0x68, 0x20, 0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e,
+  0x64, 0x2f, 0x72, 0x63, 0x2e, 0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x73,
+  0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20,
+  0x4d, 0x41, 0x56, 0x4c, 0x69, 0x6e, 0x6b, 0x0a, 0x23, 0x0a, 0x6d, 0x61,
+  0x76, 0x6c, 0x69, 0x6e, 0x6b, 0x20, 0x2d, 0x64, 0x20, 0x2f, 0x64, 0x65,
+  0x76, 0x2f, 0x74, 0x74, 0x79, 0x53, 0x30, 0x20, 0x2d, 0x62, 0x20, 0x35,
+  0x37, 0x36, 0x30, 0x30, 0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x6f,
+  0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x65, 0x72, 0x2e, 0x0a, 0x23, 0x0a, 0x23,
+  0x20, 0x58, 0x58, 0x58, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68,
+  0x6f, 0x75, 0x6c, 0x64, 0x20, 0x62, 0x65, 0x20, 0x27, 0x3c, 0x63, 0x6f,
+  0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x3e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74,
+  0x27, 0x2e, 0x0a, 0x23, 0x0a, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64,
+  0x65, 0x72, 0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74,
+  0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x61, 0x74, 0x74, 0x69,
+  0x74, 0x75, 0x64, 0x65, 0x20, 0x65, 0x73, 0x74, 0x69, 0x6d, 0x61, 0x74,
+  0x6f, 0x72, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58, 0x58, 0x20, 0x74,
+  0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x62,
+  0x65, 0x20, 0x27, 0x3c, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x3e,
+  0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27, 0x2e, 0x0a, 0x23, 0x0a, 0x61,
+  0x74, 0x74, 0x69, 0x74, 0x75, 0x64, 0x65, 0x5f, 0x65, 0x73, 0x74, 0x69,
+  0x6d, 0x61, 0x74, 0x6f, 0x72, 0x5f, 0x62, 0x6d, 0x20, 0x26, 0x0a, 0x23,
+  0x70, 0x6f, 0x73, 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x65, 0x73, 0x74,
+  0x69, 0x6d, 0x61, 0x74, 0x6f, 0x72, 0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a,
+  0x23, 0x20, 0x43, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x65, 0x20,
+  0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x6f,
+  0x70, 0x65, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x77, 0x69, 0x74,
+  0x68, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x58, 0x58, 0x58, 0x20, 0x61, 0x72, 0x67, 0x75, 0x6d, 0x65, 0x6e, 0x74,
+  0x73, 0x3f, 0x0a, 0x23, 0x0a, 0x70, 0x78, 0x34, 0x66, 0x6d, 0x75, 0x20,
+  0x73, 0x74, 0x61, 0x72, 0x74, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53,
+  0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x66, 0x69, 0x78,
+  0x65, 0x64, 0x2d, 0x77, 0x69, 0x6e, 0x67, 0x20, 0x63, 0x6f, 0x6e, 0x74,
+  0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58,
+  0x58, 0x58, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75,
+  0x6c, 0x64, 0x20, 0x62, 0x65, 0x20, 0x27, 0x3c, 0x63, 0x6f, 0x6d, 0x6d,
+  0x61, 0x6e, 0x64, 0x3e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27, 0x2e,
+  0x0a, 0x23, 0x0a, 0x66, 0x69, 0x78, 0x65, 0x64, 0x77, 0x69, 0x6e, 0x67,
+  0x5f, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x20, 0x26, 0x0a, 0x0a,
+  0x23, 0x0a, 0x23, 0x20, 0x46, 0x69, 0x72, 0x65, 0x20, 0x75, 0x70, 0x20,
+  0x74, 0x68, 0x65, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x20, 0x69, 0x6e,
+  0x74, 0x65, 0x72, 0x66, 0x61, 0x63, 0x65, 0x2e, 0x0a, 0x23, 0x0a, 0x70,
+  0x78, 0x34, 0x69, 0x6f, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x0a, 0x0a,
+  0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x6c, 0x6f,
+  0x6f, 0x6b, 0x69, 0x6e, 0x67, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x61, 0x20,
+  0x47, 0x50, 0x53, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58, 0x58,
+  0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64,
+  0x20, 0x6e, 0x6f, 0x74, 0x20, 0x6e, 0x65, 0x65, 0x64, 0x20, 0x74, 0x6f,
+  0x20, 0x62, 0x65, 0x20, 0x62, 0x61, 0x63, 0x6b, 0x67, 0x72, 0x6f, 0x75,
+  0x6e, 0x64, 0x65, 0x64, 0x0a, 0x23, 0x0a, 0x67, 0x70, 0x73, 0x20, 0x2d,
+  0x64, 0x20, 0x2f, 0x64, 0x65, 0x76, 0x2f, 0x74, 0x74, 0x79, 0x53, 0x33,
+  0x20, 0x2d, 0x6d, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x26, 0x0a, 0x0a, 0x23,
+  0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x6c, 0x6f, 0x67,
+  0x67, 0x69, 0x6e, 0x67, 0x20, 0x74, 0x6f, 0x20, 0x6d, 0x69, 0x63, 0x72,
+  0x6f, 0x53, 0x44, 0x20, 0x69, 0x66, 0x20, 0x77, 0x65, 0x20, 0x63, 0x61,
+  0x6e, 0x0a, 0x23, 0x0a, 0x73, 0x68, 0x20, 0x2f, 0x65, 0x74, 0x63, 0x2f,
+  0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f, 0x72, 0x63, 0x2e, 0x6c, 0x6f,
+  0x67, 0x67, 0x69, 0x6e, 0x67, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x73,
+  0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x69, 0x73, 0x20, 0x64, 0x6f,
+  0x6e, 0x65, 0x3b, 0x20, 0x77, 0x65, 0x20, 0x64, 0x6f, 0x6e, 0x27, 0x74,
+  0x20, 0x77, 0x61, 0x6e, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x73, 0x68,
+  0x65, 0x6c, 0x6c, 0x20, 0x62, 0x65, 0x63, 0x61, 0x75, 0x73, 0x65, 0x20,
+  0x77, 0x65, 0x0a, 0x23, 0x20, 0x75, 0x73, 0x65, 0x20, 0x74, 0x68, 0x65,
+  0x20, 0x73, 0x61, 0x6d, 0x65, 0x20, 0x55, 0x41, 0x52, 0x54, 0x20, 0x66,
+  0x6f, 0x72, 0x20, 0x74, 0x65, 0x6c, 0x65, 0x6d, 0x65, 0x74, 0x72, 0x79,
+  0x20, 0x28, 0x64, 0x75, 0x6d, 0x62, 0x29, 0x2e, 0x0a, 0x23, 0x0a, 0x65,
+  0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20,
+  0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x64, 0x6f, 0x6e, 0x65,
+  0x2c, 0x20, 0x65, 0x78, 0x69, 0x74, 0x69, 0x6e, 0x67, 0x2e, 0x22, 0x0a,
+  0x65, 0x78, 0x69, 0x74, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x09, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xd6,
+  0xf4, 0x16, 0x7b, 0x19, 0x72, 0x63, 0x2e, 0x50, 0x58, 0x34, 0x49, 0x4f,
+  0x41, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x21, 0x6e, 0x73,
+  0x68, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x46, 0x6c, 0x69, 0x67, 0x68, 0x74,
+  0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x73, 0x63, 0x72,
+  0x69, 0x70, 0x74, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x50, 0x58, 0x34, 0x46,
+  0x4d, 0x55, 0x20, 0x6f, 0x6e, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x41,
+  0x52, 0x20, 0x63, 0x61, 0x72, 0x72, 0x69, 0x65, 0x72, 0x20, 0x62, 0x6f,
+  0x61, 0x72, 0x64, 0x2e, 0x0a, 0x23, 0x0a, 0x0a, 0x65, 0x63, 0x68, 0x6f,
+  0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20, 0x64, 0x6f, 0x69,
+  0x6e, 0x67, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x41, 0x52, 0x20, 0x73,
+  0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x2e, 0x2e, 0x2e, 0x22, 0x0a, 0x0a,
+  0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x68,
+  0x65, 0x20, 0x4f, 0x52, 0x42, 0x0a, 0x23, 0x0a, 0x75, 0x6f, 0x72, 0x62,
+  0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x73, 0x65,
+  0x6e, 0x73, 0x6f, 0x72, 0x73, 0x2e, 0x0a, 0x23, 0x0a, 0x73, 0x68, 0x20,
+  0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f,
+  0x72, 0x63, 0x2e, 0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x73, 0x0a, 0x0a,
+  0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x4d, 0x41,
+  0x56, 0x4c, 0x69, 0x6e, 0x6b, 0x0a, 0x23, 0x0a, 0x6d, 0x61, 0x76, 0x6c,
+  0x69, 0x6e, 0x6b, 0x20, 0x2d, 0x64, 0x20, 0x2f, 0x64, 0x65, 0x76, 0x2f,
+  0x74, 0x74, 0x79, 0x53, 0x30, 0x20, 0x2d, 0x62, 0x20, 0x35, 0x37, 0x36,
+  0x30, 0x30, 0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74,
+  0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x6f, 0x6d, 0x6d,
+  0x61, 0x6e, 0x64, 0x65, 0x72, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58,
+  0x58, 0x58, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75,
+  0x6c, 0x64, 0x20, 0x62, 0x65, 0x20, 0x27, 0x3c, 0x63, 0x6f, 0x6d, 0x6d,
+  0x61, 0x6e, 0x64, 0x3e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27, 0x2e,
+  0x0a, 0x23, 0x0a, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x65, 0x72,
+  0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72,
+  0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x61, 0x74, 0x74, 0x69, 0x74, 0x75,
+  0x64, 0x65, 0x20, 0x65, 0x73, 0x74, 0x69, 0x6d, 0x61, 0x74, 0x6f, 0x72,
+  0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58, 0x58, 0x20, 0x74, 0x68, 0x69,
+  0x73, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x62, 0x65, 0x20,
+  0x27, 0x3c, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x3e, 0x20, 0x73,
+  0x74, 0x61, 0x72, 0x74, 0x27, 0x2e, 0x0a, 0x23, 0x0a, 0x61, 0x74, 0x74,
+  0x69, 0x74, 0x75, 0x64, 0x65, 0x5f, 0x65, 0x73, 0x74, 0x69, 0x6d, 0x61,
+  0x74, 0x6f, 0x72, 0x5f, 0x62, 0x6d, 0x20, 0x26, 0x0a, 0x23, 0x70, 0x6f,
+  0x73, 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x65, 0x73, 0x74, 0x69, 0x6d,
+  0x61, 0x74, 0x6f, 0x72, 0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x43, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x65, 0x20, 0x50, 0x58,
+  0x34, 0x46, 0x4d, 0x55, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x6f, 0x70, 0x65,
+  0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x77, 0x69, 0x74, 0x68, 0x20,
+  0x50, 0x58, 0x34, 0x49, 0x4f, 0x41, 0x52, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x58, 0x58, 0x58, 0x20, 0x61, 0x72, 0x67, 0x75, 0x6d, 0x65, 0x6e, 0x74,
+  0x73, 0x3f, 0x0a, 0x23, 0x0a, 0x70, 0x78, 0x34, 0x66, 0x6d, 0x75, 0x20,
+  0x73, 0x74, 0x61, 0x72, 0x74, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x46,
+  0x69, 0x72, 0x65, 0x20, 0x75, 0x70, 0x20, 0x74, 0x68, 0x65, 0x20, 0x41,
+  0x52, 0x2e, 0x44, 0x72, 0x6f, 0x6e, 0x65, 0x20, 0x63, 0x6f, 0x6e, 0x74,
+  0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x58, 0x58, 0x58, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f,
+  0x75, 0x6c, 0x64, 0x20, 0x62, 0x65, 0x20, 0x27, 0x3c, 0x63, 0x6f, 0x6d,
+  0x6d, 0x61, 0x6e, 0x64, 0x3e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27,
+  0x2e, 0x0a, 0x23, 0x0a, 0x61, 0x72, 0x64, 0x72, 0x6f, 0x6e, 0x65, 0x5f,
+  0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x20, 0x2d, 0x64, 0x20, 0x2f,
+  0x64, 0x65, 0x76, 0x2f, 0x74, 0x74, 0x79, 0x53, 0x31, 0x20, 0x2d, 0x6d,
+  0x20, 0x61, 0x74, 0x74, 0x69, 0x74, 0x75, 0x64, 0x65, 0x20, 0x26, 0x0a,
+  0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x6c,
+  0x6f, 0x6f, 0x6b, 0x69, 0x6e, 0x67, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x61,
+  0x20, 0x47, 0x50, 0x53, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58,
+  0x58, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c,
+  0x64, 0x20, 0x6e, 0x6f, 0x74, 0x20, 0x6e, 0x65, 0x65, 0x64, 0x20, 0x74,
+  0x6f, 0x20, 0x62, 0x65, 0x20, 0x62, 0x61, 0x63, 0x6b, 0x67, 0x72, 0x6f,
+  0x75, 0x6e, 0x64, 0x65, 0x64, 0x0a, 0x23, 0x0a, 0x67, 0x70, 0x73, 0x20,
+  0x2d, 0x64, 0x20, 0x2f, 0x64, 0x65, 0x76, 0x2f, 0x74, 0x74, 0x79, 0x53,
+  0x33, 0x20, 0x2d, 0x6d, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x26, 0x0a, 0x0a,
+  0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x6c, 0x6f,
+  0x67, 0x67, 0x69, 0x6e, 0x67, 0x20, 0x74, 0x6f, 0x20, 0x6d, 0x69, 0x63,
+  0x72, 0x6f, 0x53, 0x44, 0x20, 0x69, 0x66, 0x20, 0x77, 0x65, 0x20, 0x63,
+  0x61, 0x6e, 0x0a, 0x23, 0x0a, 0x73, 0x68, 0x20, 0x2f, 0x65, 0x74, 0x63,
+  0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f, 0x72, 0x63, 0x2e, 0x6c,
+  0x6f, 0x67, 0x67, 0x69, 0x6e, 0x67, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x69, 0x73, 0x20, 0x64,
+  0x6f, 0x6e, 0x65, 0x3b, 0x20, 0x77, 0x65, 0x20, 0x64, 0x6f, 0x6e, 0x27,
+  0x74, 0x20, 0x77, 0x61, 0x6e, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x73,
+  0x68, 0x65, 0x6c, 0x6c, 0x20, 0x62, 0x65, 0x63, 0x61, 0x75, 0x73, 0x65,
+  0x20, 0x77, 0x65, 0x0a, 0x23, 0x20, 0x75, 0x73, 0x65, 0x20, 0x74, 0x68,
+  0x65, 0x20, 0x73, 0x61, 0x6d, 0x65, 0x20, 0x55, 0x41, 0x52, 0x54, 0x20,
+  0x66, 0x6f, 0x72, 0x20, 0x74, 0x65, 0x6c, 0x65, 0x6d, 0x65, 0x74, 0x72,
+  0x79, 0x20, 0x28, 0x64, 0x75, 0x6d, 0x62, 0x29, 0x2e, 0x0a, 0x23, 0x0a,
+  0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d,
+  0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x64, 0x6f, 0x6e,
+  0x65, 0x2c, 0x20, 0x65, 0x78, 0x69, 0x74, 0x69, 0x6e, 0x67, 0x2e, 0x22,
+  0x0a, 0x65, 0x78, 0x69, 0x74, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x02, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x01, 0x6e, 0xb5, 0xbb, 0x51, 0xae, 0x72, 0x63, 0x2e, 0x73,
+  0x65, 0x6e, 0x73, 0x6f, 0x72, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x23, 0x21, 0x6e, 0x73, 0x68, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74,
+  0x61, 0x6e, 0x64, 0x61, 0x72, 0x64, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74,
+  0x75, 0x70, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x66, 0x6f,
+  0x72, 0x20, 0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x20, 0x6f, 0x6e, 0x62,
+  0x6f, 0x61, 0x72, 0x64, 0x20, 0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x20,
+  0x64, 0x72, 0x69, 0x76, 0x65, 0x72, 0x73, 0x2e, 0x0a, 0x23, 0x0a, 0x0a,
+  0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x73, 0x65,
+  0x6e, 0x73, 0x6f, 0x72, 0x20, 0x64, 0x72, 0x69, 0x76, 0x65, 0x72, 0x73,
+  0x20, 0x68, 0x65, 0x72, 0x65, 0x2e, 0x0a, 0x23, 0x0a, 0x0a, 0x23, 0x6d,
+  0x73, 0x35, 0x36, 0x31, 0x31, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x0a,
+  0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74,
+  0x68, 0x65, 0x20, 0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x20, 0x63, 0x6f,
+  0x6c, 0x6c, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x74, 0x61, 0x73,
+  0x6b, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58, 0x58, 0x20, 0x73,
+  0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x62, 0x65, 0x20, 0x27, 0x73, 0x65,
+  0x6e, 0x73, 0x6f, 0x72, 0x73, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27,
+  0x0a, 0x23, 0x0a, 0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x73, 0x20, 0x26,
+  0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x54, 0x65, 0x73, 0x74, 0x20, 0x73,
+  0x65, 0x6e, 0x73, 0x6f, 0x72, 0x20, 0x66, 0x75, 0x6e, 0x63, 0x74, 0x69,
+  0x6f, 0x6e, 0x61, 0x6c, 0x69, 0x74, 0x79, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x58, 0x58, 0x58, 0x20, 0x69, 0x6e, 0x74, 0x65, 0x67, 0x72, 0x61, 0x74,
+  0x65, 0x20, 0x77, 0x69, 0x74, 0x68, 0x20, 0x27, 0x73, 0x65, 0x6e, 0x73,
+  0x6f, 0x72, 0x73, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27, 0x20, 0x3f,
+  0x0a, 0x23, 0x0a, 0x23, 0x69, 0x66, 0x20, 0x73, 0x65, 0x6e, 0x73, 0x6f,
+  0x72, 0x73, 0x20, 0x71, 0x75, 0x69, 0x63, 0x6b, 0x74, 0x65, 0x73, 0x74,
+  0x0a, 0x23, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x23, 0x09, 0x65, 0x63, 0x68,
+  0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20, 0x73, 0x65,
+  0x6e, 0x73, 0x6f, 0x72, 0x20, 0x69, 0x6e, 0x69, 0x74, 0x69, 0x61, 0x6c,
+  0x69, 0x73, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x46, 0x41, 0x49, 0x4c,
+  0x45, 0x44, 0x2e, 0x22, 0x0a, 0x23, 0x09, 0x72, 0x65, 0x62, 0x6f, 0x6f,
+  0x74, 0x0a, 0x23, 0x66, 0x69, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x0e, 0xf2,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xcd, 0x52, 0xce, 0xe0, 0xfc,
+  0x72, 0x63, 0x2e, 0x73, 0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c, 0x6f, 0x6e,
+  0x65, 0x00, 0x00, 0x00, 0x23, 0x21, 0x6e, 0x73, 0x68, 0x0a, 0x23, 0x0a,
+  0x23, 0x20, 0x46, 0x6c, 0x69, 0x67, 0x68, 0x74, 0x20, 0x73, 0x74, 0x61,
+  0x72, 0x74, 0x75, 0x70, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20,
+  0x66, 0x6f, 0x72, 0x20, 0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x20, 0x73,
+  0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c, 0x6f, 0x6e, 0x65, 0x20, 0x63, 0x6f,
+  0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2e,
+  0x0a, 0x23, 0x0a, 0x0a, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69,
+  0x6e, 0x69, 0x74, 0x5d, 0x20, 0x64, 0x6f, 0x69, 0x6e, 0x67, 0x20, 0x73,
+  0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c, 0x6f, 0x6e, 0x65, 0x20, 0x50, 0x58,
+  0x34, 0x46, 0x4d, 0x55, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70,
+  0x2e, 0x2e, 0x2e, 0x22, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74,
+  0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x4f, 0x52, 0x42, 0x0a,
+  0x23, 0x0a, 0x23, 0x75, 0x6f, 0x72, 0x62, 0x20, 0x73, 0x74, 0x61, 0x72,
+  0x74, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74,
+  0x20, 0x74, 0x68, 0x65, 0x20, 0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x73,
+  0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x73, 0x68, 0x20, 0x2f, 0x65, 0x74, 0x63,
+  0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f, 0x72, 0x63, 0x2e, 0x73,
+  0x65, 0x6e, 0x73, 0x6f, 0x72, 0x73, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x4d, 0x41, 0x56, 0x4c, 0x69, 0x6e,
+  0x6b, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x6d, 0x61, 0x76, 0x6c, 0x69, 0x6e,
+  0x6b, 0x20, 0x2d, 0x64, 0x20, 0x2f, 0x64, 0x65, 0x76, 0x2f, 0x74, 0x74,
+  0x79, 0x53, 0x30, 0x20, 0x2d, 0x62, 0x20, 0x35, 0x37, 0x36, 0x30, 0x30,
+  0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72,
+  0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e,
+  0x64, 0x65, 0x72, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58, 0x58,
+  0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64,
+  0x20, 0x62, 0x65, 0x20, 0x27, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64,
+  0x65, 0x72, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x27, 0x2e, 0x0a, 0x23,
+  0x0a, 0x23, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x65, 0x72, 0x20,
+  0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74, 0x61, 0x72, 0x74,
+  0x20, 0x74, 0x68, 0x65, 0x20, 0x61, 0x74, 0x74, 0x69, 0x74, 0x75, 0x64,
+  0x65, 0x20, 0x65, 0x73, 0x74, 0x69, 0x6d, 0x61, 0x74, 0x6f, 0x72, 0x0a,
+  0x23, 0x0a, 0x23, 0x20, 0x58, 0x58, 0x58, 0x20, 0x74, 0x68, 0x69, 0x73,
+  0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x62, 0x65, 0x20, 0x27,
+  0x3c, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x3e, 0x20, 0x73, 0x74,
+  0x61, 0x72, 0x74, 0x27, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x61, 0x74, 0x74,
+  0x69, 0x74, 0x75, 0x64, 0x65, 0x5f, 0x65, 0x73, 0x74, 0x69, 0x6d, 0x61,
+  0x74, 0x6f, 0x72, 0x5f, 0x62, 0x6d, 0x20, 0x26, 0x0a, 0x23, 0x70, 0x6f,
+  0x73, 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x5f, 0x65, 0x73, 0x74, 0x69, 0x6d,
+  0x61, 0x74, 0x6f, 0x72, 0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20, 0x66, 0x69,
+  0x78, 0x65, 0x64, 0x2d, 0x77, 0x69, 0x6e, 0x67, 0x20, 0x63, 0x6f, 0x6e,
+  0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x2e, 0x0a, 0x23, 0x0a, 0x23,
+  0x20, 0x58, 0x58, 0x58, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20,
+  0x74, 0x68, 0x69, 0x73, 0x20, 0x62, 0x65, 0x20, 0x6c, 0x6f, 0x6f, 0x6b,
+  0x69, 0x6e, 0x67, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x63, 0x6f, 0x6e, 0x66,
+  0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x74, 0x6f,
+  0x20, 0x64, 0x65, 0x63, 0x69, 0x64, 0x65, 0x0a, 0x23, 0x20, 0x77, 0x68,
+  0x65, 0x74, 0x68, 0x65, 0x72, 0x20, 0x74, 0x68, 0x65, 0x20, 0x62, 0x6f,
+  0x61, 0x72, 0x64, 0x20, 0x69, 0x73, 0x20, 0x63, 0x6f, 0x6e, 0x66, 0x69,
+  0x67, 0x75, 0x72, 0x65, 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x66, 0x69,
+  0x78, 0x65, 0x64, 0x2d, 0x77, 0x69, 0x6e, 0x67, 0x20, 0x75, 0x73, 0x65,
+  0x3f, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58, 0x58, 0x20, 0x74, 0x68,
+  0x69, 0x73, 0x20, 0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x62, 0x65,
+  0x20, 0x27, 0x66, 0x69, 0x78, 0x65, 0x64, 0x77, 0x69, 0x6e, 0x67, 0x5f,
+  0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x20, 0x73, 0x74, 0x61, 0x72,
+  0x74, 0x27, 0x2e, 0x0a, 0x23, 0x0a, 0x23, 0x66, 0x69, 0x78, 0x65, 0x64,
+  0x77, 0x69, 0x6e, 0x67, 0x5f, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c,
+  0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x43, 0x6f, 0x6e, 0x66,
+  0x69, 0x67, 0x75, 0x72, 0x65, 0x20, 0x46, 0x4d, 0x55, 0x20, 0x66, 0x6f,
+  0x72, 0x20, 0x73, 0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c, 0x6f, 0x6e, 0x65,
+  0x20, 0x6d, 0x6f, 0x64, 0x65, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x58, 0x58,
+  0x58, 0x20, 0x61, 0x72, 0x67, 0x75, 0x6d, 0x65, 0x6e, 0x74, 0x73, 0x3f,
+  0x0a, 0x23, 0x0a, 0x23, 0x70, 0x78, 0x34, 0x66, 0x6d, 0x75, 0x20, 0x73,
+  0x74, 0x61, 0x72, 0x74, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74,
+  0x61, 0x72, 0x74, 0x20, 0x6c, 0x6f, 0x6f, 0x6b, 0x69, 0x6e, 0x67, 0x20,
+  0x66, 0x6f, 0x72, 0x20, 0x61, 0x20, 0x47, 0x50, 0x53, 0x2e, 0x0a, 0x23,
+  0x0a, 0x23, 0x20, 0x58, 0x58, 0x58, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20,
+  0x73, 0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x6e, 0x6f, 0x74, 0x20, 0x6e,
+  0x65, 0x65, 0x64, 0x20, 0x74, 0x6f, 0x20, 0x62, 0x65, 0x20, 0x62, 0x61,
+  0x63, 0x6b, 0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x65, 0x64, 0x0a, 0x23,
+  0x0a, 0x23, 0x67, 0x70, 0x73, 0x20, 0x2d, 0x64, 0x20, 0x2f, 0x64, 0x65,
+  0x76, 0x2f, 0x74, 0x74, 0x79, 0x53, 0x33, 0x20, 0x2d, 0x6d, 0x20, 0x61,
+  0x6c, 0x6c, 0x20, 0x26, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x53, 0x74,
+  0x61, 0x72, 0x74, 0x20, 0x6c, 0x6f, 0x67, 0x67, 0x69, 0x6e, 0x67, 0x20,
+  0x74, 0x6f, 0x20, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x53, 0x44, 0x20, 0x69,
+  0x66, 0x20, 0x77, 0x65, 0x20, 0x63, 0x61, 0x6e, 0x0a, 0x23, 0x0a, 0x73,
+  0x68, 0x20, 0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e,
+  0x64, 0x2f, 0x72, 0x63, 0x2e, 0x6c, 0x6f, 0x67, 0x67, 0x69, 0x6e, 0x67,
+  0x0a, 0x0a, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69,
+  0x74, 0x5d, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x64,
+  0x6f, 0x6e, 0x65, 0x22, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x76, 0x8d, 0x9c, 0xa3, 0x80,
+  0x72, 0x63, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x23, 0x21, 0x6e, 0x73, 0x68, 0x0a, 0x23, 0x0a,
+  0x23, 0x20, 0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x20, 0x73, 0x74, 0x61,
+  0x72, 0x74, 0x75, 0x70, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x2e,
+  0x0a, 0x23, 0x0a, 0x23, 0x20, 0x54, 0x68, 0x69, 0x73, 0x20, 0x73, 0x63,
+  0x72, 0x69, 0x70, 0x74, 0x20, 0x69, 0x73, 0x20, 0x72, 0x65, 0x73, 0x70,
+  0x6f, 0x6e, 0x73, 0x69, 0x62, 0x6c, 0x65, 0x20, 0x66, 0x6f, 0x72, 0x3a,
+  0x0a, 0x23, 0x0a, 0x23, 0x20, 0x2d, 0x20, 0x6d, 0x6f, 0x75, 0x6e, 0x74,
+  0x69, 0x6e, 0x67, 0x20, 0x74, 0x68, 0x65, 0x20, 0x6d, 0x69, 0x63, 0x72,
+  0x6f, 0x53, 0x44, 0x20, 0x63, 0x61, 0x72, 0x64, 0x20, 0x28, 0x69, 0x66,
+  0x20, 0x70, 0x72, 0x65, 0x73, 0x65, 0x6e, 0x74, 0x29, 0x0a, 0x23, 0x20,
+  0x2d, 0x20, 0x72, 0x75, 0x6e, 0x6e, 0x69, 0x6e, 0x67, 0x20, 0x74, 0x68,
+  0x65, 0x20, 0x75, 0x73, 0x65, 0x72, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74,
+  0x75, 0x70, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x66, 0x72,
+  0x6f, 0x6d, 0x20, 0x74, 0x68, 0x65, 0x20, 0x6d, 0x69, 0x63, 0x72, 0x6f,
+  0x53, 0x44, 0x20, 0x63, 0x61, 0x72, 0x64, 0x20, 0x28, 0x69, 0x66, 0x20,
+  0x70, 0x72, 0x65, 0x73, 0x65, 0x6e, 0x74, 0x29, 0x0a, 0x23, 0x20, 0x2d,
+  0x20, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x74,
+  0x68, 0x65, 0x20, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x61,
+  0x74, 0x69, 0x6f, 0x6e, 0x20, 0x6f, 0x66, 0x20, 0x74, 0x68, 0x65, 0x20,
+  0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x70,
+  0x69, 0x63, 0x6b, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x20, 0x73, 0x75, 0x69,
+  0x74, 0x61, 0x62, 0x6c, 0x65, 0x0a, 0x23, 0x20, 0x20, 0x20, 0x73, 0x74,
+  0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74,
+  0x20, 0x74, 0x6f, 0x20, 0x63, 0x6f, 0x6e, 0x74, 0x69, 0x6e, 0x75, 0x65,
+  0x20, 0x77, 0x69, 0x74, 0x68, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x4e, 0x6f,
+  0x74, 0x65, 0x3a, 0x20, 0x44, 0x4f, 0x20, 0x4e, 0x4f, 0x54, 0x20, 0x61,
+  0x64, 0x64, 0x20, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x61,
+  0x74, 0x69, 0x6f, 0x6e, 0x2d, 0x73, 0x70, 0x65, 0x63, 0x69, 0x66, 0x69,
+  0x63, 0x20, 0x63, 0x6f, 0x6d, 0x6d, 0x61, 0x6e, 0x64, 0x73, 0x20, 0x74,
+  0x6f, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70,
+  0x74, 0x3b, 0x0a, 0x23, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x61,
+  0x64, 0x64, 0x20, 0x74, 0x68, 0x65, 0x6d, 0x20, 0x74, 0x6f, 0x20, 0x74,
+  0x68, 0x65, 0x20, 0x70, 0x65, 0x72, 0x2d, 0x63, 0x6f, 0x6e, 0x66, 0x69,
+  0x67, 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x73, 0x63, 0x72,
+  0x69, 0x70, 0x74, 0x73, 0x20, 0x69, 0x6e, 0x73, 0x74, 0x65, 0x61, 0x64,
+  0x2e, 0x0a, 0x23, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x44, 0x65, 0x66,
+  0x61, 0x75, 0x6c, 0x74, 0x20, 0x74, 0x6f, 0x20, 0x61, 0x75, 0x74, 0x6f,
+  0x2d, 0x73, 0x74, 0x61, 0x72, 0x74, 0x20, 0x6d, 0x6f, 0x64, 0x65, 0x2e,
+  0x20, 0x20, 0x41, 0x6e, 0x20, 0x69, 0x6e, 0x69, 0x74, 0x20, 0x73, 0x63,
+  0x72, 0x69, 0x70, 0x74, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20,
+  0x6d, 0x69, 0x63, 0x72, 0x6f, 0x53, 0x44, 0x20, 0x63, 0x61, 0x72, 0x64,
+  0x0a, 0x23, 0x20, 0x63, 0x61, 0x6e, 0x20, 0x63, 0x68, 0x61, 0x6e, 0x67,
+  0x65, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x74, 0x6f, 0x20, 0x70, 0x72,
+  0x65, 0x76, 0x65, 0x6e, 0x74, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x6d, 0x61,
+  0x74, 0x69, 0x63, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x20,
+  0x6f, 0x66, 0x20, 0x74, 0x68, 0x65, 0x20, 0x66, 0x6c, 0x69, 0x67, 0x68,
+  0x74, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x2e, 0x0a, 0x23, 0x0a,
+  0x73, 0x65, 0x74, 0x20, 0x4d, 0x4f, 0x44, 0x45, 0x20, 0x61, 0x75, 0x74,
+  0x6f, 0x73, 0x74, 0x61, 0x72, 0x74, 0x0a, 0x73, 0x65, 0x74, 0x20, 0x55,
+  0x53, 0x42, 0x5f, 0x41, 0x4c, 0x4c, 0x4f, 0x57, 0x45, 0x44, 0x20, 0x79,
+  0x65, 0x73, 0x0a, 0x73, 0x65, 0x74, 0x20, 0x55, 0x53, 0x42, 0x20, 0x6e,
+  0x6f, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x54, 0x72, 0x79, 0x20, 0x74,
+  0x6f, 0x20, 0x6d, 0x6f, 0x75, 0x6e, 0x74, 0x20, 0x74, 0x68, 0x65, 0x20,
+  0x6d, 0x69, 0x63, 0x72, 0x6f, 0x53, 0x44, 0x20, 0x63, 0x61, 0x72, 0x64,
+  0x2e, 0x0a, 0x23, 0x0a, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69,
+  0x6e, 0x69, 0x74, 0x5d, 0x20, 0x6c, 0x6f, 0x6f, 0x6b, 0x69, 0x6e, 0x67,
+  0x20, 0x66, 0x6f, 0x72, 0x20, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x53, 0x44,
+  0x2e, 0x2e, 0x2e, 0x22, 0x0a, 0x69, 0x66, 0x20, 0x6d, 0x6f, 0x75, 0x6e,
+  0x74, 0x20, 0x2d, 0x74, 0x20, 0x76, 0x66, 0x61, 0x74, 0x20, 0x2f, 0x64,
+  0x65, 0x76, 0x2f, 0x6d, 0x6d, 0x63, 0x73, 0x64, 0x30, 0x20, 0x2f, 0x66,
+  0x73, 0x2f, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x73, 0x64, 0x0a, 0x74, 0x68,
+  0x65, 0x6e, 0x0a, 0x09, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69,
+  0x6e, 0x69, 0x74, 0x5d, 0x20, 0x63, 0x61, 0x72, 0x64, 0x20, 0x6d, 0x6f,
+  0x75, 0x6e, 0x74, 0x65, 0x64, 0x20, 0x61, 0x74, 0x20, 0x2f, 0x66, 0x73,
+  0x2f, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x73, 0x64, 0x22, 0x0a, 0x65, 0x6c,
+  0x73, 0x65, 0x0a, 0x09, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69,
+  0x6e, 0x69, 0x74, 0x5d, 0x20, 0x6e, 0x6f, 0x20, 0x6d, 0x69, 0x63, 0x72,
+  0x6f, 0x53, 0x44, 0x20, 0x63, 0x61, 0x72, 0x64, 0x20, 0x66, 0x6f, 0x75,
+  0x6e, 0x64, 0x22, 0x0a, 0x66, 0x69, 0x0a, 0x0a, 0x23, 0x0a, 0x23, 0x20,
+  0x4c, 0x6f, 0x6f, 0x6b, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x61, 0x6e, 0x20,
+  0x69, 0x6e, 0x69, 0x74, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20,
+  0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x6d, 0x69, 0x63, 0x72, 0x6f,
+  0x53, 0x44, 0x20, 0x63, 0x61, 0x72, 0x64, 0x2e, 0x0a, 0x23, 0x0a, 0x23,
+  0x20, 0x54, 0x6f, 0x20, 0x70, 0x72, 0x65, 0x76, 0x65, 0x6e, 0x74, 0x20,
+  0x61, 0x75, 0x74, 0x6f, 0x6d, 0x61, 0x74, 0x69, 0x63, 0x20, 0x73, 0x74,
+  0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x69, 0x6e, 0x20, 0x74, 0x68, 0x65,
+  0x20, 0x63, 0x75, 0x72, 0x72, 0x65, 0x6e, 0x74, 0x20, 0x66, 0x6c, 0x69,
+  0x67, 0x68, 0x74, 0x20, 0x6d, 0x6f, 0x64, 0x65, 0x2c, 0x0a, 0x23, 0x20,
+  0x74, 0x68, 0x65, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x73,
+  0x68, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x73, 0x65, 0x74, 0x20, 0x4d, 0x4f,
+  0x44, 0x45, 0x20, 0x74, 0x6f, 0x20, 0x73, 0x6f, 0x6d, 0x65, 0x20, 0x6f,
+  0x74, 0x68, 0x65, 0x72, 0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x2e, 0x0a,
+  0x23, 0x0a, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x2d, 0x66, 0x20, 0x2f, 0x66,
+  0x73, 0x2f, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x73, 0x64, 0x2f, 0x65, 0x74,
+  0x63, 0x2f, 0x72, 0x63, 0x20, 0x5d, 0x0a, 0x74, 0x68, 0x65, 0x6e, 0x0a,
+  0x09, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74,
+  0x5d, 0x20, 0x72, 0x65, 0x61, 0x64, 0x69, 0x6e, 0x67, 0x20, 0x2f, 0x66,
+  0x73, 0x2f, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x73, 0x64, 0x2f, 0x65, 0x74,
+  0x63, 0x2f, 0x72, 0x63, 0x22, 0x0a, 0x09, 0x73, 0x68, 0x20, 0x2f, 0x66,
+  0x73, 0x2f, 0x6d, 0x69, 0x63, 0x72, 0x6f, 0x73, 0x64, 0x2f, 0x65, 0x74,
+  0x63, 0x2f, 0x72, 0x63, 0x0a, 0x66, 0x69, 0x0a, 0x0a, 0x23, 0x0a, 0x23,
+  0x20, 0x43, 0x68, 0x65, 0x63, 0x6b, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x55,
+  0x53, 0x42, 0x20, 0x68, 0x6f, 0x73, 0x74, 0x0a, 0x23, 0x0a, 0x69, 0x66,
+  0x20, 0x5b, 0x20, 0x24, 0x55, 0x53, 0x42, 0x5f, 0x41, 0x4c, 0x4c, 0x4f,
+  0x57, 0x45, 0x44, 0x20, 0x3d, 0x3d, 0x20, 0x79, 0x65, 0x73, 0x20, 0x5d,
+  0x0a, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x69, 0x66, 0x20, 0x73, 0x65,
+  0x72, 0x63, 0x6f, 0x6e, 0x0a, 0x09, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09,
+  0x09, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74,
+  0x5d, 0x20, 0x55, 0x53, 0x42, 0x20, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x66,
+  0x61, 0x63, 0x65, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x65,
+  0x64, 0x22, 0x0a, 0x09, 0x66, 0x69, 0x0a, 0x66, 0x69, 0x0a, 0x0a, 0x23,
+  0x0a, 0x23, 0x20, 0x49, 0x66, 0x20, 0x77, 0x65, 0x20, 0x61, 0x72, 0x65,
+  0x20, 0x73, 0x74, 0x69, 0x6c, 0x6c, 0x20, 0x69, 0x6e, 0x20, 0x66, 0x6c,
+  0x69, 0x67, 0x68, 0x74, 0x20, 0x6d, 0x6f, 0x64, 0x65, 0x2c, 0x20, 0x77,
+  0x6f, 0x72, 0x6b, 0x20, 0x6f, 0x75, 0x74, 0x20, 0x77, 0x68, 0x61, 0x74,
+  0x20, 0x61, 0x69, 0x72, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x20, 0x0a, 0x23,
+  0x20, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69,
+  0x6f, 0x6e, 0x20, 0x77, 0x65, 0x20, 0x68, 0x61, 0x76, 0x65, 0x20, 0x61,
+  0x6e, 0x64, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x20, 0x75, 0x70, 0x20,
+  0x61, 0x63, 0x63, 0x6f, 0x72, 0x64, 0x69, 0x6e, 0x67, 0x6c, 0x79, 0x2e,
+  0x0a, 0x23, 0x0a, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x24, 0x4d, 0x4f, 0x44,
+  0x45, 0x20, 0x21, 0x3d, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x73, 0x74, 0x61,
+  0x72, 0x74, 0x20, 0x5d, 0x0a, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x65,
+  0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20,
+  0x61, 0x75, 0x74, 0x6f, 0x6d, 0x61, 0x74, 0x69, 0x63, 0x20, 0x73, 0x74,
+  0x61, 0x72, 0x74, 0x75, 0x70, 0x20, 0x63, 0x61, 0x6e, 0x63, 0x65, 0x6c,
+  0x6c, 0x65, 0x64, 0x20, 0x62, 0x79, 0x20, 0x75, 0x73, 0x65, 0x72, 0x20,
+  0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x22, 0x0a, 0x65, 0x6c, 0x73, 0x65,
+  0x0a, 0x09, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69,
+  0x74, 0x5d, 0x20, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74, 0x69, 0x6e, 0x67,
+  0x20, 0x61, 0x74, 0x74, 0x61, 0x63, 0x68, 0x65, 0x64, 0x20, 0x68, 0x61,
+  0x72, 0x64, 0x77, 0x61, 0x72, 0x65, 0x2e, 0x2e, 0x2e, 0x22, 0x0a, 0x0a,
+  0x09, 0x23, 0x0a, 0x09, 0x23, 0x20, 0x41, 0x73, 0x73, 0x75, 0x6d, 0x65,
+  0x20, 0x74, 0x68, 0x61, 0x74, 0x20, 0x77, 0x65, 0x20, 0x61, 0x72, 0x65,
+  0x20, 0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x20, 0x69, 0x6e, 0x20, 0x73,
+  0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c, 0x6f, 0x6e, 0x65, 0x20, 0x6d, 0x6f,
+  0x64, 0x65, 0x0a, 0x09, 0x23, 0x0a, 0x09, 0x73, 0x65, 0x74, 0x20, 0x42,
+  0x4f, 0x41, 0x52, 0x44, 0x20, 0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x0a,
+  0x0a, 0x09, 0x23, 0x0a, 0x09, 0x23, 0x20, 0x41, 0x72, 0x65, 0x20, 0x77,
+  0x65, 0x20, 0x61, 0x74, 0x74, 0x61, 0x63, 0x68, 0x65, 0x64, 0x20, 0x74,
+  0x6f, 0x20, 0x61, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x41, 0x52, 0x20,
+  0x28, 0x41, 0x52, 0x2e, 0x44, 0x72, 0x6f, 0x6e, 0x65, 0x20, 0x63, 0x61,
+  0x72, 0x72, 0x69, 0x65, 0x72, 0x20, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x29,
+  0x3f, 0x0a, 0x09, 0x23, 0x0a, 0x09, 0x69, 0x66, 0x20, 0x62, 0x6f, 0x61,
+  0x72, 0x64, 0x69, 0x6e, 0x66, 0x6f, 0x20, 0x2d, 0x74, 0x20, 0x37, 0x0a,
+  0x09, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x09, 0x73, 0x65, 0x74, 0x20,
+  0x42, 0x4f, 0x41, 0x52, 0x44, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x41,
+  0x52, 0x0a, 0x09, 0x09, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x2d, 0x66, 0x20,
+  0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f,
+  0x72, 0x63, 0x2e, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x41, 0x52, 0x20, 0x5d,
+  0x0a, 0x09, 0x09, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x09, 0x09, 0x65,
+  0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20,
+  0x72, 0x65, 0x61, 0x64, 0x69, 0x6e, 0x67, 0x20, 0x2f, 0x65, 0x74, 0x63,
+  0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f, 0x72, 0x63, 0x2e, 0x50,
+  0x58, 0x34, 0x49, 0x4f, 0x41, 0x52, 0x22, 0x0a, 0x09, 0x09, 0x09, 0x73,
+  0x68, 0x20, 0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e,
+  0x64, 0x2f, 0x72, 0x63, 0x2e, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x41, 0x52,
+  0x0a, 0x09, 0x09, 0x66, 0x69, 0x0a, 0x09, 0x65, 0x6c, 0x73, 0x65, 0x0a,
+  0x09, 0x09, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69,
+  0x74, 0x5d, 0x20, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x41, 0x52, 0x20, 0x6e,
+  0x6f, 0x74, 0x20, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74, 0x65, 0x64, 0x22,
+  0x0a, 0x09, 0x66, 0x69, 0x0a, 0x0a, 0x09, 0x23, 0x0a, 0x09, 0x23, 0x20,
+  0x41, 0x72, 0x65, 0x20, 0x77, 0x65, 0x20, 0x61, 0x74, 0x74, 0x61, 0x63,
+  0x68, 0x65, 0x64, 0x20, 0x74, 0x6f, 0x20, 0x61, 0x20, 0x50, 0x58, 0x34,
+  0x49, 0x4f, 0x3f, 0x0a, 0x09, 0x23, 0x0a, 0x09, 0x69, 0x66, 0x20, 0x62,
+  0x6f, 0x61, 0x72, 0x64, 0x69, 0x6e, 0x66, 0x6f, 0x20, 0x2d, 0x74, 0x20,
+  0x36, 0x0a, 0x09, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x09, 0x73, 0x65,
+  0x74, 0x20, 0x42, 0x4f, 0x41, 0x52, 0x44, 0x20, 0x50, 0x58, 0x34, 0x49,
+  0x4f, 0x0a, 0x09, 0x09, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x2d, 0x66, 0x20,
+  0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f,
+  0x72, 0x63, 0x2e, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x20, 0x5d, 0x0a, 0x09,
+  0x09, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x09, 0x09, 0x65, 0x63, 0x68,
+  0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20, 0x72, 0x65,
+  0x61, 0x64, 0x69, 0x6e, 0x67, 0x20, 0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69,
+  0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f, 0x72, 0x63, 0x2e, 0x50, 0x58, 0x34,
+  0x49, 0x4f, 0x22, 0x0a, 0x09, 0x09, 0x09, 0x73, 0x68, 0x20, 0x2f, 0x65,
+  0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f, 0x72, 0x63,
+  0x2e, 0x50, 0x58, 0x34, 0x49, 0x4f, 0x0a, 0x09, 0x09, 0x66, 0x69, 0x0a,
+  0x09, 0x65, 0x6c, 0x73, 0x65, 0x0a, 0x09, 0x09, 0x65, 0x63, 0x68, 0x6f,
+  0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20, 0x50, 0x58, 0x34,
+  0x49, 0x4f, 0x20, 0x6e, 0x6f, 0x74, 0x20, 0x64, 0x65, 0x74, 0x65, 0x63,
+  0x74, 0x65, 0x64, 0x22, 0x0a, 0x09, 0x66, 0x69, 0x0a, 0x0a, 0x09, 0x23,
+  0x0a, 0x09, 0x23, 0x20, 0x4c, 0x6f, 0x6f, 0x6b, 0x73, 0x20, 0x6c, 0x69,
+  0x6b, 0x65, 0x20, 0x77, 0x65, 0x20, 0x61, 0x72, 0x65, 0x20, 0x73, 0x74,
+  0x61, 0x6e, 0x64, 0x2d, 0x61, 0x6c, 0x6f, 0x6e, 0x65, 0x0a, 0x09, 0x23,
+  0x0a, 0x09, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x24, 0x42, 0x4f, 0x41, 0x52,
+  0x44, 0x20, 0x3d, 0x3d, 0x20, 0x50, 0x58, 0x34, 0x46, 0x4d, 0x55, 0x20,
+  0x5d, 0x0a, 0x09, 0x74, 0x68, 0x65, 0x6e, 0x0a, 0x09, 0x09, 0x65, 0x63,
+  0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20, 0x6e,
+  0x6f, 0x20, 0x65, 0x78, 0x70, 0x61, 0x6e, 0x73, 0x69, 0x6f, 0x6e, 0x20,
+  0x62, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74,
+  0x65, 0x64, 0x22, 0x0a, 0x09, 0x09, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x2d,
+  0x66, 0x20, 0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e,
+  0x64, 0x2f, 0x72, 0x63, 0x2e, 0x73, 0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c,
+  0x6f, 0x6e, 0x65, 0x20, 0x5d, 0x0a, 0x09, 0x09, 0x74, 0x68, 0x65, 0x6e,
+  0x0a, 0x09, 0x09, 0x09, 0x65, 0x63, 0x68, 0x6f, 0x20, 0x22, 0x5b, 0x69,
+  0x6e, 0x69, 0x74, 0x5d, 0x20, 0x72, 0x65, 0x61, 0x64, 0x69, 0x6e, 0x67,
+  0x20, 0x2f, 0x65, 0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64,
+  0x2f, 0x72, 0x63, 0x2e, 0x73, 0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c, 0x6f,
+  0x6e, 0x65, 0x22, 0x0a, 0x09, 0x09, 0x09, 0x73, 0x68, 0x20, 0x2f, 0x65,
+  0x74, 0x63, 0x2f, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x2f, 0x72, 0x63,
+  0x2e, 0x73, 0x74, 0x61, 0x6e, 0x64, 0x61, 0x6c, 0x6f, 0x6e, 0x65, 0x0a,
+  0x09, 0x09, 0x66, 0x69, 0x0a, 0x09, 0x66, 0x69, 0x0a, 0x0a, 0x09, 0x23,
+  0x0a, 0x09, 0x23, 0x20, 0x57, 0x65, 0x20, 0x6d, 0x61, 0x79, 0x20, 0x6e,
+  0x6f, 0x74, 0x20, 0x72, 0x65, 0x61, 0x63, 0x68, 0x20, 0x68, 0x65, 0x72,
+  0x65, 0x20, 0x69, 0x66, 0x20, 0x74, 0x68, 0x65, 0x20, 0x61, 0x69, 0x72,
+  0x66, 0x72, 0x61, 0x6d, 0x65, 0x2d, 0x73, 0x70, 0x65, 0x63, 0x69, 0x66,
+  0x69, 0x63, 0x20, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x65, 0x78,
+  0x69, 0x74, 0x73, 0x20, 0x74, 0x68, 0x65, 0x20, 0x73, 0x68, 0x65, 0x6c,
+  0x6c, 0x2e, 0x0a, 0x09, 0x23, 0x0a, 0x09, 0x65, 0x63, 0x68, 0x6f, 0x20,
+  0x22, 0x5b, 0x69, 0x6e, 0x69, 0x74, 0x5d, 0x20, 0x73, 0x74, 0x61, 0x72,
+  0x74, 0x75, 0x70, 0x20, 0x64, 0x6f, 0x6e, 0x65, 0x2e, 0x22, 0x0a, 0x66,
+  0x69, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00
+};
+unsigned int romfs_img_len = 7168;
diff --git a/nuttx/configs/px4fmu/include/rcS.template b/nuttx/configs/px4fmu/include/rcS.template
new file mode 100644
index 000000000..2f97a7223
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/rcS.template
@@ -0,0 +1,39 @@
+#echo "---------------------------"
+# Start apps
+echo "init: Starting applications.."
+echo "---------------------------"
+# WARNING:
+# ttyS0 is ALWAYS the NSH UART
+# ttyS1..SN are enumerated according to HW
+# uart indices (ttyS1 is the first UART NOT
+# configured for NSH, e.g. UART2)
+# ttyS0: UART1
+# ttyS1: UART2
+# ttyS2: UART5
+# ttyS3: UART6
+uorb start
+mavlink -d /dev/ttyS0 -b 57600 &
+echo "Trying to mount microSD card to /fs/microsd.."
+if mount -t vfat /dev/mmcsd0 /fs/microsd
+then
+echo "Successfully mounted SD card."
+else
+echo "FAILED mounting SD card."
+fi
+commander &
+sensors &
+attitude_estimator_bm &
+#position_estimator &
+ardrone_control -d /dev/ttyS1 -m attitude &
+gps -d /dev/ttyS3 -m all &
+#sdlog &
+#fixedwing_control &
+echo "---------------------------"
+echo "init: All applications started"
+echo "INIT DONE, RUNNING SYSTEM.."
+
+
+# WARNING! USE EXIT ONLY ON AR.DRONE
+# NO NSH COMMANDS CAN BE USED AFTER
+
+exit
diff --git a/nuttx/configs/px4fmu/include/up_adc.h b/nuttx/configs/px4fmu/include/up_adc.h
new file mode 100644
index 000000000..699c6a59a
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/up_adc.h
@@ -0,0 +1,60 @@
+/************************************************************************************
+ * configs/stm3240g-eval/src/up_adc.c
+ * arch/arm/src/board/up_adc.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifdef CONFIG_ADC
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: adc_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/adc.
+ *
+ ************************************************************************************/
+
+int adc_devinit(void);
+
+#endif /* CONFIG_ADC */
diff --git a/nuttx/configs/px4fmu/include/up_cpuload.h b/nuttx/configs/px4fmu/include/up_cpuload.h
new file mode 100644
index 000000000..b61c5c550
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/up_cpuload.h
@@ -0,0 +1,62 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef UP_CPULOAD_H_
+#define UP_CPULOAD_H_
+
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+
+#include <nuttx/sched.h>
+
+struct system_load_taskinfo_s {
+	uint64_t total_runtime;      ///< Runtime since start (start_time - total_runtime)/(start_time - current_time) = load
+	uint64_t curr_start_time;     ///< Start time of the current scheduling slot
+	uint64_t start_time;         ///< FIRST start time of task
+	FAR struct _TCB *tcb;               ///<
+	bool valid;                  ///< Task is currently active / valid
+};
+
+struct system_load_s {
+	uint64_t start_time;         ///< Global start time of measurements
+	struct system_load_taskinfo_s tasks[CONFIG_MAX_TASKS];
+	uint8_t initialized;
+	int total_count;
+	int running_count;
+	int sleeping_count;
+};
+
+void cpuload_initialize_once(void);
+
+#endif
+
+#endif
diff --git a/nuttx/configs/px4fmu/include/up_hrt.h b/nuttx/configs/px4fmu/include/up_hrt.h
new file mode 100644
index 000000000..6fd66ad74
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/up_hrt.h
@@ -0,0 +1,130 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * High-resolution timer callouts and timekeeping.
+ */
+
+#ifndef UP_HRT_H_
+#define UP_HRT_H_
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <time.h>
+#include <queue.h>
+
+/*
+ * Absolute time, in microsecond units.
+ *
+ * Absolute time is measured from some arbitrary epoch shortly after
+ * system startup.  It should never wrap or go backwards.
+ */
+typedef uint64_t	hrt_abstime;
+
+/*
+ * Callout function type.
+ *
+ * Note that callouts run in the timer interrupt context, so
+ * they are serialised with respect to each other, and must not
+ * block.
+ */
+typedef void		(* hrt_callout)(void *arg);
+
+/*
+ * Callout record.
+ */
+typedef struct hrt_call {
+	struct sq_entry_s	link;
+
+	hrt_abstime		deadline;
+	hrt_abstime		period;
+	hrt_callout		callout;
+	void			*arg;
+} *hrt_call_t;
+
+/*
+ * Get absolute time.
+ */
+extern hrt_abstime hrt_absolute_time(void);
+
+/*
+ * Convert a timespec to absolute time.
+ */
+extern hrt_abstime ts_to_abstime(struct timespec *ts);
+
+/*
+ * Convert absolute time to a timespec.
+ */
+extern void	abstime_to_ts(struct timespec *ts, hrt_abstime abstime);
+
+/*
+ * Call callout(arg) after delay has elapsed.
+ *
+ * If callout is NULL, this can be used to implement a timeout by testing the call
+ * with hrt_called().
+ */
+extern void	hrt_call_after(struct hrt_call *entry, hrt_abstime delay, hrt_callout callout, void *arg);
+
+/*
+ * Call callout(arg) at absolute time calltime.
+ */
+extern void	hrt_call_at(struct hrt_call *entry, hrt_abstime calltime, hrt_callout callout, void *arg);
+
+/*
+ * Call callout(arg) after delay, and then after every interval.
+ *
+ * Note thet the interval is timed between scheduled, not actual, call times, so the call rate may
+ * jitter but should not drift.
+ */
+extern void	hrt_call_every(struct hrt_call *entry, hrt_abstime delay, hrt_abstime interval, hrt_callout callout, void *arg);
+
+/*
+ * If this returns true, the entry has been invoked and removed from the callout list, 
+ * or it has never been entered.
+ *
+ * Always returns false for repeating callouts.
+ */
+extern bool	hrt_called(struct hrt_call *entry);
+
+/*
+ * Remove the entry from the callout list.
+ */
+extern void	hrt_cancel(struct hrt_call *entry);
+
+/*
+ * Initialise the HRT.
+ */
+extern void	hrt_init(void);
+
+#endif /* UP_HRT_H_ */
diff --git a/nuttx/configs/px4fmu/include/up_pwm_servo.h b/nuttx/configs/px4fmu/include/up_pwm_servo.h
new file mode 100644
index 000000000..0b35035d5
--- /dev/null
+++ b/nuttx/configs/px4fmu/include/up_pwm_servo.h
@@ -0,0 +1,117 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Low-level PWM servo control.
+ *
+ * The pwm_servo module supports servos connected to STM32 timer
+ * blocks.
+ *
+ * On PX4FMU, the outputs are:
+ *
+ * 0 : USART2/multi CTS
+ * 1 : USART2/multi RTS
+ * 2 : USART2/multi TX
+ * 3 : USART2/multi RX
+ * 4 : CAN2 TX
+ * 5 : CAN2 RX
+ */
+
+#ifndef UP_PWM_SERVO_H
+#define UP_PWM_SERVO_H
+
+typedef uint16_t	servo_position_t;
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * Intialise the PWM servo outputs using the specified configuration.
+ *
+ * @param channel_mask	Bitmask of channels (LSB = channel 0) to enable.
+ *			This allows some of the channels to remain configured
+ *			as GPIOs or as another function.
+ * @return		OK on success.
+ */
+extern int		up_pwm_servo_init(uint32_t channel_mask);
+
+/**
+ * De-initialise the PWM servo outputs.
+ */
+extern void		up_pwm_servo_deinit(void);
+
+/**
+ * Arm or disarm servo outputs.
+ *
+ * When disarmed, servos output no pulse.
+ *
+ * @bug This function should, but does not, guarantee that any pulse 
+ *      currently in progress is cleanly completed.
+ *
+ * @param armed		If true, outputs are armed; if false they
+ *			are disarmed.
+ */
+extern void		up_pwm_servo_arm(bool armed);
+
+/**
+ * Set the servo update rate
+ *
+ * @param rate		The update rate in Hz to set.
+ * @return		OK on success, -ERANGE if an unsupported update rate is set.
+ */
+extern int		up_pwm_servo_set_rate(unsigned rate);
+
+/**
+ * Set the current output value for a channel.
+ *
+ * @param channel	The channel to set.
+ * @param value		The output pulse width in microseconds.
+ */
+extern int		up_pwm_servo_set(unsigned channel, servo_position_t value);
+
+/**
+ * Get the current output value for a channel.
+ *
+ * @param channel	The channel to read.
+ * @return		The output pulse width in microseconds, or zero if
+ *			outputs are not armed or not configured.
+ */
+extern servo_position_t	up_pwm_servo_get(unsigned channel);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* UP_PWM_SERVO_H */
diff --git a/nuttx/configs/px4fmu/nsh/Make.defs b/nuttx/configs/px4fmu/nsh/Make.defs
new file mode 100644
index 000000000..87508e22e
--- /dev/null
+++ b/nuttx/configs/px4fmu/nsh/Make.defs
@@ -0,0 +1,3 @@
+include ${TOPDIR}/.config
+
+include $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/Make.defs
diff --git a/nuttx/configs/px4fmu/nsh/appconfig b/nuttx/configs/px4fmu/nsh/appconfig
new file mode 100644
index 000000000..85762f4c6
--- /dev/null
+++ b/nuttx/configs/px4fmu/nsh/appconfig
@@ -0,0 +1,92 @@
+############################################################################
+# configs/px4fmu/nsh/appconfig
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Path to example in apps/examples containing the user_start entry point
+
+CONFIGURED_APPS	+= examples/nsh
+
+# The NSH application library
+CONFIGURED_APPS += nshlib
+CONFIGURED_APPS += system/readline
+
+# System library - utility functions
+CONFIGURED_APPS += systemlib
+
+CONFIGURED_APPS += systemcmds/reboot
+CONFIGURED_APPS += systemcmds/perf
+CONFIGURED_APPS += systemcmds/top
+CONFIGURED_APPS += systemcmds/boardinfo
+#CONFIGURED_APPS += systemcmds/calibration
+
+CONFIGURED_APPS += uORB
+
+ifeq ($(CONFIG_MAVLINK),y)
+CONFIGURED_APPS += mavlink
+endif
+
+CONFIGURED_APPS += gps
+CONFIGURED_APPS += commander
+#CONFIGURED_APPS += sdlog
+CONFIGURED_APPS += sensors
+CONFIGURED_APPS += ardrone_control
+CONFIGURED_APPS += px4/attitude_estimator_bm
+CONFIGURED_APPS += fixedwing_control
+CONFIGURED_APPS += mix_and_link
+CONFIGURED_APPS += position_estimator
+CONFIGURED_APPS += attitude_estimator_ekf
+
+#CONFIGURED_APPS += system/i2c
+#CONFIGURED_APPS += tools/i2c_dev
+
+# Communication and Drivers
+CONFIGURED_APPS	+= drivers/device
+#CONFIGURED_APPS += drivers/ms5611
+CONFIGURED_APPS	+= px4/px4io/driver
+CONFIGURED_APPS += px4/fmu
+
+# Testing stuff
+CONFIGURED_APPS += px4/sensors_bringup
+CONFIGURED_APPS += px4/tests
+
+ifeq ($(CONFIG_CAN),y)
+#CONFIGURED_APPS += examples/can
+endif
+
+#ifeq ($(CONFIG_USBDEV),y)
+#ifeq ($(CONFIG_CDCACM),y)
+CONFIGURED_APPS += examples/cdcacm
+#endif
+#endif
+
diff --git a/nuttx/configs/px4fmu/nsh/defconfig b/nuttx/configs/px4fmu/nsh/defconfig
new file mode 100755
index 000000000..58c9ca45c
--- /dev/null
+++ b/nuttx/configs/px4fmu/nsh/defconfig
@@ -0,0 +1,1053 @@
+############################################################################
+# configs/px4fmu/nsh/defconfig
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+#
+# architecture selection
+#
+# CONFIG_ARCH - identifies the arch subdirectory and, hence, the
+#   processor architecture.
+# CONFIG_ARCH_family - for use in C code.  This identifies the
+#   particular chip family that the architecture is implemented
+#   in.
+# CONFIG_ARCH_architecture - for use in C code.  This identifies the
+#   specific architecture within the chip familyl.
+# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+# CONFIG_ARCH_CHIP_name - For use in C code
+# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
+#   the board that supports the particular chip or SoC.
+# CONFIG_ARCH_BOARD_name - for use in C code
+# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
+# CONFIG_BOARD_LOOPSPERMSEC - for delay loops
+# CONFIG_DRAM_SIZE - Describes the installed DRAM.
+# CONFIG_DRAM_START - The start address of DRAM (physical)
+# CONFIG_DRAM_END - Last address+1 of installed RAM
+# CONFIG_ARCH_IRQPRIO - The STM3240xxx supports interrupt prioritization
+# CONFIG_ARCH_FPU - The STM3240xxx supports a floating point unit (FPU).
+# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+#   stack. If defined, this symbol is the size of the interrupt
+#   stack in bytes.  If not defined, the user task stacks will be
+#   used during interrupt handling.
+# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+# CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
+# CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS -  Enable support for buttons. Unique to board architecture.
+# CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+#   cause a 100 second delay during boot-up.  This 100 second delay
+#   serves no purpose other than it allows you to calibrate
+#   CONFIG_BOARD_LOOPSPERMSEC.  You simply use a stop watch to measure
+#   the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
+#   the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
+#
+CONFIG_ARCH=arm
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_CORTEXM4=y
+CONFIG_ARCH_CHIP=stm32
+CONFIG_ARCH_CHIP_STM32F405RG=y
+CONFIG_ARCH_BOARD=px4fmu
+CONFIG_ARCH_BOARD_PX4FMU=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_DRAM_SIZE=0x00030000
+CONFIG_DRAM_START=0x20000000
+CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+CONFIG_ARCH_IRQPRIO=y
+CONFIG_ARCH_FPU=y
+CONFIG_ARCH_INTERRUPTSTACK=n
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_BOOTLOADER=n
+CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_BUTTONS=n
+CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=y
+CONFIG_ARCH_MATH_H=y
+
+CONFIG_ARMV7M_CMNVECTOR=y
+
+#
+# LIBC printf() options
+#   
+#   CONFIG_LIBC_FLOATINGPOINT - Enables printf("%f")
+#   CONFIG_LIBC_FIXEDPRECISION - Sets 7 digits after dot for printing:
+#                                5.1234567
+#   CONFIG_HAVE_LONG_LONG - Enabled printf("%llu)
+#
+CONFIG_LIBC_FLOATINGPOINT=y
+CONFIG_HAVE_LONG_LONG=y
+#CONFIG_LIBC_FIXEDPRECISION=7
+
+#
+# CMSIS options
+#
+#    CONFIG_DSPLIB_TARGET - Target for the CMSIS DSP library, one of
+#   CortexM0, CortexM3 or CortexM4 (with fpu)
+#
+CONFIG_CMSIS_DSPLIB_TARGET=CortexM4
+
+#
+# JTAG Enable settings (by default JTAG-DP and SW-DP are enabled):
+#
+#   CONFIG_STM32_DFU - Use the DFU bootloader, not JTAG (ignored)
+#
+# JTAG Enable options:
+#
+#   CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+#   CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+#     but without JNTRST.
+#   CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+#
+CONFIG_STM32_DFU=n
+CONFIG_STM32_JTAG_FULL_ENABLE=y
+CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n
+CONFIG_STM32_JTAG_SW_ENABLE=n
+
+#
+# On-board FSMC SRAM configuration
+#
+# CONFIG_STM32_FSMC - Required.  See below
+# CONFIG_MM_REGIONS - Required.  Must be 2 or 3 (see above)
+#
+# CONFIG_STM32_FSMC_SRAM=y - Indicates that SRAM is available via the
+#   FSMC (as opposed to an LCD or FLASH).
+# CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space
+# CONFIG_HEAP2_END - The end (+1) of the SRAM in the FSMC address space
+#
+#CONFIG_STM32_FSMC_SRAM=n
+#CONFIG_HEAP2_BASE=0x64000000
+#CONFIG_HEAP2_END=(0x64000000+(2*1024*1024))
+
+#
+#  Individual subsystems can be enabled:
+#
+# This set is exhaustive for PX4FMU and should be safe to cut and
+# paste into any other config.
+#
+# AHB1:
+CONFIG_STM32_CRC=n
+CONFIG_STM32_BKPSRAM=y
+CONFIG_STM32_CCMDATARAM=y
+CONFIG_STM32_DMA1=y
+CONFIG_STM32_DMA2=y
+CONFIG_STM32_ETHMAC=n
+CONFIG_STM32_OTGHS=n
+# AHB2:
+CONFIG_STM32_DCMI=n
+CONFIG_STM32_CRYP=n
+CONFIG_STM32_HASH=n
+CONFIG_STM32_RNG=n
+CONFIG_STM32_OTGFS=y
+# AHB3:
+CONFIG_STM32_FSMC=n
+# APB1:
+# TIM2 is owned by PWM output
+CONFIG_STM32_TIM2=n
+# TIM3 is owned by TONE_ALARM
+CONFIG_STM32_TIM3=n
+CONFIG_STM32_TIM4=y
+CONFIG_STM32_TIM5=y
+CONFIG_STM32_TIM6=y
+CONFIG_STM32_TIM7=y
+CONFIG_STM32_TIM12=y
+CONFIG_STM32_TIM13=y
+CONFIG_STM32_TIM14=y
+CONFIG_STM32_WWDG=y
+CONFIG_STM32_SPI2=n
+CONFIG_STM32_SPI3=y
+CONFIG_STM32_USART2=y
+CONFIG_STM32_USART3=n
+CONFIG_STM32_UART4=n
+CONFIG_STM32_UART5=y
+CONFIG_STM32_I2C1=y
+CONFIG_STM32_I2C2=y
+CONFIG_STM32_I2C3=y
+CONFIG_STM32_CAN1=n
+CONFIG_STM32_CAN2=y
+CONFIG_STM32_DAC=n
+CONFIG_STM32_PWR=y
+# APB2:
+# TIM1 is owned by the HRT
+CONFIG_STM32_TIM1=n
+# TIM8 is owned by PWM output
+CONFIG_STM32_TIM8=n
+CONFIG_STM32_USART1=y
+CONFIG_STM32_USART6=y
+CONFIG_STM32_ADC1=n
+CONFIG_STM32_ADC2=n
+CONFIG_STM32_ADC3=y
+CONFIG_STM32_SDIO=n
+CONFIG_STM32_SPI1=y
+CONFIG_STM32_SYSCFG=y
+CONFIG_STM32_TIM9=y
+CONFIG_STM32_TIM10=y
+CONFIG_STM32_TIM11=y
+
+#
+# Configure the ADC
+#
+CONFIG_ADC=y
+# select trigger timer 
+CONFIG_STM32_TIM4_ADC3=y
+# select sample frequency  1^=1.5Msamples/second
+# 65535^=10samples/second 16bit-timer runs at 84/128 MHz
+CONFIG_STM32_ADC3_SAMPLE_FREQUENCY=6000
+# select timer channel 0=CC1,...,3=CC4
+CONFIG_STM32_ADC3_TIMTRIG=3
+CONFIG_ADC_DMA=y
+# only 4 places usable!
+CONFIG_ADC_FIFOSIZE=5
+
+#
+# Timer and I2C devices may need to the following to force power to be applied:
+#
+#CONFIG_STM32_FORCEPOWER=y
+
+#
+# I2C configuration
+#
+CONFIG_I2C=y
+CONFIG_I2C_POLLED=y
+CONFIG_I2C_TRANSFER=y
+CONFIG_I2C_WRITEREAD=y
+CONFIG_I2C_TRACE=n
+# Allow 180 us per byte, a wide margin for the 400 KHz clock we're using
+# e.g. 9.6 ms for an EEPROM page write, 0.9 ms for a MAG update
+CONFIG_STM32_I2CTIMEOUS_PER_BYTE=200
+# Constant overhead for generating I2C start / stop conditions
+CONFIG_STM32_I2CTIMEOUS_START_STOP=700
+CONFIG_DEBUG_I2C=n
+
+#
+# STM32F40xxx specific serial device driver settings
+#
+# CONFIG_SERIAL_TERMIOS - Serial driver supports termios.h interfaces (tcsetattr,
+#   tcflush, etc.).  If this is not defined, then the terminal settings (baud,
+#   parity, etc.) are not configurable at runtime; serial streams cannot be
+#   flushed, etc.
+#
+# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the
+#   console and ttys0 (default is the USART1).
+# CONFIG_USARTn_RXBUFSIZE - Characters are buffered as received.
+#   This specific the size of the receive buffer
+# CONFIG_USARTn_TXBUFSIZE - Characters are buffered before
+#   being sent.  This specific the size of the transmit buffer
+# CONFIG_USARTn_BAUD - The configure BAUD of the UART.  Must be
+# CONFIG_USARTn_BITS - The number of bits.  Must be either 7 or 8.
+# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+# CONFIG_USARTn_2STOP - Two stop bits
+#
+CONFIG_SERIAL_TERMIOS=y
+
+CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_USART2_SERIAL_CONSOLE=n
+CONFIG_USART3_SERIAL_CONSOLE=n
+CONFIG_USART4_SERIAL_CONSOLE=n
+CONFIG_USART5_SERIAL_CONSOLE=n
+CONFIG_USART6_SERIAL_CONSOLE=n
+
+#Mavlink messages can be bigger than 128
+CONFIG_USART1_TXBUFSIZE=512
+CONFIG_USART2_TXBUFSIZE=128
+CONFIG_USART3_TXBUFSIZE=128
+CONFIG_USART4_TXBUFSIZE=128
+CONFIG_USART5_TXBUFSIZE=64
+CONFIG_USART6_TXBUFSIZE=128
+
+CONFIG_USART1_RXBUFSIZE=512
+CONFIG_USART2_RXBUFSIZE=128
+CONFIG_USART3_RXBUFSIZE=128
+CONFIG_USART4_RXBUFSIZE=128
+CONFIG_USART5_RXBUFSIZE=128
+CONFIG_USART6_RXBUFSIZE=128
+
+CONFIG_USART1_BAUD=57600
+CONFIG_USART2_BAUD=115200
+CONFIG_USART3_BAUD=115200
+CONFIG_USART4_BAUD=115200
+CONFIG_USART5_BAUD=115200
+CONFIG_USART6_BAUD=9600
+
+CONFIG_USART1_BITS=8
+CONFIG_USART2_BITS=8
+CONFIG_USART3_BITS=8
+CONFIG_USART4_BITS=8
+CONFIG_USART5_BITS=8
+CONFIG_USART6_BITS=8
+
+CONFIG_USART1_PARITY=0
+CONFIG_USART2_PARITY=0
+CONFIG_USART3_PARITY=0
+CONFIG_USART4_PARITY=0
+CONFIG_USART5_PARITY=0
+CONFIG_USART6_PARITY=0
+
+CONFIG_USART1_2STOP=0
+CONFIG_USART2_2STOP=0
+CONFIG_USART3_2STOP=0
+CONFIG_USART4_2STOP=0
+CONFIG_USART5_2STOP=0
+CONFIG_USART6_2STOP=0
+
+CONFIG_USART1_RXDMA=n
+CONFIG_USART2_RXDMA=y
+CONFIG_USART3_RXDMA=n
+CONFIG_USART4_RXDMA=n
+CONFIG_USART5_RXDMA=y
+CONFIG_USART6_RXDMA=y
+
+#
+# PX4FMU specific driver settings
+#
+# CONFIG_HRT_TIMER
+#   Enables the high-resolution timer.  The board definition must
+#   set HRT_TIMER and HRT_TIMER_CHANNEL to the timer and capture/
+#   compare channels to be used.
+# CONFIG_HRT_PPM
+#   Enables R/C PPM input using the HRT.  The board definition must
+#   set HRT_PPM_CHANNEL to the timer capture/compare channel to be
+#   used, and define GPIO_PPM_IN to configure the appropriate timer
+#   GPIO.
+# CONFIG_TONE_ALARM
+#   Enables the tone alarm (buzzer) driver  The board definition must
+#   set TONE_ALARM_TIMER and TONE_ALARM_CHANNEL to the timer and
+#   capture/compare channels to be used.
+# CONFIG_PWM_SERVO
+#   Enables the PWM servo driver.  The driver configuration must be
+#   supplied by the board support at initialisation time.
+#   Note that USART2 must be disabled on the PX4 board for this to
+#   be available.
+# CONFIG_MULTIPORT
+#   Enabled support for run-time (or EEPROM based boot-time) configuration
+#   of ports for different functions (e.g. USART2 or ARDrone or PWM out)
+#
+#
+CONFIG_HRT_TIMER=y
+CONFIG_HRT_PPM=y
+CONFIG_TONE_ALARM=y
+CONFIG_PWM_SERVO=n
+CONFIG_MULTIPORT=n
+
+#
+# CONFIG_UART2_RTS_CTS_AS_GPIO
+#   If set, enables RTS and CTS pins as additional GPIOs 2 and 3
+# 
+CONFIG_PX4_UART2_RTS_CTS_AS_GPIO=y
+
+
+#
+# STM32F40xxx specific SPI device driver settings
+#
+CONFIG_SPI_EXCHANGE=y
+# DMA needs more work, not implemented on STM32F4x yet
+#CONFIG_STM32_SPI_DMA=y
+
+#
+# STM32F40xxx specific CAN device driver settings
+#
+# CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+#   CONFIG_STM32_CAN2 must also be defined)
+# CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+#   Default: 8
+# CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+#   Default: 4
+# CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+#   mode for testing. The STM32 CAN driver does support loopback mode.
+# CONFIG_CAN1_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN1 is defined.
+# CONFIG_CAN2_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN2 is defined.
+#
+CONFIG_CAN=n
+#CONFIG_CAN_FIFOSIZE
+#CONFIG_CAN_NPENDINGRTR
+CONFIG_CAN_LOOPBACK=n
+CONFIG_CAN1_BAUD=700000
+CONFIG_CAN2_BAUD=700000
+
+#
+# General build options
+#
+# CONFIG_RRLOAD_BINARY - make the rrload binary format used with
+#   BSPs from www.ridgerun.com using the tools/mkimage.sh script
+# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format
+#   used with many different loaders using the GNU objcopy program
+#   Should not be selected if you are not using the GNU toolchain.
+# CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format
+#   used with many different loaders using the GNU objcopy program
+#   Should not be selected if you are not using the GNU toolchain.
+# CONFIG_RAW_BINARY - make a raw binary format file used with many
+#   different loaders using the GNU objcopy program.  This option
+#   should not be selected if you are not using the GNU toolchain.
+# CONFIG_HAVE_LIBM - toolchain supports libm.a
+#
+CONFIG_RRLOAD_BINARY=n
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MOTOROLA_SREC=n
+CONFIG_RAW_BINARY=y
+CONFIG_HAVE_LIBM=y
+
+#
+# General OS setup
+#
+# CONFIG_APPS_DIR - Identifies the relative path to the directory
+#   that builds the application to link with NuttX.  Default: ../apps
+# CONFIG_DEBUG - enables built-in debug options
+# CONFIG_DEBUG_VERBOSE - enables verbose debug output
+# CONFIG_DEBUG_SYMBOLS - build without optimization and with
+#   debug symbols (needed for use with a debugger).
+# CONFIG_HAVE_CXX - Enable support for C++
+# CONFIG_MM_REGIONS - If the architecture includes multiple
+#   regions of memory to allocate from, this specifies the
+#   number of memory regions that the memory manager must
+#   handle and enables the API mm_addregion(start, end);
+# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot
+#   time console output
+# CONFIG_MSEC_PER_TICK - The default system timer is 100Hz
+#   or MSEC_PER_TICK=10.  This setting may be defined to
+#   inform NuttX that the processor hardware is providing
+#   system timer interrupts at some interrupt interval other
+#   than 10 msec.
+# CONFIG_RR_INTERVAL - The round robin timeslice will be set
+#   this number of milliseconds;  Round robin scheduling can
+#   be disabled by setting this value to zero.
+# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in 
+#   scheduler to monitor system performance
+# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a
+#   task name to save in the TCB.  Useful if scheduler
+#   instrumentation is selected.  Set to zero to disable.
+# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY -
+#   Used to initialize the internal time logic.
+# CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions.
+#   You would only need this if you are concerned about accurate
+#   time conversions in the past or in the distant future.
+# CONFIG_JULIAN_TIME - Enables Julian time conversions. You
+#   would only need this if you are concerned about accurate
+#   time conversion in the distand past.  You must also define
+#   CONFIG_GREGORIAN_TIME in order to use Julian time.
+# CONFIG_DEV_CONSOLE - Set if architecture-specific logic
+#   provides /dev/console.  Enables stdout, stderr, stdin.
+# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console
+#   driver (minimul support)
+# CONFIG_MUTEX_TYPES: Set to enable support for recursive and
+#   errorcheck mutexes. Enables pthread_mutexattr_settype().
+# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority
+#   inheritance on mutexes and semaphores. 
+# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority
+#   inheritance is enabled.  It defines the maximum number of
+#   different threads (minus one) that can take counts on a
+#   semaphore with priority inheritance support.  This may be 
+#   set to zero if priority inheritance is disabled OR if you
+#   are only using semaphores as mutexes (only one holder) OR
+#   if no more than two threads participate using a counting
+#   semaphore.
+# CONFIG_SEM_NNESTPRIO.  If priority inheritance is enabled,
+#   then this setting is the maximum number of higher priority
+#   threads (minus 1) than can be waiting for another thread
+#   to release a count on a semaphore.  This value may be set
+#   to zero if no more than one thread is expected to wait for
+#   a semaphore.
+# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors
+#   by task_create() when a new task is started.  If set, all
+#   files/drivers will appear to be closed in the new task.
+# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first
+#   three file descriptors (stdin, stdout, stderr) by task_create()
+#   when a new task is started. If set, all files/drivers will
+#   appear to be closed in the new task except for stdin, stdout,
+#   and stderr.
+# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket
+#   desciptors by task_create() when a new task is started. If
+#   set, all sockets will appear to be closed in the new task.
+# CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+#  handle delayed processing from interrupt handlers.  This feature
+#  is required for some drivers but, if there are not complaints,
+#  can be safely disabled.  The worker thread also performs
+#  garbage collection -- completing any delayed memory deallocations
+#  from interrupt handlers.  If the worker thread is disabled,
+#  then that clean will be performed by the IDLE thread instead
+#  (which runs at the lowest of priority and may not be appropriate
+#  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+#  is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+#  thread.  Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+#  work in units of microseconds.  Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+#  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+#  the worker thread.  Default: 4
+# CONFIG_SCHED_WAITPID - Enable the waitpid() API
+# CONFIG_SCHED_ATEXIT - Enabled the atexit() API
+#
+#CONFIG_APPS_DIR=
+CONFIG_DEBUG=y
+CONFIG_DEBUG_VERBOSE=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_ANALOG=n
+CONFIG_DEBUG_FS=n
+CONFIG_DEBUG_GRAPHICS=n
+CONFIG_DEBUG_LCD=n
+CONFIG_DEBUG_USB=n
+CONFIG_DEBUG_NET=n
+CONFIG_DEBUG_RTC=n
+CONFIG_HAVE_CXX=y
+CONFIG_MM_REGIONS=2
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_MSEC_PER_TICK=1
+CONFIG_RR_INTERVAL=1
+CONFIG_SCHED_INSTRUMENTATION=y
+CONFIG_TASK_NAME_SIZE=24
+CONFIG_START_YEAR=1970
+CONFIG_START_MONTH=1
+CONFIG_START_DAY=1
+CONFIG_GREGORIAN_TIME=n
+CONFIG_JULIAN_TIME=n
+CONFIG_DEV_CONSOLE=y
+CONFIG_DEV_LOWCONSOLE=n
+CONFIG_MUTEX_TYPES=n
+CONFIG_PRIORITY_INHERITANCE=y
+CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_NNESTPRIO=8
+CONFIG_FDCLONE_DISABLE=n
+CONFIG_FDCLONE_STDIO=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SCHED_WORKQUEUE=n
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SIG_SIGWORK=4
+CONFIG_SCHED_WAITPID=y
+CONFIG_SCHED_ATEXIT=n
+
+#
+# The following can be used to disable categories of
+# APIs supported by the OS.  If the compiler supports
+# weak functions, then it should not be necessary to
+# disable functions unless you want to restrict usage
+# of those APIs.
+#
+# There are certain dependency relationships in these
+# features.
+#
+# o mq_notify logic depends on signals to awaken tasks
+#   waiting for queues to become full or empty.
+# o pthread_condtimedwait() depends on signals to wake
+#   up waiting tasks.
+#
+CONFIG_DISABLE_CLOCK=n
+CONFIG_DISABLE_POSIX_TIMERS=n
+CONFIG_DISABLE_PTHREAD=n
+CONFIG_DISABLE_SIGNALS=n
+CONFIG_DISABLE_MQUEUE=n
+CONFIG_DISABLE_MOUNTPOINT=n
+CONFIG_DISABLE_ENVIRON=n
+CONFIG_DISABLE_POLL=n
+
+#
+# Misc libc settings
+#
+# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a
+#   little smaller if we do not support fieldwidthes
+#
+CONFIG_NOPRINTF_FIELDWIDTH=n
+
+#
+# Allow for architecture optimized implementations
+#
+# The architecture can provide optimized versions of the
+# following to improve system performance
+#
+CONFIG_ARCH_MEMCPY=y
+CONFIG_ARCH_MEMCMP=n
+CONFIG_ARCH_MEMMOVE=n
+CONFIG_ARCH_MEMSET=n
+CONFIG_ARCH_STRCMP=n
+CONFIG_ARCH_STRCPY=n
+CONFIG_ARCH_STRNCPY=n
+CONFIG_ARCH_STRLEN=n
+CONFIG_ARCH_STRNLEN=n
+CONFIG_ARCH_BZERO=n
+
+#
+# Sizes of configurable things (0 disables)
+#
+# CONFIG_MAX_TASKS - The maximum number of simultaneously
+#   active tasks.  This value must be a power of two.
+# CONFIG_MAX_TASK_ARGS - This controls the maximum number of
+#   of parameters that a task may receive (i.e., maxmum value
+#   of 'argc')
+# CONFIG_NPTHREAD_KEYS - The number of items of thread-
+#   specific data that can be retained
+# CONFIG_NFILE_DESCRIPTORS - The maximum number of file
+#   descriptors (one for each open)
+# CONFIG_NFILE_STREAMS - The maximum number of streams that
+#   can be fopen'ed
+# CONFIG_NAME_MAX - The maximum size of a file name.
+# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate
+#   on fopen. (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_STDIO_LINEBUFFER - If standard C buffered I/O is enabled
+#   (CONFIG_STDIO_BUFFER_SIZE > 0), then this option may be added
+#   to force automatic, line-oriented flushing the output buffer
+#   for putc(), fputc(), putchar(), puts(), fputs(), printf(),
+#   fprintf(), and vfprintf().  When a newline is encountered in
+#   the output string, the output buffer will be flushed.  This
+#   (slightly) increases the NuttX footprint but supports the kind
+#   of behavior that people expect for printf().
+# CONFIG_NUNGET_CHARS - Number of characters that can be
+#   buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message
+#   structures.  The system manages a pool of preallocated
+#   message structures to minimize dynamic allocations
+# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with
+#   a fixed payload size given by this settin (does not include
+#   other message structure overhead.
+# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that
+#   can be passed to a watchdog handler
+# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog
+#   structures.  The system manages a pool of preallocated
+#   watchdog structures to minimize dynamic allocations
+# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX
+#   timer structures.  The system manages a pool of preallocated
+#   timer structures to minimize dynamic allocations.  Set to
+#   zero for all dynamic allocations.
+#
+CONFIG_MAX_TASKS=32
+CONFIG_MAX_TASK_ARGS=8
+CONFIG_NPTHREAD_KEYS=4
+CONFIG_NFILE_DESCRIPTORS=20
+CONFIG_NFILE_STREAMS=20
+CONFIG_NAME_MAX=32
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_NUNGET_CHARS=2
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=50
+CONFIG_PREALLOC_TIMERS=50
+
+#
+# Filesystem configuration
+#
+# CONFIG_FS_FAT - Enable FAT filesystem support
+# CONFIG_FAT_SECTORSIZE - Max supported sector size
+# CONFIG_FAT_LCNAMES - Enable use of the NT-style upper/lower case 8.3
+#   file name support.
+# CONFIG_FAT_LFN - Enable FAT long file names.  NOTE:  Microsoft claims
+#   patents on FAT long file name technology.  Please read the
+#   disclaimer in the top-level COPYING file and only enable this
+#   feature if you understand these issues.
+# CONFIG_FAT_MAXFNAME - If CONFIG_FAT_LFN is defined, then the
+#   default, maximum long file name is 255 bytes.  This can eat up
+#   a lot of memory (especially stack space).  If you are willing
+#   to live with some non-standard, short long file names, then
+#   define this value.  A good choice would be the same value as
+#   selected for CONFIG_NAME_MAX which will limit the visibility
+#   of longer file names anyway.
+# CONFIG_FS_NXFFS: Enable NuttX FLASH file system (NXFF) support.
+# CONFIG_NXFFS_ERASEDSTATE: The erased state of FLASH. 
+#   This must have one of the values of 0xff or 0x00.
+#   Default: 0xff.
+# CONFIG_NXFFS_PACKTHRESHOLD: When packing flash file data,
+#   don't both with file chunks smaller than this number of data bytes.
+# CONFIG_NXFFS_MAXNAMLEN: The maximum size of an NXFFS file name.
+#   Default: 255.
+# CONFIG_NXFFS_PACKTHRESHOLD: When packing flash file data,
+#   don't both with file chunks smaller than this number of data bytes.
+#   Default: 32.
+# CONFIG_NXFFS_TAILTHRESHOLD: clean-up can either mean
+#   packing files together toward the end of the file or, if file are
+#   deleted at the end of the file, clean up can simply mean erasing
+#   the end of FLASH memory so that it can be re-used again.  However,
+#   doing this can also harm the life of the FLASH part because it can
+#   mean that the tail end of the FLASH is re-used too often. This
+#   threshold determines if/when it is worth erased the tail end of FLASH
+#   and making it available for re-use (and possible over-wear).
+#   Default: 8192.
+# CONFIG_FS_ROMFS - Enable ROMFS filesystem support
+# CONFIG_FS_RAMMAP - For file systems that do not support XIP, this
+#   option will enable a limited form of memory mapping that is
+#   implemented by copying whole files into memory.
+#
+CONFIG_FS_FAT=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FAT_MAXFNAME=32
+CONFIG_FS_NXFFS=n
+CONFIG_FS_ROMFS=y
+
+#
+# SPI-based MMC/SD driver
+#
+# CONFIG_MMCSD_NSLOTS
+#   Number of MMC/SD slots supported by the driver
+# CONFIG_MMCSD_READONLY
+#   Provide read-only access (default is read/write)
+# CONFIG_MMCSD_SPICLOCK - Maximum SPI clock to drive MMC/SD card.
+#   Default is 20MHz, current setting 24 MHz
+#
+CONFIG_MMCSD_NSLOTS=1
+CONFIG_MMCSD_READONLY=n
+CONFIG_MMCSD_SPICLOCK=24000000
+
+#
+# Block driver buffering
+#
+# CONFIG_FS_READAHEAD
+#   Enable read-ahead buffering
+# CONFIG_FS_WRITEBUFFER
+#   Enable write buffering
+#
+CONFIG_FS_READAHEAD=n
+CONFIG_FS_WRITEBUFFER=n
+
+#
+# RTC Configuration
+#
+# CONFIG_RTC - Enables general support for a hardware RTC.  Specific
+#   architectures may require other specific settings.
+# CONFIG_RTC_DATETIME - There are two general types of RTC:  (1) A simple
+#   battery backed counter that keeps the time when power is down, and (2)
+#    A full date / time RTC the provides the date and time information, often
+#   in BCD format.  If CONFIG_RTC_DATETIME is selected, it specifies this
+#   second kind of RTC. In this case, the RTC is used to "seed" the normal
+#   NuttX timer and the NuttX system timer provides for higher resoution
+#   time.
+# CONFIG_RTC_HIRES - If CONFIG_RTC_DATETIME not selected, then the simple,
+#   battery backed counter is used.  There are two different implementations
+#   of such simple counters based on the time resolution of the counter:
+#   The typical RTC keeps time to resolution of 1 second, usually
+#   supporting a 32-bit time_t value.  In this case, the RTC is used to
+#   "seed" the normal NuttX timer and the NuttX timer provides for higher
+#   resoution time. If CONFIG_RTC_HIRES is enabled in the NuttX configuration,
+#   then the RTC provides higher resolution time and completely replaces the
+#   system timer for purpose of date and time.
+# CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the frequency
+#  of the high resolution RTC must be provided.  If CONFIG_RTC_HIRES is
+#   not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
+# CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an
+#  alarm.  A callback function will be executed when the alarm goes off
+#
+CONFIG_RTC=n
+CONFIG_RTC_DATETIME=y
+CONFIG_RTC_HIRES=n
+CONFIG_RTC_FREQUENCY=n
+CONFIG_RTC_ALARM=n
+
+#
+# USB Device Configuration
+#
+# CONFIG_USBDEV
+#   Enables USB device support
+# CONFIG_USBDEV_ISOCHRONOUS
+#   Build in extra support for isochronous endpoints
+# CONFIG_USBDEV_DUALSPEED
+#   Hardware handles high and full speed operation (USB 2.0)
+# CONFIG_USBDEV_SELFPOWERED
+#   Will cause USB features to indicate that the device is
+#   self-powered
+# CONFIG_USBDEV_MAXPOWER
+#   Maximum power consumption in mA
+# CONFIG_USBDEV_TRACE
+#   Enables USB tracing for debug
+# CONFIG_USBDEV_TRACE_NRECORDS
+#   Number of trace entries to remember
+#
+CONFIG_USBDEV=y
+CONFIG_USBDEV_ISOCHRONOUS=n
+CONFIG_USBDEV_DUALSPEED=n
+CONFIG_USBDEV_SELFPOWERED=y
+CONFIG_USBDEV_REMOTEWAKEUP=n
+CONFIG_USBDEV_MAXPOWER=500
+CONFIG_USBDEV_TRACE=n
+CONFIG_USBDEV_TRACE_NRECORDS=512
+
+#
+# USB Serial Device Configuration (Prolifics PL2303 emulation)
+#
+# CONFIG_PL2303
+#   Enable compilation of the USB serial driver
+# CONFIG_PL2303_EPINTIN
+#   The logical 7-bit address of a hardware endpoint that supports
+#   interrupt IN operation
+# CONFIG_PL2303_EPBULKOUT
+#   The logical 7-bit address of a hardware endpoint that supports
+#   bulk OUT operation
+# CONFIG_PL2303_EPBULKIN
+#   The logical 7-bit address of a hardware endpoint that supports
+#   bulk IN operation
+# # CONFIG_PL2303_NWRREQS and CONFIG_PL2303_NRDREQS
+#   The number of write/read requests that can be in flight
+# CONFIG_PL2303_VENDORID and CONFIG_PL2303_VENDORSTR
+#   The vendor ID code/string
+# CONFIG_PL2303_PRODUCTID and CONFIG_PL2303_PRODUCTSTR
+#   The product ID code/string
+# CONFIG_PL2303_RXBUFSIZE and CONFIG_PL2303_TXBUFSIZE
+#   Size of the serial receive/transmit buffers
+#
+CONFIG_PL2303=n
+CONFIG_PL2303_EPINTIN=1
+CONFIG_PL2303_EPBULKOUT=2
+CONFIG_PL2303_EPBULKIN=3
+CONFIG_PL2303_NWRREQS=4
+CONFIG_PL2303_NRDREQS=4
+CONFIG_PL2303_VENDORID=0x067b
+CONFIG_PL2303_PRODUCTID=0x2303
+CONFIG_PL2303_VENDORSTR="Nuttx"
+CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
+CONFIG_PL2303_RXBUFSIZE=512
+CONFIG_PL2303_TXBUFSIZE=512
+
+#
+# USB serial device class driver (Standard CDC ACM class)
+#
+# CONFIG_CDCACM
+#   Enable compilation of the USB serial driver
+# CONFIG_CDCACM_CONSOLE
+#   Configures the CDC/ACM serial port as the console device.
+# CONFIG_CDCACM_EP0MAXPACKET
+#   Endpoint 0 max packet size. Default 64
+# CONFIG_CDCACM_EPINTIN
+#   The logical 7-bit address of a hardware endpoint that supports
+#   interrupt IN operation.  Default 2.
+# CONFIG_CDCACM_EPINTIN_FSSIZE
+#   Max package size for the interrupt IN endpoint if full speed mode.
+#   Default 64.
+# CONFIG_CDCACM_EPINTIN_HSSIZE
+#   Max package size for the interrupt IN endpoint if high speed mode.
+#   Default 64
+# CONFIG_CDCACM_EPBULKOUT
+#   The logical 7-bit address of a hardware endpoint that supports
+#   bulk OUT operation.  Default 4.
+# CONFIG_CDCACM_EPBULKOUT_FSSIZE
+#   Max package size for the bulk OUT endpoint if full speed mode.
+#   Default 64.
+# CONFIG_CDCACM_EPBULKOUT_HSSIZE
+#   Max package size for the bulk OUT  endpoint if high speed mode.
+#   Default 512.
+# CONFIG_CDCACM_EPBULKIN
+#   The logical 7-bit address of a hardware endpoint that supports
+#   bulk IN operation.  Default 3.
+# CONFIG_CDCACM_EPBULKIN_FSSIZE
+#   Max package size for the bulk IN endpoint if full speed mode.
+#   Default 64.
+# CONFIG_CDCACM_EPBULKIN_HSSIZE
+#   Max package size for the bulk IN  endpoint if high speed mode.
+#   Default 512.
+# CONFIG_CDCACM_NWRREQS and CONFIG_CDCACM_NRDREQS
+#   The number of write/read requests that can be in flight.
+#   Default 256.
+# CONFIG_CDCACM_VENDORID and CONFIG_CDCACM_VENDORSTR
+#   The vendor ID code/string.  Default 0x0525 and "NuttX"
+#   0x0525 is the Netchip vendor and should not be used in any
+#   products.  This default VID was selected for compatibility with
+#   the Linux CDC ACM default VID.
+# CONFIG_CDCACM_PRODUCTID and CONFIG_CDCACM_PRODUCTSTR
+#   The product ID code/string. Default 0xa4a7 and "CDC/ACM Serial"
+#   0xa4a7 was selected for compatibility with the Linux CDC ACM
+#   default PID.
+# CONFIG_CDCACM_RXBUFSIZE and CONFIG_CDCACM_TXBUFSIZE
+#   Size of the serial receive/transmit buffers. Default 256.
+#
+CONFIG_CDCACM=y
+CONFIG_CDCACM_CONSOLE=n
+#CONFIG_CDCACM_EP0MAXPACKET
+CONFIG_CDCACM_EPINTIN=1
+#CONFIG_CDCACM_EPINTIN_FSSIZE
+#CONFIG_CDCACM_EPINTIN_HSSIZE
+CONFIG_CDCACM_EPBULKOUT=3
+#CONFIG_CDCACM_EPBULKOUT_FSSIZE
+#CONFIG_CDCACM_EPBULKOUT_HSSIZE
+CONFIG_CDCACM_EPBULKIN=2
+#CONFIG_CDCACM_EPBULKIN_FSSIZE
+#CONFIG_CDCACM_EPBULKIN_HSSIZE
+#CONFIG_CDCACM_NWRREQS
+#CONFIG_CDCACM_NRDREQS
+CONFIG_CDCACM_VENDORID=0x26AC
+CONFIG_CDCACM_VENDORSTR="3D Robotics"
+CONFIG_CDCACM_PRODUCTID=0x0010
+CONFIG_CDCACM_PRODUCTSTR="PX4 FMU v1.6"
+#CONFIG_CDCACM_RXBUFSIZE
+#CONFIG_CDCACM_TXBUFSIZE
+
+#
+# USB Storage Device Configuration
+#
+# CONFIG_USBMSC
+#   Enable compilation of the USB storage driver
+# CONFIG_USBMSC_EP0MAXPACKET
+#   Max packet size for endpoint 0
+# CONFIG_USBMSC_EPBULKOUT and CONFIG_USBMSC_EPBULKIN
+#   The logical 7-bit address of a hardware endpoints that support
+#   bulk OUT and IN operations
+# CONFIG_USBMSC_NWRREQS and CONFIG_USBMSC_NRDREQS
+#   The number of write/read requests that can be in flight
+# CONFIG_USBMSC_BULKINREQLEN and CONFIG_USBMSC_BULKOUTREQLEN
+#   The size of the buffer in each write/read request.  This
+#   value needs to be at least as large as the endpoint
+#   maxpacket and ideally as large as a block device sector.
+# CONFIG_USBMSC_VENDORID and CONFIG_USBMSC_VENDORSTR
+#   The vendor ID code/string
+# CONFIG_USBMSC_PRODUCTID and CONFIG_USBMSC_PRODUCTSTR
+#   The product ID code/string
+# CONFIG_USBMSC_REMOVABLE
+#   Select if the media is removable
+#
+CONFIG_USBMSC=n
+CONFIG_USBMSC_EP0MAXPACKET=64
+CONFIG_USBMSC_EPBULKOUT=2
+CONFIG_USBMSC_EPBULKIN=5
+CONFIG_USBMSC_NRDREQS=2
+CONFIG_USBMSC_NWRREQS=2
+CONFIG_USBMSC_BULKINREQLEN=256
+CONFIG_USBMSC_BULKOUTREQLEN=256
+CONFIG_USBMSC_VENDORID=0x584e
+CONFIG_USBMSC_VENDORSTR="NuttX"
+CONFIG_USBMSC_PRODUCTID=0x5342
+CONFIG_USBMSC_PRODUCTSTR="USBdev Storage"
+CONFIG_USBMSC_VERSIONNO=0x0399
+CONFIG_USBMSC_REMOVABLE=y
+
+
+#
+# Settings for apps/nshlib
+#
+# CONFIG_NSH_BUILTIN_APPS - Support external registered,
+#   "named" applications that can be executed from the NSH
+#   command line (see apps/README.txt for more information).
+# CONFIG_NSH_FILEIOSIZE - Size of a static I/O buffer
+# CONFIG_NSH_STRERROR - Use strerror(errno)
+# CONFIG_NSH_LINELEN - Maximum length of one command line
+# CONFIG_NSH_STACKSIZE - Stack size to use for new threads.
+# CONFIG_NSH_NESTDEPTH - Max number of nested if-then[-else]-fi
+# CONFIG_NSH_DISABLESCRIPT - Disable scripting support
+# CONFIG_NSH_DISABLEBG - Disable background commands
+# CONFIG_NSH_ROMFSETC - Use startup script in /etc
+# CONFIG_NSH_CONSOLE - Use serial console front end
+# CONFIG_NSH_TELNET - Use telnetd console front end
+# CONFIG_NSH_ARCHINIT - Platform provides architecture
+#   specific initialization (nsh_archinitialize()).
+#
+# If CONFIG_NSH_TELNET is selected:
+# CONFIG_NSH_IOBUFFER_SIZE -- Telnetd I/O buffer size
+# CONFIG_NSH_DHCPC - Obtain address using DHCP
+# CONFIG_NSH_IPADDR - Provides static IP address
+# CONFIG_NSH_DRIPADDR - Provides static router IP address
+# CONFIG_NSH_NETMASK - Provides static network mask
+# CONFIG_NSH_NOMAC - Use a bogus MAC address
+#
+# If CONFIG_NSH_ROMFSETC is selected:
+# CONFIG_NSH_ROMFSMOUNTPT - ROMFS mountpoint
+# CONFIG_NSH_INITSCRIPT - Relative path to init script
+# CONFIG_NSH_ROMFSDEVNO - ROMFS RAM device minor
+# CONFIG_NSH_ROMFSSECTSIZE - ROMF sector size
+# CONFIG_NSH_FATDEVNO - FAT FS RAM device minor
+# CONFIG_NSH_FATSECTSIZE - FAT FS sector size
+# CONFIG_NSH_FATNSECTORS - FAT FS number of sectors
+# CONFIG_NSH_FATMOUNTPT - FAT FS mountpoint
+#
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_STRERROR=y
+CONFIG_NSH_LINELEN=128
+CONFIG_NSH_NESTDEPTH=8
+CONFIG_NSH_DISABLESCRIPT=n
+CONFIG_NSH_DISABLEBG=n
+CONFIG_NSH_ROMFSETC=y
+CONFIG_NSH_ARCHROMFS=y
+CONFIG_NSH_CONSOLE=y
+CONFIG_NSH_USBCONSOLE=n
+CONFIG_NSH_USBCONDEV="/dev/ttyACM0"
+CONFIG_NSH_TELNET=n
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_IOBUFFER_SIZE=512
+CONFIG_NSH_DHCPC=n
+CONFIG_NSH_NOMAC=y
+CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2)
+CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1)
+CONFIG_NSH_NETMASK=(255<<24|255<<16|255<<8|0)
+CONFIG_NSH_ROMFSMOUNTPT="/etc"
+CONFIG_NSH_INITSCRIPT="init.d/rcS"
+CONFIG_NSH_ROMFSDEVNO=0
+CONFIG_NSH_ROMFSSECTSIZE=128 # Default 64, increased to allow for more than 64 folders on the sdcard
+CONFIG_NSH_FATDEVNO=1
+CONFIG_NSH_FATSECTSIZE=512
+CONFIG_NSH_FATNSECTORS=1024
+CONFIG_NSH_FATMOUNTPT=/tmp
+
+#
+# Architecture-specific NSH options
+#
+CONFIG_NSH_MMCSDSPIPORTNO=3
+CONFIG_NSH_MMCSDSLOTNO=0
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Settings for  mavlink
+#
+# CONFIG_MAVLINK - Enable MAVLINK app
+# CONFIG_NSH_BUILTIN_APPS - Build the ADC test as an NSH built-in function.
+#   Default: Built as a standalone problem
+CONFIG_MAVLINK=y
+
+#
+# Stack and heap information
+#
+# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP
+#   operation from FLASH but must copy initialized .data sections to RAM.
+#   (should also be =n for the STM3240G-EVAL which always runs from flash)
+# CONFIG_BOOT_COPYTORAM -  Some configurations boot in FLASH
+#   but copy themselves entirely into RAM for better performance.
+# CONFIG_CUSTOM_STACK - The up_ implementation will handle
+#   all stack operations outside of the nuttx model.
+# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only)
+# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack.
+#  This is the thread that (1) performs the inital boot of the system up
+#  to the point where user_start() is spawned, and (2) there after is the
+#  IDLE thread that executes only when there is no other thread ready to
+#  run.
+# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate
+#  for the main user thread that begins at the user_start() entry point.
+# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size
+# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size
+# CONFIG_HEAP_BASE - The beginning of the heap
+# CONFIG_HEAP_SIZE - The size of the heap
+#
+CONFIG_BOOT_RUNFROMFLASH=n
+CONFIG_BOOT_COPYTORAM=n
+CONFIG_CUSTOM_STACK=n
+CONFIG_STACK_POINTER=
+# Idle thread needs 4096 bytes
+# default 1 KB is not enough
+CONFIG_IDLETHREAD_STACKSIZE=4096
+CONFIG_USERMAIN_STACKSIZE=3072
+CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+CONFIG_HEAP_BASE=
+CONFIG_HEAP_SIZE=
diff --git a/nuttx/configs/px4fmu/nsh/setenv.sh b/nuttx/configs/px4fmu/nsh/setenv.sh
new file mode 100755
index 000000000..265520997
--- /dev/null
+++ b/nuttx/configs/px4fmu/nsh/setenv.sh
@@ -0,0 +1,67 @@
+#!/bin/bash
+# configs/stm3240g-eval/nsh/setenv.sh
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This the Cygwin path to the location where I installed the RIDE
+# toolchain under windows.  You will also have to edit this if you install
+# the RIDE toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin"
+
+# This the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# This the Cygwin path to the location where I build the buildroot
+# toolchain.
+#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/nuttx/configs/px4fmu/src/Makefile b/nuttx/configs/px4fmu/src/Makefile
new file mode 100644
index 000000000..2e3138aaa
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/Makefile
@@ -0,0 +1,102 @@
+############################################################################
+# configs/px4fmu/src/Makefile
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+CFLAGS		+= -I$(TOPDIR)/sched
+
+ASRCS		= 
+AOBJS		= $(ASRCS:.S=$(OBJEXT))
+
+CSRCS		= up_boot.c up_leds.c up_spi.c up_hrt.c \
+		  drv_gpio.c drv_bma180.c drv_l3gd20.c \
+		  drv_led.c drv_hmc5833l.c drv_ms5611.c drv_eeprom.c \
+		  drv_tone_alarm.c up_pwm_servo.c up_usbdev.c \
+		  up_cpuload.c drv_mpu6000.c
+
+ifeq ($(CONFIG_NSH_ARCHINIT),y)
+CSRCS		+= up_nsh.c
+endif
+
+ifeq ($(CONFIG_ADC),y)
+CSRCS		+= up_adc.c
+endif
+
+ifeq ($(CONFIG_CAN),y)
+CSRCS		+= up_can.c
+endif
+
+COBJS		= $(CSRCS:.c=$(OBJEXT))
+
+SRCS		= $(ASRCS) $(CSRCS)
+OBJS		= $(AOBJS) $(COBJS)
+
+ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  CFLAGS	+= -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
+  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
+  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
+else
+  CFLAGS	+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
+endif
+
+all: libboard$(LIBEXT)
+
+$(AOBJS): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+libboard$(LIBEXT): $(OBJS)
+	@( for obj in $(OBJS) ; do \
+		$(call ARCHIVE, $@, $${obj}); \
+	done ; )
+
+.depend: Makefile $(SRCS)
+	@$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	@touch $@
+
+depend: .depend
+
+clean:
+	@rm -f libboard$(LIBEXT) *~ .*.swp
+	$(call CLEAN)
+
+distclean: clean
+	@rm -f Make.dep .depend
+
+-include Make.dep
+
diff --git a/nuttx/configs/px4fmu/src/drv_bma180.c b/nuttx/configs/px4fmu/src/drv_bma180.c
new file mode 100644
index 000000000..da80cc2e2
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_bma180.c
@@ -0,0 +1,341 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the Bosch BMA 180 MEMS accelerometer
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include <stdio.h>
+
+#include "chip.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/drv_bma180.h>
+
+/*
+ * BMA180 registers
+ */
+
+/* Important Notes:
+ *
+ *   - MAX SPI clock: 25 MHz
+ *   - Readout time: 0.417 ms in high accuracy mode
+ *   - Boot / ready time: 1.27 ms
+ *
+ */
+
+#define DIR_READ				(1<<7)
+#define DIR_WRITE				(0<<7)
+#define ADDR_INCREMENT			(1<<6)
+
+#define ADDR_CHIP_ID			0x00
+#define CHIP_ID					0x03
+#define ADDR_VERSION			0x01
+
+#define ADDR_CTRL_REG0			0x0D
+#define ADDR_CTRL_REG1			0x0E
+#define ADDR_CTRL_REG2			0x0F
+#define ADDR_BWTCS				0x20
+#define ADDR_CTRL_REG3			0x21
+#define ADDR_CTRL_REG4			0x22
+#define ADDR_OLSB1				0x35
+
+#define ADDR_ACC_X_LSB			0x02
+#define ADDR_ACC_Z_MSB			0x07
+#define ADDR_TEMPERATURE		0x08
+
+#define ADDR_STATUS_REG1		0x09
+#define ADDR_STATUS_REG2		0x0A
+#define ADDR_STATUS_REG3		0x0B
+#define ADDR_STATUS_REG4		0x0C
+
+#define ADDR_RESET				0x10
+#define SOFT_RESET				0xB6
+
+#define ADDR_DIS_I2C         	0x27
+
+#define REG0_WRITE_ENABLE		0x10
+
+#define RANGEMASK 0x0E
+#define BWMASK 0xF0
+
+
+static ssize_t	bma180_read(struct file *filp, FAR char *buffer, size_t buflen);
+static int	bma180_ioctl(struct file *filp, int cmd, unsigned long arg);
+
+static const struct file_operations bma180_fops = {
+	.read  = bma180_read,
+	.ioctl = bma180_ioctl,
+};
+
+struct bma180_dev_s
+{
+	struct spi_dev_s		*spi;
+	int						spi_id;
+	uint8_t					rate;
+	struct bma180_buffer	*buffer;
+};
+
+static struct bma180_dev_s	bma180_dev;
+
+static void	bma180_write_reg(uint8_t address, uint8_t data);
+static uint8_t	bma180_read_reg(uint8_t address);
+static bool	read_fifo(uint16_t *data);
+static int	bma180_set_range(uint8_t range);
+static int	bma180_set_rate(uint8_t rate);
+
+static void
+bma180_write_reg(uint8_t address, uint8_t data)
+{
+	uint8_t cmd[2] = { address | DIR_WRITE, data };
+    
+	SPI_SELECT(bma180_dev.spi, bma180_dev.spi_id, true);
+    SPI_SNDBLOCK(bma180_dev.spi, &cmd, sizeof(cmd));
+	SPI_SELECT(bma180_dev.spi, bma180_dev.spi_id, false);
+}
+
+static uint8_t
+bma180_read_reg(uint8_t address)
+{
+	uint8_t	cmd[2] = {address | DIR_READ, 0};
+	uint8_t data[2];
+    
+	SPI_SELECT(bma180_dev.spi, bma180_dev.spi_id, true);
+	SPI_EXCHANGE(bma180_dev.spi, cmd, data, sizeof(cmd));
+	SPI_SELECT(bma180_dev.spi, bma180_dev.spi_id, false);
+    
+	return data[1];	
+}
+
+static bool
+read_fifo(uint16_t *data)
+{
+	struct {		/* status register and data as read back from the device */
+		uint8_t		cmd;
+		int16_t		x;
+		int16_t		y;
+		int16_t		z;
+		uint8_t		temp;
+	} __attribute__((packed))	report;
+
+	report.cmd = ADDR_ACC_X_LSB | DIR_READ | ADDR_INCREMENT;
+
+	SPI_LOCK(bma180_dev.spi, true);
+	report.x = bma180_read_reg(ADDR_ACC_X_LSB);
+	report.x |= (bma180_read_reg(ADDR_ACC_X_LSB+1) << 8);
+	report.y = bma180_read_reg(ADDR_ACC_X_LSB+2);
+	report.y |= (bma180_read_reg(ADDR_ACC_X_LSB+3) << 8);
+	report.z = bma180_read_reg(ADDR_ACC_X_LSB+4);
+	report.z |= (bma180_read_reg(ADDR_ACC_X_LSB+5) << 8);
+	report.temp = bma180_read_reg(ADDR_ACC_X_LSB+6);
+	SPI_LOCK(bma180_dev.spi, false);
+
+	/* Collect status and remove two top bits */
+
+	uint8_t new_data = (report.x & 0x01) + (report.x & 0x01) + (report.x & 0x01);
+	report.x = (report.x >> 2);
+	report.y = (report.y >> 2);
+	report.z = (report.z >> 2);
+
+	data[0] = report.x;
+	data[1] = report.y;
+	data[2] = report.z;
+    
+	/* return 1 for all three axes new */
+	return (new_data > 0); // bit funky, depends on timing
+}
+
+static int
+bma180_set_range(uint8_t range)
+{
+	/* enable writing to chip config */
+	uint8_t ctrl0 = bma180_read_reg(ADDR_CTRL_REG0);
+	ctrl0 |= REG0_WRITE_ENABLE;
+	bma180_write_reg(ADDR_CTRL_REG0, ctrl0);
+
+	/* set range */
+	uint8_t olsb1 = bma180_read_reg(ADDR_OLSB1);
+	olsb1 &= (~RANGEMASK);
+	olsb1 |= (range);// & RANGEMASK);
+	bma180_write_reg(ADDR_OLSB1, olsb1);
+
+	// up_udelay(500);
+
+	/* block writing to chip config */
+	ctrl0 = bma180_read_reg(ADDR_CTRL_REG0);
+	ctrl0 &= (~REG0_WRITE_ENABLE);
+	bma180_write_reg(ADDR_CTRL_REG0, ctrl0);
+
+	uint8_t new_olsb1 = bma180_read_reg(ADDR_OLSB1);
+
+	/* return 0 on success, 1 on failure */
+	return !(olsb1 == new_olsb1);
+}
+
+static int
+bma180_set_rate(uint8_t rate)
+{
+	/* enable writing to chip config */
+	uint8_t ctrl0 = bma180_read_reg(ADDR_CTRL_REG0);
+	ctrl0 |= REG0_WRITE_ENABLE;
+	bma180_write_reg(ADDR_CTRL_REG0, ctrl0);
+
+	/* set rate / bandwidth */
+	uint8_t bwtcs = bma180_read_reg(ADDR_BWTCS);
+	bwtcs &= (~BWMASK);
+	bwtcs |= (rate);// & BWMASK);
+	bma180_write_reg(ADDR_BWTCS, bwtcs);
+
+	// up_udelay(500);
+
+	/* block writing to chip config */
+	ctrl0 = bma180_read_reg(ADDR_CTRL_REG0);
+	ctrl0 &= (~REG0_WRITE_ENABLE);
+	bma180_write_reg(ADDR_CTRL_REG0, ctrl0);
+
+	uint8_t new_bwtcs = bma180_read_reg(ADDR_BWTCS);
+
+	/* return 0 on success, 1 on failure */
+	return !(bwtcs == new_bwtcs);
+}
+
+static ssize_t
+bma180_read(struct file *filp, char *buffer, size_t buflen)
+{
+	/* if the buffer is large enough, and data are available, return success */
+	if (buflen >= 6) {
+		if (read_fifo((uint16_t *)buffer))
+			return 6;
+
+		/* no data */
+		return 0;
+	}
+    
+	/* buffer too small */
+	errno = ENOSPC;
+	return ERROR;
+}
+
+static int
+bma180_ioctl(struct file *filp, int cmd, unsigned long arg)
+{
+	int	result = ERROR;
+    
+	switch (cmd) {
+        case BMA180_SETRATE:
+            result = bma180_set_rate(arg);
+            break;
+
+        case BMA180_SETRANGE:
+            result = bma180_set_range(arg);
+            break;
+
+        case BMA180_SETBUFFER:
+            bma180_dev.buffer = (struct bma180_buffer *)arg;
+            result = 0;
+            break;
+	}
+    
+	if (result)
+		errno = EINVAL;
+	return result;
+}
+
+int
+bma180_attach(struct spi_dev_s *spi, int spi_id)
+{
+	int	result = ERROR;
+	
+	bma180_dev.spi = spi;
+	bma180_dev.spi_id = spi_id;
+    
+	SPI_LOCK(bma180_dev.spi, true);
+
+	/* verify that the device is attached and functioning */
+	if (bma180_read_reg(ADDR_CHIP_ID) == CHIP_ID) {
+        
+		bma180_write_reg(ADDR_RESET, SOFT_RESET);       // page 48
+
+		up_udelay(13000);                               // wait 12 ms, see page 49
+
+		/* Configuring the BMA180 */
+
+		/* enable writing to chip config */
+		uint8_t ctrl0 = bma180_read_reg(ADDR_CTRL_REG0);
+		ctrl0 |= REG0_WRITE_ENABLE;
+		bma180_write_reg(ADDR_CTRL_REG0, ctrl0);
+
+		/* disable I2C interface, datasheet page 31 */
+		uint8_t disi2c = bma180_read_reg(ADDR_DIS_I2C);
+		disi2c |= 0x01;
+		bma180_write_reg(ADDR_DIS_I2C, disi2c);
+
+		/* block writing to chip config */
+		ctrl0 = bma180_read_reg(ADDR_CTRL_REG0);
+		ctrl0 &= (~REG0_WRITE_ENABLE);
+		bma180_write_reg(ADDR_CTRL_REG0, ctrl0);
+
+		// up_udelay(500);
+
+		/* set rate */
+		result = bma180_set_rate(BMA180_RATE_LP_600HZ);
+
+		// up_udelay(500);
+
+		/* set range */
+		result += bma180_set_range(BMA180_RANGE_4G);
+
+		// up_udelay(500);
+
+		if (result == 0) {
+			/* make ourselves available */
+			register_driver("/dev/bma180", &bma180_fops, 0666, NULL);
+		}
+	} else {
+		errno = EIO;
+	}
+
+	SPI_LOCK(bma180_dev.spi, false);
+    
+	return result;
+}
+
diff --git a/nuttx/configs/px4fmu/src/drv_eeprom.c b/nuttx/configs/px4fmu/src/drv_eeprom.c
new file mode 100644
index 000000000..c22062ec5
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_eeprom.c
@@ -0,0 +1,522 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Generic driver for I2C EEPROMs with 8 bit or 16 bit addressing
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include <nuttx/i2c.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/drv_eeprom.h>
+
+/* Split I2C transfers into smaller chunks to make sure to stay within tight timeout limits */
+
+/* check defines */
+#ifndef MAX_EEPROMS
+  #error MAX_EEPROMS number must be defined (1-3)
+#endif
+
+#if (MAX_EEPROMS > 3)
+  #error Currently only a maximum of three EEPROMS is supported, add missing code around here: __FILE__:__LINE__
+#endif
+static int eeprom_open0(FAR struct file *filp);
+static int eeprom_close0(FAR struct file *filp);
+static ssize_t eeprom_read0(struct file *filp, FAR char *buffer, size_t buflen);
+static ssize_t eeprom_write0(struct file *filp, FAR const char *buffer, size_t buflen);
+static off_t eeprom_seek0(FAR struct file *filp, off_t offset, int whence);
+#if (MAX_EEPROMS > 1)
+static int eeprom_open1(FAR struct file *filp);
+static int eeprom_close1(FAR struct file *filp);
+static ssize_t eeprom_read1(struct file *filp, FAR char *buffer, size_t buflen);
+static ssize_t eeprom_write1(struct file *filp, FAR const char *buffer, size_t buflen);
+static off_t eeprom_seek1(FAR struct file *filp, off_t offset, int whence);
+#endif
+#if (MAX_EEPROMS > 2)
+static int eeprom_open2(FAR struct file *filp);
+static int eeprom_close2(FAR struct file *filp);
+static ssize_t eeprom_read2(struct file *filp, FAR char *buffer, size_t buflen);
+static ssize_t eeprom_write2(struct file *filp, FAR const char *buffer, size_t buflen);
+static off_t eeprom_seek2(FAR struct file *filp, off_t offset, int whence);
+#endif
+
+static const struct file_operations eeprom_fops[MAX_EEPROMS] = {{
+	.open  = eeprom_open0,
+	.close = eeprom_close0,
+	.read  = eeprom_read0,
+	.write = eeprom_write0,
+	.seek  = eeprom_seek0,
+	.ioctl = 0,
+#ifndef CONFIG_DISABLE_POLL
+	.poll  = 0
+#endif
+}
+#if (MAX_EEPROMS > 1)
+,{
+	.open  = eeprom_open1,
+	.close = eeprom_close1,
+	.read  = eeprom_read1,
+	.write = eeprom_write1,
+	.seek  = eeprom_seek1,
+}
+#endif
+#if (MAX_EEPROMS > 2)
+,{
+	.open  = eeprom_open2,
+	.close = eeprom_close2,
+	.read  = eeprom_read2,
+	.write = eeprom_write2,
+	.seek  = eeprom_seek2,
+}
+#endif
+};
+
+static FAR struct eeprom_dev_s
+{
+	struct i2c_dev_s	*i2c;
+	uint8_t eeprom_address;
+	uint16_t eeprom_size_bytes;
+	uint16_t eeprom_page_size_bytes;
+	uint16_t eeprom_page_write_time;
+	off_t offset;
+	bool is_open;
+} eeprom_dev[MAX_EEPROMS];
+
+static int
+eeprom_open0(FAR struct file *filp)
+{
+	/* only allow one open at a time */
+	if (eeprom_dev[0].is_open) {
+		errno = EBUSY;
+		return -EBUSY;
+	}
+	/* reset pointer */
+	//eeprom_dev[0].is_open = true;
+	eeprom_dev[0].offset = 0;
+	return OK;
+}
+#if (MAX_EEPROMS > 1)
+static int
+eeprom_open1(FAR struct file *filp)
+{
+	/* only allow one open at a time */
+	if (eeprom_dev[1].is_open) {
+		errno = EBUSY;
+		return -EBUSY;
+	}
+	/* reset pointer */
+	//eeprom_dev[1].is_open = true;
+	eeprom_dev[1].offset = 0;
+	return OK;
+}
+#endif
+#if (MAX_EEPROMS > 2)
+static int
+eeprom_open2(FAR struct file *filp)
+{
+	/* only allow one open at a time */
+	if (eeprom_dev[2].is_open) {
+		errno = EBUSY;
+		return -EBUSY;
+	}
+	/* reset pointer */
+	//eeprom_dev[2].is_open = true;
+	eeprom_dev[2].offset = 0;
+	return OK;
+}
+#endif
+
+static int
+eeprom_close0(FAR struct file *filp)
+{
+	eeprom_dev[0].is_open = false;
+	return OK;
+}
+#if (MAX_EEPROMS > 1)
+static int
+eeprom_close1(FAR struct file *filp)
+{
+	eeprom_dev[1].is_open = false;
+	return OK;
+}
+#endif
+#if (MAX_EEPROMS > 2)
+static int
+eeprom_close2(FAR struct file *filp)
+{
+	eeprom_dev[2].is_open = false;
+	return OK;
+}
+#endif
+
+static int
+eeprom_read_internal(int dev, uint16_t len, uint8_t *data)
+{
+	/* abort if the number of requested bytes exceeds the EEPROM size */
+	if (eeprom_dev[dev].offset + len > eeprom_dev[dev].eeprom_size_bytes)
+	{
+		errno = ENOSPC;
+		return -ENOSPC;
+	}
+
+	/* set device address */
+	I2C_SETADDRESS(eeprom_dev[dev].i2c, eeprom_dev[dev].eeprom_address, 7);
+
+	uint8_t cmd[2] = {0, 0}; /* first (or only) part of address */
+	/* second part of address, omitted if eeprom has 256 bytes or less */
+	int ret = 0;
+	int remaining = len;
+	int readcounts = 0;
+
+	while (remaining > 0)
+	{
+		/* read all requested bytes over potentially multiple pages */
+		//int readlen = (remaining < eeprom_dev[dev].eeprom_page_size_bytes) ? remaining : eeprom_dev[dev].eeprom_page_size_bytes;
+		int read_offset = eeprom_dev[dev].offset + len - remaining;//+ write_counts*eeprom_dev[dev].eeprom_page_size_bytes;
+		/* set read length to page border */
+		int readlen = eeprom_dev[dev].eeprom_page_size_bytes - (read_offset % eeprom_dev[dev].eeprom_page_size_bytes);//(remaining < eeprom_dev[dev].eeprom_page_size_bytes) ? remaining : eeprom_dev[dev].eeprom_page_size_bytes;
+		/* cap read length if not a full page read is needed */
+		if (readlen > remaining) readlen = remaining;
+
+		if (eeprom_dev[dev].eeprom_size_bytes <= 256)
+		{
+			cmd[0] = (read_offset); /* set at first byte */
+			/* 8 bit addresses */
+			ret = I2C_WRITEREAD(eeprom_dev[dev].i2c, cmd, 1, (data+(readcounts*eeprom_dev[dev].eeprom_page_size_bytes)), readlen);
+		}
+		else
+		{
+			/* 16 bit addresses */
+			/* EEPROM: first address high, then address low */
+			cmd[0] = (((uint16_t)read_offset) >> 8);
+			cmd[1] = (((uint8_t)read_offset));
+			ret = I2C_WRITEREAD(eeprom_dev[dev].i2c, cmd, 2, (data+(readcounts*eeprom_dev[dev].eeprom_page_size_bytes)), readlen);
+		}
+
+		/* abort on error */
+		if (ret < 0) break;
+
+		/* handled another chunk */
+		remaining -= readlen;
+		readcounts++;
+	}
+
+	/* use the negated value from I2C_TRANSFER to fill errno */
+	errno = -ret;
+
+	/* return len if data was read, < 0 else */
+	if (ret == OK)
+		eeprom_dev[dev].offset += len;
+		return len;
+
+	/* no data, return negated value from I2C_TRANSFER */
+	return ret;
+}
+
+static int
+eeprom_write_internal(int dev, uint16_t len, const uint8_t *data)
+{
+	/* abort if the number of requested bytes exceeds the EEPROM size */
+	if (eeprom_dev[dev].offset + len > eeprom_dev[dev].eeprom_size_bytes)
+	{
+		errno = ENOSPC;
+		return -ENOSPC;
+	}
+
+	int ret = 0;
+	int remaining = len;
+	int write_counts = 0;
+
+	uint8_t write_buf[2];
+
+	while (remaining > 0)
+	{
+		/* write all requested bytes over potentially multiple pages */
+		int write_offset = eeprom_dev[dev].offset + len - remaining;//+ write_counts*eeprom_dev[dev].eeprom_page_size_bytes;
+		/* set write length to page border */
+		int writelen = eeprom_dev[dev].eeprom_page_size_bytes - (write_offset % eeprom_dev[dev].eeprom_page_size_bytes);//(remaining < eeprom_dev[dev].eeprom_page_size_bytes) ? remaining : eeprom_dev[dev].eeprom_page_size_bytes;
+		/* cap write length if not a full page write is requested */
+		if (writelen > remaining) writelen = remaining;
+
+		if (eeprom_dev[dev].eeprom_size_bytes <= 256)
+		{
+			write_buf[0] = (write_offset); /* set at first byte */
+			/* 8 bit addresses */
+
+			const uint8_t* data_ptr = (data+(write_offset));
+
+			struct i2c_msg_s msgv_eeprom_write[2] = {
+					{
+							.addr   = eeprom_dev[dev].eeprom_address,
+							.flags  = I2C_M_NORESTART,
+							.buffer = write_buf,
+							.length = 1
+					},
+					{
+							.addr   = eeprom_dev[dev].eeprom_address,
+							.flags  = I2C_M_NORESTART,
+							.buffer = (uint8_t*)data_ptr,
+							.length = writelen
+					}
+			};
+
+
+			if ( (ret = I2C_TRANSFER(eeprom_dev[dev].i2c, msgv_eeprom_write, 2)) == OK )
+			{
+				//printf("SUCCESS WRITING EEPROM 8BIT ADDR: %d, bytes: %d\n", ret, writelen);
+			}
+		}
+		else
+		{
+			/* 16 bit addresses */
+			/* EEPROM: first address high, then address low */
+			write_buf[0] = (((uint16_t)write_offset) >> 8);
+			write_buf[1] = (((uint8_t)write_offset));
+
+			const uint8_t* data_ptr = data+(write_counts*eeprom_dev[dev].eeprom_page_size_bytes);
+
+			struct i2c_msg_s msgv_eeprom_write[2] = {
+					{
+							.addr   = eeprom_dev[dev].eeprom_address,
+							.flags  = I2C_M_NORESTART,
+							.buffer = write_buf,
+							.length = 2
+					},
+					{
+							.addr   = eeprom_dev[dev].eeprom_address,
+							.flags  = I2C_M_NORESTART,
+							.buffer = (uint8_t*)data_ptr,
+							.length = writelen
+					}
+			};
+
+
+			if ( (ret = I2C_TRANSFER(eeprom_dev[dev].i2c, msgv_eeprom_write, 2)) == OK )
+			{
+				//printf("SUCCESS WRITING EEPROM 16BIT ADDR: %d, bytes: %d\n", ret, writelen);
+			}
+		}
+
+		/* abort on error */
+		if (ret < 0) break;
+
+		/* handled another chunk */
+		remaining -= writelen;
+		write_counts++;
+		/* wait for the device to write the page */
+		usleep(eeprom_dev[dev].eeprom_page_write_time);
+	}
+
+	/* use the negated value from I2C_TRANSFER to fill errno */
+	errno = -ret;
+
+	/* return length if data was written, < 0 else */
+	if (ret == OK)
+		eeprom_dev[dev].offset += len;
+		return len;
+
+	/* no data, return negated value from I2C_TRANSFER */
+	return ret;
+}
+
+static ssize_t
+eeprom_read0(struct file *filp, char *buffer, size_t buflen)
+{
+	return eeprom_read_internal(0, buflen, (uint8_t *)buffer);
+}
+#if (MAX_EEPROMS > 1)
+static ssize_t
+eeprom_read1(struct file *filp, char *buffer, size_t buflen)
+{
+	return eeprom_read_internal(1, buflen, (uint8_t *)buffer);
+}
+#endif
+#if (MAX_EEPROMS > 2)
+static ssize_t
+eeprom_read2(struct file *filp, char *buffer, size_t buflen)
+{
+	return eeprom_read_internal(2, buflen, (uint8_t *)buffer);
+}
+#endif
+
+static ssize_t
+eeprom_write0(struct file *filp, const char *buffer, size_t buflen)
+{
+	return eeprom_write_internal(0, buflen, (const uint8_t *)buffer);
+}
+#if (MAX_EEPROMS > 1)
+static ssize_t
+eeprom_write1(struct file *filp, const char *buffer, size_t buflen)
+{
+	return eeprom_write_internal(1, buflen, (const uint8_t *)buffer);
+}
+#endif
+#if (MAX_EEPROMS > 2)
+static ssize_t
+eeprom_write2(struct file *filp, const char *buffer, size_t buflen)
+{
+	return eeprom_write_internal(2, buflen, (const uint8_t *)buffer);
+}
+#endif
+
+static off_t eeprom_seek0(FAR struct file *filp, off_t offset, int whence)
+{
+	switch (whence)
+	{
+	case SEEK_SET:
+		if (offset < eeprom_dev[0].eeprom_size_bytes - 1) {
+			eeprom_dev[0].offset = offset;
+		} else {
+			errno = ESPIPE;
+			return -ESPIPE;
+		}
+		break;
+	case SEEK_CUR:
+		if (eeprom_dev[0].offset + offset < eeprom_dev[0].eeprom_size_bytes - 1) {
+			eeprom_dev[0].offset = eeprom_dev[0].offset + offset;
+		} else {
+			errno = ESPIPE;
+			return -ESPIPE;
+		}
+		break;
+	case SEEK_END:
+		errno = ESPIPE;
+		return -ESPIPE;
+		break;
+	}
+	return eeprom_dev[0].offset;
+}
+#if (MAX_EEPROMS > 1)
+static off_t eeprom_seek1(FAR struct file *filp, off_t offset, int whence)
+{
+	switch (whence)
+	{
+	case SEEK_SET:
+		if (offset < eeprom_dev[1].eeprom_size_bytes - 1) {
+			eeprom_dev[1].offset = offset;
+		} else {
+			errno = ESPIPE;
+			return -ESPIPE;
+		}
+		break;
+	case SEEK_CUR:
+		if (eeprom_dev[1].offset + offset < eeprom_dev[1].eeprom_size_bytes - 1) {
+			eeprom_dev[1].offset = eeprom_dev[1].offset + offset;
+		} else {
+			errno = ESPIPE;
+			return -ESPIPE;
+		}
+		break;
+	case SEEK_END:
+		errno = ESPIPE;
+		return -ESPIPE;
+		break;
+	}
+	return eeprom_dev[1].offset;
+}
+#endif
+#if (MAX_EEPROMS > 2)
+static off_t eeprom_seek2(FAR struct file *filp, off_t offset, int whence)
+{
+	switch (whence)
+	{
+	case SEEK_SET:
+		if (offset < eeprom_dev[2].eeprom_size_bytes - 1) {
+			eeprom_dev[2].offset = offset;
+		} else {
+			errno = ESPIPE;
+			return -ESPIPE;
+		}
+		break;
+	case SEEK_CUR:
+		if (eeprom_dev[2].offset + offset < eeprom_dev[2].eeprom_size_bytes - 1) {
+			eeprom_dev[2].offset = eeprom_dev[2].offset + offset;
+		} else {
+			errno = ESPIPE;
+			return -ESPIPE;
+		}
+		break;
+	case SEEK_END:
+		errno = ESPIPE;
+		return -ESPIPE;
+		break;
+	}
+	return eeprom_dev[2].offset;
+}
+#endif
+
+int
+eeprom_attach(struct i2c_dev_s *i2c, uint8_t device_address, uint16_t total_size_bytes, uint16_t page_size_bytes, uint16_t page_write_time_us, const char* device_name, uint8_t fail_if_missing)
+{
+	static int eeprom_dev_counter = 0;
+	eeprom_dev[eeprom_dev_counter].i2c = i2c;
+	eeprom_dev[eeprom_dev_counter].eeprom_address = device_address;
+	eeprom_dev[eeprom_dev_counter].eeprom_size_bytes = total_size_bytes;
+	eeprom_dev[eeprom_dev_counter].eeprom_page_size_bytes = page_size_bytes;
+	eeprom_dev[eeprom_dev_counter].eeprom_page_write_time = page_write_time_us;
+	eeprom_dev[eeprom_dev_counter].offset = 0;
+	eeprom_dev[eeprom_dev_counter].is_open = false;
+
+	int ret;
+
+	if (fail_if_missing) {
+		/* read first value */
+		uint8_t read_test;
+		ret = (eeprom_read_internal(eeprom_dev_counter, 1, &read_test) == 1) ? OK : ERROR;
+	} else {
+		ret = OK;
+	}
+
+	/* make ourselves available */
+	if (ret == OK)
+	{
+		register_driver(device_name, &(eeprom_fops[eeprom_dev_counter]), 0666, NULL);
+		eeprom_dev_counter++;
+	}
+
+	/* Return 0 for device found, error number else */
+	return ret;
+}
diff --git a/nuttx/configs/px4fmu/src/drv_gpio.c b/nuttx/configs/px4fmu/src/drv_gpio.c
new file mode 100644
index 000000000..be95420dd
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_gpio.c
@@ -0,0 +1,195 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * GPIO driver for PX4FMU.
+ *
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/drv_gpio.h>
+
+static int	px4fmu_gpio_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+static const struct file_operations px4fmu_gpio_fops = {
+	.ioctl = px4fmu_gpio_ioctl,
+};
+
+static struct {
+	uint32_t	input;
+	uint32_t	output;
+	uint32_t	alt;
+} gpio_tab[] = {
+	{GPIO_GPIO0_INPUT, GPIO_GPIO0_OUTPUT, 0},
+	{GPIO_GPIO1_INPUT, GPIO_GPIO1_OUTPUT, 0},
+	{GPIO_GPIO2_INPUT, GPIO_GPIO2_OUTPUT, GPIO_USART2_CTS_1},
+	{GPIO_GPIO3_INPUT, GPIO_GPIO3_OUTPUT, GPIO_USART2_RTS_1},
+	{GPIO_GPIO4_INPUT, GPIO_GPIO4_OUTPUT, GPIO_USART2_TX_1},
+	{GPIO_GPIO5_INPUT, GPIO_GPIO5_OUTPUT, GPIO_USART2_RX_1},
+	{GPIO_GPIO6_INPUT, GPIO_GPIO6_OUTPUT, GPIO_CAN2_TX_2},
+	{GPIO_GPIO7_INPUT, GPIO_GPIO7_OUTPUT, GPIO_CAN2_RX_2},
+};
+
+#define NGPIO	(sizeof(gpio_tab) / sizeof(gpio_tab[0]))
+
+
+static void
+px4fmu_gpio_reset(void)
+{
+	/*
+	 * Setup default GPIO config - all pins as GPIOs, GPIO driver chip 
+	 * to input mode.
+	 */
+	for (unsigned i = 0; i < NGPIO; i++)
+		stm32_configgpio(gpio_tab[i].input);
+
+	stm32_gpiowrite(GPIO_GPIO_DIR, 0);
+	stm32_configgpio(GPIO_GPIO_DIR);
+}
+
+static void
+px4fmu_gpio_set_function(uint32_t gpios, int function)
+{
+	/*
+	 * GPIOs 0 and 1 must have the same direction as they are buffered
+	 * by a shared 2-port driver.  Any attempt to set either sets both.
+	 */
+	if (gpios & 3) {
+		gpios |= 3;
+
+		/* flip the buffer to output mode if required */
+		if (GPIO_SET_OUTPUT == function)
+			stm32_gpiowrite(GPIO_GPIO_DIR, 1);
+	}
+
+	/* configure selected GPIOs as required */
+	for (unsigned i = 0; i < NGPIO; i++) {
+		if (gpios & (1<<i)) {
+			switch (function) {
+			case GPIO_SET_INPUT:
+				stm32_configgpio(gpio_tab[i].input);
+				break;
+			case GPIO_SET_OUTPUT:
+				stm32_configgpio(gpio_tab[i].output);
+				break;
+			case GPIO_SET_ALT_1:
+				if (gpio_tab[i].alt != 0)
+					stm32_configgpio(gpio_tab[i].alt);
+				break;
+			}
+		}
+	}
+
+	/* flip buffer to input mode if required */
+	if ((GPIO_SET_INPUT == function) && (gpios & 3))
+		stm32_gpiowrite(GPIO_GPIO_DIR, 0);
+}
+
+static void
+px4fmu_gpio_write(uint32_t gpios, int function)
+{
+	int value = (function == GPIO_SET) ? 1 : 0;
+
+	for (unsigned i = 0; i < NGPIO; i++)
+		if (gpios & (1<<i))
+			stm32_gpiowrite(gpio_tab[i].output, value);
+}
+
+static uint32_t
+px4fmu_gpio_read(void)
+{
+	uint32_t bits = 0;
+
+	for (unsigned i = 0; i < NGPIO; i++)
+		if (stm32_gpioread(gpio_tab[i].input))
+			bits |= (1 << i);
+
+	return bits;
+}
+
+void
+px4fmu_gpio_init(void)
+{
+	/* reset all GPIOs to default state */
+	px4fmu_gpio_reset();
+
+	/* register the driver */
+	register_driver(GPIO_DEVICE_PATH, &px4fmu_gpio_fops, 0666, NULL);
+}
+
+static int
+px4fmu_gpio_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+	int	result = OK;
+
+	switch (cmd) {
+		
+	case GPIO_RESET:
+		px4fmu_gpio_reset();
+		break;
+
+	case GPIO_SET_OUTPUT:
+	case GPIO_SET_INPUT:
+	case GPIO_SET_ALT_1:
+		px4fmu_gpio_set_function(arg, cmd);
+		break;
+
+	case GPIO_SET:
+	case GPIO_CLEAR:
+		px4fmu_gpio_write(arg, cmd);
+		break;
+
+	case GPIO_GET:
+		*(uint32_t *)arg = px4fmu_gpio_read();
+		break;
+
+	default:
+		result = -ENOTTY;
+	}
+	return result;
+}
+
diff --git a/nuttx/configs/px4fmu/src/drv_hmc5833l.c b/nuttx/configs/px4fmu/src/drv_hmc5833l.c
new file mode 100644
index 000000000..0e6dbe2ac
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_hmc5833l.c
@@ -0,0 +1,352 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the Honeywell/ST HMC5883L MEMS magnetometer
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/i2c.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/drv_hmc5883l.h>
+
+#define ADDR_CONF_A				0x00
+#define ADDR_CONF_B				0x01
+#define ADDR_MODE				0x02
+#define ADDR_DATA_OUT_X_MSB		0x03
+#define ADDR_DATA_OUT_X_LSB		0x04
+#define ADDR_DATA_OUT_Z_MSB		0x05
+#define ADDR_DATA_OUT_Z_LSB		0x06
+#define ADDR_DATA_OUT_Y_MSB		0x07
+#define ADDR_DATA_OUT_Y_LSB		0x08
+#define ADDR_STATUS				0x09
+#define ADDR_ID_A				0x10
+#define ADDR_ID_B				0x11
+#define ADDR_ID_C				0x12
+
+#define HMC5883L_ADDRESS		0x1E
+
+/* modes not changeable outside of driver */
+#define HMC5883L_MODE_NORMAL			(0 << 0)  /* default */
+#define HMC5883L_MODE_POSITIVE_BIAS		(1 << 0)  /* positive bias */
+#define HMC5883L_MODE_NEGATIVE_BIAS		(1 << 1)  /* negative bias */
+
+#define HMC5883L_AVERAGING_1		(0 << 5) /* conf a register */
+#define HMC5883L_AVERAGING_2		(1 << 5)
+#define HMC5883L_AVERAGING_4		(2 << 5)
+#define HMC5883L_AVERAGING_8		(3 << 5)
+
+#define MODE_REG_CONTINOUS_MODE		(0 << 0)
+#define MODE_REG_SINGLE_MODE		(1 << 0) /* default */
+
+#define STATUS_REG_DATA_OUT_LOCK	(1 << 1) /* page 16: set if data is only partially read, read device to reset */
+#define STATUS_REG_DATA_READY		(1 << 0) /* page 16: set if all axes have valid measurements */
+
+#define ID_A_WHO_AM_I			'H'
+#define ID_B_WHO_AM_I			'4'
+#define ID_C_WHO_AM_I			'3'
+
+static FAR struct hmc5883l_dev_s	hmc5883l_dev;
+
+static ssize_t hmc5883l_read(struct file *filp, FAR char *buffer, size_t buflen);
+static int hmc5883l_ioctl(struct file *filp, int cmd, unsigned long arg);
+
+static const struct file_operations hmc5883l_fops = {
+	.open  = 0,
+	.close = 0,
+	.read  = hmc5883l_read,
+	.write = 0,
+	.seek  = 0,
+	.ioctl = hmc5883l_ioctl,
+#ifndef CONFIG_DISABLE_POLL
+	.poll  = 0
+#endif
+};
+
+struct hmc5883l_dev_s
+{
+	struct i2c_dev_s	*i2c;
+	uint8_t			rate;
+	struct hmc5883l_buffer	*buffer;
+};
+
+static int hmc5883l_write_reg(uint8_t address, uint8_t data);
+static int hmc5883l_read_reg(uint8_t address);
+static int hmc5883l_reset(void);
+
+static int
+hmc5883l_write_reg(uint8_t address, uint8_t data)
+{
+	uint8_t cmd[] = {address, data};
+	return I2C_WRITE(hmc5883l_dev.i2c, cmd, 2);
+}
+
+static int
+hmc5883l_read_reg(uint8_t address)
+{
+	uint8_t cmd = address;
+	uint8_t data;
+
+	int ret = I2C_WRITEREAD(hmc5883l_dev.i2c, &cmd, 1, &data, 1);
+	/* return data on success, error code on failure */
+	if (ret == OK) {
+		ret = data;
+	}
+	return ret;
+}
+
+static int
+hmc5883l_set_range(uint8_t range)
+{
+	I2C_SETADDRESS(hmc5883l_dev.i2c, HMC5883L_ADDRESS, 7);
+
+
+	/* mask out illegal bit positions */
+	uint8_t write_range = range; //& REG4_RANGE_MASK;
+	/* immediately return if user supplied invalid value */
+	if (write_range != range) return EINVAL;
+	/* set remaining bits to a sane value */
+//	write_range |= REG4_BDU;
+	/* write to device */
+	hmc5883l_write_reg(ADDR_CONF_B, write_range);
+	/* return 0 if register value is now written value, 1 if unchanged */
+	return !(hmc5883l_read_reg(ADDR_CONF_B) == write_range);
+}
+
+static int
+hmc5883l_set_rate(uint8_t rate)
+{
+	I2C_SETADDRESS(hmc5883l_dev.i2c, HMC5883L_ADDRESS, 7);
+	/* mask out illegal bit positions */
+	uint8_t write_rate = rate;// & REG1_RATE_LP_MASK;
+	/* immediately return if user supplied invalid value */
+	if (write_rate != rate) return EINVAL;
+	/* set remaining bits to a sane value */
+//	write_rate |= REG1_POWER_NORMAL | REG1_Z_ENABLE | REG1_Y_ENABLE | REG1_X_ENABLE;
+	write_rate |= HMC5883L_AVERAGING_8;
+	/* write to device */
+	hmc5883l_write_reg(ADDR_CONF_A, write_rate);
+	/* return 0 if register value is now written value, 1 if unchanged */
+	return !(hmc5883l_read_reg(ADDR_CONF_A) == write_rate);
+}
+
+static bool
+read_values(int16_t *data)
+{
+	struct { /* status register and data as read back from the device */
+		int16_t		x;
+		int16_t		z;
+		int16_t		y;
+		uint8_t		status;
+	} __attribute__((packed))	hmc_report;
+	hmc_report.status = 0;
+
+	static int read_err_count = 0;
+
+	/* exchange the report structure with the device */
+
+	uint8_t cmd = ADDR_DATA_OUT_X_MSB;
+
+	int ret = 0;
+
+	I2C_SETADDRESS(hmc5883l_dev.i2c, HMC5883L_ADDRESS, 7);
+
+	/* set device into single mode, trigger next measurement */
+	ret = hmc5883l_write_reg(ADDR_MODE, MODE_REG_SINGLE_MODE);
+
+	/* Only execute consecutive steps on success */
+	if (ret == OK)
+	  {
+		cmd = ADDR_DATA_OUT_X_MSB;
+		ret = I2C_WRITEREAD(hmc5883l_dev.i2c, &cmd, 1, (uint8_t*)&hmc_report, 6);
+		if (ret == OK)
+		  {
+			/* Six bytes to read, stop if timed out */
+			int hmc_status = hmc5883l_read_reg(ADDR_STATUS);
+			if (hmc_status < 0)
+			  {
+			  	if (ret == ETIMEDOUT) hmc5883l_reset();
+			  	ret = hmc_status;
+			  }
+			else
+			  {
+			  	hmc_report.status = hmc_status;
+			  	ret = OK;
+			  }
+		  }
+		  else
+		  {
+		  	if (ret == ETIMEDOUT) hmc5883l_reset();
+		  }
+	  }
+	  else
+	  {
+	  	if (ret == ETIMEDOUT) hmc5883l_reset();
+	  }
+
+	if (ret != OK)
+	{
+		read_err_count++;
+		/* If the last reads failed as well, reset the bus and chip */
+		if (read_err_count > 3) hmc5883l_reset();
+
+		*get_errno_ptr() = -ret;
+	} else {
+		read_err_count = 0;
+		/* write values, and exchange the two 8bit blocks (big endian to little endian) */
+		data[0] = ((hmc_report.x & 0x00FF) << 8) | ((hmc_report.x & 0xFF00) >> 8);
+		data[1] = ((hmc_report.y & 0x00FF) << 8) | ((hmc_report.y & 0xFF00) >> 8);
+		data[2] = ((hmc_report.z & 0x00FF) << 8) | ((hmc_report.z & 0xFF00) >> 8);
+		if ((hmc_report.status & STATUS_REG_DATA_READY) > 0)
+		{
+			ret = 6;
+		} else {
+			ret = -EAGAIN;
+		}
+	}
+
+	/* return len if new data is available, error else. hmc_report.status is 0 on errors */
+	return ret;
+}
+
+static ssize_t
+hmc5883l_read(struct file *filp, char *buffer, size_t buflen)
+{
+	/* if the buffer is large enough, and data are available, return success */
+	if (buflen >= 6) {
+		return read_values((int16_t *)buffer);
+	}
+
+	/* buffer too small */
+	*get_errno_ptr() = ENOSPC;
+	return -ERROR;
+}
+
+static int
+hmc5883l_ioctl(struct file *filp, int cmd, unsigned long arg)
+{
+	int	result = ERROR;
+
+	switch (cmd) {
+       case HMC5883L_SETRATE:
+        	result = hmc5883l_set_rate(arg);
+        	break;
+
+       case HMC5883L_SETRANGE:
+        	result = hmc5883l_set_range(arg);
+        	break;
+//
+//    case HMC5883L_SETBUFFER:
+//        hmc5883l_dev.buffer = (struct hmc5883l_buffer *)arg;
+//        result = 0;
+//        break;
+
+        case HMC5883L_RESET:
+            result = hmc5883l_reset();
+            break;
+	}
+
+	if (result)
+		errno = EINVAL;
+	return result;
+}
+
+int hmc5883l_reset()
+{
+	int ret;
+	printf("[hmc5883l drv] Resettet I2C2 BUS\n");
+	up_i2cuninitialize(hmc5883l_dev.i2c);
+	hmc5883l_dev.i2c = up_i2cinitialize(2);
+	I2C_SETFREQUENCY(hmc5883l_dev.i2c, 400000);
+	// up_i2creset(hmc5883l_dev.i2c);
+	//I2C_SETADDRESS(hmc5883l_dev.i2c, HMC5883L_ADDRESS, 7);
+	//hmc5883l_set_range(HMC5883L_RANGE_0_88GA);
+	//hmc5883l_set_rate(HMC5883L_RATE_75HZ);
+	/* set device into single mode, start measurement */
+	//ret = hmc5883l_write_reg(ADDR_MODE, MODE_REG_SINGLE_MODE);
+	return ret;
+}
+
+int
+hmc5883l_attach(struct i2c_dev_s *i2c)
+{
+	int	result = ERROR;
+
+	hmc5883l_dev.i2c = i2c;
+
+//	I2C_LOCK(hmc5883l_dev.i2c, true);
+	I2C_SETADDRESS(hmc5883l_dev.i2c, HMC5883L_ADDRESS, 7);
+
+	uint8_t cmd = ADDR_STATUS;
+	uint8_t status_id[4] = {0, 0, 0, 0};
+
+
+	int ret = I2C_WRITEREAD(i2c, &cmd, 1, status_id, 4);
+
+	/* verify that the device is attached and functioning */
+	if ((ret >= 0) && (status_id[1] == ID_A_WHO_AM_I) && (status_id[2] == ID_B_WHO_AM_I) && (status_id[3] == ID_C_WHO_AM_I)) {
+
+		/* set update rate to 75 Hz */
+		/* set 0.88 Ga range */
+		if ((ret != 0) || (hmc5883l_set_range(HMC5883L_RANGE_0_88GA) != 0) ||
+				(hmc5883l_set_rate(HMC5883L_RATE_75HZ) != 0))
+		{
+			errno = EIO;
+		} else {
+
+			/* set device into single mode, start measurement */
+			ret = hmc5883l_write_reg(ADDR_MODE, MODE_REG_SINGLE_MODE);
+
+			/* make ourselves available */
+			register_driver("/dev/hmc5883l", &hmc5883l_fops, 0666, NULL);
+
+			result = 0;
+		}
+
+	} else {
+		errno = EIO;
+	}
+
+
+
+	return result;
+}
diff --git a/nuttx/configs/px4fmu/src/drv_l3gd20.c b/nuttx/configs/px4fmu/src/drv_l3gd20.c
new file mode 100644
index 000000000..1c6c05449
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_l3gd20.c
@@ -0,0 +1,364 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Driver for the ST L3GD20 MEMS gyroscope
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi.h>
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+#include <arch/board/drv_l3gd20.h>
+
+#include "chip.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+#define DIR_READ					(1<<7)
+#define DIR_WRITE					(0<<7)
+#define ADDR_INCREMENT				(1<<6)
+
+#define ADDR_WHO_AM_I				0x0F
+#define WHO_I_AM					0xD4
+#define ADDR_CTRL_REG1				0x20
+#define ADDR_CTRL_REG2				0x21
+#define ADDR_CTRL_REG3				0x22
+#define ADDR_CTRL_REG4				0x23
+#define ADDR_CTRL_REG5				0x24
+#define ADDR_REFERENCE				0x25
+#define ADDR_OUT_TEMP				0x26
+#define ADDR_STATUS_REG				0x27
+#define ADDR_OUT_X_L				0x28
+#define ADDR_OUT_X_H				0x29
+#define ADDR_OUT_Y_L				0x2A
+#define ADDR_OUT_Y_H				0x2B
+#define ADDR_OUT_Z_L				0x2C
+#define ADDR_OUT_Z_H				0x2D
+#define ADDR_FIFO_CTRL_REG			0x2E
+#define ADDR_FIFO_SRC_REG			0x2F
+#define ADDR_INT1_CFG				0x30
+#define ADDR_INT1_SRC				0x31
+#define ADDR_INT1_TSH_XH			0x32
+#define ADDR_INT1_TSH_XL			0x33
+#define ADDR_INT1_TSH_YH			0x34
+#define ADDR_INT1_TSH_YL			0x35
+#define ADDR_INT1_TSH_ZH			0x36
+#define ADDR_INT1_TSH_ZL			0x37
+#define ADDR_INT1_DURATION			0x38
+
+#define REG1_RATE_LP_MASK			0xF0 /* Mask to guard partial register update */
+#define REG4_RANGE_MASK				0x30 /* Mask to guard partial register update */
+
+/* Internal configuration values */
+#define REG1_POWER_NORMAL			(1<<3)
+#define REG1_Z_ENABLE				(1<<2)
+#define REG1_Y_ENABLE				(1<<1)
+#define REG1_X_ENABLE				(1<<0)
+
+#define REG4_BDU					(1<<7)
+#define REG4_BLE					(1<<6)
+//#define REG4_SPI_3WIRE				(1<<0)
+
+#define REG5_FIFO_ENABLE			(1<<6)
+#define REG5_REBOOT_MEMORY			(1<<7)
+
+#define STATUS_ZYXOR				(1<<7)
+#define STATUS_ZOR					(1<<6)
+#define STATUS_YOR					(1<<5)
+#define STATUS_XOR					(1<<4)
+#define STATUS_ZYXDA				(1<<3)
+#define STATUS_ZDA					(1<<2)
+#define STATUS_YDA					(1<<1)
+#define STATUS_XDA					(1<<0)
+
+#define FIFO_CTRL_BYPASS_MODE				(0<<5)
+#define FIFO_CTRL_FIFO_MODE					(1<<5)
+#define FIFO_CTRL_STREAM_MODE				(1<<6)
+#define FIFO_CTRL_STREAM_TO_FIFO_MODE		(3<<5)
+#define FIFO_CTRL_BYPASS_TO_STREAM_MODE		(1<<7)
+
+static FAR struct l3gd20_dev_s	l3gd20_dev;
+
+static ssize_t l3gd20_read(struct file *filp, FAR char *buffer, size_t buflen);
+static int l3gd20_ioctl(struct file *filp, int cmd, unsigned long arg);
+
+static const struct file_operations l3gd20_fops = {
+	.open  = 0,
+	.close = 0,
+	.read  = l3gd20_read,
+	.write = 0,
+	.seek  = 0,
+	.ioctl = l3gd20_ioctl,
+#ifndef CONFIG_DISABLE_POLL
+	.poll  = 0
+#endif
+};
+
+struct l3gd20_dev_s
+{
+	struct spi_dev_s	*spi;
+	int			spi_id;
+	uint8_t			rate;
+	struct l3gd20_buffer	*buffer;
+};
+
+static void	l3gd20_write_reg(uint8_t address, uint8_t data);
+static uint8_t	l3gd20_read_reg(uint8_t address);
+
+static void
+l3gd20_write_reg(uint8_t address, uint8_t data)
+{
+	uint8_t cmd[2] = { address | DIR_WRITE, data };
+
+	SPI_SELECT(l3gd20_dev.spi, l3gd20_dev.spi_id, true);
+    SPI_SNDBLOCK(l3gd20_dev.spi, &cmd, sizeof(cmd));
+	SPI_SELECT(l3gd20_dev.spi, l3gd20_dev.spi_id, false);
+}
+
+static uint8_t
+l3gd20_read_reg(uint8_t address)
+{
+	uint8_t	cmd[2] = {address | DIR_READ, 0};
+	uint8_t data[2];
+
+	SPI_SELECT(l3gd20_dev.spi, l3gd20_dev.spi_id, true);
+	SPI_EXCHANGE(l3gd20_dev.spi, cmd, data, sizeof(cmd));
+	SPI_SELECT(l3gd20_dev.spi, l3gd20_dev.spi_id, false);
+
+	return data[1];
+}
+
+static int
+set_range(uint8_t range)
+{
+	/* mask out illegal bit positions */
+	uint8_t write_range = range & REG4_RANGE_MASK;
+	/* immediately return if user supplied invalid value */
+	if (write_range != range) return EINVAL;
+	/* set remaining bits to a sane value */
+	write_range |= REG4_BDU;
+	/* write to device */
+	l3gd20_write_reg(ADDR_CTRL_REG4, write_range);
+	/* return 0 if register value is now written value, 1 if unchanged */
+	return !(l3gd20_read_reg(ADDR_CTRL_REG4) == write_range);
+}
+
+static int
+set_rate(uint8_t rate)
+{
+	/* mask out illegal bit positions */
+	uint8_t write_rate = rate & REG1_RATE_LP_MASK;
+	/* immediately return if user supplied invalid value */
+	if (write_rate != rate) return EINVAL;
+	/* set remaining bits to a sane value */
+	write_rate |= REG1_POWER_NORMAL | REG1_Z_ENABLE | REG1_Y_ENABLE | REG1_X_ENABLE;
+	/* write to device */
+	l3gd20_write_reg(ADDR_CTRL_REG1, write_rate);
+	/* return 0 if register value is now written value, 1 if unchanged */
+	return !(l3gd20_read_reg(ADDR_CTRL_REG1) == write_rate);
+}
+
+static int
+read_fifo(int16_t *data)
+{
+
+	struct {					/* status register and data as read back from the device */
+		uint8_t		cmd;
+		uint8_t		temp;
+		uint8_t		status;
+		int16_t		x;
+		int16_t		y;
+		int16_t		z;
+	} __attribute__((packed))	report = {.status = 11};
+
+	report.cmd = 0x26 | DIR_READ | ADDR_INCREMENT;
+
+	SPI_LOCK(l3gd20_dev.spi, true);
+	SPI_SELECT(l3gd20_dev.spi, PX4_SPIDEV_GYRO, true);
+	SPI_SETFREQUENCY(l3gd20_dev.spi, 25000000);
+
+	SPI_EXCHANGE(l3gd20_dev.spi, &report, &report, sizeof(report));
+
+	/* XXX if the status value is unchanged, attempt a second exchange */
+	if (report.status == 11) SPI_EXCHANGE(l3gd20_dev.spi, &report, &report, sizeof(report));
+	/* XXX set magic error value if this still didn't succeed */
+	if (report.status == 11) report.status = 12;
+
+	SPI_SETFREQUENCY(l3gd20_dev.spi, 10000000);
+	SPI_SELECT(l3gd20_dev.spi, PX4_SPIDEV_GYRO, false);
+	SPI_LOCK(l3gd20_dev.spi, false);
+
+	data[0] = report.x;
+	data[1] = report.y;
+	data[2] = report.z;
+
+	/* if all axes are valid, return buflen (6), else return negative status */
+	int ret = -((int)report.status);
+	if (STATUS_ZYXDA == (report.status & STATUS_ZYXDA) || STATUS_ZYXOR == (report.status & STATUS_ZYXOR))
+	{
+		ret = 6;
+	}
+
+	return ret;
+}
+
+static ssize_t
+l3gd20_read(struct file *filp, char *buffer, size_t buflen)
+{
+	/* if the buffer is large enough, and data are available, return success */
+	if (buflen >= 6) {
+		/* return buflen or a negative value */
+		int ret = read_fifo((int16_t *)buffer);
+		if (ret != 6) *get_errno_ptr() = EAGAIN;
+		return ret;
+	}
+
+	/* buffer too small */
+	*get_errno_ptr() = ENOSPC;
+	return ERROR;
+}
+
+static int
+l3gd20_ioctl(struct file *filp, int cmd, unsigned long arg)
+{
+	int	result = ERROR;
+
+	switch (cmd) {
+        case L3GD20_SETRATE:
+            if ((arg & REG1_RATE_LP_MASK) == arg) {
+            	SPI_LOCK(l3gd20_dev.spi, true);
+                set_rate(arg);
+                SPI_LOCK(l3gd20_dev.spi, false);
+                result = 0;
+                l3gd20_dev.rate = arg;
+            }
+            break;
+
+        case L3GD20_SETRANGE:
+            if ((arg & REG4_RANGE_MASK) == arg) {
+            	SPI_LOCK(l3gd20_dev.spi, true);
+                set_range(arg);
+                SPI_LOCK(l3gd20_dev.spi, false);
+                result = 0;
+            }
+            break;
+
+        case L3GD20_SETBUFFER:
+            l3gd20_dev.buffer = (struct l3gd20_buffer *)arg;
+            result = 0;
+            break;
+	}
+
+	if (result)
+		errno = EINVAL;
+	return result;
+}
+
+int
+l3gd20_attach(struct spi_dev_s *spi, int spi_id)
+{
+	int	result = ERROR;
+
+	l3gd20_dev.spi = spi;
+	l3gd20_dev.spi_id = spi_id;
+
+	SPI_LOCK(l3gd20_dev.spi, true);
+	/* read dummy value to void to clear SPI statemachine on sensor */
+	(void)l3gd20_read_reg(ADDR_WHO_AM_I);
+
+	/* verify that the device is attached and functioning */
+	if (l3gd20_read_reg(ADDR_WHO_AM_I) == WHO_I_AM) {
+
+		/* reset device memory */
+		//l3gd20_write_reg(ADDR_CTRL_REG5, REG5_REBOOT_MEMORY);
+		//up_udelay(1000);
+
+		/* set default configuration */
+ 	 	l3gd20_write_reg(ADDR_CTRL_REG1, REG1_POWER_NORMAL | REG1_Z_ENABLE | REG1_Y_ENABLE | REG1_X_ENABLE);
+		l3gd20_write_reg(ADDR_CTRL_REG2, 0);		/* disable high-pass filters */
+		l3gd20_write_reg(ADDR_CTRL_REG3, 0);		/* no interrupts - we don't use them */
+		l3gd20_write_reg(ADDR_CTRL_REG4, 0x10);
+		l3gd20_write_reg(ADDR_CTRL_REG5, 0);
+
+		l3gd20_write_reg(ADDR_CTRL_REG5, REG5_FIFO_ENABLE);	  /* disable wake-on-interrupt */
+		l3gd20_write_reg(ADDR_FIFO_CTRL_REG, FIFO_CTRL_STREAM_MODE); /* Enable FIFO, old data is overwritten */
+
+		if ((set_range(L3GD20_RANGE_500DPS) != 0) ||
+				(set_rate(L3GD20_RATE_760HZ_LP_100HZ) != 0))	/* takes device out of low-power mode */
+		{
+			errno = EIO;
+		} else {
+			/* Read out the first few funky values */
+			struct {					/* status register and data as read back from the device */
+				uint8_t		cmd;
+				uint8_t		temp;
+				uint8_t		status;
+				int16_t		x;
+				int16_t		y;
+				int16_t		z;
+			} __attribute__((packed))	report;
+
+			report.cmd = 0x26 | DIR_READ | ADDR_INCREMENT;
+
+			SPI_SELECT(spi, PX4_SPIDEV_GYRO, true);
+			SPI_EXCHANGE(spi, &report, &report, sizeof(report));
+			SPI_SELECT(spi, PX4_SPIDEV_GYRO, false);
+			up_udelay(500);
+			/* And read another set */
+			SPI_SELECT(spi, PX4_SPIDEV_GYRO, true);
+			SPI_EXCHANGE(spi, &report, &report, sizeof(report));
+			SPI_SELECT(spi, PX4_SPIDEV_GYRO, false);
+
+
+			/* make ourselves available */
+			register_driver("/dev/l3gd20", &l3gd20_fops, 0666, NULL);
+
+			result = 0;
+		}
+
+	} else {
+
+		errno = EIO;
+	}
+
+	SPI_LOCK(l3gd20_dev.spi, false);
+
+	return result;
+}
diff --git a/nuttx/configs/px4fmu/src/drv_led.c b/nuttx/configs/px4fmu/src/drv_led.c
new file mode 100644
index 000000000..13d8eb22a
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_led.c
@@ -0,0 +1,113 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * led driver for PX4FMU
+ *
+ * This is something of an experiment currently (ha, get it?)
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/drv_led.h>
+
+static int	px4fmu_led_ioctl(struct file *filep, int cmd, unsigned long arg);
+static ssize_t	px4fmu_led_pseudoread(struct file *filp, FAR char *buffer, size_t buflen);
+
+static const struct file_operations px4fmu_led_fops = {
+	.read  = px4fmu_led_pseudoread,
+	.ioctl = px4fmu_led_ioctl,
+};
+
+int
+px4fmu_led_init(void)
+{
+	/* register the driver */
+	return register_driver("/dev/led", &px4fmu_led_fops, 0666, NULL);
+}
+
+static ssize_t
+px4fmu_led_pseudoread(struct file *filp, FAR char *buffer, size_t buflen)
+{
+	return 0;
+}
+
+static int
+px4fmu_led_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+	int	result = 0;
+
+	switch (cmd) {
+
+	case LED_ON:
+		switch (arg) {
+		case 0:
+		case 1:
+			up_ledon(arg);
+			break;
+		default:
+			result = -1;
+			break;
+		}
+		break;
+
+	case LED_OFF:
+		switch (arg) {
+		case 0:
+		case 1:
+			up_ledoff(arg);
+			break;
+		default:
+			result = -1;
+			break;
+		}
+		break;
+		default:
+			result = -1;
+			break;
+	}
+	return result;
+}
+
diff --git a/nuttx/configs/px4fmu/src/drv_lis331.c b/nuttx/configs/px4fmu/src/drv_lis331.c
new file mode 100644
index 000000000..fd477b46f
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_lis331.c
@@ -0,0 +1,272 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Driver for the ST LIS331 MEMS accelerometer
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/drv_lis331.h>
+
+/*
+ * LIS331 registers
+ */
+
+#define DIR_READ		(1<<7)
+#define DIR_WRITE		(0<<7)
+#define ADDR_INCREMENT		(1<<6)
+
+#define ADDR_WHO_AM_I		0x0f
+#define WHO_I_AM		0x32
+
+#define ADDR_CTRL_REG1		0x20		/* sample rate constants are in the public header */
+#define REG1_POWER_NORMAL		(1<<5)
+#define REG1_RATE_MASK			(3<<3)
+#define REG1_Z_ENABLE			(1<<2)
+#define REG1_Y_ENABLE			(1<<1)
+#define REG1_X_ENABLE			(1<<0)
+
+#define ADDR_CTRL_REG2		0x21
+
+#define ADDR_CTRL_REG3		0x22
+
+#define ADDR_CTRL_REG4		0x23
+#define REG4_BDU			(1<<7)
+#define REG4_BIG_ENDIAN			(1<<6)
+#define REG4_RANGE_MASK			(3<<4)
+#define REG4_SPI_3WIRE			(1<<0)
+
+#define ADDR_CTRL_REG5		0x24
+
+#define ADDR_HP_FILTER_RESET	0x25
+#define ADDR_REFERENCE		0x26
+#define ADDR_STATUS_REG		0x27
+#define STATUS_ZYXOR			(1<<7)
+#define STATUS_ZOR				(1<<6)
+#define STATUS_YOR				(1<<5)
+#define STATUS_XOR				(1<<4)
+#define STATUS_ZYXDA			(1<<3)
+#define STATUS_ZDA				(1<<2)
+#define STATUS_YDA				(1<<1)
+#define STATUS_XDA				(1<<0)
+
+#define ADDR_OUT_X		0x28	/* 16 bits */
+#define ADDR_OUT_Y		0x2A	/* 16 bits */
+#define ADDR_OUT_Z		0x2C	/* 16 bits */
+
+
+static ssize_t	lis331_read(struct file *filp, FAR char *buffer, size_t buflen);
+static int	lis331_ioctl(struct file *filp, int cmd, unsigned long arg);
+
+static const struct file_operations lis331_fops = {
+	.read  = lis331_read,
+	.ioctl = lis331_ioctl,
+};
+
+struct lis331_dev_s
+{
+	struct spi_dev_s	*spi;
+	int			spi_id;
+
+	uint8_t			rate;
+	struct lis331_buffer	*buffer;
+};
+
+static struct lis331_dev_s	lis331_dev;
+
+static void	write_reg(uint8_t address, uint8_t data);
+static uint8_t	read_reg(uint8_t address);
+static bool	read_fifo(uint16_t *data);
+static void	set_range(uint8_t range);
+static void	set_rate(uint8_t rate);
+
+static void
+write_reg(uint8_t address, uint8_t data)
+{
+	uint8_t cmd[2] = { address | DIR_WRITE, data };
+
+	SPI_SELECT(lis331_dev.spi, lis331_dev.spi_id, true);
+      	SPI_SNDBLOCK(lis331_dev.spi, &cmd, sizeof(cmd));
+	SPI_SELECT(lis331_dev.spi, lis331_dev.spi_id, false);
+}
+
+static uint8_t
+read_reg(uint8_t address)
+{
+	uint8_t	cmd[2] = {address | DIR_READ, 0};
+	uint8_t data[2];
+
+	SPI_SELECT(lis331_dev.spi, lis331_dev.spi_id, true);
+	SPI_EXCHANGE(lis331_dev.spi, cmd, data, sizeof(cmd));
+	SPI_SELECT(lis331_dev.spi, lis331_dev.spi_id, false);
+
+	return data[1];	
+}
+
+static bool
+read_fifo(uint16_t *data)
+{
+	struct {					/* status register and data as read back from the device */
+		uint8_t		cmd;
+		uint8_t		status;
+		int16_t		x;
+		int16_t		y;
+		int16_t		z;
+	} __attribute__((packed))	report;
+
+	report.cmd = ADDR_STATUS_REG | DIR_READ | ADDR_INCREMENT;
+
+	/* exchange the report structure with the device */
+	SPI_LOCK(lis331_dev.spi, true);
+	SPI_SELECT(lis331_dev.spi, lis331_dev.spi_id, true);
+	SPI_EXCHANGE(lis331_dev.spi, &report, &report, sizeof(report));
+	SPI_SELECT(lis331_dev.spi, lis331_dev.spi_id, false);
+	SPI_LOCK(lis331_dev.spi, false);
+
+	data[0] = report.x;
+	data[1] = report.y;
+	data[2] = report.z;
+
+	return report.status & STATUS_ZYXDA;
+}
+
+static void
+set_range(uint8_t range)
+{
+	range &= REG4_RANGE_MASK;
+	write_reg(ADDR_CTRL_REG4, range | REG4_BDU);
+}
+
+static void
+set_rate(uint8_t rate)
+{
+	rate &= REG1_RATE_MASK;
+	write_reg(ADDR_CTRL_REG1, rate | REG1_POWER_NORMAL | REG1_Z_ENABLE | REG1_Y_ENABLE | REG1_X_ENABLE);
+}
+
+static ssize_t
+lis331_read(struct file *filp, char *buffer, size_t buflen)
+{
+	/* if the buffer is large enough, and data are available, return success */
+	if (buflen >= 12) {
+		if (read_fifo((uint16_t *)buffer))
+			return 12;
+
+		/* no data */
+		return 0;
+	}
+
+	/* buffer too small */
+	errno = ENOSPC;
+	return ERROR;
+}
+
+static int
+lis331_ioctl(struct file *filp, int cmd, unsigned long arg)
+{
+	int	result = ERROR;
+
+	switch (cmd) {
+	case LIS331_SETRATE:
+		if ((arg & REG1_RATE_MASK) == arg) {
+			set_rate(arg);
+			result = 0;
+			lis331_dev.rate = arg;
+		}
+		break;
+
+	case LIS331_SETRANGE:
+		if ((arg & REG4_RANGE_MASK) == arg) {
+			set_range(arg);
+			result = 0;
+		}
+		break;
+
+	case LIS331_SETBUFFER:
+		lis331_dev.buffer = (struct lis331_buffer *)arg;
+		result = 0;
+		break;
+	}
+
+	if (result)
+		errno = EINVAL;
+	return result;
+}
+
+int
+lis331_attach(struct spi_dev_s *spi, int spi_id)
+{
+	int	result = ERROR;
+	
+	lis331_dev.spi = spi;
+
+	SPI_LOCK(lis331_dev.spi, true);
+
+	/* verify that the device is attached and functioning */
+	if (read_reg(ADDR_WHO_AM_I) == WHO_I_AM) {
+
+		/* set default configuration */
+		write_reg(ADDR_CTRL_REG2, 0);	/* disable interrupt-generating high-pass filters */
+		write_reg(ADDR_CTRL_REG3, 0);	/* no interrupts - we don't use them */
+		write_reg(ADDR_CTRL_REG5, 0);	/* disable wake-on-interrupt */
+
+		set_range(LIS331_RANGE_4G);
+		set_rate(LIS331_RATE_400Hz);	/* takes device out of low-power mode */
+
+		/* make ourselves available */
+		register_driver("/dev/lis331", &lis331_fops, 0666, NULL);
+
+		result = 0;
+	} else {
+		errno = EIO;
+	}
+
+	SPI_LOCK(lis331_dev.spi, false);
+
+	return result;
+}
+
diff --git a/nuttx/configs/px4fmu/src/drv_mpu6000.c b/nuttx/configs/px4fmu/src/drv_mpu6000.c
new file mode 100644
index 000000000..47f655563
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_mpu6000.c
@@ -0,0 +1,411 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the ST mpu6000 MEMS gyroscope
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+#include <unistd.h>
+#include <stdio.h>
+
+#include <nuttx/spi.h>
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+
+#include "chip.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/drv_mpu6000.h>
+
+#define DIR_READ					(0x80)
+#define DIR_WRITE					(0<<7)
+#define ADDR_INCREMENT				(1<<6)
+
+#define WHO_I_AM					0xD4
+
+// MPU 6000 registers
+#define MPUREG_WHOAMI 0x75 //
+#define MPUREG_SMPLRT_DIV 0x19 //
+#define MPUREG_CONFIG 0x1A //
+#define MPUREG_GYRO_CONFIG 0x1B
+#define MPUREG_ACCEL_CONFIG 0x1C
+#define MPUREG_FIFO_EN 0x23
+#define MPUREG_INT_PIN_CFG 0x37
+#define MPUREG_INT_ENABLE 0x38
+#define MPUREG_INT_STATUS 0x3A
+#define MPUREG_ACCEL_XOUT_H 0x3B //
+#define MPUREG_ACCEL_XOUT_L 0x3C //
+#define MPUREG_ACCEL_YOUT_H 0x3D //
+#define MPUREG_ACCEL_YOUT_L 0x3E //
+#define MPUREG_ACCEL_ZOUT_H 0x3F //
+#define MPUREG_ACCEL_ZOUT_L 0x40 //
+#define MPUREG_TEMP_OUT_H 0x41//
+#define MPUREG_TEMP_OUT_L 0x42//
+#define MPUREG_GYRO_XOUT_H 0x43 //
+#define MPUREG_GYRO_XOUT_L 0x44 //
+#define MPUREG_GYRO_YOUT_H 0x45 //
+#define MPUREG_GYRO_YOUT_L 0x46 //
+#define MPUREG_GYRO_ZOUT_H 0x47 //
+#define MPUREG_GYRO_ZOUT_L 0x48 //
+#define MPUREG_USER_CTRL 0x6A //
+#define MPUREG_PWR_MGMT_1 0x6B //
+#define MPUREG_PWR_MGMT_2 0x6C //
+#define MPUREG_FIFO_COUNTH 0x72
+#define MPUREG_FIFO_COUNTL 0x73
+#define MPUREG_FIFO_R_W 0x74
+#define MPUREG_PRODUCT_ID 			0x0C	// Product ID Register
+
+
+// Configuration bits MPU 3000 and MPU 6000 (not revised)?
+#define BIT_SLEEP 0x40
+#define BIT_H_RESET 0x80
+#define BITS_CLKSEL 0x07
+#define MPU_CLK_SEL_PLLGYROX 0x01
+#define MPU_CLK_SEL_PLLGYROZ 0x03
+#define MPU_EXT_SYNC_GYROX 0x02
+#define BITS_FS_250DPS              0x00
+#define BITS_FS_500DPS              0x08
+#define BITS_FS_1000DPS             0x10
+#define BITS_FS_2000DPS             0x18
+#define BITS_FS_MASK                0x18
+#define BITS_DLPF_CFG_256HZ_NOLPF2  0x00
+#define BITS_DLPF_CFG_188HZ         0x01
+#define BITS_DLPF_CFG_98HZ          0x02
+#define BITS_DLPF_CFG_42HZ          0x03
+#define BITS_DLPF_CFG_20HZ          0x04
+#define BITS_DLPF_CFG_10HZ          0x05
+#define BITS_DLPF_CFG_5HZ           0x06
+#define BITS_DLPF_CFG_2100HZ_NOLPF  0x07
+#define BITS_DLPF_CFG_MASK          0x07
+#define BIT_INT_ANYRD_2CLEAR      0x10
+#define BIT_RAW_RDY_EN        0x01
+#define BIT_I2C_IF_DIS              0x10
+#define BIT_INT_STATUS_DATA   0x01
+											// Product ID Description for MPU6000
+											// high 4 bits 	low 4 bits
+											// Product Name	Product Revision
+#define MPU6000ES_REV_C4 			0x14 	// 0001			0100
+#define MPU6000ES_REV_C5 			0x15 	// 0001			0101
+#define MPU6000ES_REV_D6 			0x16	// 0001			0110
+#define MPU6000ES_REV_D7 			0x17	// 0001			0111
+#define MPU6000ES_REV_D8 			0x18	// 0001			1000	
+#define MPU6000_REV_C4 				0x54	// 0101			0100 
+#define MPU6000_REV_C5 				0x55	// 0101			0101
+#define MPU6000_REV_D6 				0x56	// 0101			0110	
+#define MPU6000_REV_D7 				0x57	// 0101			0111
+#define MPU6000_REV_D8 				0x58	// 0101			1000
+#define MPU6000_REV_D9 				0x59	// 0101			1001
+#define MPU6000_REV_D10 			0x5A	// 0101			1010
+
+static FAR struct mpu6000_dev_s	mpu6000_dev;
+
+static ssize_t mpu6000_read(struct file *filp, FAR char *buffer, size_t buflen);
+static int mpu6000_ioctl(struct file *filp, int cmd, unsigned long arg);
+
+static const struct file_operations mpu6000_fops = {
+	.open  = 0,
+	.close = 0,
+	.read  = mpu6000_read,
+	.write = 0,
+	.seek  = 0,
+	.ioctl = mpu6000_ioctl,
+#ifndef CONFIG_DISABLE_POLL
+	.poll  = 0
+#endif
+};
+
+struct mpu6000_dev_s
+{
+	struct spi_dev_s	*spi;
+	int			spi_id;
+	uint8_t			rate;
+	struct mpu6000_buffer	*buffer;
+};
+
+static void	mpu6000_write_reg(uint8_t address, uint8_t data);
+static uint8_t	mpu6000_read_reg(uint8_t address);
+
+static void
+mpu6000_write_reg(uint8_t address, uint8_t data)
+{
+	uint8_t cmd[2] = { address | DIR_WRITE, data };
+
+	SPI_SELECT(mpu6000_dev.spi, mpu6000_dev.spi_id, true);
+    SPI_SNDBLOCK(mpu6000_dev.spi, &cmd, sizeof(cmd));
+	SPI_SELECT(mpu6000_dev.spi, mpu6000_dev.spi_id, false);
+}
+
+static uint8_t
+mpu6000_read_reg(uint8_t address)
+{
+	uint8_t	cmd[2] = {address | DIR_READ, 0};
+	uint8_t data[2];
+
+	SPI_SELECT(mpu6000_dev.spi, mpu6000_dev.spi_id, true);
+	SPI_EXCHANGE(mpu6000_dev.spi, cmd, data, sizeof(cmd));
+	SPI_SELECT(mpu6000_dev.spi, mpu6000_dev.spi_id, false);
+
+	return data[1];
+}
+
+static int
+mpu6000_set_range(uint8_t range)
+{
+//	/* mask out illegal bit positions */
+//	uint8_t write_range = range & REG4_RANGE_MASK;
+//	/* immediately return if user supplied invalid value */
+//	if (write_range != range) return EINVAL;
+//	/* set remaining bits to a sane value */
+//	write_range |= REG4_BDU;
+//	/* write to device */
+//	write_reg(ADDR_CTRL_REG4, write_range);
+//	/* return 0 if register value is now written value, 1 if unchanged */
+//	return !(read_reg(ADDR_CTRL_REG4) == write_range);
+}
+
+static int
+mpu6000_set_rate(uint8_t rate)
+{
+//	/* mask out illegal bit positions */
+//	uint8_t write_rate = rate & REG1_RATE_LP_MASK;
+//	/* immediately return if user supplied invalid value */
+//	if (write_rate != rate) return EINVAL;
+//	/* set remaining bits to a sane value */
+//	write_rate |= REG1_POWER_NORMAL | REG1_Z_ENABLE | REG1_Y_ENABLE | REG1_X_ENABLE;
+//	/* write to device */
+//	write_reg(ADDR_CTRL_REG1, write_rate);
+//	/* return 0 if register value is now written value, 1 if unchanged */
+//	return !(read_reg(ADDR_CTRL_REG1) == write_rate);
+}
+
+static int
+mpu6000_read_fifo(int16_t *data)
+{
+//	struct {					/* status register and data as read back from the device */
+//		uint8_t		cmd;
+//		uint8_t		temp;
+//		uint8_t		status;
+//		int16_t		x;
+//		int16_t		y;
+//		int16_t		z;
+//	} __attribute__((packed))	report;
+//
+//	report.cmd = ADDR_OUT_TEMP | DIR_READ | ADDR_INCREMENT;
+//
+//	/* exchange the report structure with the device */
+//	SPI_LOCK(mpu6000_dev.spi, true);
+//
+//	SPI_SELECT(mpu6000_dev.spi, mpu6000_dev.spi_id, true);
+//
+//	read_reg(ADDR_WHO_AM_I);
+//
+//	SPI_EXCHANGE(mpu6000_dev.spi, &report, &report, sizeof(report));
+//	SPI_SELECT(mpu6000_dev.spi, mpu6000_dev.spi_id, false);
+//
+//	SPI_LOCK(mpu6000_dev.spi, false);
+//
+//
+//
+	//
+
+	// Device has MSB first at lower address (big endian)
+
+
+	struct {					/* status register and data as read back from the device */
+		uint8_t		cmd;
+		uint8_t		int_status;
+		int16_t		xacc;
+		int16_t		yacc;
+		int16_t		zacc;
+		int8_t		temp;
+		int16_t		rollspeed;
+		int16_t		pitchspeed;
+		int16_t		yawspeed;
+	} __attribute__((packed))	report;
+
+	report.cmd = 0x26 | DIR_READ | ADDR_INCREMENT;
+
+	SPI_LOCK(mpu6000_dev.spi, true);
+	SPI_SELECT(mpu6000_dev.spi, PX4_SPIDEV_MPU, true);
+	SPI_EXCHANGE(mpu6000_dev.spi, &report, &report, sizeof(report));
+	SPI_SELECT(mpu6000_dev.spi, PX4_SPIDEV_MPU, false);
+	SPI_LOCK(mpu6000_dev.spi, false);
+
+	data[0] = report.xacc;
+	data[1] = report.yacc;
+	data[2] = report.zacc;
+
+	return (report.int_status & 0x01);
+}
+
+static ssize_t
+mpu6000_read(struct file *filp, char *buffer, size_t buflen)
+{
+	/* if the buffer is large enough, and data are available, return success */
+	if (buflen >= 6) {
+		if (mpu6000_read_fifo((int16_t *)buffer))
+			return 6;
+
+		/* no data */
+		return 0;
+	}
+
+	/* buffer too small */
+	errno = ENOSPC;
+	return ERROR;
+}
+
+static int
+mpu6000_ioctl(struct file *filp, int cmd, unsigned long arg)
+{
+	int	result = ERROR;
+
+	switch (cmd) {
+        case MPU6000_SETRATE:
+            if ((arg & 0x00/* XXX REG MASK MISSING */) == arg) {
+            	SPI_LOCK(mpu6000_dev.spi, true);
+                mpu6000_set_rate(arg);
+                SPI_LOCK(mpu6000_dev.spi, false);
+                result = 0;
+                mpu6000_dev.rate = arg;
+            }
+            break;
+
+        case MPU6000_SETRANGE:
+            if ((arg & 0x00/* XXX REG MASK MISSING */) == arg) {
+            	SPI_LOCK(mpu6000_dev.spi, true);
+                mpu6000_set_range(arg);
+                SPI_LOCK(mpu6000_dev.spi, false);
+                result = 0;
+            }
+            break;
+
+        case MPU6000_SETBUFFER:
+            mpu6000_dev.buffer = (struct mpu6000_buffer *)arg;
+            result = 0;
+            break;
+	}
+
+	if (result)
+		errno = EINVAL;
+	return result;
+}
+
+int
+mpu6000_attach(struct spi_dev_s *spi, int spi_id)
+{
+	int	result = ERROR;
+
+	mpu6000_dev.spi = spi;
+	mpu6000_dev.spi_id = spi_id;
+
+	SPI_LOCK(mpu6000_dev.spi, true);
+
+	// Set sensor-specific SPI mode
+	SPI_SETFREQUENCY(mpu6000_dev.spi, 10000000); // 500 KHz
+	SPI_SETBITS(mpu6000_dev.spi, 8);
+	// Either mode 1 or mode 3
+	SPI_SETMODE(mpu6000_dev.spi, SPIDEV_MODE3);
+
+	// Chip reset
+	mpu6000_write_reg(MPUREG_PWR_MGMT_1, BIT_H_RESET);
+	up_udelay(10000);
+	// Wake up device and select GyroZ clock (better performance)
+	mpu6000_write_reg(MPUREG_PWR_MGMT_1, MPU_CLK_SEL_PLLGYROZ);
+	up_udelay(1000);
+	// Disable I2C bus (recommended on datasheet)
+	mpu6000_write_reg(MPUREG_USER_CTRL, BIT_I2C_IF_DIS);
+	up_udelay(1000);
+    // SAMPLE RATE
+	mpu6000_write_reg(MPUREG_SMPLRT_DIV,0x04);     // Sample rate = 200Hz    Fsample= 1Khz/(4+1) = 200Hz
+    usleep(1000);
+    // FS & DLPF   FS=2000¼/s, DLPF = 98Hz (low pass filter)
+    mpu6000_write_reg(MPUREG_CONFIG, BITS_DLPF_CFG_98HZ);
+    usleep(1000);
+    mpu6000_write_reg(MPUREG_GYRO_CONFIG,BITS_FS_2000DPS);  // Gyro scale 2000¼/s
+    usleep(1000);
+
+	uint8_t _product_id = mpu6000_read_reg(MPUREG_PRODUCT_ID);
+	printf("MPU-6000 product id: %d\n", (int)_product_id);
+
+	if ((_product_id == MPU6000ES_REV_C4) || (_product_id == MPU6000ES_REV_C5) ||
+		(_product_id == MPU6000_REV_C4)   || (_product_id == MPU6000_REV_C5)){
+		// Accel scale 8g (4096 LSB/g)
+		// Rev C has different scaling than rev D
+		mpu6000_write_reg(MPUREG_ACCEL_CONFIG,1<<3);
+	} else {
+		// Accel scale 8g (4096 LSB/g)
+		mpu6000_write_reg(MPUREG_ACCEL_CONFIG,2<<3);
+	}
+    usleep(1000);
+
+    // INT CFG => Interrupt on Data Ready
+    mpu6000_write_reg(MPUREG_INT_ENABLE,BIT_RAW_RDY_EN);         // INT: Raw data ready
+    usleep(1000);
+    mpu6000_write_reg(MPUREG_INT_PIN_CFG,BIT_INT_ANYRD_2CLEAR);  // INT: Clear on any read
+    usleep(1000);
+    // Oscillator set
+    // write_reg(MPUREG_PWR_MGMT_1,MPU_CLK_SEL_PLLGYROZ);
+    usleep(1000);
+
+    /* revert back to normal bus mode */
+	SPI_SETFREQUENCY(mpu6000_dev.spi, 10000000);
+	SPI_SETBITS(mpu6000_dev.spi, 8);
+	SPI_SETMODE(mpu6000_dev.spi, SPIDEV_MODE3);
+
+	/* verify that the device is attached and functioning */
+	if ((_product_id == MPU6000ES_REV_C4) || (_product_id == MPU6000ES_REV_C5) ||
+		(_product_id == MPU6000_REV_C4)   || (_product_id == MPU6000_REV_C5) ||
+		(_product_id == MPU6000_REV_D7)	  || (_product_id == MPU6000_REV_D8) ||
+		(_product_id == MPU6000_REV_D9)   || (_product_id == MPU6000_REV_D10)){
+
+		/* make ourselves available */
+		register_driver("/dev/mpu6000", &mpu6000_fops, 0666, NULL);
+
+		result = OK;
+	} else {
+
+		errno = EIO;
+	}
+
+	SPI_LOCK(mpu6000_dev.spi, false);
+
+	SPI_LOCK(mpu6000_dev.spi, false);
+
+	return result;
+}
diff --git a/nuttx/configs/px4fmu/src/drv_ms5611.c b/nuttx/configs/px4fmu/src/drv_ms5611.c
new file mode 100644
index 000000000..7fea65159
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_ms5611.c
@@ -0,0 +1,493 @@
+/*
+ *   Copyright (C) 2012 Lorenz Meier. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the author or the names of contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Driver for the Measurement Specialties MS5611 barometric pressure sensor
+ */
+
+#include <nuttx/config.h>
+#include <nuttx/i2c.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+#include <string.h>
+#include <stdio.h>
+#include <math.h>
+
+#include "chip.h"
+#include "px4fmu-internal.h"
+
+#include <arch/board/up_hrt.h>
+#include <arch/board/drv_ms5611.h>
+
+/* internal conversion time: 9.17 ms, so should not be read at rates higher than 100 Hz */
+#define MS5611_MIN_INTER_MEASUREMENT_INTERVAL 9200
+
+#define MS5611_ADDRESS_1		0x76    /* address select pins pulled high (PX4FMU series v1.6+) */
+#define MS5611_ADDRESS_2		0x77    /* address select pins pulled low (PX4FMU prototypes) */
+
+#define ADDR_RESET_CMD			0x1E /* read from this address to reset chip (0b0011110 on bus) */
+#define ADDR_CMD_CONVERT_D1		0x48 /* 4096 samples to this address to start conversion (0b01001000 on bus) */
+#define ADDR_CMD_CONVERT_D2		0x58 /* 4096 samples */
+#define ADDR_DATA				0x00 /* address of 3 bytes / 32bit pressure data */
+#define ADDR_PROM_SETUP			0xA0 /* address of 8x 2 bytes factory and calibration data */
+#define ADDR_PROM_C1			0xA2 /* address of 6x 2 bytes calibration data */
+
+static FAR struct ms5611_dev_s	ms5611_dev;
+
+static ssize_t ms5611_read(struct file *filp, FAR char *buffer, size_t buflen);
+static int ms5611_ioctl(struct file *filp, int cmd, unsigned long arg);
+
+static const struct file_operations ms5611_fops = {
+	.read  = ms5611_read,
+	.ioctl = ms5611_ioctl,
+};
+
+struct ms5611_prom_s
+{
+	uint16_t factory_setup;
+	uint16_t c1_pressure_sens;
+	uint16_t c2_pressure_offset;
+	uint16_t c3_temp_coeff_pres_sens;
+	uint16_t c4_temp_coeff_pres_offset;
+	uint16_t c5_reference_temp;
+	uint16_t c6_temp_coeff_temp;
+	uint16_t serial_and_crc;
+} __attribute__((packed));
+
+union ms5611_prom_u
+{
+	uint16_t c[8];
+	struct ms5611_prom_s s;
+} __attribute__((packed));
+
+struct ms5611_dev_s
+{
+	union ms5611_prom_u 	prom;
+	struct i2c_dev_s		*i2c;
+	struct ms5611_buffer	*buffer;
+} __attribute__((packed));
+
+static FAR uint8_t MS5611_ADDRESS;
+
+static FAR struct {
+		/* status register and data as read back from the device */
+		float		pressure;
+		float		altitude;
+		float		temperature;
+		uint32_t	d1_raw;
+		uint32_t	d2_raw;
+		uint32_t	measurements_count;
+		uint8_t		last_state;
+		uint64_t    last_read;
+	} ms5611_report = {
+			.pressure = 0.0f,
+			.altitude = 0.0f,
+			.temperature = 0.0f,
+			.last_state = 0,
+			/* make sure the first readout can be performed */
+			.last_read = 0,
+};
+
+static int ms5611_read_prom(void);
+
+static bool
+read_values(float *data)
+{
+	int ret;
+	uint8_t cmd_data[3];
+
+	/* check validity of pointer */
+	if (data == NULL)
+	{
+		*get_errno_ptr() = EINVAL;
+		return -EINVAL;
+	}
+
+	/* only start reading when data is available */
+	if (ms5611_report.measurements_count > 0)
+	{
+		/* do not read more often than at minimum 9.17 ms intervals */
+		if ((hrt_absolute_time() - ms5611_report.last_read) < MS5611_MIN_INTER_MEASUREMENT_INTERVAL)
+		{
+			/* set errno to 'come back later' */
+			ret = -EAGAIN;
+			goto handle_return;
+		}
+		else
+		{
+			/* set new value */
+			ms5611_report.last_read = hrt_absolute_time();
+		}
+
+		/* Read out last measurement */
+		cmd_data[0] = 0x00;
+
+		struct i2c_msg_s msgv[2] = {
+				{
+						.addr   = MS5611_ADDRESS,
+						.flags  = 0,
+						.buffer = cmd_data,
+						.length = 1
+				},
+				{
+						.addr   = MS5611_ADDRESS,
+						.flags  = I2C_M_READ,
+						.buffer = cmd_data,
+						.length = 3
+				}
+		};
+		ret = I2C_TRANSFER(ms5611_dev.i2c, msgv, 2);
+		if (ret != OK) goto handle_return;
+
+
+		/* at value 1 the last reading was temperature */
+		if (ms5611_report.last_state == 1)
+		{
+			/* put temperature into the raw set */
+			ms5611_report.d2_raw = (((uint32_t)cmd_data[0]) << 16) | (((uint32_t)cmd_data[1]) << 8) | ((uint32_t)cmd_data[2]);
+		}
+		else
+		{
+			/* put altitude into the raw set */
+			ms5611_report.d1_raw = (((uint32_t)cmd_data[0]) << 16) | (((uint32_t)cmd_data[1]) << 8) | ((uint32_t)cmd_data[2]);
+		}
+	}
+	ms5611_report.measurements_count++;
+
+	/*
+	 * this block reads four pressure values and one temp value,
+	 * resulting in 80 Hz pressure update and 20 Hz temperature updates
+	 * at 100 Hz continuous operation.
+	 */
+	if (ms5611_report.last_state == 0)
+	{
+		/* request first a temperature reading */
+		cmd_data[0] = ADDR_CMD_CONVERT_D2;
+	}
+	else
+	{
+		/* request pressure reading */
+		cmd_data[0] = ADDR_CMD_CONVERT_D1;
+	}
+
+	if (ms5611_report.last_state == 3)
+	{
+		ms5611_report.last_state = 0;
+	}
+	else
+	{
+		ms5611_report.last_state++;
+	}
+
+
+	/* write measurement command */
+	struct i2c_msg_s conv_cmd[1] = {
+			{
+					.addr   = MS5611_ADDRESS,
+					.flags  = 0,
+					.buffer = cmd_data,
+					.length = 1
+			},
+	};
+
+	ret = I2C_TRANSFER(ms5611_dev.i2c, conv_cmd, 1);
+	if (ret != OK) goto handle_return;
+
+	/* only write back values after first complete set */
+	if (ms5611_report.measurements_count > 2)
+	{
+		/* Calculate results */
+
+		/* temperature calculation */
+		int32_t dT = ms5611_report.d2_raw - (((int32_t)ms5611_dev.prom.s.c5_reference_temp)*256);
+		int64_t temp_int64 = 2000 + (((int64_t)dT)*ms5611_dev.prom.s.c6_temp_coeff_temp)/8388608;
+
+		/* pressure calculation */
+		int64_t offset = (int64_t)ms5611_dev.prom.s.c2_pressure_offset * 65536 + ((int64_t)dT*ms5611_dev.prom.s.c4_temp_coeff_pres_offset)/128;
+		int64_t sens = (int64_t)ms5611_dev.prom.s.c1_pressure_sens * 32768 + ((int64_t)dT*ms5611_dev.prom.s.c3_temp_coeff_pres_sens)/256;
+
+		/* it's pretty cold, second order temperature compensation needed */
+		if (temp_int64 < 2000)
+		{
+			/* second order temperature compensation */
+			int64_t temp2 = (((int64_t)dT)*dT) >> 31;
+			int64_t tmp_64 = (temp_int64-2000)*(temp_int64-2000);
+			int64_t offset2 = (5*tmp_64)>>1;
+			int64_t sens2 = (5*tmp_64)>>2;
+			temp_int64 = temp_int64 - temp2;
+			offset = offset - offset2;
+			sens = sens - sens2;
+		}
+
+		int64_t press_int64 = (((ms5611_report.d1_raw*sens)/2097152-offset)/32768);
+
+		ms5611_report.temperature = temp_int64 / 100.0f;
+		ms5611_report.pressure = press_int64 / 100.0f;
+		/* convert as double for max. precision, store as float (more than enough precision) */
+		ms5611_report.altitude = (44330.0 * (1.0 - pow((press_int64 / 101325.0), 0.190295)));
+
+		/* Write back float values */
+		data[0] = ms5611_report.pressure;
+		data[1] = ms5611_report.altitude;
+		data[2] = ms5611_report.temperature;
+	}
+	else
+	{
+		/* not ready, try again */
+		ret = -EINPROGRESS;
+	}
+
+	/* return 1 if new data is available, 0 else */
+	handle_return:
+	if (ret == OK)
+	{
+		return (sizeof(ms5611_report.d1_raw) + sizeof(ms5611_report.altitude) + sizeof(ms5611_report.d2_raw));
+	}
+	else
+	{
+		errno = -ret;
+		return ret;
+	}
+}
+
+static ssize_t
+ms5611_read(struct file *filp, char *buffer, size_t buflen)
+{
+	/* if the buffer is large enough, and data are available, return success */
+	if (buflen >= 12) {
+		return read_values((float *)buffer);
+	}
+
+	/* buffer too small */
+	errno = ENOSPC;
+	return -ENOSPC;
+}
+
+static int
+ms5611_ioctl(struct file *filp, int cmd, unsigned long arg)
+{
+	return -ENOSYS;
+
+//	switch (cmd) {
+//        case MS5611_SETRATE:
+//            if ((arg & REG1_RATE_LP_MASK) == arg) {
+//                set_rate(arg);
+//                result = 0;
+//                dev.rate = arg;
+//            }
+//            break;
+//
+//        case MS5611_SETBUFFER:
+//            dev.buffer = (struct ms5611_buffer *)arg;
+//            result = 0;
+//            break;
+//	}
+//
+//	if (result)
+//		errno = EINVAL;
+//	return result;
+}
+
+
+
+int ms5611_crc4(uint16_t n_prom[])
+{
+	/* routine ported from MS5611 application note */
+	int16_t cnt;
+	uint16_t n_rem;
+	uint16_t crc_read;
+	uint8_t n_bit;
+	n_rem = 0x00;
+	/* save the read crc */
+	crc_read = n_prom[7];
+	/* remove CRC byte */
+	n_prom[7] = (0xFF00 & (n_prom[7]));
+	for (cnt = 0; cnt < 16; cnt++)
+	{
+		/* uneven bytes */
+		if (cnt & 1)
+			{
+			n_rem ^= (uint8_t) ((n_prom[cnt>>1]) & 0x00FF);
+			}
+		else
+		{
+			n_rem ^= (uint8_t) (n_prom[cnt>>1] >> 8);
+		}
+		for (n_bit = 8; n_bit > 0; n_bit--)
+		{
+			if (n_rem & 0x8000)
+			{
+				n_rem = (n_rem << 1) ^ 0x3000;
+
+			}
+			else
+			{
+				n_rem = (n_rem << 1);
+			}
+		}
+	}
+	/* final 4 bit remainder is CRC value */
+	n_rem = (0x000F & (n_rem >> 12));
+	n_prom[7] = crc_read;
+
+	/* return 0 == OK if CRCs match, 1 else */
+	return !((0x000F & crc_read) == (n_rem ^ 0x00));
+}
+
+
+int ms5611_read_prom()
+{
+	/* read PROM data */
+	uint8_t prom_buf[2] = {255,255};
+
+	int retval = 0;
+
+	for (int i = 0; i < 8; i++)
+	{
+		uint8_t cmd = {ADDR_PROM_SETUP + (i*2)};
+
+		I2C_SETADDRESS(ms5611_dev.i2c, MS5611_ADDRESS, 7);
+		retval = I2C_WRITEREAD(ms5611_dev.i2c, &cmd, 1, prom_buf, 2);
+
+		/* assemble 16 bit value and convert from big endian (sensor) to little endian (MCU) */
+		ms5611_dev.prom.c[i] = (((uint16_t)prom_buf[0])<<8) | ((uint16_t)prom_buf[1]);
+
+		if (retval != OK)
+		{
+			break;
+		}
+	}
+
+	/* calculate CRC and return error if mismatch */
+	return ms5611_crc4(ms5611_dev.prom.c);
+}
+
+int
+ms5611_attach(struct i2c_dev_s *i2c)
+{
+	int	result = ERROR;
+
+	ms5611_dev.i2c = i2c;
+
+	MS5611_ADDRESS = MS5611_ADDRESS_1;
+
+	/* write reset command */
+	uint8_t cmd_data = ADDR_RESET_CMD;
+
+	struct i2c_msg_s reset_cmd[1] = {
+			{
+					.addr   = MS5611_ADDRESS,
+					.flags  = 0,
+					.buffer = &cmd_data,
+					.length = 1
+			},
+	};
+
+	int ret = I2C_TRANSFER(ms5611_dev.i2c, reset_cmd, 1);
+
+	if (ret == OK)
+	{
+		/* wait for PROM contents to be in the device (2.8 ms) */
+		up_udelay(3000);
+
+		/* read PROM */
+		ret = ms5611_read_prom();
+	}
+
+	/* check if the address was wrong */
+	if (ret != OK)
+	{
+		/* try second address */
+		MS5611_ADDRESS = MS5611_ADDRESS_2;
+
+		/* write reset command */
+		cmd_data = ADDR_RESET_CMD;
+
+		struct i2c_msg_s reset_cmd_2[1] = {
+				{
+						.addr   = MS5611_ADDRESS,
+						.flags  = 0,
+						.buffer = &cmd_data,
+						.length = 1
+				},
+		};
+
+		ret = I2C_TRANSFER(ms5611_dev.i2c, reset_cmd_2, 1);
+
+		/* wait for PROM contents to be in the device (2.8 ms) */
+		up_udelay(3000);
+
+		/* read PROM */
+		ret = ms5611_read_prom();
+	}
+
+	if (ret < 0) return -EIO;
+
+
+	/* verify that the device is attached and functioning */
+	if (ret == OK) {
+
+		if (MS5611_ADDRESS == MS5611_ADDRESS_1)
+		{
+			printf("[ms5611 driver] Attached MS5611 at addr #1 (0x76)\n");
+		}
+		else
+		{
+			printf("[ms5611 driver] Attached MS5611 at addr #2 (0x77)\n");
+		}
+
+		/* trigger temperature read */
+		(void)read_values(NULL);
+		/* wait for conversion to complete */
+		up_udelay(9200);
+
+		/* trigger pressure read */
+		(void)read_values(NULL);
+		/* wait for conversion to complete */
+		up_udelay(9200);
+		/* now a read_values call would obtain valid results */
+
+		/* make ourselves available */
+		register_driver("/dev/ms5611", &ms5611_fops, 0666, NULL);
+
+		result = OK;
+
+	} else {
+		errno = EIO;
+	}
+
+	return result;
+}
diff --git a/nuttx/configs/px4fmu/src/drv_tone_alarm.c b/nuttx/configs/px4fmu/src/drv_tone_alarm.c
new file mode 100644
index 000000000..958a18904
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/drv_tone_alarm.c
@@ -0,0 +1,511 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Speaker driver supporting alarm sequences.
+ *
+ * Works with any of the 'generic' STM32 timers that has an output
+ * pin, does not require an interrupt.
+ *
+ * Depends on the HRT timer.
+ */
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <time.h>
+#include <queue.h>
+#include <errno.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <arch/board/board.h>
+#include <arch/board/drv_tone_alarm.h>
+#include <arch/board/up_hrt.h>
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_internal.h"
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+#ifdef CONFIG_TONE_ALARM
+# ifndef CONFIG_HRT_TIMER
+#  error CONFIG_TONE_ALARM requires CONFIG_HRT_TIMER
+# endif
+
+/* Tone alarm configuration */
+#if   TONE_ALARM_TIMER == 2
+# define TONE_ALARM_BASE		STM32_TIM2_BASE
+# define TONE_ALARM_CLOCK		STM32_APB1_TIM2_CLKIN
+# define TONE_ALARM_CLOCK_ENABLE	RCC_APB1ENR_TIM2EN
+# ifdef CONFIG_STM32_TIM2
+#  error Must not set CONFIG_STM32_TIM2 when TONE_ALARM_TIMER is 2
+# endif
+#elif TONE_ALARM_TIMER == 3
+# define TONE_ALARM_BASE		STM32_TIM3_BASE
+# define TONE_ALARM_CLOCK		STM32_APB1_TIM3_CLKIN
+# define TONE_ALARM_CLOCK_ENABLE	RCC_APB1ENR_TIM3EN
+# ifdef CONFIG_STM32_TIM3
+#  error Must not set CONFIG_STM32_TIM3 when TONE_ALARM_TIMER is 3
+# endif
+#elif TONE_ALARM_TIMER == 4
+# define TONE_ALARM_BASE		STM32_TIM4_BASE
+# define TONE_ALARM_CLOCK		STM32_APB1_TIM4_CLKIN
+# define TONE_ALARM_CLOCK_ENABLE	RCC_APB1ENR_TIM4EN
+# ifdef CONFIG_STM32_TIM4
+#  error Must not set CONFIG_STM32_TIM4 when TONE_ALARM_TIMER is 4
+# endif
+#elif TONE_ALARM_TIMER == 5
+# define TONE_ALARM_BASE		STM32_TIM5_BASE
+# define TONE_ALARM_CLOCK		STM32_APB1_TIM5_CLKIN
+# define TONE_ALARM_CLOCK_ENABLE	RCC_APB1ENR_TIM5EN
+# ifdef CONFIG_STM32_TIM5
+#  error Must not set CONFIG_STM32_TIM5 when TONE_ALARM_TIMER is 5
+# endif
+#elif TONE_ALARM_TIMER == 9
+# define TONE_ALARM_BASE		STM32_TIM9_BASE
+# define TONE_ALARM_CLOCK		STM32_APB1_TIM9_CLKIN
+# define TONE_ALARM_CLOCK_ENABLE	RCC_APB1ENR_TIM9EN
+# ifdef CONFIG_STM32_TIM9
+#  error Must not set CONFIG_STM32_TIM9 when TONE_ALARM_TIMER is 9
+# endif
+#elif TONE_ALARM_TIMER == 10
+# define TONE_ALARM_BASE		STM32_TIM10_BASE
+# define TONE_ALARM_CLOCK		STM32_APB1_TIM10_CLKIN
+# define TONE_ALARM_CLOCK_ENABLE	RCC_APB1ENR_TIM10EN
+# ifdef CONFIG_STM32_TIM10
+#  error Must not set CONFIG_STM32_TIM10 when TONE_ALARM_TIMER is 10
+# endif
+#elif TONE_ALARM_TIMER == 11
+# define TONE_ALARM_BASE		STM32_TIM11_BASE
+# define TONE_ALARM_CLOCK		STM32_APB1_TIM11_CLKIN
+# define TONE_ALARM_CLOCK_ENABLE	RCC_APB1ENR_TIM11EN
+# ifdef CONFIG_STM32_TIM11
+#  error Must not set CONFIG_STM32_TIM11 when TONE_ALARM_TIMER is 11
+# endif
+#else
+# error Must set TONE_ALARM_TIMER to a generic timer if CONFIG_TONE_ALARM is set
+#endif
+
+#if TONE_ALARM_CHANNEL == 1
+# define TONE_CCMR1	(3 << 4)
+# define TONE_CCMR2	0
+# define TONE_CCER	(1 << 0)
+# define TONE_rCCR	rCCR1
+#elif TONE_ALARM_CHANNEL == 2
+# define TONE_CCMR1	(3 << 12)
+# define TONE_CCMR2	0
+# define TONE_CCER	(1 << 4)
+# define TONE_rCCR	rCCR2
+#elif TONE_ALARM_CHANNEL == 3
+# define TONE_CCMR1	0
+# define TONE_CCMR2	(3 << 4)
+# define TONE_CCER	(1 << 8)
+# define TONE_rCCR	rCCR3
+#elif TONE_ALARM_CHANNEL == 4
+# define TONE_CCMR1	0
+# define TONE_CCMR2	(3 << 12)
+# define TONE_CCER	(1 << 12)
+# define TONE_rCCR	rCCR4
+#else
+# error Must set TONE_ALARM_CHANNEL to a value between 1 and 4
+#endif
+
+/*
+ * Timer register accessors
+ */
+#define REG(_reg)	(*(volatile uint32_t *)(TONE_ALARM_BASE + _reg))
+
+#define rCR1     	REG(STM32_GTIM_CR1_OFFSET)
+#define rCR2     	REG(STM32_GTIM_CR2_OFFSET)
+#define rSMCR    	REG(STM32_GTIM_SMCR_OFFSET)
+#define rDIER    	REG(STM32_GTIM_DIER_OFFSET)
+#define rSR      	REG(STM32_GTIM_SR_OFFSET)
+#define rEGR     	REG(STM32_GTIM_EGR_OFFSET)
+#define rCCMR1   	REG(STM32_GTIM_CCMR1_OFFSET)
+#define rCCMR2   	REG(STM32_GTIM_CCMR2_OFFSET)
+#define rCCER    	REG(STM32_GTIM_CCER_OFFSET)
+#define rCNT     	REG(STM32_GTIM_CNT_OFFSET)
+#define rPSC     	REG(STM32_GTIM_PSC_OFFSET)
+#define rARR     	REG(STM32_GTIM_ARR_OFFSET)
+#define rCCR1    	REG(STM32_GTIM_CCR1_OFFSET)
+#define rCCR2    	REG(STM32_GTIM_CCR2_OFFSET)
+#define rCCR3    	REG(STM32_GTIM_CCR3_OFFSET)
+#define rCCR4    	REG(STM32_GTIM_CCR4_OFFSET)
+#define rDCR     	REG(STM32_GTIM_DCR_OFFSET)
+#define rDMAR    	REG(STM32_GTIM_DMAR_OFFSET)
+
+#define TONE_MAX_PATTERN	6
+#define TONE_MAX_PATTERN_LEN	40
+
+/* predefined patterns for alarms 1-TONE_MAX_PATTERN */
+const struct tone_note patterns[TONE_MAX_PATTERN][TONE_MAX_PATTERN_LEN] = {
+	{
+		{TONE_NOTE_A7, 12},
+		{TONE_NOTE_D8, 12},
+		{TONE_NOTE_C8, 12},
+		{TONE_NOTE_A7, 12},
+		{TONE_NOTE_D8, 12},
+		{TONE_NOTE_C8, 12},
+		{TONE_NOTE_D8, 4},
+		{TONE_NOTE_C8, 4},
+		{TONE_NOTE_D8, 4},
+		{TONE_NOTE_C8, 4},
+		{TONE_NOTE_D8, 4},
+		{TONE_NOTE_C8, 4},
+	},
+	{{TONE_NOTE_B6, 100}},
+	{{TONE_NOTE_C7, 100}},
+	{{TONE_NOTE_D7, 100}},
+	{{TONE_NOTE_E7, 100}},
+	{	//This is tetris ;)
+		{TONE_NOTE_C6, 40},
+		{TONE_NOTE_G5, 20},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_A5S, 40},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_G5, 20},
+		{TONE_NOTE_F5, 40},
+		{TONE_NOTE_F5, 20},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_C6, 40},
+		{TONE_NOTE_A5S, 20},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_G5, 60},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_A5S, 40},
+		{TONE_NOTE_C6, 40},
+		{TONE_NOTE_G5S, 40},
+		{TONE_NOTE_F5, 40},
+		{TONE_NOTE_F5, 60},
+
+		{TONE_NOTE_A5S, 40},
+		{TONE_NOTE_C6S, 20},
+		{TONE_NOTE_F6, 40},
+		{TONE_NOTE_D6S, 20},
+		{TONE_NOTE_C6S, 20},
+		{TONE_NOTE_C6, 60},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_C6, 40},
+		{TONE_NOTE_A5S, 20},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_G5, 40},
+		{TONE_NOTE_G5, 20},
+		{TONE_NOTE_G5S, 20},
+		{TONE_NOTE_A5S, 40},
+		{TONE_NOTE_C6, 40},
+		{TONE_NOTE_G5S, 40},
+		{TONE_NOTE_F5, 40},
+		{TONE_NOTE_F5, 60},
+	}
+};
+
+static uint16_t notes[TONE_NOTE_MAX] = {
+	63707, /* E4 */
+	60132, /* F4 */
+	56758, /* F#4/Gb4 */
+	53571, /* G4 */
+	50565, /* G#4/Ab4 */
+	47727, /* A4 */
+	45048, /* A#4/Bb4 */
+	42520, /* B4 */
+	40133, /* C5 */
+	37880, /* C#5/Db5 */
+	35755, /* D5 */
+	33748, /* D#5/Eb5 */
+	31853, /* E5 */
+	30066, /* F5 */
+	28378, /* F#5/Gb5 */
+	26786, /* G5 */
+	25282, /* G#5/Ab5 */
+	23863, /* A5 */
+	22524, /* A#5/Bb5 */
+	21260, /* B5 */
+	20066, /* C6 */
+	18940, /* C#6/Db6 */
+	17877, /* D6 */
+	16874, /* D#6/Eb6 */
+	15927, /* E6 */
+	15033, /* F6 */
+	14189, /* F#6/Gb6 */
+	13393, /* G6 */
+	12641, /* G#6/Ab6 */
+	11931, /* A6 */
+	11262, /* A#6/Bb6 */
+	10630, /* B6 */
+	10033, /* C7 */
+	9470, /* C#7/Db7 */
+	8938, /* D7 */
+	8437, /* D#7/Eb7 */
+	7963, /* E7 */
+	7516, /* F7 */
+	7094, /* F#7/Gb7 */
+	6696, /* G7 */
+	6320, /* G#7/Ab7 */
+	5965, /* A7 */
+	5631, /* A#7/Bb7 */
+	5315, /* B7 */
+	5016, /* C8 */
+	4735, /* C#8/Db8 */
+	4469, /* D8 */
+	4218  /* D#8/Eb8 */
+};
+
+/* current state of the tone driver */
+struct state {
+	int		pattern;				/* current pattern */
+#define PATTERN_NONE	-1
+#define PATTERN_USER	0
+	int		note;					/* next note to play */
+	struct hrt_call	note_end;
+	struct tone_note user_pattern[TONE_MAX_PATTERN_LEN];	/* user-supplied pattern (plays at pattern 0) */
+};
+
+static struct state tone_state;
+
+static int	tone_write(struct file *filp, const char *buffer, size_t len);
+static int	tone_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+static const struct file_operations tone_fops = {
+	.write = tone_write,
+	.ioctl = tone_ioctl
+};
+
+static void	tone_next(void);
+static bool	tone_ok(struct tone_note *pattern);
+int
+tone_alarm_init(void)
+{
+	/* configure the GPIO */
+	stm32_configgpio(GPIO_TONE_ALARM);
+
+	/* clock/power on our timer */
+        modifyreg32(STM32_RCC_APB1ENR, 0, TONE_ALARM_CLOCK_ENABLE);
+
+	/* default the state */
+	tone_state.pattern = -1;
+
+	/* initialise the timer */
+        rCR1 = 0;
+        rCR2 = 0;
+        rSMCR = 0;
+        rDIER = 0;
+        rCCER = 0;		/* unlock CCMR* registers */
+        rCCMR1 = TONE_CCMR1;
+        rCCMR2 = TONE_CCMR2;
+        rCCER = TONE_CCER;
+        rDCR = 0;
+
+        /* toggle the CC output each time the count passes 1 */
+        TONE_rCCR = 1;
+
+        /* 
+         * Configure the timebase to free-run at half max frequency.
+         * XXX this should be more flexible in order to get a better
+         * frequency range, but for the F4 with the APB1 timers based
+         * at 42MHz, this gets us down to ~320Hz or so.
+         */
+        rPSC = 1;
+
+        tone_state.pattern = PATTERN_NONE;
+        tone_state.note = 0;
+
+	/* play the startup tune */
+    tone_ioctl(NULL, TONE_SET_ALARM, 1);
+
+	/* register the device */
+	return register_driver("/dev/tone_alarm", &tone_fops, 0666, NULL);
+}
+
+static int
+tone_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+	int result = 0;
+	int new = (int)arg;
+
+	irqstate_t flags = irqsave();
+
+	/* decide whether to increase the alarm level to cmd or leave it alone */
+	switch (cmd) {
+	case TONE_SET_ALARM:
+		if (new == 0) {
+			/* cancel any current alarm */
+			tone_state.pattern = PATTERN_NONE;
+			tone_next();
+
+		} else if (new > TONE_MAX_PATTERN) {
+
+			/* not a legal alarm value */
+			result = -ERANGE;
+
+		} else if (new > tone_state.pattern) {
+
+			/* higher priority than the current alarm */
+			tone_state.pattern = new;
+			tone_state.note = 0;
+
+			/* and start playing it */
+			tone_next();
+		}
+		break;
+	default:
+		result = -EINVAL;
+		break;
+	}
+
+	irqrestore(flags);
+	return result;
+}
+
+static int
+tone_write(struct file *filp, const char *buffer, size_t len)
+{
+	irqstate_t flags;
+
+	/* sanity-check the size of the write */
+	if (len > (TONE_MAX_PATTERN_LEN * sizeof(struct tone_note)))
+		return -EFBIG;
+	if ((len % sizeof(struct tone_note)) || (len == 0))
+		return -EIO;
+	if (!tone_ok((struct tone_note *)buffer))
+		return -EIO;
+
+	flags = irqsave();
+
+	/* if we aren't playing an alarm tone */
+	if (tone_state.pattern <= PATTERN_USER) {
+
+		/* reset the tone state to play the new user pattern */
+		tone_state.pattern = PATTERN_USER;
+		tone_state.note = 0;
+
+		/* copy in the new pattern */
+		memset(tone_state.user_pattern, 0, sizeof(tone_state.user_pattern));
+		memcpy(tone_state.user_pattern, buffer, len);
+
+		/* and start it */
+		tone_next();
+	}
+	irqrestore(flags);
+
+	return len;
+}
+
+static void
+tone_next(void)
+{
+	const struct tone_note *np;
+
+	/* stop the current note */
+	rCR1 = 0;
+
+	/* if we are no longer playing a pattern, we have nothing else to do here */
+	if (tone_state.pattern == PATTERN_NONE) {
+		return;
+	}
+
+	/* if the current pattern has ended, clear the pattern and stop */
+	if (tone_state.note == TONE_NOTE_MAX) {
+		tone_state.pattern = PATTERN_NONE;
+		return;
+	}
+
+	/* find the note to play */
+	if (tone_state.pattern == PATTERN_USER) {
+		np = &tone_state.user_pattern[tone_state.note];
+	} else {
+		np = &patterns[tone_state.pattern - 1][tone_state.note];
+	}
+
+	/* work out which note is next */
+	tone_state.note++;
+	if (tone_state.note >= TONE_NOTE_MAX) {
+		/* hit the end of the pattern, stop */
+		tone_state.pattern = PATTERN_NONE;
+	} else if (np[1].duration == DURATION_END) {
+		/* hit the end of the pattern, stop */
+		tone_state.pattern = PATTERN_NONE;
+	} else if (np[1].duration == DURATION_REPEAT) {
+		/* next note is a repeat, rewind in preparation */
+		tone_state.note = 0;
+	}
+
+	/* set the timer to play the note, if required */
+	if (np->pitch <= TONE_NOTE_SILENCE) {
+
+		/* set reload based on the pitch */
+		rARR = notes[np->pitch];
+
+	        /* force an update, reloads the counter and all registers */
+	        rEGR = GTIM_EGR_UG;
+
+	        /* start the timer */
+	        rCR1 = GTIM_CR1_CEN;
+	}
+
+	/* arrange a callback when the note/rest is done */
+	hrt_call_after(&tone_state.note_end, (hrt_abstime)10000 * np->duration, (hrt_callout)tone_next, NULL);
+
+}
+
+static bool
+tone_ok(struct tone_note *pattern)
+{
+	int	i;
+
+	for (i = 0; i < TONE_NOTE_MAX; i++) {
+
+		/* first note must not be repeat or end */
+		if ((i == 0) &&
+		    ((pattern[i].duration == DURATION_END) || (pattern[i].duration == DURATION_REPEAT)))
+			return false;
+		if (pattern[i].duration == DURATION_END)
+			break;
+
+		/* pitch must be legal */
+		if (pattern[i].pitch >= TONE_NOTE_MAX)
+			return false;
+	}
+	return true;
+}
+
+#endif /* CONFIG_TONE_ALARM */
\ No newline at end of file
diff --git a/nuttx/configs/px4fmu/src/px4fmu-internal.h b/nuttx/configs/px4fmu/src/px4fmu-internal.h
new file mode 100644
index 000000000..f48b1bf5e
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/px4fmu-internal.h
@@ -0,0 +1,166 @@
+/****************************************************************************************************
+ * configs/px4fmu/src/px4fmu_internal.h
+ * arch/arm/src/board/px4fmu_internal.n
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __CONFIGS_PX4FMU_SRC_PX4FMU_INTERNAL_H
+#define __CONFIGS_PX4FMU_SRC_PX4FMU_INTERNAL_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+/****************************************************************************************************
+ * Definitions
+ ****************************************************************************************************/
+/* Configuration ************************************************************************************/
+
+#ifdef CONFIG_STM32_SPI2
+#  error "SPI2 is not supported on this board"
+#endif
+
+#if defined(CONFIG_STM32_CAN1)
+#  warning "CAN1 is not supported on this board"
+#endif
+
+/* PX4FMU GPIOs ***********************************************************************************/
+/* LEDs */
+
+#define GPIO_LED1		(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_LED2		(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN14)
+
+/* External interrupts */
+#define GPIO_EXTI_COMPASS	(GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN1)
+// XXX MPU6000 DRDY?
+
+/* SPI chip selects */
+#define GPIO_SPI_CS_GYRO	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN14)
+#define GPIO_SPI_CS_ACCEL	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN15)
+#define GPIO_SPI_CS_MPU		(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_SPI_CS_SDCARD	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4)
+
+/* User GPIOs
+ *
+ * GPIO0-1 are the buffered high-power GPIOs.
+ * GPIO2-5 are the USART2 pins.
+ * GPIO6-7 are the CAN2 pins.
+ */
+#define GPIO_GPIO0_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_GPIO1_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_GPIO2_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_GPIO3_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_GPIO4_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_GPIO5_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_GPIO6_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_GPIO7_INPUT	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_GPIO0_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_GPIO1_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_GPIO2_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_GPIO3_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_GPIO4_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_GPIO5_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_GPIO6_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_GPIO7_OUTPUT	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_GPIO_DIR		(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13)
+
+/* USB OTG FS
+ *
+ * PA9  OTG_FS_VBUS VBUS sensing (also connected to the green LED)
+ */
+#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+
+/* PWM
+ *
+ * The PX4FMU has five PWM outputs, of which only the output on
+ * pin PC8 is fixed assigned to this function. The other four possible
+ * pwm sources are the TX, RX, RTS and CTS pins of USART2
+ *
+ * Alternate function mapping:
+ * PC8 - BUZZER - TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2
+ */
+
+#ifdef CONFIG_PWM
+#  if defined(CONFIG_STM32_TIM3_PWM)
+#    define BUZZER_PWMCHANNEL 3
+#	 define BUZZER_PWMTIMER 3
+#  elif defined(CONFIG_STM32_TIM8_PWM)
+#    define BUZZER_PWMCHANNEL 3
+#    define BUZZER_PWMTIMER 8
+#  endif
+#endif
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ****************************************************************************************************/
+
+extern void stm32_spiinitialize(void);
+
+/****************************************************************************************************
+ * Name: px4fmu_gpio_init
+ *
+ * Description:
+ *   Called to configure the PX4FMU user GPIOs
+ *
+ ****************************************************************************************************/
+
+extern void px4fmu_gpio_init(void);
+
+
+// XXX additional SPI chipselect functions required?
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_PX4FMU_SRC_PX4FMU_INTERNAL_H */
+
diff --git a/nuttx/configs/px4fmu/src/up_adc.c b/nuttx/configs/px4fmu/src/up_adc.c
new file mode 100644
index 000000000..2d74e6f00
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_adc.c
@@ -0,0 +1,173 @@
+/************************************************************************************
+ * configs/stm3240g-eval/src/up_adc.c
+ * arch/arm/src/board/up_adc.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+#include <stdio.h>
+
+#include <nuttx/analog/adc.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+//#include "stm32_pwm.h"
+#include "stm32_adc.h"
+#include "px4fmu-internal.h"
+
+#ifdef CONFIG_ADC
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Configuration ************************************************************/
+/* Up to 3 ADC interfaces are supported */
+
+#if STM32_NADC < 3
+#  undef CONFIG_STM32_ADC3
+#endif
+
+#if STM32_NADC < 2
+#  undef CONFIG_STM32_ADC2
+#endif
+
+#if STM32_NADC < 1
+#  undef CONFIG_STM32_ADC3
+#endif
+
+#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3)
+#ifndef CONFIG_STM32_ADC3
+#  warning "Channel information only available for ADC3"
+#endif
+
+#define ADC3_NCHANNELS 4
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+/* The PX4FMU board has four ADC channels: ADC323 IN10-13
+ */
+
+/* Identifying number of each ADC channel: Variable Resistor. */
+
+#ifdef CONFIG_STM32_ADC3
+static const uint8_t  g_chanlist[ADC3_NCHANNELS] = {10, 11};// , 12, 13}; ADC12 and 13 are used by MPU on v1.5 boards
+
+/* Configurations of pins used byte each ADC channels */
+static const uint32_t g_pinlist[ADC3_NCHANNELS]  = {GPIO_ADC3_IN10, GPIO_ADC3_IN11}; // ADC12 and 13 are used by MPU on v1.5 boards, GPIO_ADC3_IN12, GPIO_ADC3_IN13};
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: adc_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/adc.
+ *
+ ************************************************************************************/
+
+int adc_devinit(void)
+{
+#ifdef CONFIG_STM32_ADC3
+	static bool initialized = false;
+	struct adc_dev_s *adc[ADC3_NCHANNELS];
+	int ret;
+	int i;
+
+	/* Check if we have already initialized */
+
+	if (!initialized)
+	{
+		char name[11];
+
+		for (i = 0; i < ADC3_NCHANNELS; i++)
+		{
+		stm32_configgpio(g_pinlist[i]);
+		}
+
+		for (i = 0; i < 1; i++)
+		{
+			/* Configure the pins as analog inputs for the selected channels */
+			//stm32_configgpio(g_pinlist[i]);
+
+			/* Call stm32_adcinitialize() to get an instance of the ADC interface */
+			//multiple channels only supported with dma!
+			adc[i] = stm32_adcinitialize(3, (g_chanlist), 4);
+			if (adc == NULL)
+			{
+				adbg("ERROR: Failed to get ADC interface\n");
+				return -ENODEV;
+			}
+
+
+			/* Register the ADC driver at "/dev/adc0" */
+			sprintf(name, "/dev/adc%d", i);
+			ret = adc_register(name, adc[i]);
+			if (ret < 0)
+			{
+				adbg("adc_register failed for adc %s: %d\n", name, ret);
+				return ret;
+			}
+		}
+
+		/* Now we are initialized */
+
+		initialized = true;
+	}
+
+	return OK;
+#else
+	return -ENOSYS;
+#endif
+}
+
+#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */
+#endif /* CONFIG_ADC */
diff --git a/nuttx/configs/px4fmu/src/up_boot.c b/nuttx/configs/px4fmu/src/up_boot.c
new file mode 100644
index 000000000..da396cdd6
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_boot.c
@@ -0,0 +1,76 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "px4fmu-internal.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the intitialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32_boardinitialize(void)
+{
+	/* configure SPI interfaces */
+	stm32_spiinitialize();
+
+	/* configure LEDs */
+	up_ledinit();
+}
diff --git a/nuttx/configs/px4fmu/src/up_can.c b/nuttx/configs/px4fmu/src/up_can.c
new file mode 100644
index 000000000..daf6484f2
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_can.c
@@ -0,0 +1,142 @@
+/************************************************************************************
+ * configs/px4fmu/src/up_can.c
+ * arch/arm/src/board/up_can.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "stm32.h"
+#include "stm32_can.h"
+#include "px4fmu-internal.h"
+
+#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2))
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
+#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#  undef CONFIG_STM32_CAN2
+#endif
+
+#ifdef CONFIG_STM32_CAN1
+#  define CAN_PORT 1
+#else
+#  define CAN_PORT 2
+#endif
+
+/* Debug ***************************************************************************/
+/* Non-standard debug that may be enabled just for testing CAN */
+
+#ifdef CONFIG_DEBUG_CAN
+#  define candbg    dbg
+#  define canvdbg   vdbg
+#  define canlldbg  lldbg
+#  define canllvdbg llvdbg
+#else
+#  define candbg(x...)
+#  define canvdbg(x...)
+#  define canlldbg(x...)
+#  define canllvdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: can_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/can.
+ *
+ ************************************************************************************/
+
+int can_devinit(void)
+{
+  static bool initialized = false;
+  struct can_dev_s *can;
+  int ret;
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+      /* Call stm32_caninitialize() to get an instance of the CAN interface */
+
+      can = stm32_caninitialize(CAN_PORT);
+      if (can == NULL)
+        {
+          candbg("ERROR:  Failed to get CAN interface\n");
+          return -ENODEV;
+        }
+
+      /* Register the CAN driver at "/dev/can0" */
+
+      ret = can_register("/dev/can0", can);
+      if (ret < 0)
+        {
+          candbg("ERROR: can_register failed: %d\n", ret);
+          return ret;
+        }
+
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+}
+
+#endif /* CONFIG_STM32_CAN || CONFIG_STM32_CAN2 || CONFIG_STM32_CAN3 */
diff --git a/nuttx/configs/px4fmu/src/up_cpuload.c b/nuttx/configs/px4fmu/src/up_cpuload.c
new file mode 100644
index 000000000..750ec4852
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_cpuload.c
@@ -0,0 +1,182 @@
+/****************************************************************************
+ * configs/px4fmu/src/up_leds.c
+ * arch/arm/src/board/up_leds.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <sys/time.h>
+
+#include <arch/board/board.h>
+#include <arch/board/up_hrt.h>
+#include <arch/board/up_cpuload.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name:
+ ****************************************************************************/
+
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+
+struct system_load_s system_load;
+
+extern FAR _TCB *sched_gettcb(pid_t pid);
+
+void cpuload_initialize_once(void);
+
+void cpuload_initialize_once()
+{
+//	if (!system_load.initialized)
+//	{
+		system_load.start_time = hrt_absolute_time();
+		int i;
+		for (i = 0; i < CONFIG_MAX_TASKS; i++)
+		{
+			system_load.tasks[i].valid = false;
+		}
+		system_load.total_count = 0;
+
+		uint64_t now = hrt_absolute_time();
+
+		/* initialize idle thread statically */
+		system_load.tasks[0].start_time = now;
+		system_load.tasks[0].total_runtime = 0;
+		system_load.tasks[0].curr_start_time = 0;
+		system_load.tasks[0].tcb = sched_gettcb(0);
+		system_load.tasks[0].valid = true;
+		system_load.total_count++;
+
+		/* initialize init thread statically */
+		system_load.tasks[1].start_time = now;
+		system_load.tasks[1].total_runtime = 0;
+		system_load.tasks[1].curr_start_time = 0;
+		system_load.tasks[1].tcb = sched_gettcb(1);
+		system_load.tasks[1].valid = true;
+		/* count init thread */
+		system_load.total_count++;
+		//	}
+}
+
+void sched_note_start(FAR _TCB *tcb )
+{
+	/* search first free slot */
+	int i;
+	for (i = 1; i < CONFIG_MAX_TASKS; i++)
+	{
+		if (!system_load.tasks[i].valid)
+		{
+			/* slot is available */
+			system_load.tasks[i].start_time = hrt_absolute_time();
+			system_load.tasks[i].total_runtime = 0;
+			system_load.tasks[i].curr_start_time = 0;
+			system_load.tasks[i].tcb = tcb;
+			system_load.tasks[i].valid = true;
+			system_load.total_count++;
+			break;
+		}
+	}
+}
+
+void sched_note_stop(FAR _TCB *tcb )
+{
+	int i;
+	for (i = 1; i < CONFIG_MAX_TASKS; i++)
+	{
+		if (system_load.tasks[i].tcb->pid == tcb->pid)
+		{
+			/* mark slot as fee */
+			system_load.tasks[i].valid = false;
+			system_load.tasks[i].total_runtime = 0;
+			system_load.tasks[i].curr_start_time = 0;
+			system_load.tasks[i].tcb = NULL;
+			system_load.total_count--;
+			break;
+		}
+	}
+}
+
+void sched_note_switch(FAR _TCB *pFromTcb, FAR _TCB *pToTcb)
+{
+	uint64_t new_time = hrt_absolute_time();
+
+	/* Kind of inefficient: find both tasks and update times */
+	uint8_t both_found = 0;
+	for (int i = 0; i < CONFIG_MAX_TASKS; i++)
+	{
+		/* Task ending its current scheduling run */
+		if (system_load.tasks[i].tcb->pid == pFromTcb->pid)
+		{
+			//if (system_load.tasks[i].curr_start_time != 0)
+			{
+				system_load.tasks[i].total_runtime += new_time - system_load.tasks[i].curr_start_time;
+			}
+			both_found++;
+		}
+		else if (system_load.tasks[i].tcb->pid == pToTcb->pid)
+		{
+			system_load.tasks[i].curr_start_time = new_time;
+			both_found++;
+		}
+
+		/* Do only iterate as long as needed */
+		if (both_found == 2)
+		{
+			break;
+		}
+	}
+}
+
+#endif /* CONFIG_SCHED_INSTRUMENTATION */
diff --git a/nuttx/configs/px4fmu/src/up_hrt.c b/nuttx/configs/px4fmu/src/up_hrt.c
new file mode 100644
index 000000000..35aecfe08
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_hrt.c
@@ -0,0 +1,801 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file High-resolution timer callouts and timekeeping.
+ *
+ * This can use any general or advanced STM32 timer.
+ *
+ * Note that really, this could use systick too, but that's
+ * monopolised by NuttX and stealing it would just be awkward.
+ *
+ * We don't use the NuttX STM32 driver per se; rather, we 
+ * claim the timer and then drive it directly.
+ */
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <time.h>
+#include <queue.h>
+#include <errno.h>
+#include <string.h>
+
+#include <arch/board/board.h>
+#include <arch/board/up_hrt.h>
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_internal.h"
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+#ifdef CONFIG_HRT_TIMER
+
+/* HRT configuration */
+#if   HRT_TIMER == 1
+# define HRT_TIMER_BASE		STM32_TIM1_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB2ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM1EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1CC
+# define HRT_TIMER_CLOCK	STM32_APB2_TIM1_CLKIN
+# if CONFIG_STM32_TIM1
+#  error must not set CONFIG_STM32_TIM1=y and HRT_TIMER=1
+# endif
+#elif HRT_TIMER == 2
+# define HRT_TIMER_BASE		STM32_TIM2_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM2EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM2
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM2_CLKIN
+# if CONFIG_STM32_TIM2
+#  error must not set CONFIG_STM32_TIM2=y and HRT_TIMER=2
+# endif
+#elif HRT_TIMER == 3
+# define HRT_TIMER_BASE		STM32_TIM3_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM3EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM3
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM3_CLKIN
+# if CONFIG_STM32_TIM3
+#  error must not set CONFIG_STM32_TIM3=y and HRT_TIMER=3
+# endif
+#elif HRT_TIMER == 4
+# define HRT_TIMER_BASE		STM32_TIM4_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM4EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM4
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM4_CLKIN
+# if CONFIG_STM32_TIM4
+#  error must not set CONFIG_STM32_TIM4=y and HRT_TIMER=4
+# endif
+#elif HRT_TIMER == 5
+# define HRT_TIMER_BASE		STM32_TIM5_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM5EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM5
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM5_CLKIN
+# if CONFIG_STM32_TIM5
+#  error must not set CONFIG_STM32_TIM5=y and HRT_TIMER=5
+# endif
+#elif HRT_TIMER == 8
+# define HRT_TIMER_BASE		STM32_TIM8_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB2ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM8EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM8CC
+# define HRT_TIMER_CLOCK	STM32_APB2_TIM8_CLKIN
+# if CONFIG_STM32_TIM8
+#  error must not set CONFIG_STM32_TIM8=y and HRT_TIMER=6
+# endif
+#elif HRT_TIMER == 9
+# define HRT_TIMER_BASE		STM32_TIM9_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM9EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1BRK
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM9_CLKIN
+# if CONFIG_STM32_TIM9
+#  error must not set CONFIG_STM32_TIM9=y and HRT_TIMER=9
+# endif
+#elif HRT_TIMER == 10
+# define HRT_TIMER_BASE		STM32_TIM10_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM10EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1UP
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM10_CLKIN
+# if CONFIG_STM32_TIM10
+#  error must not set CONFIG_STM32_TIM11=y and HRT_TIMER=10
+# endif
+#elif HRT_TIMER == 11
+# define HRT_TIMER_BASE		STM32_TIM11_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM11EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1TRGCOM
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM11_CLKIN
+# if CONFIG_STM32_TIM11
+#  error must not set CONFIG_STM32_TIM11=y and HRT_TIMER=11
+# endif
+#else
+# error HRT_TIMER must be set in board.h if CONFIG_HRT_TIMER=y
+#endif
+
+/*
+ * HRT clock must be a multiple of 1MHz greater than 1MHz
+ */
+#if (HRT_TIMER_CLOCK % 1000000) != 0
+# error HRT_TIMER_CLOCK must be a multiple of 1MHz
+#endif
+#if HRT_TIMER_CLOCK <= 1000000
+# error HRT_TIMER_CLOCK must be greater than 1MHz
+#endif
+
+/*
+ * Minimum/maximum deadlines.
+ *
+ * These are suitable for use with a 16-bit timer/counter clocked
+ * at 1MHz.  The high-resolution timer need only guarantee that it
+ * not wrap more than once in the 50ms period for absolute time to
+ * be consistently maintained.
+ *
+ * The minimum deadline must be such that the time taken between
+ * reading a time and writing a deadline to the timer cannot
+ * result in missing the deadline.
+ */
+#define HRT_INTERVAL_MIN	50
+#define HRT_INTERVAL_MAX	50000
+
+/*
+ * Period of the free-running counter, in microseconds.
+ */
+#define HRT_COUNTER_PERIOD	65536
+
+/*
+ * Scaling factor(s) for the free-running counter; convert an input
+ * in counts to a time in microseconds.
+ */
+#define HRT_COUNTER_SCALE(_c)	(_c)
+
+/*
+ * Timer register accessors
+ */
+#define REG(_reg)	(*(volatile uint32_t *)(HRT_TIMER_BASE + _reg))
+
+#define rCR1     	REG(STM32_GTIM_CR1_OFFSET)
+#define rCR2     	REG(STM32_GTIM_CR2_OFFSET)
+#define rSMCR    	REG(STM32_GTIM_SMCR_OFFSET)
+#define rDIER    	REG(STM32_GTIM_DIER_OFFSET)
+#define rSR      	REG(STM32_GTIM_SR_OFFSET)
+#define rEGR     	REG(STM32_GTIM_EGR_OFFSET)
+#define rCCMR1   	REG(STM32_GTIM_CCMR1_OFFSET)
+#define rCCMR2   	REG(STM32_GTIM_CCMR2_OFFSET)
+#define rCCER    	REG(STM32_GTIM_CCER_OFFSET)
+#define rCNT     	REG(STM32_GTIM_CNT_OFFSET)
+#define rPSC     	REG(STM32_GTIM_PSC_OFFSET)
+#define rARR     	REG(STM32_GTIM_ARR_OFFSET)
+#define rCCR1    	REG(STM32_GTIM_CCR1_OFFSET)
+#define rCCR2    	REG(STM32_GTIM_CCR2_OFFSET)
+#define rCCR3    	REG(STM32_GTIM_CCR3_OFFSET)
+#define rCCR4    	REG(STM32_GTIM_CCR4_OFFSET)
+#define rDCR     	REG(STM32_GTIM_DCR_OFFSET)
+#define rDMAR    	REG(STM32_GTIM_DMAR_OFFSET)
+
+/*
+ * Specific registers and bits used by HRT sub-functions
+ */
+#if HRT_TIMER_CHANNEL == 1
+# define rCCR_HRT	rCCR1			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC1IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC1IF		/* interrupt status for HRT */
+#elif HRT_TIMER_CHANNEL == 2
+# define rCCR_HRT	rCCR2			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC2IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC2IF		/* interrupt status for HRT */
+#elif HRT_TIMER_CHANNEL == 3
+# define rCCR_HRT	rCCR3			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC3IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC3IF		/* interrupt status for HRT */
+#elif HRT_TIMER_CHANNEL == 4
+# define rCCR_HRT	rCCR4			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC4IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC4IF		/* interrupt status for HRT */
+#else
+# error HRT_TIMER_CHANNEL must be a value between 1 and 4
+#endif
+
+/*
+ * Queue of callout entries.
+ */
+static struct sq_queue_s	callout_queue;
+
+/* timer-specific functions */
+static void		hrt_tim_init(void);
+static int		hrt_tim_isr(int irq, void *context);
+
+/* callout list manipulation */
+static void		hrt_call_internal(struct hrt_call *entry,
+					  hrt_abstime deadline,
+					  hrt_abstime interval,
+					  hrt_callout callout,
+					  void *arg);
+static void		hrt_call_enter(struct hrt_call *entry);
+static void		hrt_call_reschedule(void);
+static void		hrt_call_invoke(void);
+
+/*
+ * Specific registers and bits used by PPM sub-functions
+ */
+#ifdef CONFIG_HRT_PPM
+# if HRT_PPM_CHANNEL == 1
+#  define rCCR_PPM	rCCR1			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC1IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC1IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC1OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	1			/* not on TI1/TI2 */
+#  define CCMR2_PPM	0			/* on TI3, not on TI4 */
+#  define CCER_PPM	(GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP) /* CC1, both edges */
+# elif HRT_PPM_CHANNEL == 2
+#  define rCCR_PPM	rCCR2			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC2IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC2IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC2OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	2			/* not on TI1/TI2 */
+#  define CCMR2_PPM	0			/* on TI3, not on TI4 */
+#  define CCER_PPM	(GTIM_CCER_CC2E | GTIM_CCER_CC2P | GTIM_CCER_CC2NP) /* CC2, both edges */
+# elif HRT_PPM_CHANNEL == 3
+#  define rCCR_PPM	rCCR3			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC3IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC3IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC3OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	0			/* not on TI1/TI2 */
+#  define CCMR2_PPM	1			/* on TI3, not on TI4 */
+#  define CCER_PPM	(GTIM_CCER_CC3E | GTIM_CCER_CC3P | GTIM_CCER_CC3NP) /* CC3, both edges */
+# elif HRT_PPM_CHANNEL == 4
+#  define rCCR_PPM	rCCR4			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC4IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC4IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC4OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	0			/* not on TI1/TI2 */
+#  define CCMR2_PPM	2			/* on TI3, not on TI4 */
+#  define CCER_PPM	(GTIM_CCER_CC4E | GTIM_CCER_CC4P | GTIM_CCER_CC4NP) /* CC4, both edges */
+# else
+#  error HRT_PPM_CHANNEL must be a value between 1 and 4 if CONFIG_HRT_PPM is set
+# endif
+
+/*
+ * PPM decoder tuning parameters
+ */
+# define PPM_MAX_PULSE_WIDTH	500		/* maximum width of a pulse */
+# define PPM_MIN_CHANNEL_VALUE	750		/* shortest valid channel signal */
+# define PPM_MAX_CHANNEL_VALUE	2400		/* longest valid channel signal */
+# define PPM_MIN_START		5000		/* shortest valid start gap */
+
+/* decoded PPM buffer */
+#define PPM_MAX_CHANNELS	12
+uint16_t ppm_buffer[PPM_MAX_CHANNELS];
+unsigned ppm_decoded_channels;
+
+/* PPM edge history */
+uint16_t ppm_edge_history[32];
+unsigned ppm_edge_next;
+
+/* PPM pulse history */
+uint16_t ppm_pulse_history[32];
+unsigned ppm_pulse_next;
+
+static uint16_t ppm_temp_buffer[PPM_MAX_CHANNELS];
+
+/* PPM decoder state machine */
+struct {
+	uint16_t	last_edge;	/* last capture time */
+	uint16_t	last_mark;	/* last significant edge */
+	unsigned	next_channel;
+	enum {
+		UNSYNCH = 0,
+		ARM,
+		ACTIVE,
+		INACTIVE
+	} phase;
+} ppm;
+
+static void	hrt_ppm_decode(uint32_t status);
+
+#else
+/* disable the PPM configuration */
+# define rCCR_PPM	0
+# define DIER_PPM	0
+# define SR_INT_PPM	0
+# define SR_OVF_PPM	0
+# define CCMR1_PPM	0
+# define CCMR2_PPM	0
+# define CCER_PPM	0
+#endif /* CONFIG_HRT_PPM */
+
+/*
+ * Initialise the timer we are going to use.
+ *
+ * We expect that we'll own one of the reduced-function STM32 general
+ * timers, and that we can use channel 1 in compare mode.
+ */
+static void
+hrt_tim_init(void)
+{
+	/* clock/power on our timer */
+        modifyreg32(HRT_TIMER_POWER_REG, 0, HRT_TIMER_POWER_BIT);
+
+        /* claim our interrupt vector */
+        irq_attach(HRT_TIMER_VECTOR, hrt_tim_isr);
+
+        /* disable and configure the timer */
+        rCR1 = 0;
+        rCR2 = 0;
+        rSMCR = 0;
+        rDIER = DIER_HRT | DIER_PPM;
+        rCCER = 0;		/* unlock CCMR* registers */
+        rCCMR1 = CCMR1_PPM;		
+        rCCMR2 = CCMR2_PPM;
+        rCCER = CCER_PPM;
+        rDCR = 0;
+
+        /* configure the timer to free-run at 1MHz */
+        rPSC = (HRT_TIMER_CLOCK / 1000000) - 1;	/* this really only works for whole-MHz clocks */
+
+        /* run the full span of the counter */
+        rARR = 0xffff;
+
+        /* set an initial capture a little ways off */
+        rCCR_HRT = 1000;
+
+        /* generate an update event; reloads the counter, all registers */
+        rEGR = GTIM_EGR_UG;
+
+        /* enable the timer */
+        rCR1 = GTIM_CR1_CEN;
+
+        /* enable interrupts */
+        up_enable_irq(HRT_TIMER_VECTOR);
+}
+
+#ifdef CONFIG_HRT_PPM
+/*
+ * Handle the PPM decoder state machine.
+ */
+static void
+hrt_ppm_decode(uint32_t status) 
+{
+	uint16_t count = rCCR_PPM;
+	uint16_t width;
+	uint16_t interval;
+	unsigned i;
+
+	/* if we missed an edge, we have to give up */
+	if (status & SR_OVF_PPM)
+		goto error;
+
+	/* how long since the last edge? */
+	width = count - ppm.last_edge;
+	ppm.last_edge = count;
+
+	ppm_edge_history[ppm_edge_next++] = width;
+	if (ppm_edge_next >= 32)
+		ppm_edge_next = 0;
+
+	/* 
+	 * if this looks like a start pulse, then push the last set of values
+	 * and reset the state machine
+	 */
+	if (width >= PPM_MIN_START) {
+
+		/* export the last set of samples if we got something sensible */
+		if (ppm.next_channel > 4) {
+			for (i = 0; i < ppm.next_channel && i < PPM_MAX_CHANNELS; i++)
+				ppm_buffer[i] = ppm_temp_buffer[i];
+			ppm_decoded_channels = i;
+		}
+
+		/* reset for the next frame */
+		ppm.next_channel = 0;
+
+		/* next edge is the reference for the first channel */
+		ppm.phase = ARM;
+
+		return;
+	}
+
+	switch (ppm.phase) {
+	case UNSYNCH:
+		/* we are waiting for a start pulse - nothing useful to do here */
+		return;
+
+	case ARM:
+		/* we expect a pulse giving us the first mark */
+		if (width > PPM_MAX_PULSE_WIDTH)
+			goto error;		/* pulse was too long */
+	
+		/* record the mark timing, expect an inactive edge */
+		ppm.last_mark = count;
+		ppm.phase = INACTIVE;
+		return;
+
+	case INACTIVE:
+		/* this edge is not interesting, but now we are ready for the next mark */
+		ppm.phase = ACTIVE;
+		return;
+
+	case ACTIVE:
+		/* determine the interval from the last mark */
+		interval = count - ppm.last_mark;
+		ppm.last_mark = count;
+
+		ppm_pulse_history[ppm_pulse_next++] = interval;
+		if (ppm_pulse_next >= 32)
+			ppm_pulse_next = 0;
+
+		/* if the mark-mark timing is out of bounds, abandon the frame */
+		if ((interval < PPM_MIN_CHANNEL_VALUE) || (interval > PPM_MAX_CHANNEL_VALUE))
+			goto error;
+
+		/* if we have room to store the value, do so */
+		if (ppm.next_channel < PPM_MAX_CHANNELS)
+			ppm_temp_buffer[ppm.next_channel++] = interval;
+
+		ppm.phase = INACTIVE;
+		return;		
+
+	}
+
+	/* the state machine is corrupted; reset it */
+
+error:
+	/* we don't like the state of the decoder, reset it and try again */
+	ppm.phase = UNSYNCH;
+}
+#endif /* CONFIG_HRT_PPM */
+
+/*
+ * Handle the compare interupt by calling the callout dispatcher
+ * and then re-scheduling the next deadline.
+ */
+static int
+hrt_tim_isr(int irq, void *context)
+{
+	uint32_t status;
+
+	/* copy interrupt status */
+	status = rSR;
+
+	/* ack the interrupts we just read */
+	rSR = ~status;
+
+#ifdef CONFIG_HRT_PPM
+	/* was this a PPM edge? */
+	if (status & (SR_INT_PPM | SR_OVF_PPM))
+		hrt_ppm_decode(status);
+#endif
+
+	/* was this a timer tick? */
+	if (status & SR_INT_HRT) {
+		/* run any callouts that have met their deadline */
+		hrt_call_invoke();
+
+		/* and schedule the next interrupt */
+		hrt_call_reschedule();
+	}
+
+	return OK;
+}
+
+/*
+ * Fetch a never-wrapping absolute time value in microseconds from
+ * some arbitrary epoch shortly after system start.
+ */
+hrt_abstime
+hrt_absolute_time(void)
+{
+	hrt_abstime	abstime;
+	uint32_t	count;
+	uint32_t	flags;
+
+	/*
+	 * Counter state.  Marked volatile as they may change
+	 * inside this routine but outside the irqsave/restore
+	 * pair.  Discourage the compiler from moving loads/stores
+	 * to these outside of the protected range.
+	 */
+	static volatile hrt_abstime base_time;
+	static volatile uint32_t last_count;
+
+	/* prevent re-entry */
+	flags = irqsave();
+
+	/* get the current counter value */
+	count = rCNT;
+
+	/*
+	 * Determine whether the counter has wrapped since the
+	 * last time we're called.
+	 *
+	 * This simple test is sufficient due to the guarantee that
+	 * we are always called at least once per counter period.
+	 */
+	if (count < last_count)
+		base_time += HRT_COUNTER_PERIOD;
+
+	/* save the count for next time */
+	last_count = count;
+
+	/* compute the current time */
+	abstime = HRT_COUNTER_SCALE(base_time + count);
+
+	irqrestore(flags);
+
+	return abstime;
+}
+
+/*
+ * Convert a timespec to absolute time
+ */
+hrt_abstime
+ts_to_abstime(struct timespec *ts)
+{
+	hrt_abstime	result;
+
+	result = (hrt_abstime)(ts->tv_sec) * 1000000;
+	result += ts->tv_nsec / 1000;
+
+	return result;
+}
+
+/*
+ * Convert absolute time to a timespec.
+ */
+void
+abstime_to_ts(struct timespec *ts, hrt_abstime abstime)
+{
+	ts->tv_sec = abstime / 1000000;
+	abstime -= ts->tv_sec * 1000000;
+	ts->tv_nsec = abstime * 1000;
+}
+
+/*
+ * Initalise the high-resolution timing module.
+ */
+void
+hrt_init(void)
+{
+	sq_init(&callout_queue);
+	hrt_tim_init();
+
+#ifdef CONFIG_HRT_PPM
+	/* configure the PPM input pin */
+	stm32_configgpio(GPIO_PPM_IN);
+#endif
+}
+
+/*
+ * Call callout(arg) after interval has elapsed.
+ */
+void
+hrt_call_after(struct hrt_call *entry, hrt_abstime delay, hrt_callout callout, void *arg)
+{
+	hrt_call_internal(entry, 
+			  hrt_absolute_time() + delay,
+			  0,
+			  callout,
+			  arg);
+}
+
+/*
+ * Call callout(arg) at calltime.
+ */
+void
+hrt_call_at(struct hrt_call *entry, hrt_abstime calltime, hrt_callout callout, void *arg)
+{
+	hrt_call_internal(entry, calltime, 0, callout, arg);
+}
+
+/*
+ * Call callout(arg) every period.
+ */
+void
+hrt_call_every(struct hrt_call *entry, hrt_abstime delay, hrt_abstime interval, hrt_callout callout, void *arg)
+{
+	hrt_call_internal(entry,
+			  hrt_absolute_time() + delay,
+			  interval,
+			  callout,
+			  arg);
+}
+
+static void
+hrt_call_internal(struct hrt_call *entry, hrt_abstime deadline, hrt_abstime interval, hrt_callout callout, void *arg)
+{
+	irqstate_t flags = irqsave();
+
+	/* if the entry is currently queued, remove it */
+	if (entry->deadline != 0)
+		sq_rem(&entry->link, &callout_queue);
+
+	entry->deadline = deadline;
+	entry->period = interval;
+	entry->callout = callout;
+	entry->arg = arg;
+
+	hrt_call_enter(entry);
+
+	irqrestore(flags);
+}
+
+/*
+ * If this returns true, the call has been invoked and removed from the callout list.
+ *
+ * Always returns false for repeating callouts.
+ */
+bool
+hrt_called(struct hrt_call *entry)
+{
+	return (entry->deadline == 0);
+}
+
+/*
+ * Remove the entry from the callout list.
+ */
+void
+hrt_cancel(struct hrt_call *entry)
+{
+	irqstate_t flags = irqsave();
+
+	sq_rem(&entry->link, &callout_queue);
+	entry->deadline = 0;
+
+	/* if this is a periodic call being removed by the callout, prevent it from
+	 * being re-entered when the callout returns.
+	 */
+	entry->period = 0;
+
+	irqrestore(flags);
+}
+
+static void
+hrt_call_enter(struct hrt_call *entry)
+{
+	struct hrt_call	*call, *next;
+
+	call = (struct hrt_call *)sq_peek(&callout_queue);
+
+	if ((call == NULL) || (entry->deadline < call->deadline)) {
+		sq_addfirst(&entry->link, &callout_queue);
+		//lldbg("call enter at head, reschedule\n");
+		/* we changed the next deadline, reschedule the timer event */
+		hrt_call_reschedule();
+	} else {
+		do {
+			next = (struct hrt_call *)sq_next(&call->link);
+			if ((next == NULL) || (entry->deadline < next->deadline)) {
+				//lldbg("call enter after head\n");
+				sq_addafter(&call->link, &entry->link, &callout_queue);
+				break;
+			}
+		} while ((call = next) != NULL);
+	}
+
+	//lldbg("scheduled\n");
+}
+
+static void
+hrt_call_invoke(void)
+{
+	struct hrt_call	*call;
+	hrt_abstime deadline;
+
+	while (true) {
+		/* get the current time */
+		hrt_abstime now = hrt_absolute_time();
+
+		call = (struct hrt_call *)sq_peek(&callout_queue);
+		if (call == NULL)
+			break;
+		if (call->deadline > now)
+			break;
+
+		sq_rem(&call->link, &callout_queue);
+		//lldbg("call pop\n");
+
+		/* save the intended deadline for periodic calls */
+		deadline = call->deadline; 
+
+		/* zero the deadline, as the call has occurred */
+		call->deadline = 0;
+
+		/* invoke the callout (if there is one) */
+		if (call->callout) {
+			//lldbg("call %p: %p(%p)\n", call, call->callout, call->arg);
+			call->callout(call->arg);
+		}
+
+		/* if the callout has a non-zero period, it has to be re-entered */
+		if (call->period != 0) {
+			call->deadline = deadline + call->period;
+			hrt_call_enter(call);
+		}
+	}
+}
+
+/*
+ * Reschedule the next timer interrupt.
+ *
+ * This routine must be called with interrupts disabled.
+ */
+static void
+hrt_call_reschedule()
+{
+	hrt_abstime	now = hrt_absolute_time();
+	struct hrt_call	*next = (struct hrt_call *)sq_peek(&callout_queue);
+	hrt_abstime	deadline = now + HRT_INTERVAL_MAX;
+
+	/*
+	 * Determine what the next deadline will be.
+	 *
+	 * Note that we ensure that this will be within the counter
+	 * period, so that when we truncate all but the low 16 bits
+	 * the next time the compare matches it will be the deadline
+	 * we want.
+	 *
+	 * It is important for accurate timekeeping that the compare
+	 * interrupt fires sufficiently often that the base_time update in 
+	 * hrt_absolute_time runs at least once per timer period.
+	 */
+	if (next != NULL) {
+		//lldbg("entry in queue\n");
+		if (next->deadline <= (now + HRT_INTERVAL_MIN)) {
+			//lldbg("pre-expired\n");
+			/* set a minimal deadline so that we call ASAP */
+			deadline = now + HRT_INTERVAL_MIN;
+		} else if (next->deadline < deadline) {
+			//lldbg("due soon\n");
+			deadline = next->deadline;
+		}
+	}
+	//lldbg("schedule for %u at %u\n", (unsigned)(deadline & 0xffffffff), (unsigned)(now & 0xffffffff));
+
+	/* set the new compare value */
+	rCCR_HRT = deadline & 0xffff;
+}
+
+#endif /* CONFIG_HRT_TIMER */
diff --git a/nuttx/configs/px4fmu/src/up_leds.c b/nuttx/configs/px4fmu/src/up_leds.c
new file mode 100644
index 000000000..f7b76aa58
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_leds.c
@@ -0,0 +1,127 @@
+/****************************************************************************
+ * configs/px4fmu/src/up_leds.c
+ * arch/arm/src/board/up_leds.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG with
+ * CONFIG_DEBUG_VERBOSE too)
+ */
+
+#undef LED_DEBUG  /* Define to enable debug */
+
+#ifdef LED_DEBUG
+#  define leddbg  lldbg
+#  define ledvdbg llvdbg
+#else
+#  define leddbg(x...)
+#  define ledvdbg(x...)
+#endif
+
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_ledinit
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_LEDS
+void up_ledinit(void)
+{
+   /* Configure LED1-2 GPIOs for output */
+
+   stm32_configgpio(GPIO_LED1);
+   stm32_configgpio(GPIO_LED2);
+}
+
+/****************************************************************************
+ * Name: up_ledon
+ ****************************************************************************/
+
+void up_ledon(int led)
+{
+	if (led == 0)
+	{
+		/* Pull down to switch on */
+		stm32_gpiowrite(GPIO_LED1, false);
+	}
+	if (led == 1)
+	{
+		/* Pull down to switch on */
+		stm32_gpiowrite(GPIO_LED2, false);
+	}
+}
+
+/****************************************************************************
+ * Name: up_ledoff
+ ****************************************************************************/
+
+void up_ledoff(int led)
+{
+	if (led == 0)
+	{
+		/* Pull up to switch off */
+		stm32_gpiowrite(GPIO_LED1, true);
+	}
+	if (led == 1)
+	{
+		/* Pull up to switch off */
+		stm32_gpiowrite(GPIO_LED2, true);
+	}
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/nuttx/configs/px4fmu/src/up_nsh.c b/nuttx/configs/px4fmu/src/up_nsh.c
new file mode 100644
index 000000000..6e092e3b4
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_nsh.c
@@ -0,0 +1,392 @@
+/****************************************************************************
+ * config/stm3210e_eval/src/up_nsh.c
+ * arch/arm/src/board/up_nsh.c
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/spi.h>
+#include <nuttx/i2c.h>
+#include <nuttx/mmcsd.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/arch.h>
+
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+#include "stm32_uart.h"
+
+#include <arch/board/up_hrt.h>
+#include <arch/board/up_cpuload.h>
+#include <arch/board/drv_tone_alarm.h>
+#include <arch/board/up_adc.h>
+#include <arch/board/board.h>
+#include <arch/board/drv_bma180.h>
+#include <arch/board/drv_l3gd20.h>
+#include <arch/board/drv_hmc5883l.h>
+#include <arch/board/drv_mpu6000.h>
+#include <arch/board/drv_ms5611.h>
+#include <arch/board/drv_eeprom.h>
+#include <arch/board/drv_led.h>
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+#  ifdef CONFIG_DEBUG
+#    define message(...) lib_lowprintf(__VA_ARGS__)
+#  else
+#    define message(...) printf(__VA_ARGS__)
+#  endif
+#else
+#  ifdef CONFIG_DEBUG
+#    define message lib_lowprintf
+#  else
+#    define message printf
+#  endif
+#endif
+
+/****************************************************************************
+ * Protected Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: multiport_setup
+ *
+ * Description:
+ *   Perform setup of the PX4FMU's multi function ports
+ *
+ ****************************************************************************/
+int multiport_setup(void)
+{
+  int result = OK;
+
+  return result;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nsh_archinitialize
+ *
+ * Description:
+ *   Perform architecture specific initialization
+ *
+ ****************************************************************************/
+
+static struct spi_dev_s *spi1;
+static struct spi_dev_s *spi3;
+static struct i2c_dev_s *i2c1;
+static struct i2c_dev_s *i2c2;
+static struct i2c_dev_s *i2c3;
+
+#include <math.h>
+
+#ifdef __cplusplus
+int matherr(struct __exception *e) {
+  return 1;
+}
+#else
+int matherr(struct exception *e) {
+  return 1;
+}
+#endif
+
+int nsh_archinitialize(void)
+{
+  int result;
+
+  /* INIT 1 Lowest level NuttX initialization has been done at this point, LEDs and UARTs are configured */
+
+  /* INIT 2 Configuring PX4 low-level peripherals, these will be always needed */
+
+  /* configure the high-resolution time/callout interface */
+#ifdef CONFIG_HRT_TIMER
+  hrt_init();
+#endif
+
+  /* configure CPU load estimation */
+  #ifdef CONFIG_SCHED_INSTRUMENTATION
+  cpuload_initialize_once();
+  #endif
+
+  /* set up the serial DMA polling */
+#ifdef SERIAL_HAVE_DMA
+  {
+    static struct hrt_call serial_dma_call;
+    struct timespec ts;
+
+    /* 
+     * Poll at 1ms intervals for received bytes that have not triggered
+     * a DMA event.
+     */
+    ts.tv_sec = 0;
+    ts.tv_nsec = 1000000;
+
+    hrt_call_every(&serial_dma_call, 
+                   ts_to_abstime(&ts),
+                   ts_to_abstime(&ts),
+                   (hrt_callout)stm32_serial_dma_poll,
+                   NULL);
+  }
+#endif
+
+  message("\r\n");
+
+  up_ledoff(LED_BLUE);
+  up_ledoff(LED_AMBER);
+
+  up_ledon(LED_BLUE);
+
+  /* Configure user-space led driver */
+  px4fmu_led_init();
+
+  /* Configure SPI-based devices */
+
+  spi1 = up_spiinitialize(1);
+  if (!spi1)
+  {
+	  message("[boot] FAILED to initialize SPI port 1\r\n");
+	  up_ledon(LED_AMBER);
+	  return -ENODEV;
+  }
+
+  // Setup 10 MHz clock (maximum rate the BMA180 can sustain)
+  SPI_SETFREQUENCY(spi1, 10000000);
+  SPI_SETBITS(spi1, 8);
+  SPI_SETMODE(spi1, SPIDEV_MODE3);
+  SPI_SELECT(spi1, PX4_SPIDEV_GYRO, false);
+  SPI_SELECT(spi1, PX4_SPIDEV_ACCEL, false);
+  SPI_SELECT(spi1, PX4_SPIDEV_MPU, false);
+  up_udelay(20);
+
+  message("[boot] Successfully initialized SPI port 1\r\n");
+
+  /* initialize SPI peripherals redundantly */
+  int gyro_attempts = 0;
+  int gyro_fail = 0;
+
+  while (gyro_attempts < 5)
+  {
+	  gyro_fail = l3gd20_attach(spi1, PX4_SPIDEV_GYRO);
+	  gyro_attempts++;
+	  if (gyro_fail == 0) break;
+	  up_udelay(1000);
+  }
+
+  if (gyro_fail) message("[boot] FAILED to attach L3GD20 gyro\r\n");
+
+  int acc_attempts = 0;
+  int acc_fail = 0;
+
+  while (acc_attempts < 5)
+  {
+	  acc_fail = bma180_attach(spi1, PX4_SPIDEV_ACCEL);
+	  acc_attempts++;
+	  if (acc_fail == 0) break;
+	  up_udelay(1000);
+  }
+
+  if (acc_fail) message("[boot] FAILED to attach BMA180 accelerometer\r\n");
+
+  int mpu_attempts = 0;
+  int mpu_fail = 0;
+
+  while (mpu_attempts < 1)
+  {
+	  mpu_fail = mpu6000_attach(spi1, PX4_SPIDEV_MPU);
+	  mpu_attempts++;
+	  if (mpu_fail == 0) break;
+	  up_udelay(200);
+  }
+
+  if (mpu_fail) message("[boot] FAILED to attach MPU 6000 gyro/acc\r\n");
+
+  /* initialize I2C2 bus */
+
+  i2c2 = up_i2cinitialize(2);
+  if (!i2c2) {
+	  message("[boot] FAILED to initialize I2C bus 2\r\n");
+	  up_ledon(LED_AMBER);
+	  return -ENODEV;
+  }
+
+  /* set I2C2 speed */
+  I2C_SETFREQUENCY(i2c2, 400000);
+
+
+  i2c3 = up_i2cinitialize(3);
+  if (!i2c3) {
+	  message("[boot] FAILED to initialize I2C bus 3\r\n");
+	  up_ledon(LED_AMBER);
+	  return -ENODEV;
+  }
+
+  /* set I2C3 speed */
+  I2C_SETFREQUENCY(i2c3, 400000);
+
+  int mag_attempts = 0;
+  int mag_fail = 0;
+
+  while (mag_attempts < 5)
+  {
+	  mag_fail = hmc5883l_attach(i2c2);
+	  mag_attempts++;
+	  if (mag_fail == 0) break;
+	  up_udelay(1000);
+  }
+
+  if (mag_fail) message("[boot] FAILED to attach HMC5883L magnetometer\r\n");
+
+  int baro_attempts = 0;
+  int baro_fail = 0;
+  while (baro_attempts < 5)
+  {
+	  baro_fail = ms5611_attach(i2c2);
+	  baro_attempts++;
+	  if (baro_fail == 0) break;
+	  up_udelay(1000);
+  }
+
+  if (baro_fail) message("[boot] FAILED to attach MS5611 baro at addr #1 or #2 (0x76 or 0x77)\r\n");
+
+  /* try to attach, don't fail if device is not responding */
+  (void)eeprom_attach(i2c3, FMU_BASEBOARD_EEPROM_ADDRESS,
+		  FMU_BASEBOARD_EEPROM_TOTAL_SIZE_BYTES,
+		  FMU_BASEBOARD_EEPROM_PAGE_SIZE_BYTES,
+		  FMU_BASEBOARD_EEPROM_PAGE_WRITE_TIME_US, "/dev/baseboard_eeprom", 1);
+
+  int eeprom_attempts = 0;
+  int eeprom_fail;
+  while (eeprom_attempts < 5)
+  {
+	  /* try to attach, fail if device does not respond */
+	  eeprom_fail = eeprom_attach(i2c2, FMU_ONBOARD_EEPROM_ADDRESS,
+			  FMU_ONBOARD_EEPROM_TOTAL_SIZE_BYTES,
+			  FMU_ONBOARD_EEPROM_PAGE_SIZE_BYTES,
+			  FMU_ONBOARD_EEPROM_PAGE_WRITE_TIME_US, "/dev/eeprom", 1);
+	  eeprom_attempts++;
+	  if (eeprom_fail == OK) break;
+	  up_udelay(1000);
+  }
+
+  if (eeprom_fail) message("[boot] FAILED to attach FMU EEPROM\r\n");
+
+  /* Report back sensor status */
+  if (acc_fail || gyro_fail || mag_fail || baro_fail || eeprom_fail)
+  {
+	  up_ledon(LED_AMBER);
+  }
+
+#if defined(CONFIG_STM32_SPI3)
+  /* Get the SPI port */
+
+  message("[boot] Initializing SPI port 3\r\n");
+  spi3 = up_spiinitialize(3);
+  if (!spi3)
+    {
+      message("[boot] FAILED to initialize SPI port 3\r\n");
+      up_ledon(LED_AMBER);
+      return -ENODEV;
+    }
+  message("[boot] Successfully initialized SPI port 3\r\n");
+
+  /* Now bind the SPI interface to the MMCSD driver */
+  result = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, CONFIG_NSH_MMCSDSLOTNO, spi3);
+  if (result != OK)
+  {
+	  message("[boot] FAILED to bind SPI port 3 to the MMCSD driver\r\n");
+	  up_ledon(LED_AMBER);
+	  return -ENODEV;
+  }
+  message("[boot] Successfully bound SPI port 3 to the MMCSD driver\r\n");
+#endif /* SPI3 */
+
+  /* initialize I2C1 bus */
+
+  i2c1 = up_i2cinitialize(1);
+  if (!i2c1) {
+    message("[boot] FAILED to initialize I2C bus 1\r\n");
+    up_ledon(LED_AMBER);
+    return -ENODEV;
+  }
+
+  /* set I2C1 speed */
+  I2C_SETFREQUENCY(i2c1, 400000);
+
+  /* INIT 3: MULTIPORT-DEPENDENT INITIALIZATION */
+
+  /* Get board information if available */
+
+    /* Initialize the user GPIOs */
+  px4fmu_gpio_init();
+
+#ifdef CONFIG_ADC
+  int adc_state = adc_devinit();
+  if (adc_state != OK)
+  {
+    /* Try again */
+    adc_state = adc_devinit();
+    if (adc_state != OK)
+    {
+      /* Give up */
+      message("[boot] FAILED adc_devinit: %d\r\n", adc_state);
+      return -ENODEV;
+    }
+  }
+#endif
+
+    /* configure the tone generator */
+#ifdef CONFIG_TONE_ALARM
+  tone_alarm_init();
+#endif
+
+  return OK;
+}
diff --git a/nuttx/configs/px4fmu/src/up_pwm_servo.c b/nuttx/configs/px4fmu/src/up_pwm_servo.c
new file mode 100644
index 000000000..05daf1e97
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_pwm_servo.c
@@ -0,0 +1,344 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * Servo driver supporting PWM servos connected to STM32 timer blocks.
+ *
+ * Works with any of the 'generic' or 'advanced' STM32 timers that
+ * have output pins, does not require an interrupt.
+ */
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <time.h>
+#include <queue.h>
+#include <errno.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <arch/board/board.h>
+#include <arch/board/up_pwm_servo.h>
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_internal.h"
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+/* configuration limits */
+#define PWM_SERVO_MAX_TIMERS	2
+#define PWM_SERVO_MAX_CHANNELS	8
+
+/* default rate (in Hz) of PWM updates */
+static uint32_t	pwm_update_rate = 50;
+
+/*
+ * Servo configuration for all of the pins that can be used as
+ * PWM outputs on FMU.
+ */
+
+/* array of timers dedicated to PWM servo use */
+static const struct pwm_servo_timer {
+	uint32_t	base;
+	uint32_t	clock_register;
+	uint32_t	clock_bit;
+	uint32_t	clock_freq;
+} pwm_timers[] = {
+	{
+		.base = STM32_TIM2_BASE,
+		.clock_register = STM32_RCC_APB1ENR,
+		.clock_bit = RCC_APB1ENR_TIM2EN,
+		.clock_freq = STM32_APB1_TIM2_CLKIN
+	}
+};
+
+/* array of channels in logical order */
+static const struct pwm_servo_channel {
+	uint32_t	gpio;
+	uint8_t		timer_index;
+	uint8_t		timer_channel;
+	servo_position_t default_value;
+} pwm_channels[] = {
+	{
+		.gpio = GPIO_TIM2_CH1OUT,
+		.timer_index = 0,
+		.timer_channel = 1,
+		.default_value = 1000,
+	},
+	{
+		.gpio = GPIO_TIM2_CH2OUT,
+		.timer_index = 0,
+		.timer_channel = 2,
+		.default_value = 1000,
+	},
+	{
+		.gpio = GPIO_TIM2_CH3OUT,
+		.timer_index = 0,
+		.timer_channel = 3,
+		.default_value = 1000,
+	},
+	{
+		.gpio = GPIO_TIM2_CH4OUT,
+		.timer_index = 0,
+		.timer_channel = 4,
+		.default_value = 1000,
+	}
+};
+
+
+#define REG(_tmr, _reg)	(*(volatile uint32_t *)(pwm_timers[_tmr].base + _reg))
+
+#define rCR1(_tmr)    	REG(_tmr, STM32_GTIM_CR1_OFFSET)
+#define rCR2(_tmr)    	REG(_tmr, STM32_GTIM_CR2_OFFSET)
+#define rSMCR(_tmr)   	REG(_tmr, STM32_GTIM_SMCR_OFFSET)
+#define rDIER(_tmr)   	REG(_tmr, STM32_GTIM_DIER_OFFSET)
+#define rSR(_tmr)     	REG(_tmr, STM32_GTIM_SR_OFFSET)
+#define rEGR(_tmr)    	REG(_tmr, STM32_GTIM_EGR_OFFSET)
+#define rCCMR1(_tmr)  	REG(_tmr, STM32_GTIM_CCMR1_OFFSET)
+#define rCCMR2(_tmr)  	REG(_tmr, STM32_GTIM_CCMR2_OFFSET)
+#define rCCER(_tmr)   	REG(_tmr, STM32_GTIM_CCER_OFFSET)
+#define rCNT(_tmr)    	REG(_tmr, STM32_GTIM_CNT_OFFSET)
+#define rPSC(_tmr)    	REG(_tmr, STM32_GTIM_PSC_OFFSET)
+#define rARR(_tmr)    	REG(_tmr, STM32_GTIM_ARR_OFFSET)
+#define rCCR1(_tmr)   	REG(_tmr, STM32_GTIM_CCR1_OFFSET)
+#define rCCR2(_tmr)   	REG(_tmr, STM32_GTIM_CCR2_OFFSET)
+#define rCCR3(_tmr)   	REG(_tmr, STM32_GTIM_CCR3_OFFSET)
+#define rCCR4(_tmr)   	REG(_tmr, STM32_GTIM_CCR4_OFFSET)
+#define rDCR(_tmr)    	REG(_tmr, STM32_GTIM_DCR_OFFSET)
+#define rDMAR(_tmr)   	REG(_tmr, STM32_GTIM_DMAR_OFFSET)
+
+static void
+pwm_timer_init(unsigned timer)
+{
+	/* enable the timer clock before we try to talk to it */
+	modifyreg32(pwm_timers[timer].clock_register, 0, pwm_timers[timer].clock_bit);
+
+	/* disable and configure the timer */
+	rCR1(timer) = 0;
+	rCR2(timer) = 0;
+	rSMCR(timer) = 0;
+	rDIER(timer) = 0;
+	rCCER(timer) = 0;
+	rCCMR1(timer) = 0;
+	rCCMR2(timer) = 0;
+	rCCER(timer) = 0;
+	rDCR(timer) = 0;
+
+	/* configure the timer to free-run at 1MHz */
+	rPSC(timer) = pwm_timers[timer].clock_freq / 1000000;
+
+	/* and update at the desired rate */
+	rARR(timer) = 1000000 / pwm_update_rate;
+
+	/* generate an update event; reloads the counter and all registers */
+	rEGR(timer) = GTIM_EGR_UG;
+
+	/* note that the timer is left disabled - arming is performed separately */
+}
+
+static void
+pwm_timer_set_rate(unsigned timer, unsigned rate)
+{
+	/* configure the timer to update at the desired rate */
+	rARR(timer) = 1000000 / pwm_update_rate;
+
+	/* generate an update event; reloads the counter and all registers */
+	rEGR(timer) = GTIM_EGR_UG;
+}
+
+static void
+pwm_channel_init(unsigned channel)
+{
+	unsigned timer = pwm_channels[channel].timer_index;
+
+	/* configure the GPIO first */
+	stm32_configgpio(pwm_channels[channel].gpio);
+
+	/* configure the channel */
+	switch (pwm_channels[channel].timer_channel) {
+		case 1:
+			rCCMR1(timer) |= (6 << 4);
+			rCCR1(timer) = pwm_channels[channel].default_value;
+			rCCER(timer) |= (1 << 0);
+			break;
+		case 2:
+			rCCMR1(timer) |= (6 << 12);
+			rCCR2(timer) = pwm_channels[channel].default_value;
+			rCCER(timer) |= (1 << 4);
+			break;
+		case 3:
+			rCCMR2(timer) |= (6 << 4);
+			rCCR3(timer) = pwm_channels[channel].default_value;
+			rCCER(timer) |= (1 << 8);
+			break;
+		case 4:
+			rCCMR2(timer) |= (6 << 12);
+			rCCR4(timer) = pwm_channels[channel].default_value;
+			rCCER(timer) |= (1 << 12);
+			break;
+	}
+}
+
+int
+up_pwm_servo_set(unsigned channel, servo_position_t value)
+{
+	if (channel >= PWM_SERVO_MAX_CHANNELS) {
+		lldbg("pwm_channel_set: bogus channel %u\n", channel);
+		return -1;
+	}
+
+	unsigned timer = pwm_channels[channel].timer_index;
+
+	/* test timer for validity */
+	if ((pwm_timers[timer].base == 0) ||
+	    (pwm_channels[channel].gpio == 0))
+		return -1;
+
+	/* configure the channel */
+	switch (pwm_channels[channel].timer_channel) {
+		case 1:
+			rCCR1(timer) = value;
+			break;
+		case 2:
+			rCCR2(timer) = value;
+			break;
+		case 3:
+			rCCR3(timer) = value;
+			break;
+		case 4:
+			rCCR4(timer) = value;
+			break;
+		default:
+			return -1;
+	}
+	return 0;
+}
+
+servo_position_t
+up_pwm_servo_get(unsigned channel)
+{
+	if (channel >= PWM_SERVO_MAX_CHANNELS) {
+		lldbg("pwm_channel_get: bogus channel %u\n", channel);
+		return 0;
+	}
+
+	unsigned timer = pwm_channels[channel].timer_index;
+	servo_position_t value = 0;
+
+	/* test timer for validity */
+	if ((pwm_timers[timer].base == 0) ||
+	    (pwm_channels[channel].gpio == 0))
+		return 0;
+
+	/* configure the channel */
+	switch (pwm_channels[channel].timer_channel) {
+		case 1:
+			value = rCCR1(timer);
+			break;
+		case 2:
+			value = rCCR2(timer);
+			break;
+		case 3:
+			value = rCCR3(timer);
+			break;
+		case 4:
+			value = rCCR4(timer);
+			break;
+	}
+	return value;
+}
+
+int
+up_pwm_servo_init(uint32_t channel_mask)
+{
+	/* do basic timer initialisation first */
+	for (unsigned i = 0; i < PWM_SERVO_MAX_TIMERS; i++) {
+		if (pwm_timers[i].base != 0)
+			pwm_timer_init(i);
+	}
+
+	/* now init channels */
+	for (unsigned i = 0; i < PWM_SERVO_MAX_CHANNELS; i++) {
+		/* don't do init for disabled channels; this leaves the pin configs alone */
+		if (((1<<i) & channel_mask) && (pwm_channels[i].gpio != 0))
+			pwm_channel_init(i);
+	}
+	return OK;
+}
+
+void
+up_pwm_servo_deinit(void)
+{
+	/* disable the timers */
+	up_pwm_servo_arm(false);
+}
+
+int
+up_pwm_servo_set_rate(unsigned rate)
+{
+	if ((rate < 50) || (rate > 400))
+		return -ERANGE;
+
+	for (unsigned i = 0; i < PWM_SERVO_MAX_TIMERS; i++) {
+		if (pwm_timers[i].base != 0)
+			pwm_timer_set_rate(i, rate);
+	}
+	return OK;
+}
+
+void
+up_pwm_servo_arm(bool armed)
+{
+	/* 
+	 * XXX this is inelgant and in particular will either jam outputs at whatever level
+	 * they happen to be at at the time the timers stop or generate runts.
+	 * The right thing is almost certainly to kill auto-reload on the timers so that 
+	 * they just stop at the end of their count for disable, and to reset/restart them 
+	 * for enable.
+	 */
+
+	/* iterate timers and arm/disarm appropriately */
+	for (unsigned i = 0; i < PWM_SERVO_MAX_TIMERS; i++) {
+		if (pwm_timers[i].base != 0)
+			rCR1(i) = armed ? GTIM_CR1_CEN : 0;
+	}
+}
diff --git a/nuttx/configs/px4fmu/src/up_spi.c b/nuttx/configs/px4fmu/src/up_spi.c
new file mode 100644
index 000000000..ea34c30ce
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_spi.c
@@ -0,0 +1,192 @@
+/************************************************************************************
+ * configs/px4fmu/src/up_spi.c
+ * arch/arm/src/board/up_spi.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG too) */
+
+#undef SPI_DEBUG   /* Define to enable debug */
+#undef SPI_VERBOSE /* Define to enable verbose debug */
+
+#ifdef SPI_DEBUG
+#  define spidbg  lldbg
+#  ifdef SPI_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  undef SPI_VERBOSE
+#  define spidbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ************************************************************************************/
+
+void weak_function stm32_spiinitialize(void)
+{
+	stm32_configgpio(GPIO_SPI_CS_GYRO);
+	stm32_configgpio(GPIO_SPI_CS_ACCEL);
+	stm32_configgpio(GPIO_SPI_CS_MPU);
+	stm32_configgpio(GPIO_SPI_CS_SDCARD);
+
+	/* De-activate all peripherals,
+	 * required for some peripheral
+	 * state machines
+	 */
+	stm32_gpiowrite(GPIO_SPI_CS_GYRO, 1);
+	stm32_gpiowrite(GPIO_SPI_CS_ACCEL, 1);
+	stm32_gpiowrite(GPIO_SPI_CS_MPU, 1);
+	stm32_gpiowrite(GPIO_SPI_CS_SDCARD, 1);
+}
+
+/****************************************************************************
+ * Name:  stm32_spi1/2/3select and stm32_spi1/2/3status
+ *
+ * Description:
+ *   The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
+ *   provided by board-specific logic.  They are implementations of the select
+ *   and status methods of the SPI interface defined by struct spi_ops_s (see
+ *   include/nuttx/spi.h). All other methods (including up_spiinitialize())
+ *   are provided by common STM32 logic.  To use this common SPI logic on your
+ *   board:
+ *
+ *   1. Provide logic in stm32_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
+ *      board-specific logic.  These functions will perform chip selection and
+ *      status operations using GPIOs in the way your board is configured.
+ *   3. Add a calls to up_spiinitialize() in your low level application
+ *      initialization logic
+ *   4. The handle returned by up_spiinitialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32_SPI1
+void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+
+	/* SPI select is active low, so write !selected to select the device */
+
+	switch (devid) {
+	case PX4_SPIDEV_GYRO:
+		/* Making sure the other peripherals are not selected */
+		stm32_gpiowrite(GPIO_SPI_CS_GYRO, !selected);
+		stm32_gpiowrite(GPIO_SPI_CS_MPU, selected);
+		stm32_gpiowrite(GPIO_SPI_CS_ACCEL, selected);
+		break;
+	case PX4_SPIDEV_ACCEL:
+		/* Making sure the other peripherals are not selected */
+		stm32_gpiowrite(GPIO_SPI_CS_ACCEL, !selected);
+		stm32_gpiowrite(GPIO_SPI_CS_MPU, selected);
+		stm32_gpiowrite(GPIO_SPI_CS_GYRO, selected);
+		break;
+	case PX4_SPIDEV_MPU:
+		/* Making sure the other peripherals are not selected */
+		stm32_gpiowrite(GPIO_SPI_CS_ACCEL, selected);
+		stm32_gpiowrite(GPIO_SPI_CS_GYRO, selected);
+		stm32_gpiowrite(GPIO_SPI_CS_MPU, !selected);
+		break;
+	default:
+		spidbg("devid: %d - unexpected\n", devid);
+		break;
+		
+	}
+}
+
+uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+#endif
+
+#ifdef CONFIG_STM32_SPI3
+void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+
+	/* there can only be one device on this bus, so always select it */
+	stm32_gpiowrite(GPIO_SPI_CS_SDCARD, 0);
+}
+
+uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	/* this is actually bogus, but PX4 has no way to sense the presence of an SD card */
+	return SPI_STATUS_PRESENT;
+}
+#endif
+
+#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */
diff --git a/nuttx/configs/px4fmu/src/up_usbdev.c b/nuttx/configs/px4fmu/src/up_usbdev.c
new file mode 100644
index 000000000..4ef105e91
--- /dev/null
+++ b/nuttx/configs/px4fmu/src/up_usbdev.c
@@ -0,0 +1,105 @@
+/************************************************************************************
+ * configs/stm32f4discovery/src/up_usbdev.c
+ * arch/arm/src/board/up_boot.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "up_arch.h"
+#include "stm32_internal.h"
+#include "px4fmu-internal.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called to setup USB-related GPIO pins for the STM3210E-EVAL board.
+ *
+ ************************************************************************************/
+
+void stm32_usbinitialize(void)
+{
+  /* The OTG FS has an internal soft pull-up */
+
+  /* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
+
+#ifdef CONFIG_STM32_OTGFS
+  stm32_configgpio(GPIO_OTGFS_VBUS);
+  /* XXX We only support device mode
+  stm32_configgpio(GPIO_OTGFS_PWRON);
+  stm32_configgpio(GPIO_OTGFS_OVER);
+  */
+#endif
+}
+
+/************************************************************************************
+ * Name:  stm32_usbsuspend
+ *
+ * Description:
+ *   Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
+ *   used.  This function is called whenever the USB enters or leaves suspend mode.
+ *   This is an opportunity for the board logic to shutdown clocks, power, etc.
+ *   while the USB is suspended.
+ *
+ ************************************************************************************/
+
+void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
+{
+  ulldbg("resume: %d\n", resume);
+}
+
diff --git a/nuttx/configs/px4io/README.txt b/nuttx/configs/px4io/README.txt
new file mode 100755
index 000000000..9b1615f42
--- /dev/null
+++ b/nuttx/configs/px4io/README.txt
@@ -0,0 +1,806 @@
+README
+======
+
+This README discusses issues unique to NuttX configurations for the
+STMicro STM3210E-EVAL development board.
+
+Contents
+========
+
+  - Development Environment
+  - GNU Toolchain Options
+  - IDEs
+  - NuttX buildroot Toolchain
+  - DFU and JTAG
+  - OpenOCD
+  - LEDs
+  - Temperature Sensor
+  - RTC
+  - STM3210E-EVAL-specific Configuration Options
+  - Configurations
+
+Development Environment
+=======================
+
+  Either Linux or Cygwin on Windows can be used for the development environment.
+  The source has been built only using the GNU toolchain (see below).  Other
+  toolchains will likely cause problems. Testing was performed using the Cygwin
+  environment because the Raisonance R-Link emulatator and some RIDE7 development tools
+  were used and those tools works only under Windows.
+
+GNU Toolchain Options
+=====================
+
+  The NuttX make system has been modified to support the following different
+  toolchain options.
+
+  1. The CodeSourcery GNU toolchain,
+  2. The devkitARM GNU toolchain,
+  3. Raisonance GNU toolchain, or
+  4. The NuttX buildroot Toolchain (see below).
+
+  All testing has been conducted using the NuttX buildroot toolchain.  However,
+  the make system is setup to default to use the devkitARM toolchain.  To use
+  the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to
+  add one of the following configuration options to your .config (or defconfig)
+  file:
+
+    CONFIG_STM32_CODESOURCERYW=y  : CodeSourcery under Windows
+    CONFIG_STM32_CODESOURCERYL=y  : CodeSourcery under Linux
+    CONFIG_STM32_DEVKITARM=y      : devkitARM under Windows
+    CONFIG_STM32_RAISONANCE=y     : Raisonance RIDE7 under Windows
+    CONFIG_STM32_BUILDROOT=y      : NuttX buildroot under Linux or Cygwin (default)
+
+  If you are not using CONFIG_STM32_BUILDROOT, then you may also have to modify
+  the PATH in the setenv.h file if your make cannot find the tools.
+
+  NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are
+  Windows native toolchains.  The CodeSourcey (for Linux) and NuttX buildroot
+  toolchains are Cygwin and/or Linux native toolchains. There are several limitations
+  to using a Windows based toolchain in a Cygwin environment.  The three biggest are:
+
+  1. The Windows toolchain cannot follow Cygwin paths.  Path conversions are
+     performed automatically in the Cygwin makefiles using the 'cygpath' utility
+     but you might easily find some new path problems.  If so, check out 'cygpath -w'
+
+  2. Windows toolchains cannot follow Cygwin symbolic links.  Many symbolic links
+     are used in Nuttx (e.g., include/arch).  The make system works around these
+     problems for the Windows tools by copying directories instead of linking them.
+     But this can also cause some confusion for you:  For example, you may edit
+     a file in a "linked" directory and find that your changes had no effect.
+     That is because you are building the copy of the file in the "fake" symbolic
+     directory.  If you use a Windows toolchain, you should get in the habit of
+     making like this:
+
+       make clean_context all
+
+     An alias in your .bashrc file might make that less painful.
+
+  3. Dependencies are not made when using Windows versions of the GCC.  This is
+     because the dependencies are generated using Windows pathes which do not
+     work with the Cygwin make.
+
+     Support has been added for making dependencies with the windows-native toolchains.
+     That support can be enabled by modifying your Make.defs file as follows:
+
+    -  MKDEP                = $(TOPDIR)/tools/mknulldeps.sh
+    +  MKDEP                = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
+
+     If you have problems with the dependency build (for example, if you are not
+     building on C:), then you may need to modify tools/mkdeps.sh
+
+  NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
+  level of -Os (See Make.defs).  It will work with -O0, -O1, or -O2, but not with
+  -Os.
+
+  NOTE 2: The devkitARM toolchain includes a version of MSYS make.  Make sure that
+  the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
+  path or will get the wrong version of make.
+
+IDEs
+====
+
+  NuttX is built using command-line make.  It can be used with an IDE, but some
+  effort will be required to create the project (There is a simple RIDE project
+  in the RIDE subdirectory).
+  
+  Makefile Build
+  --------------
+  Under Eclipse, it is pretty easy to set up an "empty makefile project" and
+  simply use the NuttX makefile to build the system.  That is almost for free
+  under Linux.  Under Windows, you will need to set up the "Cygwin GCC" empty
+  makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
+  there is a lot of help on the internet).
+
+  Native Build
+  ------------
+  Here are a few tips before you start that effort:
+
+  1) Select the toolchain that you will be using in your .config file
+  2) Start the NuttX build at least one time from the Cygwin command line
+     before trying to create your project.  This is necessary to create
+     certain auto-generated files and directories that will be needed.
+  3) Set up include pathes:  You will need include/, arch/arm/src/stm32,
+     arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
+  4) All assembly files need to have the definition option -D __ASSEMBLY__
+     on the command line.
+
+  Startup files will probably cause you some headaches.  The NuttX startup file
+  is arch/arm/src/stm32/stm32_vectors.S.  With RIDE, I have to build NuttX
+  one time from the Cygwin command line in order to obtain the pre-built
+  startup object needed by RIDE.
+
+NuttX buildroot Toolchain
+=========================
+
+  A GNU GCC-based toolchain is assumed.  The files */setenv.sh should
+  be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
+  different from the default in your PATH variable).
+
+  If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
+  SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
+  This GNU toolchain builds and executes in the Linux or Cygwin environment.
+
+  1. You must have already configured Nuttx in <some-dir>/nuttx.
+
+     cd tools
+     ./configure.sh stm3210e-eval/<sub-dir>
+
+  2. Download the latest buildroot package into <some-dir>
+
+  3. unpack the buildroot tarball.  The resulting directory may
+     have versioning information on it like buildroot-x.y.z.  If so,
+     rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
+
+  4. cd <some-dir>/buildroot
+
+  5. cp configs/cortexm3-defconfig-4.3.3 .config
+
+  6. make oldconfig
+
+  7. make
+
+  8. Edit setenv.h, if necessary, so that the PATH variable includes
+     the path to the newly built binaries.
+
+  See the file configs/README.txt in the buildroot source tree.  That has more
+  detailed PLUS some special instructions that you will need to follow if you are
+  building a Cortex-M3 toolchain for Cygwin under Windows.
+
+DFU and JTAG
+============
+
+  Enbling Support for the DFU Bootloader
+  --------------------------------------
+  The linker files in these projects can be configured to indicate that you
+  will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
+  loader or via some JTAG emulator.  You can specify the DFU bootloader by
+  adding the following line:
+
+    CONFIG_STM32_DFU=y
+
+  to your .config file. Most of the configurations in this directory are set
+  up to use the DFU loader.
+
+  If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning
+  of FLASH (0x08000000) but will be offset to 0x08003000.  This offset is needed
+  to make space for the DFU loader and 0x08003000 is where the DFU loader expects
+  to find new applications at boot time.  If you need to change that origin for some
+  other bootloader, you will need to edit the file(s) ld.script.dfu for each
+  configuration.
+
+  The DFU SE PC-based software is available from the STMicro website,
+  http://www.st.com.  General usage instructions:
+  
+  1. Convert the NuttX Intel Hex file (nuttx.ihx) into a special DFU
+     file (nuttx.dfu)... see below for details.
+  2. Connect the STM3210E-EVAL board to your computer using a USB
+     cable.
+  3. Start the DFU loader on the STM3210E-EVAL board.  You do this by
+     resetting the board while holding the "Key" button.  Windows should
+     recognize that the DFU loader has been installed.
+  3. Run the DFU SE program to load nuttx.dfu into FLASH.
+
+  What if the DFU loader is not in FLASH?  The loader code is available
+  inside of the Demo dirctory of the USBLib ZIP file that can be downloaded
+  from the STMicro Website.  You can build it using RIDE (or other toolchains);
+  you will need a JTAG emulator to burn it into FLASH the first time.
+
+  In order to use STMicro's built-in DFU loader, you will have to get
+  the NuttX binary into a special format with a .dfu extension.  The
+  DFU SE PC_based software installation includes a file "DFU File Manager"
+  conversion program that a file in Intel Hex format to the special DFU
+  format.  When you successfully build NuttX, you will find a file called
+  nutt.ihx in the top-level directory.  That is the file that you should
+  provide to the DFU File Manager.  You will need to rename it to nuttx.hex
+  in order to find it with the DFU File Manager. You will end up with
+  a file called nuttx.dfu that you can use with the STMicro DFU SE program.
+
+  Enabling JTAG
+  -------------
+  If you are not using the DFU, then you will probably also need to enable
+  JTAG support.  By default, all JTAG support is disabled but there NuttX
+  configuration options to enable JTAG in various different ways.
+
+  These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO
+  MAPR register.  These bits are used to configure the SWJ and trace alternate function I/Os. The SWJ (SerialWire JTAG) supports JTAG or SWD access to the
+  Cortex debug port.  The default state in this port is for all JTAG support
+  to be disable.
+
+  CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full
+    SWJ (JTAG-DP + SW-DP)
+
+  CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable
+    full SWJ (JTAG-DP + SW-DP) but without JNTRST.
+
+  CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP
+    disabled and SW-DP enabled
+
+  The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
+  which disable JTAG-DP and SW-DP.
+
+OpenOCD
+=======
+
+I have also used OpenOCD with the STM3210E-EVAL.  In this case, I used
+the Olimex USB ARM OCD.  See the script in configs/stm3210e-eval/tools/oocd.sh
+for more information.  Using the script:
+
+1) Start the OpenOCD GDB server
+
+   cd <nuttx-build-directory>
+   configs/stm3210e-eval/tools/oocd.sh $PWD
+
+2) Load Nuttx
+
+   cd <nuttx-built-directory>
+   arm-none-eabi-gdb nuttx
+   gdb> target remote localhost:3333
+   gdb> mon reset
+   gdb> mon halt
+   gdb> load nuttx
+
+3) Running NuttX
+
+   gdb> mon reset
+   gdb> c
+
+LEDs
+====
+
+The STM3210E-EVAL board has four LEDs labeled LD1, LD2, LD3 and LD4 on the
+board.. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined.  In that case, the usage by the board port is defined in
+include/board.h and src/up_leds.c. The LEDs are used to encode OS-related
+events as follows:
+
+    SYMBOL           Meaning                 LED1* LED2  LED3  LED4
+    ---------------- ----------------------- ----- ----- ----- -----
+    LED_STARTED      NuttX has been started  ON    OFF   OFF   OFF
+    LED_HEAPALLOCATE Heap has been allocated OFF   ON    OFF   OFF
+    LED_IRQSENABLED  Interrupts enabled      ON    ON    OFF   OFF
+    LED_STACKCREATED Idle stack created      OFF   OFF   ON    OFF
+    LED_INIRQ        In an interrupt**       ON    N/C   N/C   OFF
+    LED_SIGNAL       In a signal handler***  N/C   ON    N/C   OFF
+    LED_ASSERTION    An assertion failed     ON    ON    N/C   OFF
+    LED_PANIC        The system has crashed  N/C   N/C   N/C   ON
+    LED_IDLE         STM32 is is sleep mode  (Optional, not used)
+
+  * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
+    and these LEDs will give you some indication of where the failure was
+ ** The normal state is LED3 ON and LED1 faintly glowing.  This faint glow
+    is because of timer interupts that result in the LED being illuminated
+    on a small proportion of the time.
+*** LED2 may also flicker normally if signals are processed.
+
+Temperature Sensor
+==================
+
+Support for the on-board LM-75 temperature sensor is available.  This supported
+has been verified, but has not been included in any of the available the
+configurations.  To set up the temperature sensor, add the following to the
+NuttX configuration file
+
+  CONFIG_I2C=y
+  CONFIG_I2C_LM75=y
+
+Then you can implement logic like the following to use the temperature sensor:
+
+  #include <nuttx/sensors/lm75.h>
+  #include <arch/board/board.h>
+
+  ret =  stm32_lm75initialize("/dev/temp");       /* Register the temperature sensor */
+  fd = open("/dev/temp", O_RDONLY);               /* Open the temperature sensor device */
+  ret = ioctl(fd, SNIOC_FAHRENHEIT, 0);           /* Select Fahrenheit */
+  bytesread = read(fd, buffer, 8*sizeof(b16_t));  /* Read temperature samples */
+
+More complex temperature sensor operations are also available.  See the IOCTAL
+commands enumerated in include/nuttx/sensors/lm75.h.  Also read the descriptions
+of the stm32_lm75initialize() and stm32_lm75attach() interfaces in the
+arch/board/board.h file (sames as configs/stm3210e-eval/include/board.h).
+
+RTC
+===
+
+  The STM32 RTC may configured using the following settings.
+
+    CONFIG_RTC - Enables general support for a hardware RTC. Specific
+      architectures may require other specific settings.
+    CONFIG_RTC_HIRES - The typical RTC keeps time to resolution of 1
+      second, usually supporting a 32-bit time_t value.  In this case,
+      the RTC is used to &quot;seed&quot; the normal NuttX timer and the
+      NuttX timer provides for higher resoution time. If CONFIG_RTC_HIRES
+      is enabled in the NuttX configuration, then the RTC provides higher
+      resolution time and completely replaces the system timer for purpose of
+      date and time.
+      CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the
+      frequency of the high resolution RTC must be provided.  If CONFIG_RTC_HIRES
+      is not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
+    CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an alarm. 
+      A callback function will be executed when the alarm goes off
+
+  In hi-res mode, the STM32 RTC operates only at 16384Hz.  Overflow interrupts
+  are handled when the 32-bit RTC counter overflows every 3 days and 43 minutes.
+  A BKP register is incremented on each overflow interrupt creating, effectively,
+  a 48-bit RTC counter.
+
+  In the lo-res mode, the RTC operates at 1Hz.  Overflow interrupts are not handled
+  (because the next overflow is not expected until the year 2106.
+
+   WARNING:  Overflow interrupts are lost whenever the STM32 is powered down.  The
+   overflow interrupt may be lost even if the STM32 is powered down only momentarily.
+   Therefore hi-res solution is only useful in systems where the power is always on.
+
+STM3210E-EVAL-specific Configuration Options
+============================================
+
+    CONFIG_ARCH - Identifies the arch/ subdirectory.  This should
+       be set to:
+
+       CONFIG_ARCH=arm
+
+    CONFIG_ARCH_family - For use in C code:
+
+       CONFIG_ARCH_ARM=y
+
+    CONFIG_ARCH_architecture - For use in C code:
+
+       CONFIG_ARCH_CORTEXM3=y
+
+    CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+       CONFIG_ARCH_CHIP=stm32
+
+    CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+       chip:
+
+       CONFIG_ARCH_CHIP_STM32F103ZET6
+
+    CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+       configuration features.
+
+       CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+ 
+    CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
+       hence, the board that supports the particular chip or SoC.
+
+       CONFIG_ARCH_BOARD=stm3210e_eval (for the STM3210E-EVAL development board)
+
+    CONFIG_ARCH_BOARD_name - For use in C code
+
+       CONFIG_ARCH_BOARD_STM3210E_EVAL=y
+
+    CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+       of delay loops
+
+    CONFIG_ENDIAN_BIG - define if big endian (default is little
+       endian)
+
+    CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+       CONFIG_DRAM_SIZE=0x00010000 (64Kb)
+
+    CONFIG_DRAM_START - The start address of installed DRAM
+
+       CONFIG_DRAM_START=0x20000000
+
+    CONFIG_DRAM_END - Last address+1 of installed RAM
+
+       CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+
+    CONFIG_ARCH_IRQPRIO - The STM32F103Z supports interrupt prioritization
+
+       CONFIG_ARCH_IRQPRIO=y
+
+    CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+       have LEDs
+
+    CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+       stack. If defined, this symbol is the size of the interrupt
+        stack in bytes.  If not defined, the user task stacks will be
+      used during interrupt handling.
+
+    CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+    CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+
+    CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+       cause a 100 second delay during boot-up.  This 100 second delay
+       serves no purpose other than it allows you to calibratre
+       CONFIG_ARCH_LOOPSPERMSEC.  You simply use a stop watch to measure
+       the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
+       the delay actually is 100 seconds.
+
+  Individual subsystems can be enabled:
+    AHB
+    ---
+    CONFIG_STM32_DMA1
+    CONFIG_STM32_DMA2
+    CONFIG_STM32_CRC
+    CONFIG_STM32_FSMC
+    CONFIG_STM32_SDIO
+
+    APB1
+    ----
+    CONFIG_STM32_TIM2
+    CONFIG_STM32_TIM3
+    CONFIG_STM32_TIM4
+    CONFIG_STM32_TIM5
+    CONFIG_STM32_TIM6
+    CONFIG_STM32_TIM7
+    CONFIG_STM32_WWDG
+    CONFIG_STM32_SPI2
+    CONFIG_STM32_SPI4
+    CONFIG_STM32_USART2
+    CONFIG_STM32_USART3
+    CONFIG_STM32_UART4
+    CONFIG_STM32_UART5
+    CONFIG_STM32_I2C1
+    CONFIG_STM32_I2C2
+    CONFIG_STM32_USB
+    CONFIG_STM32_CAN
+    CONFIG_STM32_BKP
+    CONFIG_STM32_PWR
+    CONFIG_STM32_DAC1
+    CONFIG_STM32_DAC2
+    CONFIG_STM32_USB
+
+    APB2
+    ----
+    CONFIG_STM32_ADC1
+    CONFIG_STM32_ADC2
+    CONFIG_STM32_TIM1
+    CONFIG_STM32_SPI1
+    CONFIG_STM32_TIM8
+    CONFIG_STM32_USART1
+    CONFIG_STM32_ADC3
+
+  Timer and I2C devices may need to the following to force power to be applied
+  unconditionally at power up.  (Otherwise, the device is powered when it is
+  initialized).
+
+    CONFIG_STM32_FORCEPOWER
+
+  Timer devices may be used for different purposes.  One special purpose is
+  to generate modulated outputs for such things as motor control.  If CONFIG_STM32_TIMn
+  is defined (as above) then the following may also be defined to indicate that
+  the timer is intended to be used for pulsed output modulation, ADC conversion,
+  or DAC conversion.  Note that ADC/DAC require two definition:  Not only do you have
+  to assign the timer (n) for used by the ADC or DAC, but then you also have to
+  configure which ADC or DAC (m) it is assigned to.
+
+    CONFIG_STM32_TIMn_PWM   Reserve timer n for use by PWM, n=1,..,8
+    CONFIG_STM32_TIMn_ADC   Reserve timer n for use by ADC, n=1,..,8
+    CONFIG_STM32_TIMn_ADCm  Reserve timer n to trigger ADCm, n=1,..,8, m=1,..,3
+    CONFIG_STM32_TIMn_DAC   Reserve timer n for use by DAC, n=1,..,8
+    CONFIG_STM32_TIMn_DACm  Reserve timer n to trigger DACm, n=1,..,8, m=1,..,2
+
+  For each timer that is enabled for PWM usage, we need the following additional
+  configuration settings:
+
+    CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+ 
+  NOTE: The STM32 timers are each capable of generating different signals on
+  each of the four channels with different duty cycles.  That capability is
+  not supported by this driver:  Only one output channel per timer.
+
+  Alternate pin mappings (should not be used with the STM3210E-EVAL board):
+
+    CONFIG_STM32_TIM1_FULL_REMAP
+    CONFIG_STM32_TIM1_PARTIAL_REMAP
+    CONFIG_STM32_TIM2_FULL_REMAP
+    CONFIG_STM32_TIM2_PARTIAL_REMAP_1
+    CONFIG_STM32_TIM2_PARTIAL_REMAP_2
+    CONFIG_STM32_TIM3_FULL_REMAP
+    CONFIG_STM32_TIM3_PARTIAL_REMAP
+    CONFIG_STM32_TIM4_REMAP
+    CONFIG_STM32_USART1_REMAP
+    CONFIG_STM32_USART2_REMAP
+    CONFIG_STM32_USART3_FULL_REMAP
+    CONFIG_STM32_USART3_PARTIAL_REMAP
+    CONFIG_STM32_SPI1_REMAP
+    CONFIG_STM32_SPI3_REMAP
+    CONFIG_STM32_I2C1_REMAP
+    CONFIG_STM32_CAN1_FULL_REMAP
+    CONFIG_STM32_CAN1_PARTIAL_REMAP
+    CONFIG_STM32_CAN2_REMAP
+
+  JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+    CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+    CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+      but without JNTRST.
+    CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+  STM32F103Z specific device driver settings
+
+    CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+           m (m=4,5) for the console and ttys0 (default is the USART1).
+    CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+       This specific the size of the receive buffer
+    CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+       being sent.  This specific the size of the transmit buffer
+    CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART.  Must be
+    CONFIG_U[S]ARTn_BITS - The number of bits.  Must be either 7 or 8.
+    CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+    CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+    CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+      support. Non-interrupt-driven, poll-waiting is recommended if the
+      interrupt rate would be to high in the interrupt driven case.
+    CONFIG_STM32_SPI_DMA - Use DMA to improve SPI transfer performance.
+      Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+    CONFIG_SDIO_DMA - Support DMA data transfers.  Requires CONFIG_STM32_SDIO
+      and CONFIG_STM32_DMA2.
+    CONFIG_SDIO_PRI - Select SDIO interrupt prority.  Default: 128
+    CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. 
+      Default:  Medium
+    CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode.  Default:
+      4-bit transfer mode.
+
+  STM3210E-EVAL CAN Configuration
+
+    CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+      CONFIG_STM32_CAN2 must also be defined)
+    CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID.  Default
+      Standard 11-bit IDs.
+    CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+      Default: 8
+    CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+      Default: 4
+    CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+      mode for testing. The STM32 CAN driver does support loopback mode.
+    CONFIG_CAN1_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN1 is defined.
+    CONFIG_CAN2_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN2 is defined.
+    CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
+    CONFIG_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
+    CONFIG_CAN_REGDEBUG - If CONFIG_DEBUG is set, this will generate an
+      dump of all CAN registers.
+
+  STM3210E-EVAL LCD Hardware Configuration
+
+    CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
+      support. Default is this 320x240 "landscape" orientation
+      (this setting is informative only... not used).
+    CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
+      orientation support.  In this orientation, the STM3210E-EVAL's
+      LCD ribbon cable is at the bottom of the display. Default is
+      320x240 "landscape" orientation.
+    CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
+      portrait" orientation support.  In this orientation, the
+      STM3210E-EVAL's LCD ribbon cable is at the top of the display.
+      Default is 320x240 "landscape" orientation.
+    CONFIG_LCD_BACKLIGHT - Define to support a backlight.
+    CONFIG_LCD_PWM - If CONFIG_STM32_TIM1 is also defined, then an
+      adjustable backlight will be provided using timer 1 to generate
+      various pulse widthes.  The granularity of the settings is
+      determined by CONFIG_LCD_MAXPOWER.  If CONFIG_LCD_PWM (or
+      CONFIG_STM32_TIM1) is not defined, then a simple on/off backlight
+      is provided.
+    CONFIG_LCD_RDSHIFT - When reading 16-bit gram data, there appears
+      to be a shift in the returned data.  This value fixes the offset.
+      Default 5.
+
+    The LCD driver dynamically selects the LCD based on the reported LCD
+    ID value.  However, code size can be reduced by suppressing support for
+    individual LCDs using:
+
+    CONFIG_STM32_AM240320_DISABLE
+    CONFIG_STM32_SPFD5408B_DISABLE
+    CONFIG_STM32_R61580_DISABLE
+
+Configurations
+==============
+
+Each STM3210E-EVAL configuration is maintained in a sudirectory and
+can be selected as follow:
+
+    cd tools
+    ./configure.sh stm3210e-eval/<subdir>
+    cd -
+    . ./setenv.sh
+
+Where <subdir> is one of the following:
+
+  buttons:
+  --------
+
+    Uses apps/examples/buttons to exercise STM3210E-EVAL buttons and
+    button interrupts.
+ 
+    CONFIG_STM32_CODESOURCERYW=y  : CodeSourcery under Windows
+
+  composite
+  ---------
+
+    This configuration exercises a composite USB interface consisting
+    of a CDC/ACM device and a USB mass storage device.  This configuration
+    uses apps/examples/composite.
+
+  nsh and nsh2:
+  ------------
+    Configure the NuttShell (nsh) located at examples/nsh.
+
+    Differences between the two NSH configurations:
+
+    =========== ======================= ================================
+                nsh                     nsh2
+    =========== ======================= ================================
+    Toolchain:  NuttX buildroot for     Codesourcery for Windows (1)
+                Linux or Cygwin (1,2)
+    ----------- ----------------------- --------------------------------
+    Loader:     DfuSe                   DfuSe
+    ----------- ----------------------- --------------------------------
+    Serial      Debug output: USART1    Debug output: USART1
+    Console:    NSH output:   USART1    NSH output:   USART1 (3)
+    ----------- ----------------------- --------------------------------
+    microSD     Yes                     Yes
+    Support
+    ----------- ----------------------- --------------------------------
+    FAT FS      CONFIG_FAT_LCNAME=y     CONFIG_FAT_LCNAME=y
+    Config      CONFIG_FAT_LFN=n        CONFIG_FAT_LFN=y (4)
+    ----------- ----------------------- --------------------------------
+    Support for No                      Yes
+    Built-in
+    Apps
+    ----------- ----------------------- --------------------------------
+    Built-in    None                    apps/examples/nx
+    Apps                                apps/examples/nxhello
+                                        apps/examples/usbstorage (5)
+    =========== ======================= ================================
+
+    (1) You will probably need to modify nsh/setenv.sh or nsh2/setenv.sh
+        to set up the correct PATH variable for whichever toolchain you
+        may use.
+    (2) Since DfuSe is assumed, this configuration may only work under
+        Cygwin without modification.
+    (3) When any other device other than /dev/console is used for a user
+        interface, (1) linefeeds (\n) will not be expanded to carriage return
+        / linefeeds \r\n). You will need to configure your terminal program
+        to account for this. And (2) input is not automatically echoed so
+        you will have to turn local echo on.
+    (4) Microsoft holds several patents related to the design of
+        long file names in the FAT file system.  Please refer to the
+        details in the top-level COPYING file.  Please do not use FAT
+        long file name unless you are familiar with these patent issues.
+    (5) When built as an NSH add-on command (CONFIG_EXAMPLES_USBMSC_BUILTIN=y),
+        Caution should be used to assure that the SD drive is not in use when
+        the USB storage device is configured.  Specifically, the SD driver
+        should be unmounted like:
+
+        nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Card is mounted in NSH
+        ...
+        nsh> umount /mnd/sdcard                    # Unmount before connecting USB!!!
+        nsh> msconn                                # Connect the USB storage device
+        ...
+        nsh> msdis                                 # Disconnect USB storate device
+        nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Restore the mount
+
+        Failure to do this could result in corruption of the SD card format.
+
+  nx:
+  ---
+    An example using the NuttX graphics system (NX).  This example
+    focuses on general window controls, movement, mouse and keyboard
+    input.
+
+    CONFIG_STM32_CODESOURCERYW=y  : CodeSourcery under Windows
+    CONFIG_LCD_RPORTRAIT=y        : 240x320 reverse portrait
+
+  nxlines:
+  ------
+    Another example using the NuttX graphics system (NX).   This
+    example focuses on placing lines on the background in various
+    orientations.
+
+    CONFIG_STM32_CODESOURCERYW=y  : CodeSourcery under Windows
+    CONFIG_LCD_RPORTRAIT=y        : 240x320 reverse portrait
+
+  nxtext:
+  ------
+    Another example using the NuttX graphics system (NX).   This
+    example focuses on placing text on the background while pop-up
+    windows occur.  Text should continue to update normally with
+    or without the popup windows present.
+
+    CONFIG_STM32_BUILDROOT=y      : NuttX buildroot under Linux or Cygwin
+    CONFIG_LCD_RPORTRAIT=y        : 240x320 reverse portrait
+
+    NOTE:  When I tried building this example with the CodeSourcery
+    tools, I got a hardfault inside of its libgcc.  I haven't
+    retested since then, but beware if you choose to change the
+    toolchain.
+
+  ostest:
+  ------
+    This configuration directory, performs a simple OS test using
+    examples/ostest.  By default, this project assumes that you are
+    using the DFU bootloader.
+
+    CONFIG_STM32_BUILDROOT=y      : NuttX buildroot under Linux or Cygwin
+
+  RIDE
+  ----
+    This configuration builds a trivial bring-up binary.  It is
+    useful only because it words with the RIDE7 IDE and R-Link debugger.
+
+    CONFIG_STM32_RAISONANCE=y     : Raisonance RIDE7 under Windows
+
+  usbserial:
+  ---------
+    This configuration directory exercises the USB serial class
+    driver at examples/usbserial.  See examples/README.txt for
+    more information.
+
+    CONFIG_STM32_BUILDROOT=y      : NuttX buildroot under Linux or Cygwin
+
+    USB debug output can be enabled as by changing the following
+    settings in the configuration file:
+
+    -CONFIG_DEBUG=n
+    -CONFIG_DEBUG_VERBOSE=n
+    -CONFIG_DEBUG_USB=n
+    +CONFIG_DEBUG=y
+    +CONFIG_DEBUG_VERBOSE=y
+    +CONFIG_DEBUG_USB=y
+
+    -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n
+    -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n
+    -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n
+    -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n
+    -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
+    +CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=y
+    +CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=y
+    +CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=y
+    +CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=y
+    +CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=y
+
+    By default, the usbserial example uses the Prolific PL2303
+    serial/USB converter emulation.  The example can be modified
+    to use the CDC/ACM serial class by making the following changes
+    to the configuration file:
+
+    -CONFIG_PL2303=y
+    +CONFIG_PL2303=n
+
+    -CONFIG_CDCACM=n
+    +CONFIG_CDCACM=y
+
+    The example can also be converted to use the alternative
+    USB serial example at apps/examples/usbterm by changing the 
+    following:
+
+    -CONFIGURED_APPS += examples/usbserial
+    +CONFIGURED_APPS += examples/usbterm
+
+    In either the original appconfig file (before configuring)
+    or in the final apps/.config file (after configuring).
+
+  usbstorage:
+  ----------
+    This configuration directory exercises the USB mass storage
+    class driver at examples/usbstorage.  See examples/README.txt for
+    more information.
+
+    CONFIG_STM32_BUILDROOT=y      : NuttX buildroot under Linux or Cygwin
+
diff --git a/nuttx/configs/px4io/common/Make.defs b/nuttx/configs/px4io/common/Make.defs
new file mode 100644
index 000000000..a3996a9ed
--- /dev/null
+++ b/nuttx/configs/px4io/common/Make.defs
@@ -0,0 +1,209 @@
+############################################################################
+# configs/px4fmu/common/Make.defs
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+#
+# Generic Make.defs for the PX4FMU
+# Do not specify/use this file directly - it is included by config-specific
+# Make.defs in the per-config directories.
+#
+
+#
+# We only support building with the ARM bare-metal toolchain from
+# https://launchpad.net/gcc-arm-embedded on Windows, Linux or Mac OS.
+#
+
+CROSSDEV		 = arm-none-eabi-
+
+CC			 = $(CROSSDEV)gcc
+CXX			 = $(CROSSDEV)g++
+CPP			 = $(CROSSDEV)gcc -E
+LD			 = $(CROSSDEV)ld
+AR			 = $(CROSSDEV)ar rcs
+NM			 = $(CROSSDEV)nm
+OBJCOPY			 = $(CROSSDEV)objcopy
+OBJDUMP			 = $(CROSSDEV)objdump
+
+MAXOPTIMIZATION		 = -O3
+ARCHCPUFLAGS		 = -mcpu=cortex-m3 \
+			   -mthumb \
+			   -march=armv7-m
+
+# enable precise stack overflow tracking
+#INSTRUMENTATIONDEFINES	 = -finstrument-functions \
+#			   -ffixed-r10
+
+# use our linker script
+LDSCRIPT		 = ld.script
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK		 = $(TOPDIR)/tools/winlink.sh
+  DIRUNLINK		 = $(TOPDIR)/tools/unlink.sh
+  MKDEP			 = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES		 = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES	 = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT		 = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)}"
+else
+  ifeq ($(PX4_WINTOOL),y)
+    # Windows-native toolchains (MSYS)
+    DIRLINK		 = $(TOPDIR)/tools/winlink.sh
+    DIRUNLINK		 = $(TOPDIR)/tools/unlink.sh
+    MKDEP		 = $(TOPDIR)/tools/mknulldeps.sh
+    ARCHINCLUDES	 = -I. -isystem $(TOPDIR)/include
+    ARCHXXINCLUDES	 = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+    ARCHSCRIPT		 = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)
+  else
+    # Linux/Cygwin-native toolchain 
+    MKDEP		 = $(TOPDIR)/tools/mkdeps.sh
+    ARCHINCLUDES	 = -I. -isystem $(TOPDIR)/include
+    ARCHXXINCLUDES	 = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+    ARCHSCRIPT		 = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/$(LDSCRIPT)
+  endif
+endif
+
+# tool versions
+ARCHCCVERSION		 = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR		 = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+# optimisation flags
+ARCHOPTIMIZATION	 = $(MAXOPTIMIZATION) \
+			   -fno-strict-aliasing \
+			   -fno-strength-reduce \
+			   -fomit-frame-pointer \
+   			   -funsafe-math-optimizations \
+   			   -fno-builtin-printf \
+   			   -ffunction-sections \
+   			   -fdata-sections
+
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
+ARCHOPTIMIZATION	+= -g
+ARCHSCRIPT		+= -g
+endif
+
+ARCHCFLAGS		 = -std=gnu99
+ARCHCXXFLAGS		 = -fno-exceptions -fno-rtti -std=gnu++0x
+ARCHWARNINGS		 = -Wall \
+			   -Wextra \
+			   -Wdouble-promotion \
+			   -Wshadow \
+			   -Wfloat-equal \
+			   -Wframe-larger-than=1024 \
+			   -Wpointer-arith \
+			   -Wlogical-op \
+			   -Wmissing-declarations \
+			   -Wpacked \
+			   -Wno-unused-parameter
+#   -Wcast-qual  - generates spurious noreturn attribute warnings, try again later
+#   -Wconversion - would be nice, but too many "risky-but-safe" conversions in the code
+#   -Wcast-align - would help catch bad casts in some cases, but generates too many false positives
+
+ARCHCWARNINGS		 = $(ARCHWARNINGS) \
+			   -Wbad-function-cast \
+			   -Wstrict-prototypes \
+			   -Wold-style-declaration \
+			   -Wmissing-parameter-type \
+			   -Wmissing-prototypes \
+			   -Wnested-externs \
+			   -Wunsuffixed-float-constants
+ARCHWARNINGSXX		 = $(ARCHWARNINGS)
+ARCHDEFINES		 = 
+ARCHPICFLAGS		 = -fpic -msingle-pic-base -mpic-register=r10
+
+# this seems to be the only way to add linker flags
+ARCHSCRIPT		+= --warn-common \
+			   --gc-sections
+
+CFLAGS			 = $(ARCHCFLAGS) $(ARCHCWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -fno-common
+CPICFLAGS		 = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS		 = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS		 = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS		 = $(ARCHINCLUDES) $(INSTRUMENTATIONDEFINES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS			 = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1		 = -r -d -warn-common
+NXFLATLDFLAGS2		 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections
+LDNXFLATFLAGS		 = -e main -s 2048
+
+OBJEXT			 = .o
+LIBEXT			 = .a
+EXEEXT			 =
+
+# If VERBOSE is set, don't hide the compiler invocations.
+ifeq ($(VERBOSE),YES)
+_v				 =
+else
+_v				 = @
+endif
+
+define PREPROCESS
+	@echo "CPP: $1->$2"
+	@$(CPP) $(CPPFLAGS) $(abspath $1) -o $2
+endef
+
+define COMPILE
+	@echo "CC: $1"
+	$(_v)$(CC) -c $(CFLAGS) $(abspath $1) -o $2
+endef
+
+define COMPILEXX
+	@echo "CXX: $1"
+	$(_v)$(CXX) -c $(CXXFLAGS) $(abspath $1) -o $2
+endef
+
+define ASSEMBLE
+	@echo "AS: $1"
+	$(_v)$(CC) -c $(AFLAGS) $(abspath $1) -o $2
+endef
+
+# produce partially-linked $1 from files in $2
+define PRELINK
+	@echo "PRELINK: $1"
+	@$(LD) -Ur -o $1 $2 && $(OBJCOPY) --localize-hidden $1
+endef
+
+define ARCHIVE
+	echo "AR: $2"; \
+	$(AR) $1 $2 || { echo "$(AR) $1 $2 FAILED!" ; exit 1 ; }
+endef
+
+define CLEAN
+	@rm -f *.o *.a
+endef
+
+HOSTCC			 = gcc
+HOSTINCLUDES		 = -I.
+HOSTCFLAGS		 = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS		 =
+
diff --git a/nuttx/configs/px4io/common/ld.script b/nuttx/configs/px4io/common/ld.script
new file mode 100755
index 000000000..17f816acf
--- /dev/null
+++ b/nuttx/configs/px4io/common/ld.script
@@ -0,0 +1,120 @@
+/****************************************************************************
+ * configs/stm3210e-eval/nsh/ld.script
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F100C8 has 64Kb of FLASH beginning at address 0x0800:0000 and
+ * 8Kb of SRAM beginning at address 0x2000:0000.  When booting from FLASH,
+ * FLASH memory is aliased to address 0x0000:0000 where the code expects to
+ * begin execution by jumping to the entry point in the 0x0800:0000 address
+ * range.
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08001000, LENGTH = 60K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(__start)		/* treat __start as the anchor for dead code stripping */
+EXTERN(_vectors)	/* force the vectors to be included in the output */
+
+/* 
+ * Ensure that abort() is present in the final object.  The exception handling
+ * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).
+ */
+EXTERN(abort)
+
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)        
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)        
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	/* The STM32F100CB has 8Kb of SRAM beginning at the following address */
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/nuttx/configs/px4io/common/setenv.sh b/nuttx/configs/px4io/common/setenv.sh
new file mode 100755
index 000000000..d83685192
--- /dev/null
+++ b/nuttx/configs/px4io/common/setenv.sh
@@ -0,0 +1,47 @@
+#!/bin/bash
+# configs/stm3210e-eval/dfu/setenv.sh
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$(basename $0)" = "setenv.sh" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi
+
+WD=`pwd`
+export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin"
+export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/nuttx/configs/px4io/include/README.txt b/nuttx/configs/px4io/include/README.txt
new file mode 100755
index 000000000..2264a80aa
--- /dev/null
+++ b/nuttx/configs/px4io/include/README.txt
@@ -0,0 +1 @@
+This directory contains header files unique to the PX4IO board.
diff --git a/nuttx/configs/px4io/include/board.h b/nuttx/configs/px4io/include/board.h
new file mode 100755
index 000000000..cd4d48649
--- /dev/null
+++ b/nuttx/configs/px4io/include/board.h
@@ -0,0 +1,167 @@
+/************************************************************************************
+ * configs/px4io/include/board.h
+ * include/arch/board/board.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_BOARD_BOARD_H
+#define __ARCH_BOARD_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <stdbool.h>
+#endif
+#include "stm32_rcc.h"
+#include "stm32_sdio.h"
+#include "stm32_internal.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+
+/* On-board crystal frequency is 24MHz (HSE) */
+
+#define STM32_BOARD_XTAL        24000000ul
+
+/* Use the HSE output as the system clock */
+
+#define STM32_SYSCLK_SW         RCC_CFGR_SW_HSE
+#define STM32_SYSCLK_SWS        RCC_CFGR_SWS_HSE
+#define STM32_SYSCLK_FREQUENCY  STM32_BOARD_XTAL
+
+/* AHB clock (HCLK) is SYSCLK (24MHz) */
+
+#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK
+#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY    /* same as above, to satisfy compiler */
+
+/* APB2 clock (PCLK2) is HCLK (24MHz) */
+
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_APB2_CLKIN        (STM32_PCLK2_FREQUENCY)   /* Timers 2-4 */
+
+/* APB2 timer 1 will receive PCLK2. */
+
+#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
+
+/* APB1 clock (PCLK1) is HCLK (24MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY)
+
+/* All timers run off PCLK */
+
+#define STM32_APB1_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (STM32_PCLK1_FREQUENCY)
+
+/* 
+ * High-resolution timer
+ */
+#ifdef CONFIG_HRT_TIMER
+# define HRT_TIMER		1	/* use timer1 for the HRT */
+# define HRT_TIMER_CHANNEL	2	/* use capture/compare channel 2 */
+#endif
+
+/*
+ * PPM
+ *
+ * PPM input is handled by the HRT timer.
+ *
+ * Pin is PA8, timer 1, channel 1
+ */
+#if defined(CONFIG_HRT_TIMER) && defined (CONFIG_HRT_PPM)
+# define HRT_PPM_CHANNEL	1	/* use capture/compare channel 1 */
+# define GPIO_PPM_IN		GPIO_TIM1_CH1IN
+#endif
+
+/*
+ * PWM
+ *
+ * PWM configuration is provided via the configuration structure in up_boardinitialize.c
+ */
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the intitialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+EXTERN void stm32_boardinitialize(void);
+
+/************************************************************************************
+ * Power switch support.
+ */
+extern void up_power_init(void);
+extern void up_power_set(int port, bool state);
+extern bool up_power_error(int port);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif  /* __ARCH_BOARD_BOARD_H */
diff --git a/nuttx/configs/px4io/include/drv_gpio.h b/nuttx/configs/px4io/include/drv_gpio.h
new file mode 100644
index 000000000..329d2bacf
--- /dev/null
+++ b/nuttx/configs/px4io/include/drv_gpio.h
@@ -0,0 +1,67 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file GPIO driver for PX4IO
+ */
+
+#include <sys/ioctl.h>
+
+#define _GPIO_IOCTL_BASE	0x7700
+
+#define GPIO_SET(_x)		_IOC(_GPIO_IOCTL_BASE, _x)
+#define GPIO_GET(_x)		_IOC(_GPIO_IOCTL_BASE + 1, _x)
+
+/*
+ * List of GPIOs; must be sorted with settable GPIOs first.
+ */
+#define GPIO_ACC1_POWER		0	/* settable */
+#define GPIO_ACC2_POWER		1
+#define GPIO_SERVO_POWER	2
+#define GPIO_RELAY1		3
+#define GPIO_RELAY2		4
+#define GPIO_LED_BLUE		5
+#define GPIO_LED_AMBER		6
+#define GPIO_LED_SAFETY		7
+
+#define GPIO_ACC_OVERCURRENT	8	/* readonly */
+#define GPIO_SERVO_OVERCURRENT	9
+#define GPIO_SAFETY_BUTTON	10
+
+#define GPIO_MAX_SETTABLE	7
+#define GPIO_MAX		10
+
+/*
+ * GPIO driver init function.
+ */
+extern int gpio_drv_init(void);
diff --git a/nuttx/configs/px4io/include/drv_i2c_device.h b/nuttx/configs/px4io/include/drv_i2c_device.h
new file mode 100644
index 000000000..02582bc09
--- /dev/null
+++ b/nuttx/configs/px4io/include/drv_i2c_device.h
@@ -0,0 +1,42 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+ /**
+  * @file A simple, polled I2C slave-mode driver.
+  *
+  * The master writes to and reads from a byte buffer, which the caller 
+  * can update inbetween calls to the FSM.
+  */
+
+extern void	i2c_fsm_init(uint8_t *buffer, size_t buffer_size);
+extern bool	i2c_fsm(void);
diff --git a/nuttx/configs/px4io/include/drv_ppm_input.h b/nuttx/configs/px4io/include/drv_ppm_input.h
new file mode 100644
index 000000000..78c424154
--- /dev/null
+++ b/nuttx/configs/px4io/include/drv_ppm_input.h
@@ -0,0 +1,100 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file PPM input decoder.
+ *
+ * Works in conjunction with the HRT driver, exports a device node
+ * and a message queue (if message queues are enabled).
+ *
+ * Note that the device node supports both blocking and non-blocking
+ * opens, but actually never blocks.  A nonblocking open will return
+ * EWOULDBLOCK if there has not been an update since the last read,
+ * while a blocking open will always return the most recent data.
+ */
+
+#include <sys/ioctl.h>
+
+#define _PPM_INPUT_BASE		0x7600
+
+/*
+ * Fetch the state of the PPM input detector.
+ */
+#define PPM_INPUT_STATUS	_IOC(_PPM_INPUT_BASE, 0)
+
+typedef enum {
+	PPM_STATUS_NO_SIGNAL		= 0,
+	PPM_STATUS_SIGNAL_CURRENT	= 1,
+} ppm_input_status_t;
+
+/*
+ * Fetch the number of channels decoded (only valid when PPM_STATUS_SIGNAL_CURRENT).
+ */
+#define PPM_INPUT_CHANNELS	_IOC(_PPM_INPUT_BASE, 1)
+
+typedef int ppm_input_channel_count_t;
+
+/*
+ * Device node
+ */
+#define PPM_DEVICE_NODE		"/dev/ppm_input"
+
+/*
+ * Message queue; if message queues are supported, PPM input data is
+ * supplied to the queue when a frame is decoded.
+ */
+#ifndef CONFIG_DISABLE_MQUEUE
+# define PPM_MESSAGE_QUEUE	"ppm_input"
+#endif
+
+/* 
+ * Private hook from the HRT driver to the PPM decoder.
+ *
+ * This function is called for every edge of the incoming PPM
+ * signal.
+ *
+ * @param reset		If true, the decoder should be reset (e.g.)
+ *			capture failure was detected.
+ * @param count		The counter value at which the edge
+ *			was captured.
+ */
+
+void	ppm_input_decode(bool reset, uint16_t count);
+
+/*
+ * PPM input initialisation function.
+ *
+ * If message queues are enabled, and mq_name is not NULL, received input
+ * is posted to the message queue as an array of 16-bit unsigned channel values.
+ */
+int	ppm_input_init(const char *mq_name);
\ No newline at end of file
diff --git a/nuttx/configs/px4io/include/drv_pwm_servo.h b/nuttx/configs/px4io/include/drv_pwm_servo.h
new file mode 100644
index 000000000..663468404
--- /dev/null
+++ b/nuttx/configs/px4io/include/drv_pwm_servo.h
@@ -0,0 +1,94 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file PWM servo driver.
+ *
+ * The pwm_servo driver supports servos connected to STM32 timer
+ * blocks.
+ *
+ * Servo values can be set either with the PWM_SERVO_SET ioctl, or
+ * by writing an array of servo_position_t values to the device.
+ * Writing a value of 0 to a channel suppresses any output for that
+ * channel.
+ *
+ * Servo values can be read back either with the PWM_SERVO_GET
+ * ioctl, or by reading an array of servo_position_t values
+ * from the device.
+ *
+ * Attempts to set a channel that is not configured are ignored,
+ * and unconfigured channels always read zero.
+ *
+ * The PWM_SERVO_ARM / PWM_SERVO_DISARM calls globally arm
+ * (enable) and disarm (disable) all servo outputs.
+ */
+
+#include <sys/ioctl.h>
+
+#define _PWM_SERVO_BASE		0x7500
+#define PWM_SERVO_ARM		_IOC(_PWM_SERVO_BASE, 0)
+#define PWM_SERVO_DISARM	_IOC(_PWM_SERVO_BASE, 1)
+
+#define PWM_SERVO_SET(_servo)	_IOC(_PWM_SERVO_BASE, 0x20 + _servo)
+#define PWM_SERVO_GET(_servo)	_IOC(_PWM_SERVO_BASE, 0x40 + _servo)
+
+typedef uint16_t	servo_position_t;
+
+/* configuration limits */
+#define PWM_SERVO_MAX_TIMERS	3
+#define PWM_SERVO_MAX_CHANNELS	8
+
+struct pwm_servo_config {
+	/* rate (in Hz) of PWM updates */
+	uint32_t	update_rate;
+
+	/* array of timers dedicated to PWM servo use */
+	struct pwm_servo_timer {
+		uint32_t	base;
+		uint32_t	clock_register;
+		uint32_t	clock_bit;
+		uint32_t	clock_freq;
+	} timers[PWM_SERVO_MAX_TIMERS];
+
+	/* array of channels in logical order */
+	struct pwm_servo_channel {
+		uint32_t	gpio;
+		uint8_t		timer_index;
+		uint8_t		timer_channel;
+		servo_position_t default_value;
+	} channels[PWM_SERVO_MAX_CHANNELS];
+};
+
+extern int	pwm_servo_init(const struct pwm_servo_config *config);
+
+
diff --git a/nuttx/configs/px4io/include/up_boardinitialize.h b/nuttx/configs/px4io/include/up_boardinitialize.h
new file mode 100755
index 000000000..01b9ca214
--- /dev/null
+++ b/nuttx/configs/px4io/include/up_boardinitialize.h
@@ -0,0 +1,43 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file Board initialisation prototype(s)
+ */
+
+#ifndef __UP_BOARDINITIALIZE_H
+#define __UP_BOARDINITIALIZE_H
+
+extern int up_boardinitialize(void);
+
+#endif
diff --git a/nuttx/configs/px4io/include/up_hrt.h b/nuttx/configs/px4io/include/up_hrt.h
new file mode 100644
index 000000000..c83f14ac3
--- /dev/null
+++ b/nuttx/configs/px4io/include/up_hrt.h
@@ -0,0 +1,129 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file High-resolution timer callouts and timekeeping.
+ */
+
+#ifndef UP_HRT_H_
+#define UP_HRT_H_
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <time.h>
+#include <queue.h>
+
+/*
+ * Absolute time, in microsecond units.
+ *
+ * Absolute time is measured from some arbitrary epoch shortly after
+ * system startup.  It should never wrap or go backwards.
+ */
+typedef uint64_t	hrt_abstime;
+
+/*
+ * Callout function type.
+ *
+ * Note that callouts run in the timer interrupt context, so
+ * they are serialised with respect to each other, and must not
+ * block.
+ */
+typedef void		(* hrt_callout)(void *arg);
+
+/*
+ * Callout record.
+ */
+struct hrt_call {
+	struct sq_entry_s	link;
+
+	hrt_abstime		deadline;
+	hrt_abstime		period;
+	hrt_callout		callout;
+	void			*arg;
+};
+
+/*
+ * Get absolute time.
+ */
+extern hrt_abstime hrt_absolute_time(void);
+
+/*
+ * Convert a timespec to absolute time.
+ */
+extern hrt_abstime ts_to_abstime(struct timespec *ts);
+
+/*
+ * Convert absolute time to a timespec.
+ */
+extern void	abstime_to_ts(struct timespec *ts, hrt_abstime abstime);
+
+/*
+ * Call callout(arg) after delay has elapsed.
+ *
+ * If callout is NULL, this can be used to implement a timeout by testing the call
+ * with hrt_called().
+ */
+extern void	hrt_call_after(struct hrt_call *entry, hrt_abstime delay, hrt_callout callout, void *arg);
+
+/*
+ * Call callout(arg) at absolute time calltime.
+ */
+extern void	hrt_call_at(struct hrt_call *entry, hrt_abstime calltime, hrt_callout callout, void *arg);
+
+/*
+ * Call callout(arg) after delay, and then after every interval.
+ *
+ * Note thet the interval is timed between scheduled, not actual, call times, so the call rate may
+ * jitter but should not drift.
+ */
+extern void	hrt_call_every(struct hrt_call *entry, hrt_abstime delay, hrt_abstime interval, hrt_callout callout, void *arg);
+
+/*
+ * If this returns true, the entry has been invoked and removed from the callout list.
+ *
+ * Always returns false for repeating callouts.
+ */
+extern bool	hrt_called(struct hrt_call *entry);
+
+/*
+ * Remove the entry from the callout list.
+ */
+extern void	hrt_cancel(struct hrt_call *entry);
+
+/*
+ * Initialise the HRT.
+ */
+extern void	hrt_init(int timer);
+
+#endif /* UP_HRT_H_ */
diff --git a/nuttx/configs/px4io/io/Make.defs b/nuttx/configs/px4io/io/Make.defs
new file mode 100644
index 000000000..87508e22e
--- /dev/null
+++ b/nuttx/configs/px4io/io/Make.defs
@@ -0,0 +1,3 @@
+include ${TOPDIR}/.config
+
+include $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/Make.defs
diff --git a/nuttx/configs/px4io/io/appconfig b/nuttx/configs/px4io/io/appconfig
new file mode 100644
index 000000000..94176c6dc
--- /dev/null
+++ b/nuttx/configs/px4io/io/appconfig
@@ -0,0 +1,39 @@
+############################################################################
+# configs/stm3210e-eval/nsh/appconfig
+#
+#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Path to px4io app containing the user_start entry point
+
+CONFIGURED_APPS += px4io
+CONFIGURED_APPS += systemlib
diff --git a/nuttx/configs/px4io/io/defconfig b/nuttx/configs/px4io/io/defconfig
new file mode 100755
index 000000000..8ae6afe3c
--- /dev/null
+++ b/nuttx/configs/px4io/io/defconfig
@@ -0,0 +1,517 @@
+############################################################################
+# configs/px4io/nsh/defconfig
+#
+#   Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+#
+# architecture selection
+#
+# CONFIG_ARCH - identifies the arch subdirectory and, hence, the
+#   processor architecture.
+# CONFIG_ARCH_family - for use in C code.  This identifies the
+#   particular chip family that the architecture is implemented
+#   in.
+# CONFIG_ARCH_architecture - for use in C code.  This identifies the
+#   specific architecture within the chip familyl.
+# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+# CONFIG_ARCH_CHIP_name - For use in C code
+# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
+#   the board that supports the particular chip or SoC.
+# CONFIG_ARCH_BOARD_name - for use in C code
+# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
+# CONFIG_BOARD_LOOPSPERMSEC - for delay loops
+# CONFIG_DRAM_SIZE - Describes the installed DRAM.
+# CONFIG_DRAM_START - The start address of DRAM (physical)
+# CONFIG_DRAM_END - Last address+1 of installed RAM
+# CONFIG_ARCH_IRQPRIO - The ST32F100CB supports interrupt prioritization
+# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+#   stack. If defined, this symbol is the size of the interrupt
+#   stack in bytes.  If not defined, the user task stacks will be
+#   used during interrupt handling.
+# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+# CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
+# CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS -  Enable support for buttons. Unique to board architecture.
+# CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+#   cause a 100 second delay during boot-up.  This 100 second delay
+#   serves no purpose other than it allows you to calibrate
+#   CONFIG_BOARD_LOOPSPERMSEC.  You simply use a stop watch to measure
+#   the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
+#   the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
+#
+CONFIG_ARCH=arm
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_CORTEXM3=y
+CONFIG_ARCH_CHIP=stm32
+CONFIG_ARCH_CHIP_STM32F100C8=y
+CONFIG_ARCH_BOARD=px4io
+CONFIG_ARCH_BOARD_PX4IO=y
+CONFIG_BOARD_LOOPSPERMSEC=2000
+CONFIG_DRAM_SIZE=0x00002000
+CONFIG_DRAM_START=0x20000000
+CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+CONFIG_ARCH_IRQPRIO=y
+CONFIG_ARCH_INTERRUPTSTACK=n
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_BOOTLOADER=n
+CONFIG_ARCH_LEDS=n
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=n
+CONFIG_ARMV7M_CMNVECTOR=y
+
+#
+# JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+#
+#   CONFIG_STM32_DFU - Use the DFU bootloader, not JTAG
+#
+# JTAG Enable options:
+#
+#   CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+#   CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+#     but without JNTRST.
+#   CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+#
+CONFIG_STM32_DFU=n
+CONFIG_STM32_JTAG_FULL_ENABLE=y
+CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n
+CONFIG_STM32_JTAG_SW_ENABLE=n
+
+#
+# Individual subsystems can be enabled:
+# AHB: 
+CONFIG_STM32_DMA1=n
+CONFIG_STM32_DMA2=n
+CONFIG_STM32_CRC=n
+# APB1:
+# Timers 2,3 and 4 are owned by the PWM driver
+CONFIG_STM32_TIM2=n
+CONFIG_STM32_TIM3=n
+CONFIG_STM32_TIM4=n
+CONFIG_STM32_TIM5=n
+CONFIG_STM32_TIM6=n
+CONFIG_STM32_TIM7=n
+CONFIG_STM32_WWDG=n
+CONFIG_STM32_SPI2=n
+CONFIG_STM32_USART2=y
+CONFIG_STM32_USART3=n
+CONFIG_STM32_I2C1=y
+CONFIG_STM32_I2C2=n
+CONFIG_STM32_BKP=n
+CONFIG_STM32_PWR=n
+CONFIG_STM32_DAC=n
+# APB2:
+CONFIG_STM32_ADC1=y
+CONFIG_STM32_ADC2=n
+# TIM1 is owned by the HRT
+CONFIG_STM32_TIM1=n
+CONFIG_STM32_SPI1=n
+CONFIG_STM32_TIM8=n
+CONFIG_STM32_USART1=y
+CONFIG_STM32_ADC3=n
+
+#
+# Timer and I2C devices may need to the following to force power to be applied:
+#
+#CONFIG_STM32_FORCEPOWER=y
+
+#
+# STM32F100 specific serial device driver settings
+#
+# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the
+#   console and ttys0 (default is the USART1).
+# CONFIG_USARTn_RXBUFSIZE - Characters are buffered as received.
+#   This specific the size of the receive buffer
+# CONFIG_USARTn_TXBUFSIZE - Characters are buffered before
+#   being sent.  This specific the size of the transmit buffer
+# CONFIG_USARTn_BAUD - The configure BAUD of the UART.  Must be
+# CONFIG_USARTn_BITS - The number of bits.  Must be either 7 or 8.
+# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+# CONFIG_USARTn_2STOP - Two stop bits
+#
+CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_USART2_SERIAL_CONSOLE=n
+CONFIG_USART3_SERIAL_CONSOLE=n
+
+CONFIG_USART1_TXBUFSIZE=32
+CONFIG_USART2_TXBUFSIZE=32
+CONFIG_USART3_TXBUFSIZE=32
+
+CONFIG_USART1_RXBUFSIZE=32
+CONFIG_USART2_RXBUFSIZE=32
+CONFIG_USART3_RXBUFSIZE=32
+
+CONFIG_USART1_BAUD=57600
+CONFIG_USART2_BAUD=115200
+CONFIG_USART3_BAUD=115200
+
+CONFIG_USART1_BITS=8
+CONFIG_USART2_BITS=8
+CONFIG_USART3_BITS=8
+
+CONFIG_USART1_PARITY=0
+CONFIG_USART2_PARITY=0
+CONFIG_USART3_PARITY=0
+
+CONFIG_USART1_2STOP=0
+CONFIG_USART2_2STOP=0
+CONFIG_USART3_2STOP=0
+
+#
+# PX4IO specific driver settings
+#
+# CONFIG_HRT_TIMER
+#   Enables the high-resolution timer.  The board definition must
+#   set HRT_TIMER and HRT_TIMER_CHANNEL to the timer and capture/
+#   compare channels to be used.
+# CONFIG_HRT_PPM
+#   Enables R/C PPM input using the HRT.  The board definition must
+#   set HRT_PPM_CHANNEL to the timer capture/compare channel to be
+#   used, and define GPIO_PPM_IN to configure the appropriate timer
+#   GPIO.
+# CONFIG_PWM_SERVO
+#   Enables the PWM servo driver.  The driver configuration must be
+#   supplied by the board support at initialisation time.
+#   Note that USART2 must be disabled on the PX4 board for this to
+#   be available.
+#
+#
+CONFIG_HRT_TIMER=y
+CONFIG_HRT_PPM=y
+CONFIG_PWM_SERVO=y
+
+#
+# General build options
+#
+# CONFIG_RRLOAD_BINARY - make the rrload binary format used with
+#   BSPs from www.ridgerun.com using the tools/mkimage.sh script
+# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format
+#   used with many different loaders using the GNU objcopy program
+#   Should not be selected if you are not using the GNU toolchain.
+# CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format
+#   used with many different loaders using the GNU objcopy program
+#   Should not be selected if you are not using the GNU toolchain.
+# CONFIG_RAW_BINARY - make a raw binary format file used with many
+#   different loaders using the GNU objcopy program.  This option
+#   should not be selected if you are not using the GNU toolchain.
+# CONFIG_HAVE_LIBM - toolchain supports libm.a
+#
+CONFIG_RRLOAD_BINARY=n
+CONFIG_INTELHEX_BINARY=n
+CONFIG_MOTOROLA_SREC=n
+CONFIG_RAW_BINARY=y
+CONFIG_HAVE_LIBM=n
+
+#
+# General OS setup
+#
+# CONFIG_APPS_DIR - Identifies the relative path to the directory
+#   that builds the application to link with NuttX.  Default: ../apps
+# CONFIG_DEBUG - enables built-in debug options
+# CONFIG_DEBUG_VERBOSE - enables verbose debug output
+# CONFIG_DEBUG_SYMBOLS - build without optimization and with
+#   debug symbols (needed for use with a debugger).
+# CONFIG_HAVE_CXX - Enable support for C++
+# CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support
+#   for initialization of static C++ instances for this architecture
+#   and for the selected toolchain (via up_cxxinitialize()).
+# CONFIG_MM_REGIONS - If the architecture includes multiple
+#   regions of memory to allocate from, this specifies the
+#   number of memory regions that the memory manager must
+#   handle and enables the API mm_addregion(start, end);
+# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot
+#   time console output
+# CONFIG_MSEC_PER_TICK - The default system timer is 100Hz
+#   or MSEC_PER_TICK=10.  This setting may be defined to
+#   inform NuttX that the processor hardware is providing
+#   system timer interrupts at some interrupt interval other
+#   than 10 msec.
+# CONFIG_RR_INTERVAL - The round robin timeslice will be set
+#   this number of milliseconds;  Round robin scheduling can
+#   be disabled by setting this value to zero.
+# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in 
+#   scheduler to monitor system performance
+# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a
+#   task name to save in the TCB.  Useful if scheduler
+#   instrumentation is selected.  Set to zero to disable.
+# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY -
+#   Used to initialize the internal time logic.
+# CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions.
+#   You would only need this if you are concerned about accurate
+#   time conversions in the past or in the distant future.
+# CONFIG_JULIAN_TIME - Enables Julian time conversions. You
+#   would only need this if you are concerned about accurate
+#   time conversion in the distand past.  You must also define
+#   CONFIG_GREGORIAN_TIME in order to use Julian time.
+# CONFIG_DEV_CONSOLE - Set if architecture-specific logic
+#   provides /dev/console.  Enables stdout, stderr, stdin.
+# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console
+#   driver (minimul support)
+# CONFIG_MUTEX_TYPES: Set to enable support for recursive and
+#   errorcheck mutexes. Enables pthread_mutexattr_settype().
+# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority
+#   inheritance on mutexes and semaphores. 
+# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority
+#   inheritance is enabled.  It defines the maximum number of
+#   different threads (minus one) that can take counts on a
+#   semaphore with priority inheritance support.  This may be 
+#   set to zero if priority inheritance is disabled OR if you
+#   are only using semaphores as mutexes (only one holder) OR
+#   if no more than two threads participate using a counting
+#   semaphore.
+# CONFIG_SEM_NNESTPRIO.  If priority inheritance is enabled,
+#   then this setting is the maximum number of higher priority
+#   threads (minus 1) than can be waiting for another thread
+#   to release a count on a semaphore.  This value may be set
+#   to zero if no more than one thread is expected to wait for
+#   a semaphore.
+# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors
+#   by task_create() when a new task is started.  If set, all
+#   files/drivers will appear to be closed in the new task.
+# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first
+#   three file descriptors (stdin, stdout, stderr) by task_create()
+#   when a new task is started. If set, all files/drivers will
+#   appear to be closed in the new task except for stdin, stdout,
+#   and stderr.
+# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket
+#   desciptors by task_create() when a new task is started. If
+#   set, all sockets will appear to be closed in the new task.
+# CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
+#  This format will support execution of NuttX binaries located
+#  in a ROMFS filesystem (see examples/nxflat).
+# CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+#  handle delayed processing from interrupt handlers.  This feature
+#  is required for some drivers but, if there are not complaints,
+#  can be safely disabled.  The worker thread also performs
+#  garbage collection -- completing any delayed memory deallocations
+#  from interrupt handlers.  If the worker thread is disabled,
+#  then that clean will be performed by the IDLE thread instead
+#  (which runs at the lowest of priority and may not be appropriate
+#  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+#  is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+#  thread.  Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+#  work in units of microseconds.  Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+#  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+#  the worker thread.  Default: 4
+#
+#CONFIG_APPS_DIR=
+CONFIG_DEBUG=n
+CONFIG_DEBUG_VERBOSE=n
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_HAVE_CXX=n
+CONFIG_HAVE_CXXINITIALIZE=n
+CONFIG_MM_REGIONS=1
+CONFIG_MM_SMALL=y
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_INSTRUMENTATION=n
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_START_YEAR=2009
+CONFIG_START_MONTH=9
+CONFIG_START_DAY=21
+CONFIG_GREGORIAN_TIME=n
+CONFIG_JULIAN_TIME=n
+CONFIG_DEV_CONSOLE=y
+CONFIG_DEV_LOWCONSOLE=n
+CONFIG_MUTEX_TYPES=n
+CONFIG_PRIORITY_INHERITANCE=n
+CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_NNESTPRIO=0
+CONFIG_FDCLONE_DISABLE=n
+CONFIG_FDCLONE_STDIO=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NXFLAT=n
+CONFIG_SCHED_WORKQUEUE=n
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SIG_SIGWORK=4
+
+#
+# The following can be used to disable categories of
+# APIs supported by the OS.  If the compiler supports
+# weak functions, then it should not be necessary to
+# disable functions unless you want to restrict usage
+# of those APIs.
+#
+# There are certain dependency relationships in these
+# features.
+#
+# o mq_notify logic depends on signals to awaken tasks
+#   waiting for queues to become full or empty.
+# o pthread_condtimedwait() depends on signals to wake
+#   up waiting tasks.
+#
+CONFIG_DISABLE_CLOCK=n
+CONFIG_DISABLE_POSIX_TIMERS=y
+CONFIG_DISABLE_PTHREAD=y
+CONFIG_DISABLE_SIGNALS=y
+CONFIG_DISABLE_MQUEUE=n
+CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_DISABLE_ENVIRON=y
+CONFIG_DISABLE_POLL=y
+
+#
+# Misc libc settings
+#
+# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a
+#   little smaller if we do not support fieldwidthes
+#
+CONFIG_NOPRINTF_FIELDWIDTH=n
+
+#
+# Allow for architecture optimized implementations
+#
+# The architecture can provide optimized versions of the
+# following to improve system performance
+#
+CONFIG_ARCH_MEMCPY=n
+CONFIG_ARCH_MEMCMP=n
+CONFIG_ARCH_MEMMOVE=n
+CONFIG_ARCH_MEMSET=n
+CONFIG_ARCH_STRCMP=n
+CONFIG_ARCH_STRCPY=n
+CONFIG_ARCH_STRNCPY=n
+CONFIG_ARCH_STRLEN=n
+CONFIG_ARCH_STRNLEN=n
+CONFIG_ARCH_BZERO=n
+
+#
+# Sizes of configurable things (0 disables)
+#
+# CONFIG_MAX_TASKS - The maximum number of simultaneously
+#   active tasks.  This value must be a power of two.
+# CONFIG_MAX_TASK_ARGS - This controls the maximum number of
+#   of parameters that a task may receive (i.e., maxmum value
+#   of 'argc')
+# CONFIG_NPTHREAD_KEYS - The number of items of thread-
+#   specific data that can be retained
+# CONFIG_NFILE_DESCRIPTORS - The maximum number of file
+#   descriptors (one for each open)
+# CONFIG_NFILE_STREAMS - The maximum number of streams that
+#   can be fopen'ed
+# CONFIG_NAME_MAX - The maximum size of a file name.
+# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate
+#   on fopen. (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_NUNGET_CHARS - Number of characters that can be
+#   buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message
+#   structures.  The system manages a pool of preallocated
+#   message structures to minimize dynamic allocations
+# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with
+#   a fixed payload size given by this settin (does not include
+#   other message structure overhead.
+# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that
+#   can be passed to a watchdog handler
+# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog
+#   structures.  The system manages a pool of preallocated
+#   watchdog structures to minimize dynamic allocations
+# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX
+#   timer structures.  The system manages a pool of preallocated
+#   timer structures to minimize dynamic allocations.  Set to
+#   zero for all dynamic allocations.
+#
+CONFIG_MAX_TASKS=8
+CONFIG_MAX_TASK_ARGS=4
+CONFIG_NPTHREAD_KEYS=4
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=0
+CONFIG_NAME_MAX=32
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_NUNGET_CHARS=2
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PREALLOC_TIMERS=0
+
+
+#
+# Settings for apps/nshlib
+#
+# CONFIG_NSH_BUILTIN_APPS - Support external registered,
+#   "named" applications that can be executed from the NSH
+#   command line (see apps/README.txt for more information).
+# CONFIG_NSH_FILEIOSIZE - Size of a static I/O buffer
+# CONFIG_NSH_STRERROR - Use strerror(errno)
+# CONFIG_NSH_LINELEN - Maximum length of one command line
+# CONFIG_NSH_NESTDEPTH - Max number of nested if-then[-else]-fi
+# CONFIG_NSH_DISABLESCRIPT - Disable scripting support
+# CONFIG_NSH_DISABLEBG - Disable background commands
+# CONFIG_NSH_ROMFSETC - Use startup script in /etc
+# CONFIG_NSH_CONSOLE - Use serial console front end
+# CONFIG_NSH_TELNET - Use telnetd console front end
+# CONFIG_NSH_ARCHINIT - Platform provides architecture
+#   specific initialization (nsh_archinitialize()).
+#
+
+# Disable NSH completely
+CONFIG_NSH_CONSOLE=n
+
+#
+# Stack and heap information
+#
+# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP
+#   operation from FLASH but must copy initialized .data sections to RAM.
+#   (should also be =n for the STM3210E-EVAL which always runs from flash)
+# CONFIG_BOOT_COPYTORAM -  Some configurations boot in FLASH
+#   but copy themselves entirely into RAM for better performance.
+# CONFIG_CUSTOM_STACK - The up_ implementation will handle
+#   all stack operations outside of the nuttx model.
+# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only)
+# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack.
+#  This is the thread that (1) performs the inital boot of the system up
+#  to the point where user_start() is spawned, and (2) there after is the
+#  IDLE thread that executes only when there is no other thread ready to
+#  run.
+# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate
+#  for the main user thread that begins at the user_start() entry point.
+# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size
+# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size
+# CONFIG_HEAP_BASE - The beginning of the heap
+# CONFIG_HEAP_SIZE - The size of the heap
+#
+CONFIG_BOOT_RUNFROMFLASH=n
+CONFIG_BOOT_COPYTORAM=n
+CONFIG_CUSTOM_STACK=n
+CONFIG_STACK_POINTER=
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=1024
+CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_PTHREAD_STACK_DEFAULT=1024
+CONFIG_HEAP_BASE=
+CONFIG_HEAP_SIZE=
diff --git a/nuttx/configs/px4io/io/setenv.sh b/nuttx/configs/px4io/io/setenv.sh
new file mode 100755
index 000000000..d83685192
--- /dev/null
+++ b/nuttx/configs/px4io/io/setenv.sh
@@ -0,0 +1,47 @@
+#!/bin/bash
+# configs/stm3210e-eval/dfu/setenv.sh
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$(basename $0)" = "setenv.sh" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi
+
+WD=`pwd`
+export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin"
+export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/nuttx/configs/px4io/nsh/Make.defs b/nuttx/configs/px4io/nsh/Make.defs
new file mode 100644
index 000000000..87508e22e
--- /dev/null
+++ b/nuttx/configs/px4io/nsh/Make.defs
@@ -0,0 +1,3 @@
+include ${TOPDIR}/.config
+
+include $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/common/Make.defs
diff --git a/nuttx/configs/px4io/nsh/appconfig b/nuttx/configs/px4io/nsh/appconfig
new file mode 100644
index 000000000..d5809a939
--- /dev/null
+++ b/nuttx/configs/px4io/nsh/appconfig
@@ -0,0 +1,43 @@
+############################################################################
+# configs/stm3210e-eval/nsh/appconfig
+#
+#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Path to example in apps/examples containing the user_start entry point
+
+CONFIGURED_APPS += examples/nsh
+
+CONFIGURED_APPS += system/readline
+CONFIGURED_APPS += nshlib
+CONFIGURED_APPS += reboot
+
diff --git a/nuttx/configs/px4io/nsh/defconfig b/nuttx/configs/px4io/nsh/defconfig
new file mode 100755
index 000000000..6f4e20869
--- /dev/null
+++ b/nuttx/configs/px4io/nsh/defconfig
@@ -0,0 +1,565 @@
+############################################################################
+# configs/px4io/nsh/defconfig
+#
+#   Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+#
+# architecture selection
+#
+# CONFIG_ARCH - identifies the arch subdirectory and, hence, the
+#   processor architecture.
+# CONFIG_ARCH_family - for use in C code.  This identifies the
+#   particular chip family that the architecture is implemented
+#   in.
+# CONFIG_ARCH_architecture - for use in C code.  This identifies the
+#   specific architecture within the chip familyl.
+# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+# CONFIG_ARCH_CHIP_name - For use in C code
+# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
+#   the board that supports the particular chip or SoC.
+# CONFIG_ARCH_BOARD_name - for use in C code
+# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
+# CONFIG_BOARD_LOOPSPERMSEC - for delay loops
+# CONFIG_DRAM_SIZE - Describes the installed DRAM.
+# CONFIG_DRAM_START - The start address of DRAM (physical)
+# CONFIG_DRAM_END - Last address+1 of installed RAM
+# CONFIG_ARCH_IRQPRIO - The ST32F100CB supports interrupt prioritization
+# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+#   stack. If defined, this symbol is the size of the interrupt
+#   stack in bytes.  If not defined, the user task stacks will be
+#   used during interrupt handling.
+# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+# CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
+# CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS -  Enable support for buttons. Unique to board architecture.
+# CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+#   cause a 100 second delay during boot-up.  This 100 second delay
+#   serves no purpose other than it allows you to calibrate
+#   CONFIG_BOARD_LOOPSPERMSEC.  You simply use a stop watch to measure
+#   the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
+#   the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
+#
+CONFIG_ARCH=arm
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_CORTEXM3=y
+CONFIG_ARCH_CHIP=stm32
+CONFIG_ARCH_CHIP_STM32F100C8=y
+CONFIG_ARCH_BOARD=px4io
+CONFIG_ARCH_BOARD_PX4IO=y
+CONFIG_BOARD_LOOPSPERMSEC=24000
+CONFIG_DRAM_SIZE=0x00002000
+CONFIG_DRAM_START=0x20000000
+CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+CONFIG_ARCH_IRQPRIO=y
+CONFIG_ARCH_INTERRUPTSTACK=n
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_BOOTLOADER=n
+CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=n
+CONFIG_ARMV7M_CMNVECTOR=y
+
+#
+# JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+#
+#   CONFIG_STM32_DFU - Use the DFU bootloader, not JTAG
+#
+# JTAG Enable options:
+#
+#   CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+#   CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+#     but without JNTRST.
+#   CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+#
+CONFIG_STM32_DFU=n
+CONFIG_STM32_JTAG_FULL_ENABLE=y
+CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n
+CONFIG_STM32_JTAG_SW_ENABLE=n
+
+#
+# Individual subsystems can be enabled:
+# AHB: 
+CONFIG_STM32_DMA1=n
+CONFIG_STM32_DMA2=n
+CONFIG_STM32_CRC=n
+# APB1:
+# Timers 2,3 and 4 are owned by the PWM driver
+CONFIG_STM32_TIM2=n
+CONFIG_STM32_TIM3=n
+CONFIG_STM32_TIM4=n
+CONFIG_STM32_TIM5=n
+CONFIG_STM32_TIM6=n
+CONFIG_STM32_TIM7=n
+CONFIG_STM32_WWDG=n
+CONFIG_STM32_SPI2=n
+CONFIG_STM32_USART2=y
+CONFIG_STM32_USART3=y
+CONFIG_STM32_I2C1=y
+CONFIG_STM32_I2C2=n
+CONFIG_STM32_BKP=n
+CONFIG_STM32_PWR=n
+CONFIG_STM32_DAC=n
+# APB2:
+CONFIG_STM32_ADC1=y
+CONFIG_STM32_ADC2=n
+# TIM1 is owned by the HRT
+CONFIG_STM32_TIM1=n
+CONFIG_STM32_SPI1=n
+CONFIG_STM32_TIM8=n
+CONFIG_STM32_USART1=y
+CONFIG_STM32_ADC3=n
+
+#
+# Timer and I2C devices may need to the following to force power to be applied:
+#
+#CONFIG_STM32_FORCEPOWER=y
+
+#
+# STM32F100 specific serial device driver settings
+#
+# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the
+#   console and ttys0 (default is the USART1).
+# CONFIG_USARTn_RXBUFSIZE - Characters are buffered as received.
+#   This specific the size of the receive buffer
+# CONFIG_USARTn_TXBUFSIZE - Characters are buffered before
+#   being sent.  This specific the size of the transmit buffer
+# CONFIG_USARTn_BAUD - The configure BAUD of the UART.  Must be
+# CONFIG_USARTn_BITS - The number of bits.  Must be either 7 or 8.
+# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+# CONFIG_USARTn_2STOP - Two stop bits
+#
+CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_USART2_SERIAL_CONSOLE=n
+CONFIG_USART3_SERIAL_CONSOLE=n
+
+CONFIG_USART1_TXBUFSIZE=64
+CONFIG_USART2_TXBUFSIZE=64
+CONFIG_USART3_TXBUFSIZE=64
+
+CONFIG_USART1_RXBUFSIZE=64
+CONFIG_USART2_RXBUFSIZE=64
+CONFIG_USART3_RXBUFSIZE=64
+
+CONFIG_USART1_BAUD=57600
+CONFIG_USART2_BAUD=115200
+CONFIG_USART3_BAUD=115200
+
+CONFIG_USART1_BITS=8
+CONFIG_USART2_BITS=8
+CONFIG_USART3_BITS=8
+
+CONFIG_USART1_PARITY=0
+CONFIG_USART2_PARITY=0
+CONFIG_USART3_PARITY=0
+
+CONFIG_USART1_2STOP=0
+CONFIG_USART2_2STOP=0
+CONFIG_USART3_2STOP=0
+
+#
+# PX4IO specific driver settings
+#
+# CONFIG_HRT_TIMER
+#   Enables the high-resolution timer.  The board definition must
+#   set HRT_TIMER and HRT_TIMER_CHANNEL to the timer and capture/
+#   compare channels to be used.
+# CONFIG_HRT_PPM
+#   Enables R/C PPM input using the HRT.  The board definition must
+#   set HRT_PPM_CHANNEL to the timer capture/compare channel to be
+#   used, and define GPIO_PPM_IN to configure the appropriate timer
+#   GPIO.
+# CONFIG_PWM_SERVO
+#   Enables the PWM servo driver.  The driver configuration must be
+#   supplied by the board support at initialisation time.
+#   Note that USART2 must be disabled on the PX4 board for this to
+#   be available.
+#
+#
+CONFIG_HRT_TIMER=y
+CONFIG_HRT_PPM=y
+CONFIG_PWM_SERVO=y
+
+#
+# General build options
+#
+# CONFIG_RRLOAD_BINARY - make the rrload binary format used with
+#   BSPs from www.ridgerun.com using the tools/mkimage.sh script
+# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format
+#   used with many different loaders using the GNU objcopy program
+#   Should not be selected if you are not using the GNU toolchain.
+# CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format
+#   used with many different loaders using the GNU objcopy program
+#   Should not be selected if you are not using the GNU toolchain.
+# CONFIG_RAW_BINARY - make a raw binary format file used with many
+#   different loaders using the GNU objcopy program.  This option
+#   should not be selected if you are not using the GNU toolchain.
+# CONFIG_HAVE_LIBM - toolchain supports libm.a
+#
+CONFIG_RRLOAD_BINARY=n
+CONFIG_INTELHEX_BINARY=n
+CONFIG_MOTOROLA_SREC=n
+CONFIG_RAW_BINARY=y
+CONFIG_HAVE_LIBM=n
+
+#
+# General OS setup
+#
+# CONFIG_APPS_DIR - Identifies the relative path to the directory
+#   that builds the application to link with NuttX.  Default: ../apps
+# CONFIG_DEBUG - enables built-in debug options
+# CONFIG_DEBUG_VERBOSE - enables verbose debug output
+# CONFIG_DEBUG_SYMBOLS - build without optimization and with
+#   debug symbols (needed for use with a debugger).
+# CONFIG_HAVE_CXX - Enable support for C++
+# CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support
+#   for initialization of static C++ instances for this architecture
+#   and for the selected toolchain (via up_cxxinitialize()).
+# CONFIG_MM_REGIONS - If the architecture includes multiple
+#   regions of memory to allocate from, this specifies the
+#   number of memory regions that the memory manager must
+#   handle and enables the API mm_addregion(start, end);
+# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot
+#   time console output
+# CONFIG_MSEC_PER_TICK - The default system timer is 100Hz
+#   or MSEC_PER_TICK=10.  This setting may be defined to
+#   inform NuttX that the processor hardware is providing
+#   system timer interrupts at some interrupt interval other
+#   than 10 msec.
+# CONFIG_RR_INTERVAL - The round robin timeslice will be set
+#   this number of milliseconds;  Round robin scheduling can
+#   be disabled by setting this value to zero.
+# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in 
+#   scheduler to monitor system performance
+# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a
+#   task name to save in the TCB.  Useful if scheduler
+#   instrumentation is selected.  Set to zero to disable.
+# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY -
+#   Used to initialize the internal time logic.
+# CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions.
+#   You would only need this if you are concerned about accurate
+#   time conversions in the past or in the distant future.
+# CONFIG_JULIAN_TIME - Enables Julian time conversions. You
+#   would only need this if you are concerned about accurate
+#   time conversion in the distand past.  You must also define
+#   CONFIG_GREGORIAN_TIME in order to use Julian time.
+# CONFIG_DEV_CONSOLE - Set if architecture-specific logic
+#   provides /dev/console.  Enables stdout, stderr, stdin.
+# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console
+#   driver (minimul support)
+# CONFIG_MUTEX_TYPES: Set to enable support for recursive and
+#   errorcheck mutexes. Enables pthread_mutexattr_settype().
+# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority
+#   inheritance on mutexes and semaphores. 
+# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority
+#   inheritance is enabled.  It defines the maximum number of
+#   different threads (minus one) that can take counts on a
+#   semaphore with priority inheritance support.  This may be 
+#   set to zero if priority inheritance is disabled OR if you
+#   are only using semaphores as mutexes (only one holder) OR
+#   if no more than two threads participate using a counting
+#   semaphore.
+# CONFIG_SEM_NNESTPRIO.  If priority inheritance is enabled,
+#   then this setting is the maximum number of higher priority
+#   threads (minus 1) than can be waiting for another thread
+#   to release a count on a semaphore.  This value may be set
+#   to zero if no more than one thread is expected to wait for
+#   a semaphore.
+# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors
+#   by task_create() when a new task is started.  If set, all
+#   files/drivers will appear to be closed in the new task.
+# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first
+#   three file descriptors (stdin, stdout, stderr) by task_create()
+#   when a new task is started. If set, all files/drivers will
+#   appear to be closed in the new task except for stdin, stdout,
+#   and stderr.
+# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket
+#   desciptors by task_create() when a new task is started. If
+#   set, all sockets will appear to be closed in the new task.
+# CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
+#  This format will support execution of NuttX binaries located
+#  in a ROMFS filesystem (see examples/nxflat).
+# CONFIG_SCHED_WORKQUEUE.  Create a dedicated "worker" thread to
+#  handle delayed processing from interrupt handlers.  This feature
+#  is required for some drivers but, if there are not complaints,
+#  can be safely disabled.  The worker thread also performs
+#  garbage collection -- completing any delayed memory deallocations
+#  from interrupt handlers.  If the worker thread is disabled,
+#  then that clean will be performed by the IDLE thread instead
+#  (which runs at the lowest of priority and may not be appropriate
+#  if memory reclamation is of high priority).  If CONFIG_SCHED_WORKQUEUE
+#  is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+#  thread.  Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+#  work in units of microseconds.  Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+#  thread.  Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+#  the worker thread.  Default: 4
+#
+#CONFIG_APPS_DIR=
+CONFIG_DEBUG=n
+CONFIG_DEBUG_VERBOSE=n
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_HAVE_CXX=n
+CONFIG_HAVE_CXXINITIALIZE=n
+CONFIG_MM_REGIONS=1
+CONFIG_MM_SMALL=y
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_INSTRUMENTATION=n
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_START_YEAR=2009
+CONFIG_START_MONTH=9
+CONFIG_START_DAY=21
+CONFIG_GREGORIAN_TIME=n
+CONFIG_JULIAN_TIME=n
+CONFIG_DEV_CONSOLE=y
+CONFIG_DEV_LOWCONSOLE=n
+CONFIG_MUTEX_TYPES=n
+CONFIG_PRIORITY_INHERITANCE=n
+CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_NNESTPRIO=0
+CONFIG_FDCLONE_DISABLE=n
+CONFIG_FDCLONE_STDIO=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_NXFLAT=n
+CONFIG_SCHED_WORKQUEUE=n
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=512
+CONFIG_SIG_SIGWORK=4
+
+#
+# The following can be used to disable categories of
+# APIs supported by the OS.  If the compiler supports
+# weak functions, then it should not be necessary to
+# disable functions unless you want to restrict usage
+# of those APIs.
+#
+# There are certain dependency relationships in these
+# features.
+#
+# o mq_notify logic depends on signals to awaken tasks
+#   waiting for queues to become full or empty.
+# o pthread_condtimedwait() depends on signals to wake
+#   up waiting tasks.
+#
+CONFIG_DISABLE_CLOCK=n
+CONFIG_DISABLE_POSIX_TIMERS=y
+CONFIG_DISABLE_PTHREAD=n
+CONFIG_DISABLE_SIGNALS=n
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_DISABLE_ENVIRON=y
+CONFIG_DISABLE_POLL=y
+
+#
+# Misc libc settings
+#
+# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a
+#   little smaller if we do not support fieldwidthes
+#
+CONFIG_NOPRINTF_FIELDWIDTH=n
+
+#
+# Allow for architecture optimized implementations
+#
+# The architecture can provide optimized versions of the
+# following to improve system performance
+#
+CONFIG_ARCH_MEMCPY=n
+CONFIG_ARCH_MEMCMP=n
+CONFIG_ARCH_MEMMOVE=n
+CONFIG_ARCH_MEMSET=n
+CONFIG_ARCH_STRCMP=n
+CONFIG_ARCH_STRCPY=n
+CONFIG_ARCH_STRNCPY=n
+CONFIG_ARCH_STRLEN=n
+CONFIG_ARCH_STRNLEN=n
+CONFIG_ARCH_BZERO=n
+
+#
+# Sizes of configurable things (0 disables)
+#
+# CONFIG_MAX_TASKS - The maximum number of simultaneously
+#   active tasks.  This value must be a power of two.
+# CONFIG_MAX_TASK_ARGS - This controls the maximum number of
+#   of parameters that a task may receive (i.e., maxmum value
+#   of 'argc')
+# CONFIG_NPTHREAD_KEYS - The number of items of thread-
+#   specific data that can be retained
+# CONFIG_NFILE_DESCRIPTORS - The maximum number of file
+#   descriptors (one for each open)
+# CONFIG_NFILE_STREAMS - The maximum number of streams that
+#   can be fopen'ed
+# CONFIG_NAME_MAX - The maximum size of a file name.
+# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate
+#   on fopen. (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_NUNGET_CHARS - Number of characters that can be
+#   buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message
+#   structures.  The system manages a pool of preallocated
+#   message structures to minimize dynamic allocations
+# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with
+#   a fixed payload size given by this settin (does not include
+#   other message structure overhead.
+# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that
+#   can be passed to a watchdog handler
+# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog
+#   structures.  The system manages a pool of preallocated
+#   watchdog structures to minimize dynamic allocations
+# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX
+#   timer structures.  The system manages a pool of preallocated
+#   timer structures to minimize dynamic allocations.  Set to
+#   zero for all dynamic allocations.
+#
+CONFIG_MAX_TASKS=4
+CONFIG_MAX_TASK_ARGS=4
+CONFIG_NPTHREAD_KEYS=2
+CONFIG_NFILE_DESCRIPTORS=6
+CONFIG_NFILE_STREAMS=4
+CONFIG_NAME_MAX=32
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_NUNGET_CHARS=2
+CONFIG_PREALLOC_MQ_MSGS=1
+CONFIG_MQ_MAXMSGSIZE=32
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=3
+CONFIG_PREALLOC_TIMERS=1
+
+
+#
+# Settings for apps/nshlib
+#
+# CONFIG_NSH_BUILTIN_APPS - Support external registered,
+#   "named" applications that can be executed from the NSH
+#   command line (see apps/README.txt for more information).
+# CONFIG_NSH_FILEIOSIZE - Size of a static I/O buffer
+# CONFIG_NSH_STRERROR - Use strerror(errno)
+# CONFIG_NSH_LINELEN - Maximum length of one command line
+# CONFIG_NSH_NESTDEPTH - Max number of nested if-then[-else]-fi
+# CONFIG_NSH_DISABLESCRIPT - Disable scripting support
+# CONFIG_NSH_DISABLEBG - Disable background commands
+# CONFIG_NSH_ROMFSETC - Use startup script in /etc
+# CONFIG_NSH_CONSOLE - Use serial console front end
+# CONFIG_NSH_TELNET - Use telnetd console front end
+# CONFIG_NSH_ARCHINIT - Platform provides architecture
+#   specific initialization (nsh_archinitialize()).
+#
+# If CONFIG_NSH_TELNET is selected:
+# CONFIG_NSH_IOBUFFER_SIZE -- Telnetd I/O buffer size
+# CONFIG_NSH_DHCPC - Obtain address using DHCP
+# CONFIG_NSH_IPADDR - Provides static IP address
+# CONFIG_NSH_DRIPADDR - Provides static router IP address
+# CONFIG_NSH_NETMASK - Provides static network mask
+# CONFIG_NSH_NOMAC - Use a bogus MAC address
+#
+# If CONFIG_NSH_ROMFSETC is selected:
+# CONFIG_NSH_ROMFSMOUNTPT - ROMFS mountpoint
+# CONFIG_NSH_INITSCRIPT - Relative path to init script
+# CONFIG_NSH_ROMFSDEVNO - ROMFS RAM device minor
+# CONFIG_NSH_ROMFSSECTSIZE - ROMF sector size
+# CONFIG_NSH_FATDEVNO - FAT FS RAM device minor
+# CONFIG_NSH_FATSECTSIZE - FAT FS sector size
+# CONFIG_NSH_FATNSECTORS - FAT FS number of sectors
+# CONFIG_NSH_FATMOUNTPT - FAT FS mountpoint
+#
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_STRERROR=n
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_NESTDEPTH=1
+CONFIG_NSH_DISABLESCRIPT=y
+CONFIG_NSH_DISABLEBG=n
+CONFIG_NSH_ROMFSETC=n
+CONFIG_NSH_CONSOLE=y
+CONFIG_NSH_TELNET=n
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_IOBUFFER_SIZE=256
+#CONFIG_NSH_STACKSIZE=1024
+CONFIG_NSH_DHCPC=n
+CONFIG_NSH_NOMAC=n
+CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2)
+CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1)
+CONFIG_NSH_NETMASK=(255<<24|255<<16|255<<8|0)
+CONFIG_NSH_ROMFSMOUNTPT="/etc"
+CONFIG_NSH_INITSCRIPT="init.d/rcS"
+CONFIG_NSH_ROMFSDEVNO=0
+CONFIG_NSH_ROMFSSECTSIZE=64
+CONFIG_NSH_FATDEVNO=1
+CONFIG_NSH_FATSECTSIZE=512
+CONFIG_NSH_FATNSECTORS=1024
+CONFIG_NSH_FATMOUNTPT=/tmp
+
+#
+# Architecture-specific NSH options
+#
+CONFIG_NSH_MMCSDSPIPORTNO=0
+CONFIG_NSH_MMCSDSLOTNO=0
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Stack and heap information
+#
+# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP
+#   operation from FLASH but must copy initialized .data sections to RAM.
+#   (should also be =n for the STM3210E-EVAL which always runs from flash)
+# CONFIG_BOOT_COPYTORAM -  Some configurations boot in FLASH
+#   but copy themselves entirely into RAM for better performance.
+# CONFIG_CUSTOM_STACK - The up_ implementation will handle
+#   all stack operations outside of the nuttx model.
+# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only)
+# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack.
+#  This is the thread that (1) performs the inital boot of the system up
+#  to the point where user_start() is spawned, and (2) there after is the
+#  IDLE thread that executes only when there is no other thread ready to
+#  run.
+# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate
+#  for the main user thread that begins at the user_start() entry point.
+# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size
+# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size
+# CONFIG_HEAP_BASE - The beginning of the heap
+# CONFIG_HEAP_SIZE - The size of the heap
+#
+CONFIG_BOOT_RUNFROMFLASH=n
+CONFIG_BOOT_COPYTORAM=n
+CONFIG_CUSTOM_STACK=n
+CONFIG_STACK_POINTER=
+CONFIG_IDLETHREAD_STACKSIZE=800
+CONFIG_USERMAIN_STACKSIZE=1024
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=512
+CONFIG_HEAP_BASE=
+CONFIG_HEAP_SIZE=
diff --git a/nuttx/configs/px4io/nsh/setenv.sh b/nuttx/configs/px4io/nsh/setenv.sh
new file mode 100755
index 000000000..d83685192
--- /dev/null
+++ b/nuttx/configs/px4io/nsh/setenv.sh
@@ -0,0 +1,47 @@
+#!/bin/bash
+# configs/stm3210e-eval/dfu/setenv.sh
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$(basename $0)" = "setenv.sh" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi
+
+WD=`pwd`
+export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin"
+export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
+export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/nuttx/configs/px4io/src/Makefile b/nuttx/configs/px4io/src/Makefile
new file mode 100644
index 000000000..0ce004658
--- /dev/null
+++ b/nuttx/configs/px4io/src/Makefile
@@ -0,0 +1,95 @@
+############################################################################
+# configs/stm3210e-eval/src/Makefile
+#
+#   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+CFLAGS		+= -I$(TOPDIR)/sched
+
+ASRCS		= 
+AOBJS		= $(ASRCS:.S=$(OBJEXT))
+
+CSRCS		= up_boot.c up_hrt.c\
+		  drv_pwm_servo.c drv_ppm_input.c drv_gpio.c \
+		  up_boardinitialize.c
+
+ifeq ($(CONFIG_NSH_ARCHINIT),y)
+CSRCS		+= up_nsh.c
+endif
+
+ifeq ($(CONFIG_ADC),y)
+CSRCS		+= up_adc.c
+endif
+
+COBJS		= $(CSRCS:.c=$(OBJEXT))
+
+SRCS		= $(ASRCS) $(CSRCS)
+OBJS		= $(AOBJS) $(COBJS)
+
+ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  CFLAGS	+= -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
+  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
+  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
+else
+  CFLAGS	+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
+endif
+
+all: libboard$(LIBEXT)
+
+$(AOBJS): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+libboard$(LIBEXT): $(OBJS)
+	@( for obj in $(OBJS) ; do \
+		$(call ARCHIVE, $@, $${obj}); \
+	done ; )
+
+.depend: Makefile $(SRCS)
+	@$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	@touch $@
+
+depend: .depend
+
+clean:
+	@rm -f libboard$(LIBEXT) *~ .*.swp
+	$(call CLEAN)
+
+distclean: clean
+	@rm -f Make.dep .depend
+
+-include Make.dep
diff --git a/nuttx/configs/px4io/src/README.txt b/nuttx/configs/px4io/src/README.txt
new file mode 100644
index 000000000..d4eda82fd
--- /dev/null
+++ b/nuttx/configs/px4io/src/README.txt
@@ -0,0 +1 @@
+This directory contains drivers unique to the STMicro STM3210E-EVAL development board.
diff --git a/nuttx/configs/px4io/src/drv_gpio.c b/nuttx/configs/px4io/src/drv_gpio.c
new file mode 100644
index 000000000..e53660a3c
--- /dev/null
+++ b/nuttx/configs/px4io/src/drv_gpio.c
@@ -0,0 +1,110 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file GPIO driver for PX4IO.
+ */
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <errno.h>
+
+#include <arch/board/board.h>
+#include <arch/board/drv_gpio.h>
+
+#include "px4io_internal.h"
+#include "stm32_gpio.h"
+
+static int	gpio_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+static const struct file_operations gpio_fops = {
+	.ioctl = gpio_ioctl
+};
+
+/*
+ * Order of initialisers in this array must match the order of
+ * GPIO_ definitions in drv_gpio.h
+ */
+static const uint32_t gpios[] = {
+	/* settable */
+	GPIO_ACC1_PWR_EN,
+	GPIO_ACC2_PWR_EN,
+	GPIO_SERVO_PWR_EN,
+	GPIO_RELAY1_EN,
+	GPIO_RELAY2_EN,
+	GPIO_LED1,
+	GPIO_LED2,
+	GPIO_LED3,
+
+	/* readonly */
+	GPIO_ACC_OC_DETECT,
+	GPIO_SERVO_OC_DETECT,
+	GPIO_BTN_SAFETY
+};
+
+int
+gpio_drv_init(void)
+{
+	int i;
+
+	/* initialise GPIOs */
+	for (i = 0; i < GPIO_MAX; i++)
+		if (gpios[i])
+			stm32_configgpio(gpios[i]);
+
+	/* register the device */
+	return register_driver("/dev/gpio", &gpio_fops, 0666, NULL);
+}
+
+static int
+gpio_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+	/* attempt to set a GPIO? */
+	if ((cmd >= GPIO_SET(0)) && (cmd <= GPIO_SET(GPIO_MAX_SETTABLE))) {
+		uint32_t gpio = gpios[cmd - GPIO_SET(0)];
+
+		if (gpio != 0) {
+			stm32_gpiowrite(gpio, arg ? true : false);
+			return 0;
+		}
+	} else if ((cmd >= GPIO_GET(0)) && (cmd <= GPIO_GET(GPIO_MAX))) {
+		uint32_t gpio = gpios[cmd - GPIO_GET(0)];
+
+		if (gpio != 0)
+			return stm32_gpioread(gpio) ? 1 : 0;
+	}
+	return -ENOTTY;
+}
\ No newline at end of file
diff --git a/nuttx/configs/px4io/src/drv_i2c_device.c b/nuttx/configs/px4io/src/drv_i2c_device.c
new file mode 100644
index 000000000..1f5931ae5
--- /dev/null
+++ b/nuttx/configs/px4io/src/drv_i2c_device.c
@@ -0,0 +1,618 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+ /**
+  * @file A simple, polled I2C slave-mode driver.
+  *
+  * The master writes to and reads from a byte buffer, which the caller 
+  * can update inbetween calls to the FSM.
+  */
+
+#include <stdbool.h>
+
+#include "stm32_i2c.h"
+
+#include <string.h>
+
+/*
+ * I2C register definitions.
+ */
+#define I2C_BASE	STM32_I2C1_BASE
+
+#define REG(_reg)	(*(volatile uint32_t *)(I2C_BASE + _reg))
+
+#define rCR1		REG(STM32_I2C_CR1_OFFSET)
+#define rCR2		REG(STM32_I2C_CR2_OFFSET)
+#define rOAR1		REG(STM32_I2C_OAR1_OFFSET)
+#define rOAR2		REG(STM32_I2C_OAR2_OFFSET)
+#define rDR		REG(STM32_I2C_DR_OFFSET)
+#define rSR1		REG(STM32_I2C_SR1_OFFSET)
+#define rSR2		REG(STM32_I2C_SR2_OFFSET)
+#define rCCR		REG(STM32_I2C_CCR_OFFSET)
+#define rTRISE		REG(STM32_I2C_TRISE_OFFSET)
+
+/*
+ * "event" values (cr2 << 16 | cr1) as described in the ST DriverLib
+ */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010) /* STOPF flag */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400) /* AF flag */
+
+/**
+ * States implemented by the I2C FSM.
+ */
+enum fsm_state {
+	BAD_PHASE,	 // must be zero, default exit on a bad state transition
+
+	WAIT_FOR_MASTER,
+
+	/* write from master */
+	WAIT_FOR_COMMAND,
+	RECEIVE_COMMAND,
+	RECEIVE_DATA,
+	HANDLE_COMMAND,
+
+	/* read from master */
+	WAIT_TO_SEND,
+	SEND_STATUS,
+	SEND_DATA,
+
+	NUM_STATES
+};
+
+/**
+ * Events recognised by the I2C FSM.
+ */
+enum fsm_event {
+	/* automatic transition */
+	AUTO,
+
+	/* write from master */
+	ADDRESSED_WRITE,
+	BYTE_RECEIVED,
+	STOP_RECEIVED,
+
+	/* read from master */
+	ADDRESSED_READ,
+	BYTE_SENDABLE,
+	ACK_FAILED,
+
+	NUM_EVENTS
+};
+
+/**
+ * Context for the I2C FSM
+ */
+static struct fsm_context {
+	enum fsm_state		state;
+
+	/* XXX want to eliminate these */
+	uint8_t			command;
+	uint8_t			status;
+
+	uint8_t			*data_ptr;
+	uint32_t		data_count;
+
+	size_t			buffer_size;
+	uint8_t			*buffer;
+} context;
+
+/**
+ * Structure defining one FSM state and its outgoing transitions.
+ */
+struct fsm_transition {
+		void (*handler)(void);
+		enum fsm_state next_state[NUM_EVENTS];
+};
+
+static bool	i2c_command_received;
+
+static void	fsm_event(enum fsm_event event);
+
+static void	go_bad(void);
+static void	go_wait_master(void);
+
+static void	go_wait_command(void);
+static void	go_receive_command(void);
+static void	go_receive_data(void);
+static void	go_handle_command(void);
+
+static void	go_wait_send(void);
+static void	go_send_status(void);
+static void	go_send_buffer(void);
+
+/**
+ * The FSM state graph.
+ */
+static const struct fsm_transition fsm[NUM_STATES] = {
+		[BAD_PHASE] = {
+				.handler = go_bad,
+				.next_state = {
+						[AUTO] = WAIT_FOR_MASTER,
+				},
+		},
+
+		[WAIT_FOR_MASTER] = {
+				.handler = go_wait_master,
+				.next_state = {
+						[ADDRESSED_WRITE] = WAIT_FOR_COMMAND,
+						[ADDRESSED_READ] = WAIT_TO_SEND,
+				},
+		},
+
+		/* write from master*/
+		[WAIT_FOR_COMMAND] = {
+				.handler = go_wait_command,
+				.next_state = {
+						[BYTE_RECEIVED] = RECEIVE_COMMAND,
+						[STOP_RECEIVED] = WAIT_FOR_MASTER,
+				},
+		},
+		[RECEIVE_COMMAND] = {
+				.handler = go_receive_command,
+				.next_state = {
+						[BYTE_RECEIVED] = RECEIVE_DATA,
+						[STOP_RECEIVED] = HANDLE_COMMAND,
+				},
+		},
+		[RECEIVE_DATA] = {
+				.handler = go_receive_data,
+				.next_state = {
+						[BYTE_RECEIVED] = RECEIVE_DATA,
+						[STOP_RECEIVED] = HANDLE_COMMAND,
+				},
+		},
+		[HANDLE_COMMAND] = {
+				.handler = go_handle_command,
+				.next_state = {
+						[AUTO] = WAIT_FOR_MASTER,
+				},
+		},
+
+		/* buffer send */
+		[WAIT_TO_SEND] = {
+			.handler = go_wait_send,
+			.next_state = {
+					[BYTE_SENDABLE] = SEND_STATUS,
+			},
+		},
+		[SEND_STATUS] = {
+				.handler = go_send_status,
+				.next_state = {
+						[BYTE_SENDABLE] = SEND_DATA,
+						[ACK_FAILED] = WAIT_FOR_MASTER,
+				},
+		},
+		[SEND_DATA] = {
+				.handler = go_send_buffer,
+				.next_state = {
+						[BYTE_SENDABLE] = SEND_DATA,
+						[ACK_FAILED] = WAIT_FOR_MASTER,
+				},
+		},
+};
+
+
+/* debug support */
+#if 1
+struct fsm_logentry {
+	char		kind;
+	uint32_t	code;
+};
+
+#define LOG_ENTRIES	32
+static struct fsm_logentry fsm_log[LOG_ENTRIES];
+int	fsm_logptr;
+#define LOG_NEXT(_x)	(((_x) + 1) % LOG_ENTRIES)
+#define LOGx(_kind, _code)		\
+		do {					\
+			fsm_log[fsm_logptr].kind = _kind; \
+			fsm_log[fsm_logptr].code = _code; \
+			fsm_logptr = LOG_NEXT(fsm_logptr); \
+			fsm_log[fsm_logptr].kind = 0; \
+		} while(0)
+
+#define LOG(_kind, _code) \
+		do {\
+			if (fsm_logptr < LOG_ENTRIES) { \
+				fsm_log[fsm_logptr].kind = _kind; \
+				fsm_log[fsm_logptr].code = _code; \
+				fsm_logptr++;\
+			}\
+		}while(0)
+
+#else
+#define LOG(_kind, _code)
+#endif
+
+
+static void i2c_setclock(uint32_t frequency);
+
+/**
+ * Initialise I2C
+ *
+ */
+void
+i2c_fsm_init(uint8_t *buffer, size_t buffer_size)
+{
+	/* save the buffer */
+	context.buffer = buffer;
+	context.buffer_size = buffer_size;
+
+	// initialise the FSM
+	context.status = 0;
+	context.command = 0;
+	context.state = BAD_PHASE;
+	fsm_event(AUTO);
+
+#if 0
+	// enable the i2c block clock and reset it
+	modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C1EN);
+	modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C1RST);
+	modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST, 0);
+
+	// configure the i2c GPIOs
+	stm32_configgpio(GPIO_I2C1_SCL);
+	stm32_configgpio(GPIO_I2C1_SDA);
+
+	// set the peripheral clock to match the APB clock
+	rCR2 = STM32_PCLK1_FREQUENCY / 1000000;
+
+	// configure for 100kHz operation
+	i2c_setclock(100000);
+
+	// enable i2c
+	rCR1 = I2C_CR1_PE;
+#endif
+}
+
+/**
+ * Run the I2C FSM for some period.
+ *
+ * @return True if the buffer has been updated by a command.
+ */
+bool
+i2c_fsm(void)
+{
+	uint32_t	event;
+	int		idle_iterations = 0;
+
+	for (;;) {
+		// handle bus error states by discarding the current operation
+		if (rSR1 & I2C_SR1_BERR) {
+			context.state = WAIT_FOR_MASTER;
+			rSR1 = ~I2C_SR1_BERR;
+		}
+
+		// we do not anticipate over/underrun errors as clock-stretching is enabled
+
+		// fetch the most recent event
+		event = ((rSR2 << 16) | rSR1) & 0x00ffffff;
+
+		// generate FSM events based on I2C events
+		switch (event) {
+		case I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED:
+			LOG('w', 0);
+			fsm_event(ADDRESSED_WRITE);
+			break;
+
+		case I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED:
+			LOG('r', 0);
+			fsm_event(ADDRESSED_READ);
+			break;
+
+		case I2C_EVENT_SLAVE_BYTE_RECEIVED:
+			LOG('R', 0);
+			fsm_event(BYTE_RECEIVED);
+			break;
+
+		case I2C_EVENT_SLAVE_STOP_DETECTED:
+			LOG('s', 0);
+			fsm_event(STOP_RECEIVED);
+			break;
+
+		case I2C_EVENT_SLAVE_BYTE_TRANSMITTING:
+		//case I2C_EVENT_SLAVE_BYTE_TRANSMITTED:
+			LOG('T', 0);
+			fsm_event(BYTE_SENDABLE);
+			break;
+
+		case I2C_EVENT_SLAVE_ACK_FAILURE:
+			LOG('a', 0);
+			fsm_event(ACK_FAILED);
+			break;
+
+		default:
+			idle_iterations++;
+//			if ((event) && (event != 0x00020000))
+//				LOG('e', event);
+			break;
+		}
+
+		/* if we have just received something, drop out and let the caller handle it */
+		if (i2c_command_received) {
+			i2c_command_received = false;
+			return true;
+		}
+
+		/* if we have done nothing recently, drop out and let the caller have a slice */
+		if (idle_iterations > 1000)
+			return false;
+	}
+}
+
+/**
+ * Update the FSM with an event
+ *
+ * @param event	New event.
+ */
+static void
+fsm_event(enum fsm_event event)
+{
+	// move to the next state
+	context.state = fsm[context.state].next_state[event];
+
+	LOG('f', context.state);
+
+	// call the state entry handler
+	if (fsm[context.state].handler) {
+		fsm[context.state].handler();
+	}
+}
+
+static void
+go_bad()
+{
+	LOG('B', 0);
+	fsm_event(AUTO);
+}
+
+/**
+ * Wait for the master to address us.
+ *
+ */
+static void
+go_wait_master()
+{
+	// We currently don't have a command byte.
+	//
+	context.command = '\0';
+
+	// The data pointer starts pointing to the start of the data buffer.
+	//
+	context.data_ptr = context.buffer;
+
+	// The data count is either:
+	// - the size of the data buffer
+	// - some value less than or equal the size of the data buffer during a write or a read
+	//
+	context.data_count = context.buffer_size;
+
+	// (re)enable the peripheral, clear the stop event flag in
+	// case we just finished receiving data
+	rCR1 |= I2C_CR1_PE;
+
+	// clear the ACK failed flag in case we just finished sending data
+	rSR1 = ~I2C_SR1_AF;
+}
+
+/**
+ * Prepare to receive a command byte.
+ *
+ */
+static void
+go_wait_command()
+{
+	// NOP
+}
+
+/**
+ * Command byte has been received, save it and prepare to handle the data.
+ *
+ */
+static void
+go_receive_command()
+{
+
+	// fetch the command byte
+	context.command = (uint8_t)rDR;
+	LOG('c', context.command);
+
+}
+
+/**
+ * Receive a data byte.
+ *
+ */
+static void
+go_receive_data()
+{
+	uint8_t	d;
+
+	// fetch the byte
+	d = (uint8_t)rDR;
+	LOG('d', d);
+
+	// if we have somewhere to put it, do so
+	if (context.data_count) {
+		*context.data_ptr++ = d;
+		context.data_count--;
+	}
+}
+
+/**
+ * Handle a command once the host is done sending it to us.
+ *
+ */
+static void
+go_handle_command()
+{
+	// presume we are happy with the command
+	context.status = 0;
+
+	// make a note that the buffer contains a fresh command
+	i2c_command_received = true;
+
+	// kick along to the next state
+	fsm_event(AUTO);
+}
+
+/**
+ * Wait to be able to send the status byte.
+ *
+ */
+static void
+go_wait_send()
+{
+	// NOP
+}
+
+/**
+ * Send the status byte.
+ *
+ */
+static void
+go_send_status()
+{
+	rDR = context.status;
+	LOG('?', context.status);
+}
+
+/**
+ * Send a data or pad byte.
+ *
+ */
+static void
+go_send_buffer()
+{
+	if (context.data_count) {
+		LOG('D', *context.data_ptr);
+		rDR = *(context.data_ptr++);
+		context.data_count--;
+	} else {
+		LOG('-', 0);
+		rDR = 0xff;
+	}
+}
+
+/* cribbed directly from the NuttX master driver */
+static void 
+i2c_setclock(uint32_t frequency)
+{
+	uint16_t cr1;
+	uint16_t ccr;
+	uint16_t trise;
+	uint16_t freqmhz;
+	uint16_t speed;
+
+	/* Disable the selected I2C peripheral to configure TRISE */
+
+	cr1 = rCR1;
+	rCR1 &= ~I2C_CR1_PE;
+
+	/* Update timing and control registers */
+
+	freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000);
+	ccr = 0;
+
+	/* Configure speed in standard mode */
+
+	if (frequency <= 100000) {
+		/* Standard mode speed calculation */
+
+		speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1));
+
+		/* The CCR fault must be >= 4 */
+
+		if (speed < 4) {
+			/* Set the minimum allowed value */
+
+			speed = 4;  
+		}
+		ccr |= speed;
+
+		/* Set Maximum Rise Time for standard mode */
+
+		trise = freqmhz + 1; 
+				
+	/* Configure speed in fast mode */
+	} else { /* (frequency <= 400000) */
+		/* Fast mode speed calculation with Tlow/Thigh = 16/9 */
+
+#ifdef CONFIG_I2C_DUTY16_9
+	      speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25));
+
+		/* Set DUTY and fast speed bits */
+
+		ccr |= (I2C_CCR_DUTY|I2C_CCR_FS);
+#else
+		/* Fast mode speed calculation with Tlow/Thigh = 2 */
+
+		speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3));
+
+		/* Set fast speed bit */
+
+		ccr |= I2C_CCR_FS;
+#endif
+
+		/* Verify that the CCR speed value is nonzero */
+
+		if (speed < 1) {
+	        	/* Set the minimum allowed value */
+
+	        	speed = 1;  
+	        }
+		ccr |= speed;
+
+		/* Set Maximum Rise Time for fast mode */
+
+		trise = (uint16_t)(((freqmhz * 300) / 1000) + 1);  
+	}
+
+	/* Write the new values of the CCR and TRISE registers */
+
+	rCCR = ccr;
+	rTRISE = trise;
+
+	/* Bit 14 of OAR1 must be configured and kept at 1 */
+
+	rOAR1 = I2C_OAR1_ONE);
+
+	/* Re-enable the peripheral (or not) */
+
+	rCR1 = cr1;
+}
diff --git a/nuttx/configs/px4io/src/drv_ppm_input.c b/nuttx/configs/px4io/src/drv_ppm_input.c
new file mode 100644
index 000000000..f25ae41e2
--- /dev/null
+++ b/nuttx/configs/px4io/src/drv_ppm_input.c
@@ -0,0 +1,373 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file PPM input decoder.
+ *
+ * Works in conjunction with the HRT driver.
+ */
+
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <time.h>
+#include <queue.h>
+#include <errno.h>
+#include <string.h>
+#include <stdio.h>
+#include <fcntl.h>
+
+#include <arch/board/board.h>
+#include <arch/board/drv_ppm_input.h>
+#include <arch/board/up_hrt.h>
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_internal.h"
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+#ifdef CONFIG_HRT_PPM
+# ifndef CONFIG_HRT_TIMER
+#  error CONFIG_HRT_PPM requires CONFIG_HRT_TIMER
+# endif
+
+/*
+ * PPM decoder tuning parameters.
+ *
+ * The PPM decoder works as follows.
+ *
+ * Initially, the decoder waits in the UNSYNCH state for two edges 
+ * separated by PPM_MIN_START.  Once the second edge is detected,
+ * the decoder moves to the ARM state.
+ *
+ * The ARM state expects an edge within PPM_MAX_PULSE_WIDTH, being the
+ * timing mark for the first channel.  If this is detected, it moves to
+ * the INACTIVE state.
+ *
+ * The INACTIVE phase waits for and discards the next edge, as it is not
+ * significant.  Once the edge is detected, it moves to the ACTIVE stae.
+ *
+ * The ACTIVE state expects an edge within PPM_MAX_PULSE_WIDTH, and when
+ * received calculates the time from the previous mark and records
+ * this time as the value for the next channel. 
+ *
+ * If at any time waiting for an edge, the delay from the previous edge 
+ * exceeds PPM_MIN_START the frame is deemed to have ended and the recorded
+ * values are advertised to clients.
+ */
+#define PPM_MAX_PULSE_WIDTH	500		/* maximum width of a pulse */
+#define PPM_MIN_CHANNEL_VALUE	750		/* shortest valid channel signal */
+#define PPM_MAX_CHANNEL_VALUE	2400		/* longest valid channel signal */
+#define PPM_MIN_START		5000		/* shortest valid start gap */
+
+/* Input timeout - after this interval we assume signal is lost */
+#define PPM_INPUT_TIMEOUT	100 * 1000	/* 100ms */
+
+/* Number of same-sized frames required to 'lock' */
+#define PPM_CHANNEL_LOCK	3		/* should be less than the input timeout */
+
+/* decoded PPM buffer */
+#define PPM_MIN_CHANNELS	4
+#define PPM_MAX_CHANNELS	12
+static uint16_t ppm_buffer[PPM_MAX_CHANNELS];
+static unsigned ppm_decoded_channels;
+
+static uint16_t ppm_temp_buffer[PPM_MAX_CHANNELS];
+
+/* PPM decoder state machine */
+static struct {
+	uint16_t	last_edge;	/* last capture time */
+	uint16_t	last_mark;	/* last significant edge */
+	unsigned	next_channel;
+	enum {
+		UNSYNCH = 0,
+		ARM,
+		ACTIVE,
+		INACTIVE
+	} phase;
+} ppm;
+
+/* last time we got good data */
+static hrt_abstime ppm_timestamp;
+
+#ifndef CONFIG_DISABLE_MQUEUE
+/* message queue we advertise PPM data on */
+static mqd_t ppm_message_queue;
+#endif
+
+/* set if PPM data has not been read */
+static bool ppm_fresh_data;
+
+/* PPM device node file ops */
+
+static int ppm_read(struct file *filp, char *buffer, size_t len);
+static int ppm_ioctl(struct file *filp, int cmd, unsigned long arg);
+
+static const struct file_operations ppm_fops = {
+	.read = ppm_read,
+	.ioctl = ppm_ioctl
+};
+
+/*
+ * Initialise the PPM system for client use.
+ */
+int
+ppm_input_init(const char *mq_name)
+{
+	int	err;
+
+	/* configure the PPM input pin */
+	stm32_configgpio(GPIO_PPM_IN);
+
+	/* and register the device node */
+	if (OK != (err = register_driver(PPM_DEVICE_NODE, &ppm_fops, 0666, NULL)))
+		return err;
+
+#ifndef CONFIG_DISABLE_MQUEUE
+	if (mq_name != NULL) {
+		/* create the message queue */
+		struct mq_attr attr = {
+			.mq_maxmsg = 1,
+			.mq_msgsize = sizeof(ppm_buffer)
+		};
+		ppm_message_queue = mq_open(mq_name, O_WRONLY | O_CREAT | O_NONBLOCK, 0666, &attr);
+		if (ppm_message_queue < 0)
+			return -errno;
+	}
+#endif
+
+	return OK;
+}
+
+/*
+ * Handle the PPM decoder state machine.
+ */
+void
+ppm_input_decode(bool reset, uint16_t count) 
+{
+	uint16_t width;
+	uint16_t interval;
+	unsigned i;
+
+	/* if we missed an edge, we have to give up */
+	if (reset)
+		goto error;
+
+	/* how long since the last edge? */
+	width = count - ppm.last_edge;
+	ppm.last_edge = count;
+
+	/* 
+	 * If this looks like a start pulse, then push the last set of values
+	 * and reset the state machine.
+	 *
+	 * Note that this is not a "high performance" design; it implies a whole
+	 * frame of latency between the pulses being received and their being 
+	 * considered valid.
+	 */
+	if (width >= PPM_MIN_START) {
+
+		/* 
+		 * If the number of channels changes unexpectedly, we don't want
+		 * to just immediately jump on the new count as it may be a result
+		 * of noise or dropped edges.  Instead, take a few frames to settle.
+		 */
+		if (ppm.next_channel != ppm_decoded_channels) {
+			static int new_channel_count;
+			static int new_channel_holdoff;
+
+			if (new_channel_count != ppm.next_channel) {
+				/* start the lock counter for the new channel count */
+				new_channel_count = ppm.next_channel;
+				new_channel_holdoff = PPM_CHANNEL_LOCK;
+
+			} else if (new_channel_holdoff > 0) {
+				/* this frame matched the last one, decrement the lock counter */
+				new_channel_holdoff--;
+
+			} else {
+				/* we have seen PPM_CHANNEL_LOCK frames with the new count, accept it */
+				ppm_decoded_channels = new_channel_count;
+				new_channel_count = 0;
+			}
+		} else {
+			/* frame channel count matches expected, let's use it */
+			if (ppm.next_channel > PPM_MIN_CHANNELS) {
+				for (i = 0; i < ppm.next_channel; i++)
+					ppm_buffer[i] = ppm_temp_buffer[i];
+				ppm_timestamp = hrt_absolute_time();
+				ppm_fresh_data = true;
+#ifndef CONFIG_DISABLE_MQUEUE
+				/* advertise the new data to the message queue */
+				mq_send(ppm_message_queue, ppm_buffer, ppm_decoded_channels * sizeof(ppm_buffer[0]), 0);
+#endif
+			}
+		}
+
+		/* reset for the next frame */
+		ppm.next_channel = 0;
+
+		/* next edge is the reference for the first channel */
+		ppm.phase = ARM;
+
+		return;
+	}
+
+	switch (ppm.phase) {
+	case UNSYNCH:
+		/* we are waiting for a start pulse - nothing useful to do here */
+		return;
+
+	case ARM:
+		/* we expect a pulse giving us the first mark */
+		if (width > PPM_MAX_PULSE_WIDTH)
+			goto error;		/* pulse was too long */
+	
+		/* record the mark timing, expect an inactive edge */
+		ppm.last_mark = count;
+		ppm.phase = INACTIVE;
+		return;
+
+	case INACTIVE:
+		/* this edge is not interesting, but now we are ready for the next mark */
+		ppm.phase = ACTIVE;
+
+		/* note that we don't bother looking at the timing of this edge */
+
+		return;
+
+	case ACTIVE:
+		/* we expect a well-formed pulse */
+		if (width > PPM_MAX_PULSE_WIDTH)
+			goto error;		/* pulse was too long */
+
+		/* determine the interval from the last mark */
+		interval = count - ppm.last_mark;
+		ppm.last_mark = count;
+
+		/* if the mark-mark timing is out of bounds, abandon the frame */
+		if ((interval < PPM_MIN_CHANNEL_VALUE) || (interval > PPM_MAX_CHANNEL_VALUE))
+			goto error;
+
+		/* if we have room to store the value, do so */
+		if (ppm.next_channel < PPM_MAX_CHANNELS)
+			ppm_temp_buffer[ppm.next_channel++] = interval;
+
+		ppm.phase = INACTIVE;
+		return;		
+
+	}
+
+	/* the state machine is corrupted; reset it */
+
+error:
+	/* we don't like the state of the decoder, reset it and try again */
+	ppm.phase = UNSYNCH;
+	ppm_decoded_channels = 0;
+}
+
+static int
+ppm_read(struct file *filp, char *buffer, size_t len)
+{
+	size_t avail;
+
+	/* the size of the returned data indicates the number of channels */
+	avail = ppm_decoded_channels * sizeof(ppm_buffer[0]);
+
+	/* if we have not decoded a frame, that's an I/O error */
+	if (avail == 0)
+		return -EIO;
+
+	/* if the caller's buffer is too small, that's also bad */
+	if (len < avail)
+		return -EFBIG;
+
+	/* if the caller doesn't want to block, and there is no fresh data, that's EWOULDBLOCK */
+	if ((filp->f_oflags & O_NONBLOCK) && (!ppm_fresh_data))
+		return -EWOULDBLOCK;
+
+	/*
+	 * Return the channel data.
+	 *
+	 * Note that we have to block the HRT while copying to avoid the
+	 * possibility that we'll get interrupted in the middle of copying 
+	 * a single value.
+	 */
+	irqstate_t flags = irqsave();
+
+	memcpy(buffer, ppm_buffer, avail);
+	ppm_fresh_data = false;
+
+	irqrestore(flags);
+
+	return OK;
+}
+
+static int
+ppm_ioctl(struct file *filp, int cmd, unsigned long arg)
+{
+	switch (cmd) {
+	case PPM_INPUT_STATUS:
+		/* if we have received a frame within the timeout, the signal is "good" */
+		if ((hrt_absolute_time() - ppm_timestamp) < PPM_INPUT_TIMEOUT) {
+			*(ppm_input_status_t *)arg = PPM_STATUS_SIGNAL_CURRENT;
+		} else {
+			/* reset the number of channels so that any attempt to read data will fail */
+			ppm_decoded_channels = 0;
+			*(ppm_input_status_t *)arg = PPM_STATUS_NO_SIGNAL;
+		}
+		return OK;
+
+	case PPM_INPUT_CHANNELS:
+		*(ppm_input_channel_count_t *)arg = ppm_decoded_channels;
+		return OK;
+
+	default:
+		return -ENOTTY;
+	}
+
+}
+
+#endif /* CONFIG_HRT_PPM */
+
+
diff --git a/nuttx/configs/px4io/src/drv_pwm_servo.c b/nuttx/configs/px4io/src/drv_pwm_servo.c
new file mode 100644
index 000000000..7f3238da3
--- /dev/null
+++ b/nuttx/configs/px4io/src/drv_pwm_servo.c
@@ -0,0 +1,316 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file Servo driver supporting PWM servos connected to STM32 timer blocks.
+ *
+ * Works with any of the 'generic' or 'advanced' STM32 timers that
+ * have output pins, does not require an interrupt.
+ */
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <debug.h>
+#include <errno.h>
+
+#include <arch/board/board.h>
+#include <arch/board/drv_pwm_servo.h>
+
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+#ifdef CONFIG_PWM_SERVO
+
+static const struct pwm_servo_config	*cfg;
+
+#define REG(_tmr, _reg)	(*(volatile uint32_t *)(cfg->timers[_tmr].base + _reg))
+
+#define rCR1(_tmr)    	REG(_tmr, STM32_GTIM_CR1_OFFSET)
+#define rCR2(_tmr)    	REG(_tmr, STM32_GTIM_CR2_OFFSET)
+#define rSMCR(_tmr)   	REG(_tmr, STM32_GTIM_SMCR_OFFSET)
+#define rDIER(_tmr)   	REG(_tmr, STM32_GTIM_DIER_OFFSET)
+#define rSR(_tmr)     	REG(_tmr, STM32_GTIM_SR_OFFSET)
+#define rEGR(_tmr)    	REG(_tmr, STM32_GTIM_EGR_OFFSET)
+#define rCCMR1(_tmr)  	REG(_tmr, STM32_GTIM_CCMR1_OFFSET)
+#define rCCMR2(_tmr)  	REG(_tmr, STM32_GTIM_CCMR2_OFFSET)
+#define rCCER(_tmr)   	REG(_tmr, STM32_GTIM_CCER_OFFSET)
+#define rCNT(_tmr)    	REG(_tmr, STM32_GTIM_CNT_OFFSET)
+#define rPSC(_tmr)    	REG(_tmr, STM32_GTIM_PSC_OFFSET)
+#define rARR(_tmr)    	REG(_tmr, STM32_GTIM_ARR_OFFSET)
+#define rCCR1(_tmr)   	REG(_tmr, STM32_GTIM_CCR1_OFFSET)
+#define rCCR2(_tmr)   	REG(_tmr, STM32_GTIM_CCR2_OFFSET)
+#define rCCR3(_tmr)   	REG(_tmr, STM32_GTIM_CCR3_OFFSET)
+#define rCCR4(_tmr)   	REG(_tmr, STM32_GTIM_CCR4_OFFSET)
+#define rDCR(_tmr)    	REG(_tmr, STM32_GTIM_DCR_OFFSET)
+#define rDMAR(_tmr)   	REG(_tmr, STM32_GTIM_DMAR_OFFSET)
+
+static void
+pwm_timer_init(unsigned timer)
+{
+	/* enable the timer clock before we try to talk to it */
+	modifyreg32(cfg->timers[timer].clock_register, 0, cfg->timers[timer].clock_bit);
+
+	/* disable and configure the timer */
+	rCR1(timer) = 0;
+	rCR2(timer) = 0;
+	rSMCR(timer) = 0;
+	rDIER(timer) = 0;
+	rCCER(timer) = 0;
+	rCCMR1(timer) = 0;
+	rCCMR2(timer) = 0;
+	rCCER(timer) = 0;
+	rDCR(timer) = 0;
+
+	/* configure the timer to free-run at 1MHz */
+	rPSC(timer) = cfg->timers[timer].clock_freq / 1000000;
+
+	/* and update at the desired rate */
+	rARR(timer) = 1000000 / cfg->update_rate;
+
+	/* generate an update event; reloads the counter and all registers */
+	rEGR(timer) = GTIM_EGR_UG;
+
+	/* note that the timer is left disabled - arming is performed separately */
+}
+
+static void
+pwm_servos_arm(bool armed)
+{
+	/* iterate timers and arm/disarm appropriately */
+	for (unsigned i = 0; i < PWM_SERVO_MAX_TIMERS; i++) {
+		if (cfg->timers[i].base != 0)
+			rCR1(i) = armed ? GTIM_CR1_CEN : 0;
+	}
+}
+
+static void
+pwm_channel_init(unsigned channel)
+{
+	unsigned timer = cfg->channels[channel].timer_index;
+
+	/* configure the GPIO first */
+	stm32_configgpio(cfg->channels[channel].gpio);
+
+	/* configure the channel */
+	switch (cfg->channels[channel].timer_channel) {
+		case 1:
+			rCCMR1(timer) |= (6 << 4);
+			rCCR1(timer) = cfg->channels[channel].default_value;
+			rCCER(timer) |= (1 << 0);
+			break;
+		case 2:
+			rCCMR1(timer) |= (6 << 12);
+			rCCR2(timer) = cfg->channels[channel].default_value;
+			rCCER(timer) |= (1 << 4);
+			break;
+		case 3:
+			rCCMR2(timer) |= (6 << 4);
+			rCCR3(timer) = cfg->channels[channel].default_value;
+			rCCER(timer) |= (1 << 8);
+			break;
+		case 4:
+			rCCMR2(timer) |= (6 << 12);
+			rCCR4(timer) = cfg->channels[channel].default_value;
+			rCCER(timer) |= (1 << 12);
+			break;
+	}
+}
+
+static void
+pwm_channel_set(unsigned channel, servo_position_t value)
+{
+	if (channel >= PWM_SERVO_MAX_CHANNELS) {
+		lldbg("pwm_channel_set: bogus channel %u\n", channel);
+		return;
+	}
+
+	unsigned timer = cfg->channels[channel].timer_index;
+
+	/* test timer for validity */
+	if ((cfg->timers[timer].base == 0) ||
+	    (cfg->channels[channel].gpio == 0))
+		return;
+
+	/* configure the channel */
+	switch (cfg->channels[channel].timer_channel) {
+		case 1:
+			rCCR1(timer) = value;
+			break;
+		case 2:
+			rCCR2(timer) = value;
+			break;
+		case 3:
+			rCCR3(timer) = value;
+			break;
+		case 4:
+			rCCR4(timer) = value;
+			break;
+	}
+}
+
+static servo_position_t
+pwm_channel_get(unsigned channel)
+{
+	if (channel >= PWM_SERVO_MAX_CHANNELS) {
+		lldbg("pwm_channel_get: bogus channel %u\n", channel);
+		return 0;
+	}
+
+	unsigned timer = cfg->channels[channel].timer_index;
+	servo_position_t value = 0;
+
+	/* test timer for validity */
+	if ((cfg->timers[timer].base == 0) ||
+	    (cfg->channels[channel].gpio == 0))
+		return 0;
+
+	/* configure the channel */
+	switch (cfg->channels[channel].timer_channel) {
+		case 1:
+			value = rCCR1(timer);
+			break;
+		case 2:
+			value = rCCR2(timer);
+			break;
+		case 3:
+			value = rCCR3(timer);
+			break;
+		case 4:
+			value = rCCR4(timer);
+			break;
+	}
+	return value;
+}
+
+static int	pwm_servo_write(struct file *filp, const char *buffer, size_t len);
+static int	pwm_servo_read(struct file *filp, char *buffer, size_t len);
+static int	pwm_servo_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+static const struct file_operations pwm_servo_fops = {
+	.write = pwm_servo_write,
+	.read = pwm_servo_read,
+	.ioctl = pwm_servo_ioctl
+};
+
+static int
+pwm_servo_write(struct file *filp, const char *buffer, size_t len)
+{
+	unsigned channels = len / sizeof(servo_position_t);
+	servo_position_t *pdata = (servo_position_t *)buffer;
+	unsigned i;
+
+	if (channels > PWM_SERVO_MAX_CHANNELS)
+		return -EIO;
+
+	for (i = 0; i < channels; i++)
+		pwm_channel_set(i, pdata[i]);
+
+	return i * sizeof(servo_position_t);
+}
+
+static int
+pwm_servo_read(struct file *filp, char *buffer, size_t len)
+{
+	unsigned channels = len / sizeof(servo_position_t);
+	servo_position_t *pdata = (servo_position_t *)buffer;
+	unsigned i;
+
+	if (channels > PWM_SERVO_MAX_CHANNELS)
+		return -EIO;
+
+	for (i = 0; i < channels; i++)
+		pdata[i] = pwm_channel_get(i);
+
+	return i * sizeof(servo_position_t);
+}
+
+static int
+pwm_servo_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+	/* regular ioctl? */
+	switch (cmd) {
+		case PWM_SERVO_ARM:
+			pwm_servos_arm(true);
+			return 0;
+
+		case PWM_SERVO_DISARM:
+			pwm_servos_arm(false);
+			return 0;
+	}
+
+	/* channel set? */
+	if ((cmd >= PWM_SERVO_SET(0)) && (cmd < PWM_SERVO_SET(PWM_SERVO_MAX_CHANNELS))) {
+		/* XXX sanity-check value? */
+		pwm_channel_set(cmd - PWM_SERVO_SET(0), (servo_position_t)arg);
+		return 0;
+	}
+
+	/* channel get? */
+	if ((cmd >= PWM_SERVO_GET(0)) && (cmd < PWM_SERVO_GET(PWM_SERVO_MAX_CHANNELS))) {
+		/* XXX sanity-check value? */
+		*(servo_position_t *)arg = pwm_channel_get(cmd - PWM_SERVO_GET(0));
+		return 0;
+	}
+
+	/* not a recognised value */
+	return -ENOTTY;
+}
+
+
+int
+pwm_servo_init(const struct pwm_servo_config *config)
+{
+	/* save a pointer to the configuration */
+	cfg = config;
+
+	/* do basic timer initialisation first */
+	for (unsigned i = 0; i < PWM_SERVO_MAX_TIMERS; i++) {
+		if (cfg->timers[i].base != 0)
+			pwm_timer_init(i);
+	}
+
+	/* now init channels */
+	for (unsigned i = 0; i < PWM_SERVO_MAX_CHANNELS; i++) {
+		if (cfg->channels[i].gpio != 0)
+			pwm_channel_init(i);
+	}
+
+	/* register the device */
+	return register_driver("/dev/pwm_servo", &pwm_servo_fops, 0666, NULL);
+}
+
+#endif /* CONFIG_PWM_SERVO */
\ No newline at end of file
diff --git a/nuttx/configs/px4io/src/px4io_internal.h b/nuttx/configs/px4io/src/px4io_internal.h
new file mode 100644
index 000000000..877a06653
--- /dev/null
+++ b/nuttx/configs/px4io/src/px4io_internal.h
@@ -0,0 +1,117 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file PX4IO hardware definitions.
+ */
+
+#ifndef __CONFIGS_PX4IO_SRC_PX4IO_INTERNAL_H
+#define __CONFIGS_PX4IO_SRC_PX4IO_INTERNAL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* PX4IO GPIOs **********************************************************************/
+/* LEDs */
+
+#define GPIO_LED1       (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
+                         GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_LED2       (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
+                         GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_LED3       (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
+                         GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
+
+/* R/C in/out channels **************************************************************/
+
+/* XXX just GPIOs for now - eventually timer pins */
+
+#define GPIO_CH1_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_CH2_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_CH3_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_CH4_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_CH5_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_CH6_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_CH7_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_CH8_IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+
+#define GPIO_CH1_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_CH2_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_CH3_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_CH4_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_CH5_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_CH6_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_CH7_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_CH8_OUT    (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1)
+
+/* Safety switch button *************************************************************/
+
+#define GPIO_BTN_SAFETY (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
+
+/* Power switch controls ************************************************************/
+
+#define GPIO_ACC1_PWR_EN  (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13)
+#define GPIO_ACC2_PWR_EN  (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN14)
+#define GPIO_SERVO_PWR_EN (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN15)
+
+#define GPIO_ACC_OC_DETECT   (GPIO_INPUT|GPIO_CNF_INPULLUP|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SERVO_OC_DETECT (GPIO_INPUT|GPIO_CNF_INPULLUP|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
+
+#define GPIO_RELAY1_EN (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_RELAY2_EN (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN12)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_PX4IO_SRC_PX4IO_INTERNAL_H */
+
diff --git a/nuttx/configs/px4io/src/up_adc.c b/nuttx/configs/px4io/src/up_adc.c
new file mode 100644
index 000000000..c19f57f96
--- /dev/null
+++ b/nuttx/configs/px4io/src/up_adc.c
@@ -0,0 +1,164 @@
+/************************************************************************************
+ * configs/stm3210e-eval/src/up_adc.c
+ * arch/arm/src/board/up_adc.c
+ *
+ *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/analog/adc.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "stm32_pwm.h"
+#include "px4io-internal.h"
+
+#ifdef CONFIG_ADC
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+/* Up to 3 ADC interfaces are supported */
+
+#if STM32_NADC < 3
+#  undef CONFIG_STM32_ADC3
+#endif
+
+#if STM32_NADC < 2
+#  undef CONFIG_STM32_ADC2
+#endif
+
+#if STM32_NADC < 1
+#  undef CONFIG_STM32_ADC1
+#endif
+
+#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3)
+#ifndef CONFIG_STM32_ADC1
+#  warning "Channel information only available for ADC1"
+#endif
+
+/* The number of ADC channels in the conversion list */
+
+#define ADC1_NCHANNELS 2
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+/* Identifying number of each ADC channel: Variable Resistor */
+
+#ifdef CONFIG_STM32_ADC1
+static const uint8_t  g_chanlist[ADC1_NCHANNELS] = {4, 5};
+
+/* Configurations of pins used byte each ADC channels */
+
+static const uint32_t g_pinlist[ADC1_NCHANNELS]  = {GPIO_ADC1_IN4, GPIO_ADC1_IN5};
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: adc_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/adc.
+ *
+ ************************************************************************************/
+
+int adc_devinit(void)
+{
+#ifdef CONFIG_STM32_ADC1
+  static bool initialized = false;
+  struct adc_dev_s *adc;
+  int ret;
+  int i;
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+      /* Configure the pins as analog inputs for the selected channels */
+
+      for (i = 0; i < ADC1_NCHANNELS; i++)
+        {
+          stm32_configgpio(g_pinlist[i]);
+        }
+
+      /* Call stm32_adcinitialize() to get an instance of the ADC interface */
+
+      adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS);
+      if (adc == NULL)
+        {
+          adbg("ERROR: Failed to get ADC interface\n");
+          return -ENODEV;
+        }
+
+      /* Register the ADC driver at "/dev/adc0" */
+
+      ret = adc_register("/dev/adc0", adc);
+      if (ret < 0)
+        {
+          adbg("adc_register failed: %d\n", ret);
+          return ret;
+        }
+
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */
+#endif /* CONFIG_ADC */
diff --git a/nuttx/configs/px4io/src/up_boardinitialize.c b/nuttx/configs/px4io/src/up_boardinitialize.c
new file mode 100644
index 000000000..f6900ebb5
--- /dev/null
+++ b/nuttx/configs/px4io/src/up_boardinitialize.c
@@ -0,0 +1,178 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file Board initialisation and configuration data.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <arch/board/board.h>
+#include <arch/board/up_boardinitialize.h>
+#include <arch/board/up_hrt.h>
+#include <arch/board/drv_pwm_servo.h>
+#include <arch/board/drv_gpio.h>
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_internal.h"
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Debug ********************************************************************/
+
+/* Configuration ************************************************************/
+
+#if CONFIG_PWM_SERVO
+  /*
+   * Servo configuration for the PX4IO board.
+   */
+  static const struct pwm_servo_config servo_config = {
+    .update_rate = 50,
+    .timers = {
+      {
+        .base = STM32_TIM2_BASE,
+        .clock_register = STM32_RCC_APB1ENR,
+        .clock_bit = RCC_APB1ENR_TIM2EN,
+        .clock_freq = STM32_APB1_TIM2_CLKIN
+      },
+      {
+        .base = STM32_TIM3_BASE,
+        .clock_register = STM32_RCC_APB1ENR,
+        .clock_bit = RCC_APB1ENR_TIM3EN,
+        .clock_freq = STM32_APB1_TIM3_CLKIN
+      },
+      {
+        .base = STM32_TIM4_BASE,
+        .clock_register = STM32_RCC_APB1ENR,
+        .clock_bit = RCC_APB1ENR_TIM4EN,
+        .clock_freq = STM32_APB1_TIM4_CLKIN
+      },
+    },
+    .channels = {
+      {
+        .gpio = GPIO_TIM2_CH1OUT,
+        .timer_index = 0,
+        .timer_channel = 1,
+        .default_value = 1000,
+      },
+      {
+        .gpio = GPIO_TIM2_CH2OUT,
+        .timer_index = 0,
+        .timer_channel = 2,
+        .default_value = 1000,
+      },
+      {
+        .gpio = GPIO_TIM4_CH3OUT,
+        .timer_index = 2,
+        .timer_channel = 3,
+        .default_value = 1000,
+      },
+      {
+        .gpio = GPIO_TIM4_CH4OUT,
+        .timer_index = 2,
+        .timer_channel = 4,
+        .default_value = 1000,
+      },
+      {
+        .gpio = GPIO_TIM3_CH1OUT,
+        .timer_index = 1,
+        .timer_channel = 1,
+        .default_value = 1000,
+      },
+      {
+        .gpio = GPIO_TIM3_CH2OUT,
+        .timer_index = 1,
+        .timer_channel = 2,
+        .default_value = 1000,
+      },
+      {
+        .gpio = GPIO_TIM3_CH3OUT,
+        .timer_index = 1,
+        .timer_channel = 3,
+        .default_value = 1000,
+      },
+      {
+        .gpio = GPIO_TIM3_CH4OUT,
+        .timer_index = 1,
+        .timer_channel = 4,
+        .default_value = 1000,
+      },
+    }
+  };
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nsh_archinitialize
+ *
+ * Description:
+ *   Perform architecture specific initialization
+ *
+ ****************************************************************************/
+
+int up_boardinitialize()
+{
+	/* configure the high-resolution time/callout interface */
+#ifdef CONFIG_HRT_TIMER
+	hrt_init(CONFIG_HRT_TIMER);
+#endif
+
+	/* configure the PWM servo driver */
+#if CONFIG_PWM_SERVO
+	pwm_servo_init(&servo_config);
+#endif
+
+  /* configure the GPIO driver */
+  gpio_drv_init();
+
+  return OK;
+}
diff --git a/nuttx/configs/px4io/src/up_boot.c b/nuttx/configs/px4io/src/up_boot.c
new file mode 100644
index 000000000..9d6a3b246
--- /dev/null
+++ b/nuttx/configs/px4io/src/up_boot.c
@@ -0,0 +1,82 @@
+/************************************************************************************

+ * configs/stm3210e-eval/src/up_boot.c

+ * arch/arm/src/board/up_boot.c

+ *

+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions

+ * are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright

+ *    notice, this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright

+ *    notice, this list of conditions and the following disclaimer in

+ *    the documentation and/or other materials provided with the

+ *    distribution.

+ * 3. Neither the name NuttX nor the names of its contributors may be

+ *    used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ ************************************************************************************/

+

+/************************************************************************************

+ * Included Files

+ ************************************************************************************/

+

+#include <nuttx/config.h>

+

+#include <debug.h>

+

+#include <arch/board/board.h>

+

+#include "up_arch.h"

+#include "px4io_internal.h"

+#include <arch/board/up_hrt.h>

+#include <arch/board/drv_pwm_servo.h>

+

+/************************************************************************************

+ * Definitions

+ ************************************************************************************/

+

+/************************************************************************************

+ * Private Functions

+ ************************************************************************************/

+

+/************************************************************************************

+ * Public Functions

+ ************************************************************************************/

+

+/************************************************************************************

+ * Name: stm32_boardinitialize

+ *

+ * Description:

+ *   All STM32 architectures must provide the following entry point.  This entry point

+ *   is called early in the intitialization -- after all memory has been configured

+ *   and mapped but before any devices have been initialized.

+ *

+ ************************************************************************************/

+

+void stm32_boardinitialize(void)

+{

+	/* Configure on-board LEDs if LED support has been selected. */

+

+#ifdef CONFIG_ARCH_LEDS

+	up_ledinit();

+#endif

+

+}

diff --git a/nuttx/configs/px4io/src/up_hrt.c b/nuttx/configs/px4io/src/up_hrt.c
new file mode 100644
index 000000000..d0c46bd26
--- /dev/null
+++ b/nuttx/configs/px4io/src/up_hrt.c
@@ -0,0 +1,664 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+ 
+/**
+ * @file High-resolution timer callouts and timekeeping.
+ *
+ * This can use any general or advanced STM32 timer.
+ *
+ * Note that really, this could use systick too, but that's
+ * monopolised by NuttX and stealing it would just be awkward.
+ *
+ * We don't use the NuttX STM32 driver per se; rather, we 
+ * claim the timer and then drive it directly.
+ */
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <time.h>
+#include <queue.h>
+#include <errno.h>
+#include <string.h>
+
+#include <arch/board/board.h>
+#include <arch/board/up_hrt.h>
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_internal.h"
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+#ifdef CONFIG_HRT_TIMER
+
+/* HRT configuration */
+#if   HRT_TIMER == 1
+# define HRT_TIMER_BASE		STM32_TIM1_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB2ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM1EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1CC
+# define HRT_TIMER_CLOCK	STM32_APB2_TIM1_CLKIN
+# if CONFIG_STM32_TIM1
+#  error must not set CONFIG_STM32_TIM1=y and HRT_TIMER=1
+# endif
+#elif HRT_TIMER == 2
+# define HRT_TIMER_BASE		STM32_TIM2_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM2EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM2
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM2_CLKIN
+# if CONFIG_STM32_TIM2
+#  error must not set CONFIG_STM32_TIM2=y and HRT_TIMER=2
+# endif
+#elif HRT_TIMER == 3
+# define HRT_TIMER_BASE		STM32_TIM3_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM3EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM3
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM3_CLKIN
+# if CONFIG_STM32_TIM3
+#  error must not set CONFIG_STM32_TIM3=y and HRT_TIMER=3
+# endif
+#elif HRT_TIMER == 4
+# define HRT_TIMER_BASE		STM32_TIM4_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM4EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM4
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM4_CLKIN
+# if CONFIG_STM32_TIM4
+#  error must not set CONFIG_STM32_TIM4=y and HRT_TIMER=4
+# endif
+#elif HRT_TIMER == 5
+# define HRT_TIMER_BASE		STM32_TIM5_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM5EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM5
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM5_CLKIN
+# if CONFIG_STM32_TIM5
+#  error must not set CONFIG_STM32_TIM5=y and HRT_TIMER=5
+# endif
+#elif HRT_TIMER == 8
+# define HRT_TIMER_BASE		STM32_TIM8_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB2ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM8EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM8CC
+# define HRT_TIMER_CLOCK	STM32_APB2_TIM8_CLKIN
+# if CONFIG_STM32_TIM8
+#  error must not set CONFIG_STM32_TIM8=y and HRT_TIMER=6
+# endif
+#elif HRT_TIMER == 9
+# define HRT_TIMER_BASE		STM32_TIM9_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM9EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1BRK
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM9_CLKIN
+# if CONFIG_STM32_TIM9
+#  error must not set CONFIG_STM32_TIM9=y and HRT_TIMER=9
+# endif
+#elif HRT_TIMER == 10
+# define HRT_TIMER_BASE		STM32_TIM10_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM10EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1UP
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM10_CLKIN
+# if CONFIG_STM32_TIM10
+#  error must not set CONFIG_STM32_TIM11=y and HRT_TIMER=10
+# endif
+#elif HRT_TIMER == 11
+# define HRT_TIMER_BASE		STM32_TIM11_BASE
+# define HRT_TIMER_POWER_REG	STM32_RCC_APB1ENR
+# define HRT_TIMER_POWER_BIT	RCC_APB2ENR_TIM11EN
+# define HRT_TIMER_VECTOR	STM32_IRQ_TIM1TRGCOM
+# define HRT_TIMER_CLOCK	STM32_APB1_TIM11_CLKIN
+# if CONFIG_STM32_TIM11
+#  error must not set CONFIG_STM32_TIM11=y and HRT_TIMER=11
+# endif
+#else
+# error HRT_TIMER must be set in board.h if CONFIG_HRT_TIMER=y
+#endif
+
+/*
+ * HRT clock must be a multiple of 1MHz greater than 1MHz
+ */
+#if (HRT_TIMER_CLOCK % 1000000) != 0
+# error HRT_TIMER_CLOCK must be a multiple of 1MHz
+#endif
+#if HRT_TIMER_CLOCK <= 1000000
+# error HRT_TIMER_CLOCK must be greater than 1MHz
+#endif
+
+/*
+ * Minimum/maximum deadlines.
+ *
+ * These are suitable for use with a 16-bit timer/counter clocked
+ * at 1MHz.  The high-resolution timer need only guarantee that it
+ * not wrap more than once in the 50ms period for absolute time to
+ * be consistently maintained.
+ *
+ * The minimum deadline must be such that the time taken between
+ * reading a time and writing a deadline to the timer cannot
+ * result in missing the deadline.
+ */
+#define HRT_INTERVAL_MIN	50
+#define HRT_INTERVAL_MAX	50000
+
+/*
+ * Period of the free-running counter, in microseconds.
+ */
+#define HRT_COUNTER_PERIOD	65536
+
+/*
+ * Scaling factor(s) for the free-running counter; convert an input
+ * in counts to a time in microseconds.
+ */
+#define HRT_COUNTER_SCALE(_c)	(_c)
+
+/*
+ * Timer register accessors
+ */
+#define REG(_reg)	(*(volatile uint32_t *)(HRT_TIMER_BASE + _reg))
+
+#define rCR1     	REG(STM32_GTIM_CR1_OFFSET)
+#define rCR2     	REG(STM32_GTIM_CR2_OFFSET)
+#define rSMCR    	REG(STM32_GTIM_SMCR_OFFSET)
+#define rDIER    	REG(STM32_GTIM_DIER_OFFSET)
+#define rSR      	REG(STM32_GTIM_SR_OFFSET)
+#define rEGR     	REG(STM32_GTIM_EGR_OFFSET)
+#define rCCMR1   	REG(STM32_GTIM_CCMR1_OFFSET)
+#define rCCMR2   	REG(STM32_GTIM_CCMR2_OFFSET)
+#define rCCER    	REG(STM32_GTIM_CCER_OFFSET)
+#define rCNT     	REG(STM32_GTIM_CNT_OFFSET)
+#define rPSC     	REG(STM32_GTIM_PSC_OFFSET)
+#define rARR     	REG(STM32_GTIM_ARR_OFFSET)
+#define rCCR1    	REG(STM32_GTIM_CCR1_OFFSET)
+#define rCCR2    	REG(STM32_GTIM_CCR2_OFFSET)
+#define rCCR3    	REG(STM32_GTIM_CCR3_OFFSET)
+#define rCCR4    	REG(STM32_GTIM_CCR4_OFFSET)
+#define rDCR     	REG(STM32_GTIM_DCR_OFFSET)
+#define rDMAR    	REG(STM32_GTIM_DMAR_OFFSET)
+
+/*
+ * Specific registers and bits used by HRT sub-functions
+ */
+#if HRT_TIMER_CHANNEL == 1
+# define rCCR_HRT	rCCR1			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC1IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC1IF		/* interrupt status for HRT */
+#elif HRT_TIMER_CHANNEL == 2
+# define rCCR_HRT	rCCR2			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC2IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC2IF		/* interrupt status for HRT */
+#elif HRT_TIMER_CHANNEL == 3
+# define rCCR_HRT	rCCR3			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC3IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC3IF		/* interrupt status for HRT */
+#elif HRT_TIMER_CHANNEL == 4
+# define rCCR_HRT	rCCR4			/* compare register for HRT */
+# define DIER_HRT	GTIM_DIER_CC4IE		/* interrupt enable for HRT */
+# define SR_INT_HRT	GTIM_SR_CC4IF		/* interrupt status for HRT */
+#else
+# error HRT_TIMER_CHANNEL must be a value between 1 and 4
+#endif
+
+/*
+ * Queue of callout entries.
+ */
+static struct sq_queue_s	callout_queue;
+
+/*
+ * The time corresponding to a counter value of zero, as of the
+ * last time that hrt_absolute_time() was called.
+ */
+static hrt_abstime		base_time;
+
+/* timer-specific functions */
+static void		hrt_tim_init(int timer);
+static int		hrt_tim_isr(int irq, void *context);
+
+/* callout list manipulation */
+static void		hrt_call_enter(struct hrt_call *entry);
+static void		hrt_call_reschedule(void);
+static void		hrt_call_invoke(void);
+
+/*
+ * Specific registers and bits used by PPM sub-functions
+ */
+#ifdef CONFIG_HRT_PPM
+# include <arch/board/drv_ppm_input.h>
+
+/* 
+ * If the timer hardware doesn't support GTIM_CCER_CCxNP, then we will work around it.
+ */
+# ifndef GTIM_CCER_CC1NP
+#  define GTIM_CCER_CC1NP 0
+#  define GTIM_CCER_CC2NP 0
+#  define GTIM_CCER_CC3NP 0
+#  define GTIM_CCER_CC4NP 0
+#  define PPM_EDGE_FLIP
+# endif
+
+# if HRT_PPM_CHANNEL == 1
+#  define rCCR_PPM	rCCR1			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC1IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC1IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC1OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	1			/* on TI1 */
+#  define CCMR2_PPM	0
+#  define CCER_PPM	(GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP) /* CC1, both edges */
+#  define CCER_PPM_FLIP	GTIM_CCER_CC1P
+# elif HRT_PPM_CHANNEL == 2
+#  define rCCR_PPM	rCCR2			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC2IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC2IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC2OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	2			/* on TI2 */
+#  define CCMR2_PPM	0
+#  define CCER_PPM	(GTIM_CCER_CC2E | GTIM_CCER_CC2P | GTIM_CCER_CC2NP) /* CC2, both edges */
+#  define CCER_PPM_FLIP	GTIM_CCER_CC2P
+# elif HRT_PPM_CHANNEL == 3
+#  define rCCR_PPM	rCCR3			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC3IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC3IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC3OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	0
+#  define CCMR2_PPM	1			/* on TI3 */
+#  define CCER_PPM	(GTIM_CCER_CC3E | GTIM_CCER_CC3P | GTIM_CCER_CC3NP) /* CC3, both edges */
+#  define CCER_PPM_FLIP	GTIM_CCER_CC3P
+# elif HRT_PPM_CHANNEL == 4
+#  define rCCR_PPM	rCCR4			/* capture register for PPM */
+#  define DIER_PPM	GTIM_DIER_CC4IE		/* capture interrupt (non-DMA mode) */
+#  define SR_INT_PPM	GTIM_SR_CC4IF		/* capture interrupt (non-DMA mode) */
+#  define SR_OVF_PPM	GTIM_SR_CC4OF		/* capture overflow (non-DMA mode) */
+#  define CCMR1_PPM	0
+#  define CCMR2_PPM	2			/* on TI4 */
+#  define CCER_PPM	(GTIM_CCER_CC4E | GTIM_CCER_CC4P | GTIM_CCER_CC4NP) /* CC4, both edges */
+#  define CCER_PPM_FLIP	GTIM_CCER_CC4P
+# else
+#  error HRT_PPM_CHANNEL must be a value between 1 and 4 if CONFIG_HRT_PPM is set
+# endif
+#else
+/* disable the PPM configuration */
+# define rCCR_PPM	0
+# define DIER_PPM	0
+# define SR_INT_PPM	0
+# define SR_OVF_PPM	0
+# define CCMR1_PPM	0
+# define CCMR2_PPM	0
+# define CCER_PPM	0
+#endif /* CONFIG_HRT_PPM */
+
+/*
+ * Initialise the timer we are going to use.
+ *
+ * We expect that we'll own one of the reduced-function STM32 general
+ * timers, and that we can use channel 1 in compare mode.
+ */
+static void
+hrt_tim_init(int timer)
+{
+	/* clock/power on our timer */
+        modifyreg32(HRT_TIMER_POWER_REG, 0, HRT_TIMER_POWER_BIT);
+
+        /* claim our interrupt vector */
+        irq_attach(HRT_TIMER_VECTOR, hrt_tim_isr);
+
+        /* disable and configure the timer */
+        rCR1 = 0;
+        rCR2 = 0;
+        rSMCR = 0;
+        rDIER = DIER_HRT | DIER_PPM;
+        rCCER = 0;		/* unlock CCMR* registers */
+        rCCMR1 = CCMR1_PPM;		
+        rCCMR2 = CCMR2_PPM;
+        rCCER = CCER_PPM;
+        rDCR = 0;
+
+        /* configure the timer to free-run at 1MHz */
+        rPSC = (HRT_TIMER_CLOCK / 1000000) - 1;	/* this really only works for whole-MHz clocks */
+
+        /* run the full span of the counter */
+        rARR = 0xffff;
+
+        /* set an initial capture a little ways off */
+        rCCR_HRT = 1000;
+
+        /* generate an update event; reloads the counter, all registers */
+        rEGR = GTIM_EGR_UG;
+
+        /* enable the timer */
+        rCR1 = GTIM_CR1_CEN;
+
+        /* enable interrupts */
+        up_enable_irq(HRT_TIMER_VECTOR);
+}
+
+/*
+ * Handle the compare interupt by calling the callout dispatcher
+ * and then re-scheduling the next deadline.
+ */
+static int
+hrt_tim_isr(int irq, void *context)
+{
+	uint32_t status;
+
+	/* copy interrupt status */
+	status = rSR;
+
+	/* ack the interrupts we just read */
+	rSR = ~status;
+
+#ifdef CONFIG_HRT_PPM
+	/* was this a PPM edge? */
+	if (status & (SR_INT_PPM | SR_OVF_PPM)) {
+
+		/* if required, flip edge sensitivity */
+# ifdef PPM_EDGE_FLIP
+		rCCER ^= CCER_PPM_FLIP;
+# endif
+
+		/* feed the edge to the PPM decoder */
+		ppm_input_decode(status & SR_OVF_PPM, rCCR_PPM);
+	}
+#endif
+
+	/* was this a timer tick? */
+	if (status & SR_INT_HRT) {
+		/* run any callouts that have met their deadline */
+		hrt_call_invoke();
+
+		/* and schedule the next interrupt */
+		hrt_call_reschedule();
+	}
+
+	return OK;
+}
+
+/*
+ * Fetch a never-wrapping absolute time value in microseconds from
+ * some arbitrary epoch shortly after system start.
+ */
+hrt_abstime
+hrt_absolute_time(void)
+{
+	static uint32_t last_count;
+	uint32_t	count;
+	uint32_t	flags = irqsave();
+
+	count = rCNT;
+
+	//lldbg("count %u last_count %u\n", count, last_count);
+
+	/* This simple test is made possible by the guarantee that
+	 * we are always called at least once per counter period.
+	 */
+	if (count < last_count)
+		base_time += HRT_COUNTER_PERIOD;
+
+	last_count = count;
+
+	irqrestore(flags);
+
+	return HRT_COUNTER_SCALE(base_time + count);
+}
+
+/*
+ * Convert a timespec to absolute time
+ */
+hrt_abstime
+ts_to_abstime(struct timespec *ts)
+{
+	hrt_abstime	result;
+
+	result = (hrt_abstime)(ts->tv_sec) * 1000000;
+	result += ts->tv_nsec / 1000;
+
+	return result;
+}
+
+/*
+ * Convert absolute time to a timespec.
+ */
+void
+abstime_to_ts(struct timespec *ts, hrt_abstime abstime)
+{
+	ts->tv_sec = abstime / 1000000;
+	abstime -= ts->tv_sec * 1000000;
+	ts->tv_nsec = abstime * 1000;
+}
+
+/*
+ * Initalise the high-resolution timing module.
+ */
+void
+hrt_init(int timer)
+{
+	sq_init(&callout_queue);
+	hrt_tim_init(timer);
+}
+
+/*
+ * Call callout(arg) after interval has elapsed.
+ */
+void
+hrt_call_after(struct hrt_call *entry, hrt_abstime delay, hrt_callout callout, void *arg)
+{
+	entry->deadline = hrt_absolute_time() + delay;
+	entry->period = 0;
+	entry->callout = callout;
+	entry->arg = arg;
+
+	hrt_call_enter(entry);
+}
+
+/*
+ * Call callout(arg) at calltime.
+ */
+void
+hrt_call_at(struct hrt_call *entry, hrt_abstime calltime, hrt_callout callout, void *arg)
+{
+	entry->deadline = calltime;
+	entry->period = 0;
+	entry->callout = callout;
+	entry->arg = arg;
+
+	hrt_call_enter(entry);	
+}
+
+/*
+ * Call callout(arg) every period.
+ */
+void
+hrt_call_every(struct hrt_call *entry, hrt_abstime delay, hrt_abstime interval, hrt_callout callout, void *arg)
+{
+	entry->deadline = hrt_absolute_time() + delay;
+	entry->period = interval;
+	entry->callout = callout;
+	entry->arg = arg;
+
+	hrt_call_enter(entry);	
+}
+
+/*
+ * If this returns true, the call has been invoked and removed from the callout list.
+ *
+ * Always returns false for repeating callouts.
+ */
+bool
+hrt_called(struct hrt_call *entry)
+{
+	bool result;
+
+	irqstate_t flags = irqsave();
+	result = (entry->deadline == 0);
+	irqrestore(flags);
+
+	return result;	
+}
+
+/*
+ * Remove the entry from the callout list.
+ */
+void
+hrt_cancel(struct hrt_call *entry)
+{
+	irqstate_t flags = irqsave();
+
+	sq_rem(&entry->link, &callout_queue);
+	entry->deadline = 0;
+
+	/* if this is a periodic call being removed by the callout, prevent it from
+	 * being re-entered when the callout returns.
+	 */
+	entry->period = 0;
+
+	irqrestore(flags);
+}
+
+static void
+hrt_call_enter(struct hrt_call *entry)
+{
+	irqstate_t flags = irqsave();
+	struct hrt_call	*call, *next;
+
+	call = (struct hrt_call *)sq_peek(&callout_queue);
+
+	if ((call == NULL) || (entry->deadline < call->deadline)) {
+		sq_addfirst(&entry->link, &callout_queue);
+		//lldbg("call enter at head, reschedule\n");
+		/* we changed the next deadline, reschedule the timer event */
+		hrt_call_reschedule();
+	} else {
+		do {
+			next = (struct hrt_call *)sq_next(&call->link);
+			if ((next == NULL) || (entry->deadline < next->deadline)) {
+				//lldbg("call enter after head\n");
+				sq_addafter(&call->link, &entry->link, &callout_queue);
+				break;
+			}
+		} while ((call = next) != NULL);
+	}
+
+	//lldbg("scheduled\n");
+	irqrestore(flags);
+}
+
+static void
+hrt_call_invoke(void)
+{
+	struct hrt_call	*call;
+	hrt_abstime deadline;
+
+	while (true) {
+		/* get the current time */
+		hrt_abstime now = hrt_absolute_time();
+
+		call = (struct hrt_call *)sq_peek(&callout_queue);
+		if (call == NULL)
+			break;
+		if (call->deadline > now)
+			break;
+
+		sq_rem(&call->link, &callout_queue);
+		//lldbg("call pop\n");
+
+		/* save the intended deadline for periodic calls */
+		deadline = call->deadline; 
+
+		/* zero the deadline, as the call has occurred */
+		call->deadline = 0;
+
+		/* invoke the callout (if there is one) */
+		if (call->callout) {
+			//lldbg("call %p: %p(%p)\n", call, call->callout, call->arg);
+			call->callout(call->arg);
+		}
+
+		/* if the callout has a non-zero period, it has to be re-entered */
+		if (call->period != 0) {
+			call->deadline = deadline + call->period;
+			hrt_call_enter(call);
+		}
+	}
+}
+
+/*
+ * Reschedule the next timer interrupt.
+ *
+ * This routine must be called with interrupts disabled.
+ */
+static void
+hrt_call_reschedule()
+{
+	hrt_abstime	now = hrt_absolute_time();
+	struct hrt_call	*next = (struct hrt_call *)sq_peek(&callout_queue);
+	hrt_abstime	deadline = now + HRT_INTERVAL_MAX;
+
+	/*
+	 * Determine what the next deadline will be.
+	 *
+	 * Note that we ensure that this will be within the counter
+	 * period, so that when we truncate all but the low 16 bits
+	 * the next time the compare matches it will be the deadline
+	 * we want.
+	 *
+	 * It is important for accurate timekeeping that the compare
+	 * interrupt fires sufficiently often that the base_time update in 
+	 * hrt_absolute_time runs at least once per timer period.
+	 */
+	if (next != NULL) {
+		//lldbg("entry in queue\n");
+		if (next->deadline <= (now + HRT_INTERVAL_MIN)) {
+			//lldbg("pre-expired\n");
+			/* set a minimal deadline so that we call ASAP */
+			deadline = now + HRT_INTERVAL_MIN;
+		} else if (next->deadline < deadline) {
+			//lldbg("due soon\n");
+			deadline = next->deadline;
+		}
+	}
+	//lldbg("schedule for %u at %u\n", (unsigned)(deadline & 0xffffffff), (unsigned)(now & 0xffffffff));
+
+	/* set the new compare value */
+	rCCR_HRT = deadline & 0xffff;
+}
+
+#endif /* CONFIG_HRT_TIMER */
diff --git a/nuttx/configs/px4io/src/up_nsh.c b/nuttx/configs/px4io/src/up_nsh.c
new file mode 100644
index 000000000..035838780
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+++ b/nuttx/configs/px4io/src/up_nsh.c
@@ -0,0 +1,63 @@
+/****************************************************************************
+ * config/stm3210e_eval/src/up_nsh.c
+ * arch/arm/src/board/up_nsh.c
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include "stm32_internal.h"
+
+#include <arch/board/up_boardinitialize.h>
+
+/****************************************************************************
+ * Name: nsh_archinitialize
+ *
+ * Description:
+ *   Perform architecture specific initialization
+ *
+ ****************************************************************************/
+
+int nsh_archinitialize(void)
+{
+	return up_boardinitialize();
+}