diff options
author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-07-05 22:38:12 +0000 |
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committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-07-05 22:38:12 +0000 |
commit | e7556608daeac18e739b6a10177a1a62662d8c72 (patch) | |
tree | 1eeeac080c7d4b884783b573a1a2c7597d44ec0e /nuttx | |
parent | f2a20bf5193d53f11635652d5c751065c8bc87ae (diff) | |
download | px4-firmware-e7556608daeac18e739b6a10177a1a62662d8c72.tar.gz px4-firmware-e7556608daeac18e739b6a10177a1a62662d8c72.tar.bz2 px4-firmware-e7556608daeac18e739b6a10177a1a62662d8c72.zip |
Add LPC43 clock initialization logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4910 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx')
-rw-r--r-- | nuttx/arch/arm/include/lpc43xx/chip.h | 74 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/Make.defs | 23 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h | 478 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c | 275 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c | 299 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_emacram.h | 62 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_emc.h | 63 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 12 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_start.c | 118 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_usbram.h | 62 | ||||
-rw-r--r-- | nuttx/configs/lpc4330-xplorer/README.txt | 15 | ||||
-rw-r--r-- | nuttx/configs/lpc4330-xplorer/include/board.h | 95 | ||||
-rw-r--r-- | nuttx/configs/lpc4330-xplorer/ostest/Make.defs | 24 | ||||
-rw-r--r-- | nuttx/configs/lpc4330-xplorer/ostest/defconfig | 25 | ||||
-rw-r--r-- | nuttx/configs/lpc4330-xplorer/scripts/ramconfig.ld | 22 | ||||
-rw-r--r-- | nuttx/configs/lpc4330-xplorer/scripts/spificonfig.ld | 22 |
18 files changed, 1321 insertions, 352 deletions
diff --git a/nuttx/arch/arm/include/lpc43xx/chip.h b/nuttx/arch/arm/include/lpc43xx/chip.h index 560420e28..196092617 100644 --- a/nuttx/arch/arm/include/lpc43xx/chip.h +++ b/nuttx/arch/arm/include/lpc43xx/chip.h @@ -60,18 +60,18 @@ * --------------------- -------- ------- ------- ------- * AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 * --------------------- -------- ------- ------- ------- - * BANK 0 (0x2000 0000) 16Kb 16Kb 64Kb 64Kb - * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 - * BANK 2 (0x2000 c000) 16Kb 16Kb NOTE 1 NOTE 1 + * BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb + * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 + * BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb * --------------------- -------- ------- ------- ------- * SUBTOTAL 32Kb 32Kb 64Kb 64Kb * --------------------- -------- ------- ------- ------- * TOTAL 168Kb 200Kb 264Kb 264Kb * --------------------- -------- ------- ------- ------- * - * NOTE 1: The 64Kb of AHB of SRAM on the LPC4330/50 span - * all AHB SRAM banks and so are treated as a single bank - * by the NuttX memory manager. + * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM + * banks but are treated as two banks of 48 an 16Kb by the NuttX memory + * manager. This gives some symmetry to all of the members of the family. */ /* Per the user manual: UM10503, Rev. 1.2 — 8 June 2012 */ @@ -88,9 +88,9 @@ * --------------------- -------- ------- ------- ------- ------- ------- * AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 * --------------------- -------- ------- ------- ------- ------- ------- - * BANK 0 (0x2000 0000) 16Kb 64Kb 64Kb 64Kb 64Kb 64Kb + * BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 - * BANK 2 (0x2000 c000) 16Kb NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 + * BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb * --------------------- -------- ------- ------- ------- ------- ------- * SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb * --------------------- -------- ------- ------- ------- ------- ------- @@ -106,9 +106,9 @@ * TOTAL None None None None 512Kb 1024Kb * --------------------- -------- ------- ------- ------- ------- ------- * - * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span - * all AHB SRAM banks and so are treated as a single bank - * by the NuttX memory manager. + * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM + * banks but are treated as two banks of 48 an 16Kb by the NuttX memory + * manager. This gives some symmetry to all of the members of the family. */ #if defined(CONFIG_ARCH_CHIP_LPC4310FBD144) @@ -218,9 +218,9 @@ # define LPC43_FLASH_BANKB_SIZE (0) # define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (72*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -243,9 +243,9 @@ # define LPC43_FLASH_BANKB_SIZE (0) # define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (72*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -268,9 +268,9 @@ # define LPC43_FLASH_BANKB_SIZE (0) # define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (72*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -293,9 +293,9 @@ # define LPC43_FLASH_BANKB_SIZE (0) # define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (72*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # undef LPC43_NLCD /* No LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -318,9 +318,9 @@ # define LPC43_FLASH_BANKB_SIZE (0) # define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (72*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # define LPC43_NLCD (1) /* One LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -343,9 +343,9 @@ # define LPC43_FLASH_BANKB_SIZE (0) # define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (72*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # define LPC43_NLCD (1) /* One LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -368,9 +368,9 @@ # define LPC43_FLASH_BANKB_SIZE (0) # define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (72*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (0) /* No EEPROM */ # define LPC43_NLCD (1) /* One LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -393,9 +393,9 @@ # define LPC43_FLASH_BANKB_SIZE (256*1025) # define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (40*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -418,9 +418,9 @@ # define LPC43_FLASH_BANKB_SIZE (256*1025) # define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (40*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -443,9 +443,9 @@ # define LPC43_FLASH_BANKB_SIZE (256*1025) # define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (40*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -468,9 +468,9 @@ # define LPC43_FLASH_BANKB_SIZE (512*1025) # define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (40*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -493,9 +493,9 @@ # define LPC43_FLASH_BANKB_SIZE (512*1025) # define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (40*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ @@ -518,9 +518,9 @@ # define LPC43_FLASH_BANKB_SIZE (512*1025) # define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/ # define LPC43_LOCSRAM_BANK1_SIZE (40*1024) -# define LPC43_AHBSRAM_BANK0_SIZE (64*1024) /* 64Kb AHB SRAM */ +# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */ # define LPC43_AHBSRAM_BANK1_SIZE (0) -# define LPC43_AHBSRAM_BANK2_SIZE (0) +# define LPC43_AHBSRAM_BANK2_SIZE (16*1024) # define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */ # define LPC43_NLCD (1) /* Has LCD controller */ # define LPC43_ETHERNET (1) /* One Ethernet controller */ diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs index a6682a272..071a9dd9e 100644 --- a/nuttx/arch/arm/src/lpc43xx/Make.defs +++ b/nuttx/arch/arm/src/lpc43xx/Make.defs @@ -58,8 +58,9 @@ CMN_ASRCS += up_fpu.S endif CHIP_ASRCS = -CHIP_CSRCS = lpc43_clrpend.c lpc43_gpio.c lpc43_irq.c lpc43_lowputc.c -CHIP_CSRCS += lpc43_pinconfig.c lpc43_rgu.c lpc43_start.c lpc43_timerisr.c +CHIP_CSRCS = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c +CHIP_CSRCS += lpc43_irq.c lpc43_lowputc.c lpc43_pinconfig.c lpc43_rgu.c +CHIP_CSRCS += lpc43_start.c lpc43_timerisr.c ifneq ($(CONFIG_IDLE_CUSTOM),y) CHIP_CSRCS += lpc43_idle.c @@ -69,6 +70,10 @@ ifeq ($(CONFIG_DEBUG),y) CHIP_CSRCS += lpc43_debug.c endif +ifeq ($(CONFIG_LPC43_GPDMA),y) +CHIP_CSRCS += lpc43_gpdma.c +endif + ifeq ($(CONFIG_LPC43_SPI),y) CHIP_CSRCS += lpc43_spi.c endif @@ -89,4 +94,18 @@ CHIP_CSRCS += lpc43_i2c.c endif endif +ifeq ($(CONFIG_LPC43_ADC0),y) +CHIP_CSRCS += lpc43_acc.c +else +ifeq ($(CONFIG_LPC43_ADC1),y) +CHIP_CSRCS += lpc43_adc.c +endif +endif +ifeq ($(CONFIG_LPC43_DAC),y) +CHIP_CSRCS += lpc43_acc.c +else +ifeq ($(CONFIG_LPC43_DAC),y) +CHIP_CSRCS += lpc43_adc.c +endif +endif diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h index c07f521d2..0c223335b 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h @@ -165,7 +165,7 @@ #define XTAL_OSC_CTRL_ENABLE (1 << 0) /* Bit 0: Oscillator-pad enable */ #define XTAL_OSC_CTRL_BYPASS (1 << 1) /* Bit 1: Configure crystal or external-clock input */ -#define XTAL_OSC_CTRL_HF (1 << 2) /* Bit 2: Select frequency range +#define XTAL_OSC_CTRL_HF (1 << 2) /* Bit 2: Select frequency range */ /* Bits 3-31: Reserved */ /* PLL0USB status register */ @@ -311,7 +311,7 @@ /* Bits 14-15: Reserved */ #define PLL1_CTRL_MSEL_SHIFT (16) /* Bits 16-17: Feedback-divider division ratio M */ #define PLL1_CTRL_MSEL_MASK (3 << PLL1_CTRL_MSEL_SHIFT) -# define PLL1_CTRL_MSEL_DIV(n) (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */ +# define PLL1_CTRL_MSEL(n) (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */ #define PLL1_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define PLL1_CTRL_CLKSEL_MASK (31 << PLL1_CTRL_CLKSEL_SHIFT) # define PLL1_CLKSEL_32KHZOSC (0 << PLL1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ @@ -422,19 +422,19 @@ /* Bits 12-23: Reserved */ #define BASE_PERIPH_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_PERIPH_CLK_CLKSEL_MASK (31 << BASE_PERIPH_CLK_CLKSEL_SHIFT) -# define BASE_PERIPH_CLKSEL_32KHZOSC (0 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_PERIPH_CLKSEL_IRC (1 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_PERIPH_CLKSEL_ENET_RXCLK (2 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_PERIPH_CLKSEL_ENET_TXCLK (3 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_PERIPH_CLKSEL_GPCLKIN (4 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_PERIPH_CLKSEL_XTAL (6 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_PERIPH_CLKSEL_PLL0AUDIO (8 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_PERIPH_CLKSEL_PLL1 (9 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_PERIPH_CLKSEL_IDIVA (12 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_PERIPH_CLKSEL_IDIVB (13 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_PERIPH_CLKSEL_IDIVC (14 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_PERIPH_CLKSEL_IDIVD (15 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_PERIPH_CLKSEL_IDIVE (16 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_PERIPH_CLKSEL_32KHZOSC (0 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_PERIPH_CLKSEL_IRC (1 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_PERIPH_CLKSEL_ENET_RXCLK (2 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_PERIPH_CLKSEL_ENET_TXCLK (3 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_PERIPH_CLKSEL_GPCLKIN (4 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_PERIPH_CLKSEL_XTAL (6 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_PERIPH_CLKSEL_PLL0AUDIO (8 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_PERIPH_CLKSEL_PLL1 (9 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_PERIPH_CLKSEL_IDIVA (12 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_PERIPH_CLKSEL_IDIVB (13 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_PERIPH_CLKSEL_IDIVC (14 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_PERIPH_CLKSEL_IDIVD (15 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_PERIPH_CLKSEL_IDIVE (16 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 3 control register (BASE_USB1_CLK) */ @@ -444,20 +444,20 @@ /* Bits 12-23: Reserved */ #define BASE_USB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_USB1_CLK_CLKSEL_MASK (31 << BASE_USB1_CLK_CLKSEL_SHIFT) -# define BASE_USB1_CLKSEL_32KHZOSC (0 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_USB1_CLKSEL_IRC (1 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_USB1_CLKSEL_ENET_RXCLK (2 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_USB1_CLKSEL_ENET_TXCLK (3 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_USB1_CLKSEL_GPCLKIN (4 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_USB1_CLKSEL_XTAL (6 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_USB1_CLKSEL_PLL0USB (7 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define BASE_USB1_CLKSEL_PLL0AUDIO (8 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_USB1_CLKSEL_PLL1 (9 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_USB1_CLKSEL_IDIVA (12 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_USB1_CLKSEL_IDIVB (13 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_USB1_CLKSEL_IDIVC (14 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_USB1_CLKSEL_IDIVD (15 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_USB1_CLKSEL_IDIVE (16 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_USB1_CLKSEL_32KHZOSC (0 << BASE_USB1_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USB1_CLKSEL_IRC (1 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USB1_CLKSEL_ENET_RXCLK (2 << BASE_USB1_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USB1_CLKSEL_ENET_TXCLK (3 << BASE_USB1_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USB1_CLKSEL_GPCLKIN (4 << BASE_USB1_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USB1_CLKSEL_XTAL (6 << BASE_USB1_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USB1_CLKSEL_PLL0USB (7 << BASE_USB1_CLK_CLKSEL_SHIFT) /* PLL0USB */ +# define BASE_USB1_CLKSEL_PLL0AUDIO (8 << BASE_USB1_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USB1_CLKSEL_PLL1 (9 << BASE_USB1_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USB1_CLKSEL_IDIVA (12 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USB1_CLKSEL_IDIVB (13 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USB1_CLKSEL_IDIVC (14 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USB1_CLKSEL_IDIVD (15 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USB1_CLKSEL_IDIVE (16 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 4 control register (BASE_M4_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -468,19 +468,19 @@ /* Bits 12-23: Reserved */ #define BASE_M4_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_M4_CLK_CLKSEL_MASK (31 << BASE_M4_CLK_CLKSEL_SHIFT) -# define BASE_M4_CLKSEL_32KHZOSC (0 << BASE_M4_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_M4_CLKSEL_IRC (1 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_M4_CLKSEL_ENET_RXCLK (2 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_M4_CLKSEL_ENET_TXCLK (3 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_M4_CLKSEL_GPCLKIN (4 << BASE_M4_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_M4_CLKSEL_XTAL (6 << BASE_M4_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_M4_CLKSEL_PLL0AUDIO (8 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_M4_CLKSEL_PLL1 (9 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_M4_CLKSEL_IDIVA (12 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_M4_CLKSEL_IDIVB (13 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_M4_CLKSEL_IDIVC (14 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_M4_CLKSEL_IDIVD (15 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_M4_CLKSEL_IDIVE (16 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_M4_CLKSEL_32KHZOSC (0 << BASE_M4_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_M4_CLKSEL_IRC (1 << BASE_M4_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_M4_CLKSEL_ENET_RXCLK (2 << BASE_M4_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_M4_CLKSEL_ENET_TXCLK (3 << BASE_M4_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_M4_CLKSEL_GPCLKIN (4 << BASE_M4_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_M4_CLKSEL_XTAL (6 << BASE_M4_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_M4_CLKSEL_PLL0AUDIO (8 << BASE_M4_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_M4_CLKSEL_PLL1 (9 << BASE_M4_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_M4_CLKSEL_IDIVA (12 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_M4_CLKSEL_IDIVB (13 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_M4_CLKSEL_IDIVC (14 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_M4_CLKSEL_IDIVD (15 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_M4_CLKSEL_IDIVE (16 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 5 control register (BASE_SPIFI_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -491,19 +491,19 @@ /* Bits 12-23: Reserved */ #define BASE_SPIFI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_SPIFI_CLK_CLKSEL_MASK (31 << BASE_SPIFI_CLK_CLKSEL_SHIFT) -# define BASE_SPIFI_CLKSEL_32KHZOSC (0 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SPIFI_CLKSEL_IRC (1 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SPIFI_CLKSEL_ENET_RXCLK (2 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SPIFI_CLKSEL_ENET_TXCLK (3 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SPIFI_CLKSEL_GPCLKIN (4 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SPIFI_CLKSEL_XTAL (6 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SPIFI_CLKSEL_PLL0AUDIO (8 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SPIFI_CLKSEL_PLL1 (9 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SPIFI_CLKSEL_IDIVA (12 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SPIFI_CLKSEL_IDIVB (13 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SPIFI_CLKSEL_IDIVC (14 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SPIFI_CLKSEL_IDIVD (15 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SPIFI_CLKSEL_IDIVE (16 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_SPIFI_CLKSEL_32KHZOSC (0 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SPIFI_CLKSEL_IRC (1 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SPIFI_CLKSEL_ENET_RXCLK (2 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SPIFI_CLKSEL_ENET_TXCLK (3 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SPIFI_CLKSEL_GPCLKIN (4 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SPIFI_CLKSEL_XTAL (6 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SPIFI_CLKSEL_PLL0AUDIO (8 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SPIFI_CLKSEL_PLL1 (9 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SPIFI_CLKSEL_IDIVA (12 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SPIFI_CLKSEL_IDIVB (13 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SPIFI_CLKSEL_IDIVC (14 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SPIFI_CLKSEL_IDIVD (15 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SPIFI_CLKSEL_IDIVE (16 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 6 control register (BASE_SPI_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -514,19 +514,19 @@ /* Bits 12-23: Reserved */ #define BASE_SPI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_SPI_CLK_CLKSEL_MASK (31 << BASE_SPI_CLK_CLKSEL_SHIFT) -# define BASE_SPI_CLKSEL_32KHZOSC (0 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SPI_CLKSEL_IRC (1 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SPI_CLKSEL_ENET_RXCLK (2 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SPI_CLKSEL_ENET_TXCLK (3 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SPI_CLKSEL_GPCLKIN (4 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SPI_CLKSEL_XTAL (6 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SPI_CLKSEL_PLL0AUDIO (8 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SPI_CLKSEL_PLL1 (9 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SPI_CLKSEL_IDIVA (12 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SPI_CLKSEL_IDIVB (13 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SPI_CLKSEL_IDIVC (14 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SPI_CLKSEL_IDIVD (15 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SPI_CLKSEL_IDIVE (16 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_SPI_CLKSEL_32KHZOSC (0 << BASE_SPI_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SPI_CLKSEL_IRC (1 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SPI_CLKSEL_ENET_RXCLK (2 << BASE_SPI_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SPI_CLKSEL_ENET_TXCLK (3 << BASE_SPI_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SPI_CLKSEL_GPCLKIN (4 << BASE_SPI_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SPI_CLKSEL_XTAL (6 << BASE_SPI_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SPI_CLKSEL_PLL0AUDIO (8 << BASE_SPI_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SPI_CLKSEL_PLL1 (9 << BASE_SPI_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SPI_CLKSEL_IDIVA (12 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SPI_CLKSEL_IDIVB (13 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SPI_CLKSEL_IDIVC (14 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SPI_CLKSEL_IDIVD (15 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SPI_CLKSEL_IDIVE (16 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 7 control register (BASE_PHY_RX_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -537,19 +537,19 @@ /* Bits 12-23: Reserved */ #define BASE_PHYRX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_PHYRX_CLK_CLKSEL_MASK (31 << BASE_PHYRX_CLK_CLKSEL_SHIFT) -# define BASE_PHYRX_CLKSEL_32KHZOSC (0 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_PHYRX_CLKSEL_IRC (1 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_PHYRX_CLKSEL_ENET_RXCLK (2 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_PHYRX_CLKSEL_ENET_TXCLK (3 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_PHYRX_CLKSEL_GPCLKIN (4 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_PHYRX_CLKSEL_XTAL (6 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_PHYRX_CLKSEL_PLL0AUDIO (8 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_PHYRX_CLKSEL_PLL1 (9 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_PHYRX_CLKSEL_IDIVA (12 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_PHYRX_CLKSEL_IDIVB (13 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_PHYRX_CLKSEL_IDIVC (14 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_PHYRX_CLKSEL_IDIVD (15 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_PHYRX_CLKSEL_IDIVE (16 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_PHYRX_CLKSEL_32KHZOSC (0 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_PHYRX_CLKSEL_IRC (1 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_PHYRX_CLKSEL_ENET_RXCLK (2 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_PHYRX_CLKSEL_ENET_TXCLK (3 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_PHYRX_CLKSEL_GPCLKIN (4 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_PHYRX_CLKSEL_XTAL (6 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_PHYRX_CLKSEL_PLL0AUDIO (8 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_PHYRX_CLKSEL_PLL1 (9 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_PHYRX_CLKSEL_IDIVA (12 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_PHYRX_CLKSEL_IDIVB (13 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_PHYRX_CLKSEL_IDIVC (14 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_PHYRX_CLKSEL_IDIVD (15 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_PHYRX_CLKSEL_IDIVE (16 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 8 control register (BASE_PHY_TX_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -560,19 +560,19 @@ /* Bits 12-23: Reserved */ #define BASE_PHYTX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_PHYTX_CLK_CLKSEL_MASK (31 << BASE_PHYTX_CLK_CLKSEL_SHIFT) -# define BASE_PHYTX_CLKSEL_32KHZOSC (0 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_PHYTX_CLKSEL_IRC (1 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_PHYTX_CLKSEL_ENET_RXCLK (2 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_PHYTX_CLKSEL_ENET_TXCLK (3 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_PHYTX_CLKSEL_GPCLKIN (4 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_PHYTX_CLKSEL_XTAL (6 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_PHYTX_CLKSEL_PLL0AUDIO (8 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_PHYTX_CLKSEL_PLL1 (9 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_PHYTX_CLKSEL_IDIVA (12 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_PHYTX_CLKSEL_IDIVB (13 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_PHYTX_CLKSEL_IDIVC (14 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_PHYTX_CLKSEL_IDIVD (15 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_PHYTX_CLKSEL_IDIVE (16 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_PHYTX_CLKSEL_32KHZOSC (0 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_PHYTX_CLKSEL_IRC (1 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_PHYTX_CLKSEL_ENET_RXCLK (2 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_PHYTX_CLKSEL_ENET_TXCLK (3 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_PHYTX_CLKSEL_GPCLKIN (4 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_PHYTX_CLKSEL_XTAL (6 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_PHYTX_CLKSEL_PLL0AUDIO (8 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_PHYTX_CLKSEL_PLL1 (9 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_PHYTX_CLKSEL_IDIVA (12 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_PHYTX_CLKSEL_IDIVB (13 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_PHYTX_CLKSEL_IDIVC (14 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_PHYTX_CLKSEL_IDIVD (15 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_PHYTX_CLKSEL_IDIVE (16 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 9 control register (BASE_APB1_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -583,19 +583,19 @@ /* Bits 12-23: Reserved */ #define BASE_APB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_APB1_CLK_CLKSEL_MASK (31 << BASE_APB1_CLK_CLKSEL_SHIFT) -# define BASE_APB1_CLKSEL_32KHZOSC (0 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_APB1_CLKSEL_IRC (1 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_APB1_CLKSEL_ENET_RXCLK (2 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_APB1_CLKSEL_ENET_TXCLK (3 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_APB1_CLKSEL_GPCLKIN (4 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_APB1_CLKSEL_XTAL (6 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_APB1_CLKSEL_PLL0AUDIO (8 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_APB1_CLKSEL_PLL1 (9 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_APB1_CLKSEL_IDIVA (12 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_APB1_CLKSEL_IDIVB (13 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_APB1_CLKSEL_IDIVC (14 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_APB1_CLKSEL_IDIVD (15 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_APB1_CLKSEL_IDIVE (16 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_APB1_CLKSEL_32KHZOSC (0 << BASE_APB1_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_APB1_CLKSEL_IRC (1 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_APB1_CLKSEL_ENET_RXCLK (2 << BASE_APB1_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_APB1_CLKSEL_ENET_TXCLK (3 << BASE_APB1_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_APB1_CLKSEL_GPCLKIN (4 << BASE_APB1_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_APB1_CLKSEL_XTAL (6 << BASE_APB1_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_APB1_CLKSEL_PLL0AUDIO (8 << BASE_APB1_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_APB1_CLKSEL_PLL1 (9 << BASE_APB1_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_APB1_CLKSEL_IDIVA (12 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_APB1_CLKSEL_IDIVB (13 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_APB1_CLKSEL_IDIVC (14 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_APB1_CLKSEL_IDIVD (15 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_APB1_CLKSEL_IDIVE (16 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 11 control register (BASE_LCD_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -606,19 +606,19 @@ /* Bits 12-23: Reserved */ #define BASE_LCD_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_LCD_CLK_CLKSEL_MASK (31 << BASE_LCD_CLK_CLKSEL_SHIFT) -# define BASE_LCD_CLKSEL_32KHZOSC (0 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_LCD_CLKSEL_IRC (1 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_LCD_CLKSEL_ENET_RXCLK (2 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_LCD_CLKSEL_ENET_TXCLK (3 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_LCD_CLKSEL_GPCLKIN (4 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_LCD_CLKSEL_XTAL (6 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_LCD_CLKSEL_PLL0AUDIO (8 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_LCD_CLKSEL_PLL1 (9 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_LCD_CLKSEL_IDIVA (12 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_LCD_CLKSEL_IDIVB (13 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_LCD_CLKSEL_IDIVC (14 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_LCD_CLKSEL_IDIVD (15 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_LCD_CLKSEL_IDIVE (16 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_LCD_CLKSEL_32KHZOSC (0 << BASE_LCD_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_LCD_CLKSEL_IRC (1 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_LCD_CLKSEL_ENET_RXCLK (2 << BASE_LCD_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_LCD_CLKSEL_ENET_TXCLK (3 << BASE_LCD_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_LCD_CLKSEL_GPCLKIN (4 << BASE_LCD_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_LCD_CLKSEL_XTAL (6 << BASE_LCD_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_LCD_CLKSEL_PLL0AUDIO (8 << BASE_LCD_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_LCD_CLKSEL_PLL1 (9 << BASE_LCD_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_LCD_CLKSEL_IDIVA (12 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_LCD_CLKSEL_IDIVB (13 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_LCD_CLKSEL_IDIVC (14 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_LCD_CLKSEL_IDIVD (15 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_LCD_CLKSEL_IDIVE (16 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 12 control register (BASE_VADC_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -629,19 +629,19 @@ /* Bits 12-23: Reserved */ #define BASE_VADC_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_VADC_CLK_CLKSEL_MASK (31 << BASE_VADC_CLK_CLKSEL_SHIFT) -# define BASE_VADC_CLKSEL_32KHZOSC (0 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_VADC_CLKSEL_IRC (1 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_VADC_CLKSEL_ENET_RXCLK (2 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_VADC_CLKSEL_ENET_TXCLK (3 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_VADC_CLKSEL_GPCLKIN (4 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_VADC_CLKSEL_XTAL (6 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_VADC_CLKSEL_PLL0AUDIO (8 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_VADC_CLKSEL_PLL1 (9 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_VADC_CLKSEL_IDIVA (12 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_VADC_CLKSEL_IDIVB (13 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_VADC_CLKSEL_IDIVC (14 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_VADC_CLKSEL_IDIVD (15 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_VADC_CLKSEL_IDIVE (16 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_VADC_CLKSEL_32KHZOSC (0 << BASE_VADC_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_VADC_CLKSEL_IRC (1 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_VADC_CLKSEL_ENET_RXCLK (2 << BASE_VADC_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_VADC_CLKSEL_ENET_TXCLK (3 << BASE_VADC_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_VADC_CLKSEL_GPCLKIN (4 << BASE_VADC_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_VADC_CLKSEL_XTAL (6 << BASE_VADC_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_VADC_CLKSEL_PLL0AUDIO (8 << BASE_VADC_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_VADC_CLKSEL_PLL1 (9 << BASE_VADC_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_VADC_CLKSEL_IDIVA (12 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_VADC_CLKSEL_IDIVB (13 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_VADC_CLKSEL_IDIVC (14 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_VADC_CLKSEL_IDIVD (15 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_VADC_CLKSEL_IDIVE (16 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 14 control register (BASE_SSP0_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -652,19 +652,19 @@ /* Bits 12-23: Reserved */ #define BASE_SSP0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_SSP0_CLK_CLKSEL_MASK (31 << BASE_SSP0_CLK_CLKSEL_SHIFT) -# define BASE_SSP0_CLKSEL_32KHZOSC (0 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SSP0_CLKSEL_IRC (1 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SSP0_CLKSEL_ENET_RXCLK (2 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SSP0_CLKSEL_ENET_TXCLK (3 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SSP0_CLKSEL_GPCLKIN (4 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SSP0_CLKSEL_XTAL (6 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SSP0_CLKSEL_PLL0AUDIO (8 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SSP0_CLKSEL_PLL1 (9 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SSP0_CLKSEL_IDIVA (12 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SSP0_CLKSEL_IDIVB (13 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SSP0_CLKSEL_IDIVC (14 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SSP0_CLKSEL_IDIVD (15 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SSP0_CLKSEL_IDIVE (16 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_SSP0_CLKSEL_32KHZOSC (0 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SSP0_CLKSEL_IRC (1 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SSP0_CLKSEL_ENET_RXCLK (2 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SSP0_CLKSEL_ENET_TXCLK (3 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SSP0_CLKSEL_GPCLKIN (4 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SSP0_CLKSEL_XTAL (6 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SSP0_CLKSEL_PLL0AUDIO (8 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SSP0_CLKSEL_PLL1 (9 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SSP0_CLKSEL_IDIVA (12 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SSP0_CLKSEL_IDIVB (13 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SSP0_CLKSEL_IDIVC (14 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SSP0_CLKSEL_IDIVD (15 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SSP0_CLKSEL_IDIVE (16 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 15 control register (BASE_SSP1_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -675,19 +675,19 @@ /* Bits 12-23: Reserved */ #define BASE_SSP1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_SSP1_CLK_CLKSEL_MASK (31 << BASE_SSP1_CLK_CLKSEL_SHIFT) -# define BASE_SSP1_CLKSEL_32KHZOSC (0 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SSP1_CLKSEL_IRC (1 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SSP1_CLKSEL_ENET_RXCLK (2 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SSP1_CLKSEL_ENET_TXCLK (3 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SSP1_CLKSEL_GPCLKIN (4 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SSP1_CLKSEL_XTAL (6 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SSP1_CLKSEL_PLL0AUDIO (8 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SSP1_CLKSEL_PLL1 (9 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SSP1_CLKSEL_IDIVA (12 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SSP1_CLKSEL_IDIVB (13 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SSP1_CLKSEL_IDIVC (14 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SSP1_CLKSEL_IDIVD (15 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SSP1_CLKSEL_IDIVE (16 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_SSP1_CLKSEL_32KHZOSC (0 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SSP1_CLKSEL_IRC (1 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SSP1_CLKSEL_ENET_RXCLK (2 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SSP1_CLKSEL_ENET_TXCLK (3 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SSP1_CLKSEL_GPCLKIN (4 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SSP1_CLKSEL_XTAL (6 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SSP1_CLKSEL_PLL0AUDIO (8 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SSP1_CLKSEL_PLL1 (9 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SSP1_CLKSEL_IDIVA (12 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SSP1_CLKSEL_IDIVB (13 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SSP1_CLKSEL_IDIVC (14 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SSP1_CLKSEL_IDIVD (15 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SSP1_CLKSEL_IDIVE (16 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 16 control register (BASE_USART0_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -698,19 +698,19 @@ /* Bits 12-23: Reserved */ #define BASE_USART0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_USART0_CLK_CLKSEL_MASK (31 << BASE_USART0_CLK_CLKSEL_SHIFT) -# define BASE_USART0_CLKSEL_32KHZOSC (0 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_USART0_CLKSEL_IRC (1 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_USART0_CLKSEL_ENET_RXCLK (2 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_USART0_CLKSEL_ENET_TXCLK (3 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_USART0_CLKSEL_GPCLKIN (4 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_USART0_CLKSEL_XTAL (6 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_USART0_CLKSEL_PLL0AUDIO (8 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_USART0_CLKSEL_PLL1 (9 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_USART0_CLKSEL_IDIVA (12 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_USART0_CLKSEL_IDIVB (13 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_USART0_CLKSEL_IDIVC (14 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_USART0_CLKSEL_IDIVD (15 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_USART0_CLKSEL_IDIVE (16 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_USART0_CLKSEL_32KHZOSC (0 << BASE_USART0_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USART0_CLKSEL_IRC (1 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USART0_CLKSEL_ENET_RXCLK (2 << BASE_USART0_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USART0_CLKSEL_ENET_TXCLK (3 << BASE_USART0_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USART0_CLKSEL_GPCLKIN (4 << BASE_USART0_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USART0_CLKSEL_XTAL (6 << BASE_USART0_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USART0_CLKSEL_PLL0AUDIO (8 << BASE_USART0_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USART0_CLKSEL_PLL1 (9 << BASE_USART0_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USART0_CLKSEL_IDIVA (12 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USART0_CLKSEL_IDIVB (13 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USART0_CLKSEL_IDIVC (14 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USART0_CLKSEL_IDIVD (15 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USART0_CLKSEL_IDIVE (16 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 18 control register (BASE_USART2_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -721,19 +721,19 @@ /* Bits 12-23: Reserved */ #define BASE_USART2_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_USART2_CLK_CLKSEL_MASK (31 << BASE_USART2_CLK_CLKSEL_SHIFT) -# define BASE_USART2_CLKSEL_32KHZOSC (0 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_USART2_CLKSEL_IRC (1 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_USART2_CLKSEL_ENET_RXCLK (2 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_USART2_CLKSEL_ENET_TXCLK (3 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_USART2_CLKSEL_GPCLKIN (4 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_USART2_CLKSEL_XTAL (6 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_USART2_CLKSEL_PLL0AUDIO (8 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_USART2_CLKSEL_PLL1 (9 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_USART2_CLKSEL_IDIVA (12 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_USART2_CLKSEL_IDIVB (13 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_USART2_CLKSEL_IDIVC (14 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_USART2_CLKSEL_IDIVD (15 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_USART2_CLKSEL_IDIVE (16 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_USART2_CLKSEL_32KHZOSC (0 << BASE_USART2_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USART2_CLKSEL_IRC (1 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USART2_CLKSEL_ENET_RXCLK (2 << BASE_USART2_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USART2_CLKSEL_ENET_TXCLK (3 << BASE_USART2_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USART2_CLKSEL_GPCLKIN (4 << BASE_USART2_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USART2_CLKSEL_XTAL (6 << BASE_USART2_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USART2_CLKSEL_PLL0AUDIO (8 << BASE_USART2_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USART2_CLKSEL_PLL1 (9 << BASE_USART2_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USART2_CLKSEL_IDIVA (12 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USART2_CLKSEL_IDIVB (13 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USART2_CLKSEL_IDIVC (14 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USART2_CLKSEL_IDIVD (15 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USART2_CLKSEL_IDIVE (16 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 19 control register (BASE_USART3_CLK) */ /* NOTE: Clocks 4-19 are identical */ @@ -744,19 +744,19 @@ /* Bits 12-23: Reserved */ #define BASE_USART3_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_USART3_CLK_CLKSEL_MASK (31 << BASE_USART3_CLK_CLKSEL_SHIFT) -# define BASE_USART3_CLKSEL_32KHZOSC (0 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_USART3_CLKSEL_IRC (1 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_USART3_CLKSEL_ENET_RXCLK (2 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_USART3_CLKSEL_ENET_TXCLK (3 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_USART3_CLKSEL_GPCLKIN (4 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_USART3_CLKSEL_XTAL (6 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_USART3_CLKSEL_PLL0AUDIO (8 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_USART3_CLKSEL_PLL1 (9 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_USART3_CLKSEL_IDIVA (12 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_USART3_CLKSEL_IDIVB (13 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_USART3_CLKSEL_IDIVC (14 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_USART3_CLKSEL_IDIVD (15 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_USART3_CLKSEL_IDIVE (16 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_USART3_CLKSEL_32KHZOSC (0 << BASE_USART3_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USART3_CLKSEL_IRC (1 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USART3_CLKSEL_ENET_RXCLK (2 << BASE_USART3_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USART3_CLKSEL_ENET_TXCLK (3 << BASE_USART3_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USART3_CLKSEL_GPCLKIN (4 << BASE_USART3_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USART3_CLKSEL_XTAL (6 << BASE_USART3_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USART3_CLKSEL_PLL0AUDIO (8 << BASE_USART3_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USART3_CLKSEL_PLL1 (9 << BASE_USART3_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USART3_CLKSEL_IDIVA (12 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USART3_CLKSEL_IDIVB (13 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USART3_CLKSEL_IDIVC (14 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USART3_CLKSEL_IDIVD (15 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USART3_CLKSEL_IDIVE (16 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 20 control register (BASE_OUT_CLK) */ @@ -766,20 +766,20 @@ /* Bits 12-23: Reserved */ #define BASE_OUT_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_OUT_CLK_CLKSEL_MASK (31 << BASE_OUT_CLK_CLKSEL_SHIFT) -# define BASE_OUT_CLKSEL_32KHZOSC (0 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_OUT_CLKSEL_IRC (1 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_OUT_CLKSEL_ENET_RXCLK (2 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_OUT_CLKSEL_ENET_TXCLK (3 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_OUT_CLKSEL_GPCLKIN (4 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_OUT_CLKSEL_XTAL (6 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_OUT_CLKSEL_PLL0USB (7 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define BASE_OUT_CLKSEL_PLL0AUDIO (8 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_OUT_CLKSEL_PLL1 (9 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_OUT_CLKSEL_IDIVA (12 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_OUT_CLKSEL_IDIVB (13 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_OUT_CLKSEL_IDIVC (14 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_OUT_CLKSEL_IDIVD (15 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_OUT_CLKSEL_IDIVE (16 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_OUT_CLKSEL_32KHZOSC (0 << BASE_OUT_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_OUT_CLKSEL_IRC (1 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_OUT_CLKSEL_ENET_RXCLK (2 << BASE_OUT_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_OUT_CLKSEL_ENET_TXCLK (3 << BASE_OUT_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_OUT_CLKSEL_GPCLKIN (4 << BASE_OUT_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_OUT_CLKSEL_XTAL (6 << BASE_OUT_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_OUT_CLKSEL_PLL0USB (7 << BASE_OUT_CLK_CLKSEL_SHIFT) /* PLL0USB */ +# define BASE_OUT_CLKSEL_PLL0AUDIO (8 << BASE_OUT_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_OUT_CLKSEL_PLL1 (9 << BASE_OUT_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_OUT_CLKSEL_IDIVA (12 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_OUT_CLKSEL_IDIVB (13 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_OUT_CLKSEL_IDIVC (14 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_OUT_CLKSEL_IDIVD (15 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_OUT_CLKSEL_IDIVE (16 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 25 control register (BASE_APLL_CLK) */ @@ -789,19 +789,19 @@ /* Bits 12-23: Reserved */ #define BASE_APLL_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_APLL_CLK_CLKSEL_MASK (31 << BASE_APLL_CLK_CLKSEL_SHIFT) -# define BASE_APLL_CLKSEL_32KHZOSC (0 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_APLL_CLKSEL_IRC (1 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_APLL_CLKSEL_ENET_RXCLK (2 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_APLL_CLKSEL_ENET_TXCLK (3 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_APLL_CLKSEL_GPCLKIN (4 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_APLL_CLKSEL_XTAL (6 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_APLL_CLKSEL_PLL0AUDIO (8 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_APLL_CLKSEL_PLL1 (9 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_APLL_CLKSEL_IDIVA (12 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_APLL_CLKSEL_IDIVB (13 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_APLL_CLKSEL_IDIVC (14 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_APLL_CLKSEL_IDIVD (15 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_APLL_CLKSEL_IDIVE (16 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_APLL_CLKSEL_32KHZOSC (0 << BASE_APLL_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_APLL_CLKSEL_IRC (1 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_APLL_CLKSEL_ENET_RXCLK (2 << BASE_APLL_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_APLL_CLKSEL_ENET_TXCLK (3 << BASE_APLL_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_APLL_CLKSEL_GPCLKIN (4 << BASE_APLL_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_APLL_CLKSEL_XTAL (6 << BASE_APLL_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_APLL_CLKSEL_PLL0AUDIO (8 << BASE_APLL_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_APLL_CLKSEL_PLL1 (9 << BASE_APLL_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_APLL_CLKSEL_IDIVA (12 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_APLL_CLKSEL_IDIVB (13 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_APLL_CLKSEL_IDIVC (14 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_APLL_CLKSEL_IDIVD (15 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_APLL_CLKSEL_IDIVE (16 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 26/27 control register (BASE_CGU_OUT0/1_CLK) */ /* NOTE: Clocks 26-27 are identical */ @@ -812,20 +812,20 @@ /* Bits 12-23: Reserved */ #define BASE_CGU_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_CGU_CLK_CLKSEL_MASK (31 << BASE_CGU_CLK_CLKSEL_SHIFT) -# define BASE_CGU_CLKSEL_32KHZOSC (0 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_CGU_CLKSEL_IRC (1 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_CGU_CLKSEL_ENET_RXCLK (2 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_CGU_CLKSEL_ENET_TXCLK (3 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_CGU_CLKSEL_GPCLKIN (4 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_CGU_CLKSEL_XTAL (6 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_CGU_CLKSEL_PLL0USB (7 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define BASE_CGU_CLKSEL_PLL0AUDIO (8 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_CGU_CLKSEL_PLL1 (9 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_CGU_CLKSEL_IDIVA (12 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_CGU_CLKSEL_IDIVB (13 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_CGU_CLKSEL_IDIVC (14 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_CGU_CLKSEL_IDIVD (15 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_CGU_CLKSEL_IDIVE (16 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVE */ +# define BASE_CGU_CLKSEL_32KHZOSC (0 << BASE_CGU_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_CGU_CLKSEL_IRC (1 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_CGU_CLKSEL_ENET_RXCLK (2 << BASE_CGU_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_CGU_CLKSEL_ENET_TXCLK (3 << BASE_CGU_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_CGU_CLKSEL_GPCLKIN (4 << BASE_CGU_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_CGU_CLKSEL_XTAL (6 << BASE_CGU_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_CGU_CLKSEL_PLL0USB (7 << BASE_CGU_CLK_CLKSEL_SHIFT) /* PLL0USB */ +# define BASE_CGU_CLKSEL_PLL0AUDIO (8 << BASE_CGU_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_CGU_CLKSEL_PLL1 (9 << BASE_CGU_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_CGU_CLKSEL_IDIVA (12 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_CGU_CLKSEL_IDIVB (13 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_CGU_CLKSEL_IDIVC (14 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_CGU_CLKSEL_IDIVD (15 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_CGU_CLKSEL_IDIVE (16 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /**************************************************************************************************** diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h index 3efd07c54..61a62e694 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h @@ -242,7 +242,7 @@ # define CREG6_ETHMODE_MII (0 << CREG6_ETHMODE_SHIFT) # define CREG6_ETHMODE_RMII (4 << CREG6_ETHMODE_SHIFT) /* Bit 3: Reserved */ -#define CREG6_CTOUTCTRL (1 << 4) /* Bit 4: Selects the functionality of the SCT outputs +#define CREG6_CTOUTCTRL (1 << 4) /* Bit 4: Selects the functionality of the SCT outputs */ /* Bits 5-11: Reserved */ #define CREG6_I2S0_TXSCK (1 << 12) /* Bit 12: I2S0_TX_SCK input select */ #define CREG6_I2S0_RXSCK (1 << 13) /* Bit 13: I2S0_RX_SCK input select */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c new file mode 100644 index 000000000..cb15f0bc4 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c @@ -0,0 +1,275 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_allocateheap.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <nuttx/mm.h> +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc43_emacram.h" +#include "lpc43_usbram.h" + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ +/* Get customizations for each supported chip. + * + * SRAM Resources + * --------------------- -------- ------- ------- ------- ------- ------- + * Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 + * --------------------- -------- ------- ------- ------- ------- ------- + * BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb + * BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb + * --------------------- -------- ------- ------- ------- ------- ------- + * SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb + * --------------------- -------- ------- ------- ------- ------- ------- + * AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 + * --------------------- -------- ------- ------- ------- ------- ------- + * BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb + * BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 + * BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb + * --------------------- -------- ------- ------- ------- ------- ------- + * SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb + * --------------------- -------- ------- ------- ------- ------- ------- + * TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb + * --------------------- -------- ------- ------- ------- ------- ------- + * + * --------------------- -------- ------- ------- ------- ------- ------- + * FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 + * --------------------- -------- ------- ------- ------- ------- ------- + * BANK A (0x1a00 0000) 256Kb 512Kb + * BANK B (0x1b00 8000) 256Kb 512Kb + * --------------------- -------- ------- ------- ------- ------- ------- + * TOTAL None None None None 512Kb 1024Kb + * --------------------- -------- ------- ------- ------- ------- ------- + * + * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM + * banks but are treated as two banks of 48 an 16Kb by the NuttX memory + * manager. This gives some symmetry to all of the members of the family. + */ + +/* Configuration ************************************************************/ + +/* Two configurations are supported: + * + * Configuration A: + * Program memory = FLASH + * Data memory = Local RAM Bank 0 + * Additional regions = Local RAM Bank 1 + AHB SRAM (exluding DMA buffers) + * + * Configuration B: + * Program memory = Local RAM Bank 0 + * Data memory = Local RAM Bank 1 + * Additional regions = AHB SRAM (exluding DMA buffers) + * + * This file supports only memory configuration A. + * + * These should be defined in the memory map header file: + * + * LPC43_LOCSRAM_BANK0_BASE 0x10000000 + * LPC43_LOCSRAM_BANK1_BASE 0x10080000 + * LPC43_AHBSRAM_BANK0_BASE 0x20000000 + * LPC43_AHBSRAM_BANK1_BASE 0x20008000 + * LPC43_AHBSRAM_BANK2_BASE 0x2000c000 + * + * These should be defined for the specific chip in the chip.h header file. + * The value will be defined to be zero in size of the bank does not exist. + * If two banks are contiguous, the combined size will be added to the + * first bank and the size of the second bank will be defined to be zero. + * + * LPC43_LOCSRAM_BANK0_SIZE + * LPC43_LOCSRAM_BANK1_SIZE + * LPC43_AHBSRAM_BANK0_SIZE + * LPC43_AHBSRAM_BANK1_SIZE + * LPC43_AHBSRAM_BANK2_SIZE + * + * The config.h file will define only: + * + * CONFIG_DRAM_START = The start of the data RAM region which may be + * either local SRAM bank 0 (Configuration A) or 1 (Configuration B). + * CONFIG_DRAM_START = The size of the data RAM region. + * CONFIG_DRAM_END = The sum of the above + */ + +/* Check for Configuration A. */ + +#ifndef CONFIG_BOOT_SRAM + +/* Configuration A */ +/* CONFIG_DRAM_START should be set to the base of AHB SRAM, local 0. */ + +# if CONFIG_DRAM_START != LPC43_LOCSRAM_BANK0_BASE +# error "CONFIG_DRAM_START must be set to the base address of AHB SRAM Bank 0" +# endif + +/* The configured RAM size should be equal to the size of local SRAM Bank 0 */ + +# if CONFIG_DRAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE +# error "CONFIG_DRAM_SIZE must be set to size of AHB SRAM Bank 0" +# endif + +/* Now we can assign all of the memory regions for configuration A */ + +# define MM_REGION1_BASE LPC43_LOCSRAM_BANK0_BASE +# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK0_SIZE +# define MM_REGION2_BASE LPC43_LOCSRAM_BANK1_BASE +# define MM_REGION2_SIZE LPC43_LOCSRAM_BANK1_SIZE +# define MM_REGION3_BASE LPC43_AHBSRAM_BANK0_BASE +# define MM_REGION3_SIZE LPC43_AHBSRAM_BANK0_SIZE +#else + +/* Configuration B */ +/* CONFIG_DRAM_START should be set to the base of local SRAM, bank 1. */ + +# if CONFIG_DRAM_START != LPC43_LOCSRAM_BANK1_BASE +# error "CONFIG_DRAM_START must be set to the base address of AHB SRAM Bank 0" +# endif + +/* The configured RAM size should be equal to the size of local SRAM Bank 1 */ + +# if CONFIG_DRAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE +# error "CONFIG_DRAM_SIZE must be set to size of AHB SRAM Bank 0" +# endif + +/* Now we can assign all of the memory regions for configuration B */ + +# define MM_REGION1_BASE LPC43_LOCSRAM_BANK1_BASE +# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK1_SIZE +# define MM_REGION2_BASE LPC43_AHBSRAM_BANK0_BASE +# define MM_REGION2_SIZE LPC43_AHBSRAM_BANK0_SIZE +# undef MM_REGION3_BASE +# undef MM_REGION3_SIZE +#endif + +#define MM_DMAREGION_BASE LPC43_AHBSRAM_BANK2_BASE +#define MM_DMAREGION_SIZE LPC43_AHBSRAM_BANK2_SIZE + +/* Figure out how much heap we have in the DMA region that is not being + * used by USB and/or Ethernet (if any). + */ + +#warning "Missing Logic" + +#define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */ +#define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * The heap may be statically allocated by + * defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE. If these + * are not defined, then this function will be called to + * dynamically set aside the heap region. + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + /* Start with the first SRAM region */ + + up_ledon(LED_HEAPALLOCATE); + *heap_start = (FAR void*)g_heapbase; + *heap_size = CONFIG_DRAM_END - g_heapbase; +} + +/************************************************************************ + * Name: up_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void up_addregion(void) +{ +#if CONFIG_MM_REGIONS > 1 + /* Add the next SRAM region (which should exist) */ + + mm_addregion((FAR void*)MM_REGION2_BASE, MM_REGION2_SIZE); + +#ifdef MM_REGION3_BASE + /* Add the third SRAM region (which will not exist in configuration B) */ + +#if CONFIG_MM_REGIONS > 2 + /* Add the third SRAM region (which may not exist) */ + + mm_addregion((FAR void*)MM_REGION3_BASE, MM_REGION3_SIZE); + +#if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) + /* Add the DMA region (which may not be available) */ + + mm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); + +#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ +#endif /* CONFIG_MM_REGIONS > 2 */ +#else /* MM_REGION3_BASE */ + +#if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE) + /* Add the DMA region (which may not be available) */ + + mm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE); + +#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */ +#endif /* MM_REGION3_BASE */ +#endif /* CONFIG_MM_REGIONS > 1 */ +} +#endif diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c new file mode 100644 index 000000000..05a214765 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * arch/arm/src/lpc43/lpc43_cgu.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <nuttx/arch.h> +#include <errno.h> + +#include "up_arch.h" +#include "lpc43_cgu.h" +#include <arch/board/board.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Maximum/Threashold Frequencies *******************************************/ + +#define LOW_XTAL_FREQUENCY 15000000 +#define MAX_XTAL_FREQUENCY 25000000 + +#define MAX_FCLKOUT_FREQUENCY 156000000 +#define MAX_FCCO_FRQUENCY 320000000 + +/* Configuration ************************************************************/ +/* This supports configuration of CGU clocking from board-specific parameters + * that must be provided in the board.h header file. + * + * That header file must provided the following values: + * + * BOARD_XTAL_FREQUENCY - The LPC43xx XTAL oscillator input frequency + */ + +#ifndef BOARD_XTAL_FREQUENCY +# error "board.h must provide the LPC43xx cystal input frequency (BOARD_XTAL_FREQUENCY)" +#endif + +#if BOARD_XTAL_FREQUENCY >= MAX_XTAL_FREQUENCY +# error "BOARD_XTAL_FREQUENCY exceeds the maximum value" +#endif + +#if !defined(BOARD_PLL1_DIRECT) && (BOARD_FCLKOUT_FREQUENCY > MAX_FCLKOUT_FREQUENCY) +# error "BOARD_FCLKOUT_FREQUENCY exceed the maximum" +#endif + +#if BOARD_FCCO_FREQUENCY > MAX_FCCO_FRQUENCY +# error "BOARD_FCCO_FREQUENCY exceed the maximum" +#endif + +/* Convert the user-friendly definitions in board.h to register bit settings */ + +#if BOARD_PLL_PSEL == 1 +# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV1 +#elif BOARD_PLL_PSEL == 2 +# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV2 +#elif BOARD_PLL_PSEL == 4 +# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV4 +#elif BOARD_PLL_PSEL == 8 +# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV8 +#else +# error "Unsupported value of BOARD_PLL_PSEL" +#endif + +#if BOARD_PLL_NSEL == 1 +# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV1 +#elif BOARD_PLL_NSEL == 2 +# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV2 +#elif BOARD_PLL_NSEL == 3 +# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV3 +#elif BOARD_PLL_NSEL == 4 +# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV4 +#else +# error "Unsupported value of BOARD_PLL_NSEL" +#endif + +#if (BOARD_PLL_MSEL > 0) && (BOARD_PLL_MSEL < 256) +# define CTRL_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_MSEL) +#else +# error "Unsupported value of BOARD_PLL_NSEL" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_xtalconfig + * + * Description: + * Configure the cystal input to PLL1 using the settings provided in + * the board.h file. + * + ****************************************************************************/ + +static inline void lpc43_xtalconfig(void) +{ + /* Configure the crystal input to PLL1 */ + + uint32_t regval; + + /* Set/clear the HF bit in the crystal oscillator control register. + * - The bit must be cleared if low-frequency oscillators (<=15MHz) + * - The HF bit must be set for high-frequency osciallators (>20MHz) + * - For oscillators in the range 15-20 MHz, the HF setting does not matter. + */ + + regval = getreg32(LPC43_XTAL_OSC_CTRL); +#if BOARD_XTAL_FREQUENCY <= LOW_XTAL_FREQUENCY + regval &= ~XTAL_OSC_CTRL_HF; +#else + regval |= XTAL_OSC_CTRL_HF; +#endif + putreg32(regval, LPC43_XTAL_OSC_CTRL); + + /* Enable the crystal oscillator */ + + regval |= XTAL_OSC_CTRL_ENABLE; + putreg32(regval, LPC43_XTAL_OSC_CTRL); + + /* Delay for stable clock input */ + + up_mdelay(20); + + /* Select the crystal oscillator as the input to PLL1 */ + + regval = getreg32(LPC43_PLL1_CTRL); + regval &= PLL1_CTRL_CLKSEL_MASK; + regval |= PLL1_CLKSEL_XTAL | PLL1_CTRL_AUTOBLOCK; + putreg32(regval, LPC43_PLL1_CTRL); +} + +/**************************************************************************** + * Name: lpc43_clockconfig + * + * Description: + * Configure PLL1 dividers and multipliers per the settings in the board.h + * file to generate the desired Fclkcout and Fcco frequencies. + * + ****************************************************************************/ + +static inline void lpc43_pll1config(void) +{ + uint32_t regval; + + /* Clear PLL1 controls: + * + * - PLL1_CTRL_BYPASS: Input clock bypass control + * - PLL1_CTRL_FBSEL: PLL1 feedback select + * - PLL1_CTRL_DIRECT: PLL1 direct CCO output + * - PLL1_CTRL_PSEL_MASK: Post-divider division ratio P (psel) + * - PLL1_CTRL_NSEL_MASK: Pre-divider division ratio N (nsel) + * - PLL1_CTRL_MSEL_MASK: Feedback-divider division ratio M (msel) + */ + + regval = getreg32(LPC43_PLL1_CTRL); + regval &= ~(PLL1_CTRL_BYPASS | PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | + PLL1_CTRL_PSEL_MASK | PLL1_CTRL_NSEL_MASK | + PLL1_CTRL_MSEL_MASK); + putreg32(regval, LPC43_PLL1_CTRL); + + /* Clear PLL1 controls: + * + * - PLL1_CTRL_FBSEL: Set in both integer and direct modes + * - PLL1_CTRL_DIRECT: Set in direct mode + * - PLL1_CTRL_PSEL: Set to the value from board.h + * - PLL1_CTRL_NSEL: Set to the value from board.h + * - PLL1_CTRL_MSEL: Set to the value from board.h + */ + +#ifdef BOARD_PLL1_DIRECT + regval |= (PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | CTRL_PSEL_VALUE | + CTRL_NSEL_VALUE | CTRL_MSEL_VALUE); +#else + regval |= (PLL1_CTRL_FBSEL | CTRL_PSEL_VALUE | CTRL_NSEL_VALUE | + CTRL_MSEL_VALUE); +#endif + putreg32(regval, LPC43_PLL1_CTRL); +} + +/**************************************************************************** + * Name: lpc43_pll1enable + * + * Description: + * Take PLL1 out of power-down mode and wait until it is locked onto the + * input clock. + * + ****************************************************************************/ + +static inline void lpc43_pll1enable(void) +{ + uint32_t regval; + + /* Take PLL1 out of power down mode. The reset state of the PD bit + * is one, i.e., powered down. + */ + + regval = getreg32(LPC43_PLL1_CTRL); + regval &= ~PLL1_CTRL_PD; + putreg32(regval, LPC43_PLL1_CTRL); + + /* When the power-down mode is terminated, PPL1 will resume its normal + * operation and will make the lock signal high once it has regained + * lock on the input clock + * + * Wait for PLL1 to report that it is locked. + */ + + while ((getreg32(LPC43_PLL1_STAT) & PLL1_STAT_LOCK) == 0); +} + +/**************************************************************************** + * Name: lpc32_m4clkselect + * + * Description: + * Select PLL1 output as the Cortex-M4 source clock. + * + ****************************************************************************/ + +static inline void lpc32_m4clkselect(void) +{ + uint32_t regval; + + regval = getreg32(LPC43_BASE_M4_CLK); + regval &= ~BASE_M4_CLK_CLKSEL_MASK; + regval |= BASE_M4_CLKSEL_PLL1; + putreg32(regval, LPC43_BASE_M4_CLK); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_clockconfig + * + * Description: + * Called to initialize the LPC43XX. This does whatever setup is needed + * to put the MCU in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void lpc43_clockconfig(void) +{ + /* Configure the crystal input to PLL1 */ + + lpc43_xtalconfig(); + + /* Configure PLL1 */ + + lpc43_pll1config(); + + /* Enable PLL1 */ + + lpc43_pll1enable(); + + /* Set up PLL1 output as the M4 clock */ + + lpc32_m4clkselect(); +} diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h index f70a9b7e2..a25db8c52 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h @@ -41,6 +41,8 @@ ************************************************************************************/ #include <nuttx/config.h> +#include "chip.h" +#include "chip/lpc43_cgu.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_emacram.h b/nuttx/arch/arm/src/lpc43xx/lpc43_emacram.h new file mode 100644 index 000000000..2c472b616 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_emacram.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_emacram.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_EMACRAM_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_EMACRAM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMACRAM_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_emc.h b/nuttx/arch/arm/src/lpc43xx/lpc43_emc.h new file mode 100644 index 000000000..3c2bd2496 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_emc.h @@ -0,0 +1,63 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_emc.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" +#include "chip/lpc43_emc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index 73a0c92e9..22471ce1e 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -261,6 +261,11 @@ static int lpc43_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) /**************************************************************************** * Name: up_irqinitialize + * + * Description: + * Complete initialization of the interrupt system and enable normal, + * interrupt processing. + * ****************************************************************************/ void up_irqinitialize(void) @@ -273,7 +278,12 @@ void up_irqinitialize(void) putreg32(0, NVIC_IRQ0_31_ENABLE); putreg32(0, NVIC_IRQ32_63_ENABLE); - /* Make sure that we are using the correct vector table */ + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ putreg32((uint32_t)_vectors, NVIC_VECTAB); diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c index 972591019..0b917a8ea 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c @@ -33,6 +33,27 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ +/* + * Power-Up Reset Overview + * ----------------------- + * + * The ARM core starts executing code on reset with the program counter set + * to 0x0000:0000. The LPC43xx contains a shadow pointer register that + * allows areas of memory to be mapped to address 0x0000:0000. The default, + * reset value of the shadow pointer is 0x1040:0000 so that on reset code in + * the boot ROM is always executed first. + * + * The boot starts after reset is released. The IRC is selected as CPU clock + * and the Cortex-M4 starts the boot loader. By default the JTAG access to the + * chip is disabled at reset. The boot ROM determines the boot mode based on + * the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part + * boots from internal flash by default. Otherwse, the boot ROM copies the + * image to internal SRAM at location 0x1000:0000, sets the ARM's shadow + * pointer to 0x1000:0000, and jumps to that location. + * + * However, using JTAG the executable image can be also loaded directly into + * and executed from SRAM. + */ #include <nuttx/config.h> @@ -45,16 +66,20 @@ #include "up_arch.h" #include "up_internal.h" +#include "nvic.h" -#ifdef CONFIG_ARCH_FPU -# include "nvic.h" -#endif +#include "chip/lpc43_creg.h" #include "lpc43_rgu.h" #include "lpc43_cgu.h" +#include "lpc43_emc.h" #include "lpc43_lowputc.h" /**************************************************************************** + * Preprocessor Definitions + ****************************************************************************/ + + /**************************************************************************** * Name: showprogress * * Description: @@ -73,6 +98,71 @@ ****************************************************************************/ /**************************************************************************** + * Name: lpc43_setbootrom + * + * Description: + * Set the shadow register to 0x1040:0000 and the VTOR to 0x0000:0000 so + * that any exceptions (particulary things like hard faults) that occur + * before we are initialized are caught by the BOOT ROM. + * + ****************************************************************************/ + +static inline void lpc43_setbootrom(void) +{ + /* Set the shadow register to the beginning of the boot ROM (Only bits 12-31) */ + + putreg32(LPC43_ROM_BASE, LPC43_CREG_M4MEMMAP); + + /* Address zero now maps to the Boot ROM. Make sure the the VTOR will + * use the ROM vector table at that address. + */ + + putreg32(0, NVIC_VECTAB); +} + +/**************************************************************************** + * Name: lpc43_enabuffering + * + * Description: + * If we are executing from external FLASH, then enable buffering. + * + ****************************************************************************/ + +#if defined(CONFIG_BOOT_CS0FLASH) || defined(CONFIG_BOOT_CS1FLASH) || \ + defined(CONFIG_BOOT_CS2FLASH) || defined(CONFIG_BOOT_CS3FLASH) +static inline void lpc43_enabuffering(void) +{ + uint32_t regval; + +#ifdef CONFIG_BOOT_CS0FLASH + regval = getreg32(LPC43_EMC_STATCONFIG0); + regval |= EMC_STATCONFIG_BENA + putreg32(regval, LPC43_EMC_STATCONFIG0); +#endif + +#ifdef CONFIG_BOOT_CS1FLASH + regval = getreg32(LPC43_EMC_STATCONFIG1); + regval |= EMC_STATCONFIG_BENA + putreg32(regval, LPC43_EMC_STATCONFIG1); +#endif + +#ifdef CONFIG_BOOT_CS2FLASH + regval = getreg32(LPC43_EMC_STATCONFIG2); + regval |= EMC_STATCONFIG_BENA + putreg32(regval, LPC43_EMC_STATCONFIG2); +#endif + +#ifdef CONFIG_BOOT_CS3FLASH + regval = getreg32(LPC43_EMC_STATCONFIG3); + regval |= EMC_STATCONFIG_BENA + putreg32(regval, LPC43_EMC_STATCONFIG3); +#endif +} +#else +# define lpc43_enabuffering() +#endif + +/**************************************************************************** * Name: lpc43_fpuconfig * * Description: @@ -190,15 +280,24 @@ void __start(void) lpc43_softreset(); #endif + /* Make sure that any exceptions (such as hard faults) that occur before + * we are initialized are caught by the BOOT ROM. + */ + + lpc43_setbootrom(); + /* Configure the CGU clocking and the console uart so that we can get * debug output as soon as possible. */ lpc43_clockconfig(); - lpc43_fpuconfig(); lpc43_lowsetup(); showprogress('A'); + /* If we are executing from external FLASH, then enable buffering */ + + lpc43_enabuffering(); + /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ @@ -221,17 +320,22 @@ void __start(void) } showprogress('C'); + /* Initialize the FPU (if configured) */ + + lpc43_fpuconfig(); + showprogress('D'); + /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT up_earlyserialinit(); #endif - showprogress('D'); + showprogress('E'); /* Initialize onboard resources */ lpc43_boardinitialize(); - showprogress('E'); + showprogress('F'); /* Then start NuttX */ @@ -239,7 +343,7 @@ void __start(void) showprogress('\n'); os_start(); - /* Shoulnd't get here */ + /* Shouldn't get here */ for(;;); } diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usbram.h b/nuttx/arch/arm/src/lpc43xx/lpc43_usbram.h new file mode 100644 index 000000000..7f23013e4 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usbram.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_usbram.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_USBRAM_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_USBRAM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_USBRAM_H */ diff --git a/nuttx/configs/lpc4330-xplorer/README.txt b/nuttx/configs/lpc4330-xplorer/README.txt index d1fcd7fb9..701ecad97 100644 --- a/nuttx/configs/lpc4330-xplorer/README.txt +++ b/nuttx/configs/lpc4330-xplorer/README.txt @@ -406,6 +406,21 @@ LPC4330-Xplorer Configuration Options CONFIG_ARCH_FPU - The LPC43xxx supports a floating point unit (FPU) CONFIG_ARCH_FPU=y + + CONFIG_BOOT_xxx - The startup code needs to know if the code is running + from internal FLASH, external FLASH, SPIFI, or SRAM in order to + initialize properly. Note that a boot device is not specified for + cases where the code is copied into SRAM; those cases are all covered + by CONFIG_BOOT_SRAM. + + CONFIG_BOOT_SRAM=y : Running from SRAM (0x1000:0000) + CONFIG_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000) + CONFIG_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000) + CONFIG_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000) + CONFIG_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000) + CONFIG_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000) + CONFIG_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000) + CONFIG_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000) CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that have LEDs diff --git a/nuttx/configs/lpc4330-xplorer/include/board.h b/nuttx/configs/lpc4330-xplorer/include/board.h index 6a3f36158..1c2f42b2c 100644 --- a/nuttx/configs/lpc4330-xplorer/include/board.h +++ b/nuttx/configs/lpc4330-xplorer/include/board.h @@ -53,80 +53,49 @@ ****************************************************************************/ /* Clocking ****************************************************************/ -/* NOTE: The following definitions require lpc43_syscon.h. It is not included here - * because the including C file may not have that file in its include path. - */ - -#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ -#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ -#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */ -#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ - -/* This is the clock setup we configure for: +/* NOTE: The following definitions require lpc43_cgu.h. It is not included + * here because the including C file may not have that file in its include + * path. * - * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 - * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 - */ - -#define LPC43_CCLK 80000000 /* 80Mhz*/ - -/* Select the main oscillator as the frequency source. SYSCLK is then the frequency - * of the main oscillator. - */ - -#undef CONFIG_LPC43_MAINOSC -#define CONFIG_LPC43_MAINOSC 1 -#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN - -/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. - * The input to the divider (PLLCLK) will be determined by the PLL output. + * The Xplorer board has four crystals on board: + * + * Y1 - RTC 32.768 MHz oscillator input, + * Y2 - 24.576 MHz input to the UDA 1380 audio codec, + * Y3 - 12.000 MHz LPC43xx crystal oscillator input + * Y4 - 50 MHz input for Ethernet */ -#define BOARD_CCLKCFG_DIVIDER 6 -#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency (Y3) */ +#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency (Y1) */ +#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ -/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). - * - * Source clock: Main oscillator - * PLL0 Multiplier value (M): 20 - * PLL0 Pre-divider value (N): 1 +/* Integer and direct modes are supported: * - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz + * In integer mode: + * Fclkin = BOARD_XTAL_FREQUENCY + * Fclkout = Msel * FClkin / Nsel + * Fcco = 2 * Psel * Nclkout + * In direct mode: + * Fclkin = BOARD_XTAL_FREQUENCY + * Fclkout = Msel * FClkin / Nsel + * Fcco = Fclkout */ -#undef CONFIG_LPC43_PLL0 -#define CONFIG_LPC43_PLL0 1 -#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN - -#define BOARD_PLL0CFG_MSEL 20 -#define BOARD_PLL0CFG_NSEL 1 -#define BOARD_PLL0CFG_VALUE \ - (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ - ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) - -/* PLL1 -- Not used. */ - -#undef CONFIG_LPC43_PLL1 -#define BOARD_PLL1CFG_MSEL 36 -#define BOARD_PLL1CFG_NSEL 1 -#define BOARD_PLL1CFG_VALUE \ - (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ - ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) +#undef BOARD_PLL1_DIRECT /* Integer mode */ +#define BOARD_PLL_MSEL (6) /* Msel = 6 */ +#define BOARD_PLL_NSEL (1) /* Nsel = 1 */ +#define BOARD_PLL_PSEL (2) /* Psel = 2 */ +#define BOARD_FCLKOUT_FREQUENCY (72000000) /* 6 * 12,000,000 / 1 */ +#define BOARD_FCCO_FREQUENCY (244000000) /* 2 * 2 * 72,000,000 */ -/* USB divider. This divider is used when PLL1 is not enabled to get the - * USB clock from PLL0: +/* This is the clock setup we configure for: * - * USBCLK = PLL0CLK / 10 = 48MHz + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 + * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ -#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10 - -/* FLASH Configuration */ - -#undef CONFIG_LP17_FLASH -#define CONFIG_LP17_FLASH 1 -#define BOARD_FLASHCFG_VALUE 0x0000303a +#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY /* LED definitions *********************************************************/ /* The LPC4330-Xplorer has 2 user-controllable LEDs labeled D2 an D3 in the diff --git a/nuttx/configs/lpc4330-xplorer/ostest/Make.defs b/nuttx/configs/lpc4330-xplorer/ostest/Make.defs index f5746db13..1e8427c1c 100644 --- a/nuttx/configs/lpc4330-xplorer/ostest/Make.defs +++ b/nuttx/configs/lpc4330-xplorer/ostest/Make.defs @@ -87,6 +87,26 @@ ifeq ($(CONFIG_LPC43_BUILDROOT),y) MAXOPTIMIZATION = -Os endif +# Setup for the kind of memory that we are executing from + +ifeq ($(CONFIG_BOOT_SRAM),y) + LDSCRIPT = ramconfig.ld +endif +ifeq ($(CONFIG_BOOT_SPIFI),y) + LDSCRIPT = spiconfig.ld +endif +ifeq ($(CONFIG_BOOT_FLASHA),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_BOOT_FLASHB),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_BOOT_CS0FLASH),y) + LDSCRIPT = cs0flash.ld +endif + +# Setup for Windows vs Linux/Cygwin/OSX environments + ifeq ($(WINTOOL),y) # Windows-native toolchains DIRLINK = $(TOPDIR)/tools/winlink.sh @@ -94,14 +114,14 @@ ifeq ($(WINTOOL),y) MKDEP = $(TOPDIR)/tools/mknulldeps.sh ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ramconfig.ld}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" MAXOPTIMIZATION = -O2 else # Linux/Cygwin-native toolchain MKDEP = $(TOPDIR)/tools/mkdeps.sh ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ramconfig.ld + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) endif CC = $(CROSSDEV)gcc diff --git a/nuttx/configs/lpc4330-xplorer/ostest/defconfig b/nuttx/configs/lpc4330-xplorer/ostest/defconfig index bd894902d..848c43eac 100644 --- a/nuttx/configs/lpc4330-xplorer/ostest/defconfig +++ b/nuttx/configs/lpc4330-xplorer/ostest/defconfig @@ -97,6 +97,31 @@ CONFIG_ARCH_DMA=n CONFIG_ARMV7M_CMNVECTOR=y # +# CONFIG_BOOT_xxx - The startup code needs to know if the code is running +# from internal FLASH, external FLASH, SPIFI, or SRAM in order to +# initialize properly. Note that a boot device is not specified for +# cases where the code is copied into SRAM; those cases are all covered +# by CONFIG_BOOT_SRAM. +# +# CONFIG_BOOT_SRAM=y : Running from SRAM (0x1000:0000) +# CONFIG_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000) +# CONFIG_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000) +# CONFIG_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000) +# CONFIG_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000) +# CONFIG_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000) +# CONFIG_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000) +# CONFIG_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000) +# +CONFIG_BOOT_SRAM=y +CONFIG_BOOT_SPIFI=n +CONFIG_BOOT_FLASHA=n +CONFIG_BOOT_FLASHB=n +CONFIG_BOOT_CS0FLASH=n +CONFIG_BOOT_CS1FLASH=n +CONFIG_BOOT_CS2FLASH=n +CONFIG_BOOT_CS3FLASH=n + +# # Identify toolchain and linker options # CONFIG_LPC43_CODESOURCERYW=y diff --git a/nuttx/configs/lpc4330-xplorer/scripts/ramconfig.ld b/nuttx/configs/lpc4330-xplorer/scripts/ramconfig.ld index 4e4abca8a..f44d6181e 100644 --- a/nuttx/configs/lpc4330-xplorer/scripts/ramconfig.ld +++ b/nuttx/configs/lpc4330-xplorer/scripts/ramconfig.ld @@ -32,6 +32,27 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ +/* + * Power-Up Reset Overview + * ----------------------- + * + * The ARM core starts executing code on reset with the program counter set + * to 0x0000 0000. The LPC43xx contains a shadow pointer register that + * allows areas of memory to be mapped to address 0x0000 0000. The default, + * reset value of the shadow pointer is 0x1040 0000 so that on reset code in + * the boot ROM is always executed first. + * + * The boot starts after reset is released. The IRC is selected as CPU clock + * and the Cortex-M4 starts the boot loader. By default the JTAG access to the + * chip is disabled at reset. The boot ROM determines the boot mode based on + * the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part + * boots from internal flash by default. Otherwse, the boot ROM copies the + * image to internal SRAM at location 0x1000 0000, sets the ARM's shadow + * pointer to 0x1000 0000, and jumps to that location. + * + * However, using JTAG the executable image can be also loaded directly into + * and executed from SRAM. + */ /* The LPC4330 on the LPC4330-Xplorer has the following memory resources: * @@ -41,6 +62,7 @@ * b. 72KB beginning at address 0x1008:0000 and * c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000, * 0x2000:8000 and 0x2000:C000. + * 3. No internal FLASH * * Here we assume that: * diff --git a/nuttx/configs/lpc4330-xplorer/scripts/spificonfig.ld b/nuttx/configs/lpc4330-xplorer/scripts/spificonfig.ld index 6aa7c2657..7bbb3d295 100644 --- a/nuttx/configs/lpc4330-xplorer/scripts/spificonfig.ld +++ b/nuttx/configs/lpc4330-xplorer/scripts/spificonfig.ld @@ -32,6 +32,27 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ +/* + * Power-Up Reset Overview + * ----------------------- + * + * The ARM core starts executing code on reset with the program counter set + * to 0x0000 0000. The LPC43xx contains a shadow pointer register that + * allows areas of memory to be mapped to address 0x0000 0000. The default, + * reset value of the shadow pointer is 0x1040 0000 so that on reset code in + * the boot ROM is always executed first. + * + * The boot starts after reset is released. The IRC is selected as CPU clock + * and the Cortex-M4 starts the boot loader. By default the JTAG access to the + * chip is disabled at reset. The boot ROM determines the boot mode based on + * the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part + * boots from internal flash by default. Otherwse, the boot ROM copies the + * image to internal SRAM at location 0x1000 0000, sets the ARM's shadow + * pointer to 0x1000 0000, and jumps to that location. + * + * Of course, using JTAG the executable image can be also loaded directly + * into and executed from SRAM. + */ /* The LPC4330 on the LPC4330-Xplorer has the following memory resources: * @@ -41,6 +62,7 @@ * b. 72KB beginning at address 0x1008:0000 and * c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000, * 0x2000:8000 and 0x2000:C000. + * 3. No internal FLASH * * Here we assume that: * |