############################################################################
# arch/arm/src/lpc17xx/Make.defs
#
# Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
# The start-up, "head", file
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
HEAD_ASRC =
else
HEAD_ASRC = lpc17_vectors.S
endif
# Common ARM and Cortex-M3 files
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_ASRCS += vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_modifyreg8.c
CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c
CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c
CMN_CSRCS += up_hardfault.c up_svcall.c up_checkstack.c up_vfork.c
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_ASRCS += up_exception.S
CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_NET),y)
ifneq ($(CONFIG_LPC17_ETHERNET),y)
CMN_CSRCS += up_etherstub.c
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
endif
# Required LPC17xx files
CHIP_ASRCS =
CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_clrpend.c
CHIP_CSRCS += lpc17_gpio.c lpc17_i2c.c lpc17_idle.c lpc17_irq.c lpc17_lowputc.c
CHIP_CSRCS += lpc17_serial.c lpc17_spi.c lpc17_ssp.c lpc17_start.c lpc17_timerisr.c
# Configuration-dependent LPC17xx files
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CHIP_ASRCS += lpc17_vectors.S
endif
ifeq ($(CONFIG_LPC17_EMC),y)
CHIP_CSRCS += lpc17_emc.c
endif
ifeq ($(CONFIG_GPIO_IRQ),y)
CHIP_CSRCS += lpc17_gpioint.c
endif
ifeq ($(CONFIG_DEBUG_GPIO),y)
CHIP_CSRCS += lpc17_gpiodbg.c
endif
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += lpc17_usbdev.c
endif
ifeq ($(CONFIG_USBHOST),y)
CHIP_CSRCS += lpc17_usbhost.c
endif
ifeq ($(CONFIG_LPC17_GPDMA),y)
CHIP_CSRCS += lpc17_gpdma.c
endif
ifeq ($(CONFIG_NET),y)
ifeq ($(CONFIG_LPC17_ETHERNET),y)
CHIP_CSRCS += lpc17_ethernet.c
endif
endif
ifeq ($(CONFIG_CAN),y)
CHIP_CSRCS += lpc17_can.c
endif
ifeq ($(CONFIG_LPC17_ADC),y)
CHIP_CSRCS += lpc17_adc.c
endif
ifeq ($(CONFIG_LPC17_DAC),y)
CHIP_CSRCS += lpc17_dac.c
endif