Open1788 OpenOCD support

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5730 42af7a65-404d-4744-a932-0658087f49c3

3 files changed, 296 insertions, 2 deletions

diff --git a/nuttx/configs/open1788/README.txt b/nuttx/configs/open1788/README.txt
index c207254ca..da3d91821 100644
--- a/nuttx/configs/open1788/README.txt
+++ b/nuttx/configs/open1788/README.txt
@@ -11,6 +11,7 @@ CONTENTS
   o LEDs
   o Buttons
   o FPU
+  o Using OpenOCD with the Olimex ARM-USB-OCD
   o Configuration
 
 LEDs
@@ -152,8 +153,122 @@ See the section above on Toolchains, NOTE 2, for explanations for some of
 the configuration settings.  Some of the usual settings are just not supported
 by the "Lite" version of the Atollic toolchain.
 
-CONFIGURURATION
-===============
+Using OpenOCD with the Olimex ARM-USB-OCD
+=========================================
+
+  Building OpenOCD under Cygwin:
+
+    Refer to configs/olimex-lpc1766stk/README.txt
+
+  Installing OpenOCD in Ubuntu Linux:
+
+    sudo apt-get install openocd
+
+  Helper Scripts.
+
+    I have been using the Olimex ARM-USB-OCD debugger.  OpenOCD
+    requires a configuration file.  I keep the one I used last here:
+    
+      configs/open1788/tools/open1788.cfg
+
+    However, the "correct" configuration script to use with OpenOCD may
+    change as the features of OpenOCD evolve.  So you should at least
+    compare that open1788.cfg file with configuration files in
+    /usr/share/openocd/scripts.  As of this writing, the configuration
+    files of interest were:
+
+      /usr/local/share/openocd/scripts/interface/openocd-usb.cfg
+        This is the configuration file for the Olimex ARM-USB-OCD
+        debugger.  Select a different file if you are using some
+        other debugger supported by OpenOCD.
+
+      /usr/local/share/openocd/scripts/board/?
+        I don't see a board configuration file for the WaveShare
+        Open1788 board.
+
+      /usr/local/share/openocd/scripts/target/lpc1788.cfg
+        This is the configuration file for the the LPC1788 target.
+        It just sets up a few parameters then sources lpc17xx.cfg
+
+      /usr/local/share/openocd/scripts/target/lpc17xx.cfg
+        This is the generic LPC configuration for the LPC17xx
+        family.  It is included by lpc1788.cfg.
+
+    NOTE:  These files could also be located under /usr/share in some
+    installations.  They could be most anywhwere if you are using a
+    windows version of OpenOCD.
+ 
+      configs/open1788/tools/open1788.cfg
+        This is simply openocd-usb.cfg, lpc1788.cfg, and lpc17xx.cfg
+        concatenated into one file for convenience.  Don't use it
+        unless you have to.
+
+    There is also a script on the tools/ directory that I use to start
+    the OpenOCD daemon on my system called oocd.sh.  That script will
+    probably require some modifications to work in another environment:
+  
+    - Possibly the value of OPENOCD_PATH and TARGET_PATH
+    - It assumes that the correct script to use is the one at
+      configs/open1788/tools/open1788.cfg
+
+  Starting OpenOCD
+
+    Then you should be able to start the OpenOCD daemon as follows.  This
+    assumes that you have already CD'ed to the NuttX build directory:
+
+      . ./setenv.sh
+      oocd.sh $PWD
+
+    The setenv.sh script is a convenience script that you may choose to
+    use or not.  It simply sets up the PATH variable so that you can
+    automatically find oocd.sh.  You could also do:
+
+      configs/open1788/tools/oocd.sh $PWD
+
+  Connecting GDB
+
+    Once the OpenOCD daemon has been started, you can connect to it via
+    GDB using the following GDB command:
+
+      arm-nuttx-elf-gdb
+      (gdb) target remote localhost:3333
+
+    NOTE:  The name of your GDB program may differ.  For example, with the
+    CodeSourcery toolchain, the ARM GDB would be called arm-none-eabi-gdb.
+
+    OpenOCD will support several special 'monitor' sub-commands.  You can
+    use the 'monitor' (or simply 'mon') command to invoke these sub-
+    commands. These GDB commands will send comments to the OpenOCD monitor.
+    Here are a couple that you will need to use:
+  
+     (gdb) monitor reset
+     (gdb) monitor halt
+
+    NOTES:
+    1. The MCU must be halted using 'monitor halt' prior to loading code.
+    2. 'monitor reset' will restart the processor after loading code.
+    3. The 'monitor' command can be abbreviated as just 'mon'.
+
+    After starting GDB, you can load the NuttX ELF file:
+
+      (gdb) mon halt
+      (gdb) load nuttx
+
+    NOTES:
+    1. NuttX should have been built so that it has debugging symbols
+       (by setting CONFIG_DEBUG_SYMBOLS=y in the .config file).
+    2. The MCU must be halted prior to loading code.
+    3. I find that there are often undetected write failures.  I usually
+       load nuttx twice to assure good FLASH contents:
+ 
+      (gdb) mon halt
+      (gdb) load nuttx
+      (gdb) mon reset
+      (gdb) mon halt
+      (gdb) load nuttx
+
+CONFIGURATION
+=============
 
   ostest
   ------ 
diff --git a/nuttx/configs/open1788/tools/oocd.sh b/nuttx/configs/open1788/tools/oocd.sh
new file mode 100755
index 000000000..e3526c059
--- /dev/null
+++ b/nuttx/configs/open1788/tools/oocd.sh
@@ -0,0 +1,57 @@
+#!/bin/sh
+#
+# See configs/open1788/README.txt for information about
+# this file.
+
+TOPDIR=$1
+USAGE="$0 <TOPDIR> [-d]"
+if [ -z "${TOPDIR}" ]; then
+	echo "Missing argument"
+	echo $USAGE
+	exit 1
+fi
+
+# Assume that OpenOCD was installed and at /usr/local/bin.  Uncomment
+# the following to run directly from the build directory
+
+# OPENOCD_PATH="/home/OpenOCD/openocd/src"
+# OPENOCD_PATH="/usr/bin"
+OPENOCD_PATH="/usr/local/bin"
+
+# TARGET_PATH="/home/OpenOCD/openocd/tcl"
+# TARGET_PATH="/usr/share/openocd/scripts"
+TARGET_PATH="/usr/local/share/openocd/scripts"
+
+# Assume a Unix development environment.  Uncomment to use a Windows
+# like environment
+
+OPENOCD_EXE=openocd.exe
+# OPENOCD_EXE=openocd
+
+OPENOCD_CFG="${TOPDIR}/configs/open1788/tools/open1788.cfg"
+OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}"
+
+if [ "X$2" = "X-d" ]; then
+	OPENOCD_ARGS=$OPENOCD_ARGS" -d3"
+	set -x
+fi
+
+if [ ! -d ${OPENOCD_PATH} ]; then
+	echo "OpenOCD path does not exist: ${OPENOCD_PATH}"
+	exit 1
+fi
+if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then
+	echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}"
+	exit 1
+fi
+if [ ! -f ${OPENOCD_CFG} ]; then
+	echo "OpenOCD config file does not exist: ${OPENOCD_CFG}"
+	exit 1
+fi
+
+echo "Starting OpenOCD"
+cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; }
+${OPENOCD_EXE} ${OPENOCD_ARGS} &
+echo "OpenOCD daemon started"
+ps -ef | grep openocd
+echo "In GDB: target remote localhost:3333"
diff --git a/nuttx/configs/open1788/tools/open1788.cfg b/nuttx/configs/open1788/tools/open1788.cfg
new file mode 100755
index 000000000..9c251b4e9
--- /dev/null
+++ b/nuttx/configs/open1788/tools/open1788.cfg
@@ -0,0 +1,122 @@
+### From /usr/local/share/openocd/scripts/interface/olimex-arm-usb-ocd.cfg
+#
+# Olimex ARM-USB-OCD
+#
+# http://www.olimex.com/dev/arm-usb-ocd.html
+#
+
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG A"
+ft2232_layout olimex-jtag
+ft2232_vid_pid 0x15ba 0x0003
+
+### From /usr/local/share/openocd/scripts/targets/lpc1788.cfg
+# NXP LPC1788 Cortex-M3 with 512kB Flash and 96kB Local On-Chip SRAM 
+# remember to place in the same folder as lpc17xx.cfg
+
+set CHIPNAME lpc1788
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x18000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 12000
+
+### From /usr/local/share/openocd/scripts/targets/lpc17xx.cfg
+# Common LPC17xx logic
+
+# LPC17xx chips support both JTAG and SWD transports.
+# JTAG is hard-coded in this configuration
+# Adapt based on what transport is active.
+# source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	error "_CHIPNAME not set"
+}
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+	set _CCLK $CCLK
+} else {
+	set _CCLK 4000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	error "_CPUTAPID not set"
+}
+
+if { [info exists CPURAMSIZE] } {
+  set _CPURAMSIZE $CPURAMSIZE
+} else {
+	error "_CPURAMSIZE not set"
+}
+
+if { [info exists CPUROMSIZE] } {
+  set _CPUROMSIZE $CPUROMSIZE
+} else {
+	error "_CPUROMSIZE not set"
+}
+
+#delays on reset lines
+adapter_nsrst_delay 500
+jtag_ntrst_delay 500
+
+# Use of JTAG is hard-coded
+#swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
+
+# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
+
+# The LPC17xx devices have 32/64/128/256/512kB of flash memory, managed by ROM code
+# (including a boot loader which verifies the flash exception table's checksum).
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
+	lpc1700 $_CCLK calc_checksum
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter_khz 1000
+
+$_TARGETNAME configure -event reset-init {
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+
+	mww 0x4ba00477 0x01
+}
+
+# if srst is not fitted use VECTRESET to
+# perform a soft reset - SYSRESETREQ is not supported
+cortex_m3 reset_config vectreset