diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-09-12 02:22:13 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-09-12 02:22:13 +0000 |
commit | 57cfc31e7ad31696b66773e606ab4ac4213b1ab9 (patch) | |
tree | d1b8c6deaf8582b6e2e08ace70f75956d0e67018 | |
parent | 933bdd7122738de72b79110af1093f679dd2c15d (diff) | |
download | px4-nuttx-57cfc31e7ad31696b66773e606ab4ac4213b1ab9.tar.gz px4-nuttx-57cfc31e7ad31696b66773e606ab4ac4213b1ab9.tar.bz2 px4-nuttx-57cfc31e7ad31696b66773e606ab4ac4213b1ab9.zip |
Add driver for Atmel AT45DB161 FLASH
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2940 42af7a65-404d-4744-a932-0658087f49c3
-rw-r--r-- | nuttx/ChangeLog | 2 | ||||
-rw-r--r-- | nuttx/Documentation/NuttX.html | 4 | ||||
-rw-r--r-- | nuttx/Documentation/NuttxPortingGuide.html | 17 | ||||
-rw-r--r-- | nuttx/configs/README.txt | 15 | ||||
-rwxr-xr-x | nuttx/configs/ea3131/pgnsh/defconfig | 20 | ||||
-rwxr-xr-x | nuttx/configs/ea3131/src/up_fillpage.c | 62 | ||||
-rw-r--r-- | nuttx/drivers/mtd/Make.defs | 4 | ||||
-rw-r--r-- | nuttx/drivers/mtd/at45db.c | 779 | ||||
-rw-r--r-- | nuttx/include/nuttx/mtd.h | 14 |
9 files changed, 868 insertions, 49 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 96f0e79bf..0a1e206d5 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -1279,3 +1279,5 @@ * sched/sem_wait.c and sem_waitirq.c - Eliminate a race condition that can occur when a semaphore wait is interrupt by a signal. (see email thread: http://tech.groups.yahoo.com/group/nuttx/message/530) + * drivers/mtd/at45db.c - Add a driver for the Atmel AT45DB161D 4Mbit + SPI FLASH part (untested on initial check-in). diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index 403d0d697..afe46fc19 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -8,7 +8,7 @@ <tr align="center" bgcolor="#e4e4e4"> <td> <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1> - <p>Last Updated: September 9, 2010</p> + <p>Last Updated: September 11, 2010</p> </td> </tr> </table> @@ -1974,6 +1974,8 @@ nuttx-5.11 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr> * sched/sem_wait.c and sem_waitirq.c - Eliminate a race condition that can occur when a semaphore wait is interrupt by a signal. (see email thread: http://tech.groups.yahoo.com/group/nuttx/message/530) + * drivers/mtd/at45db.c - Add a driver for the Atmel AT45DB161D 4Mbit + SPI FLASH part (untested on initial check-in). pascal-2.1 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr> diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index 63b2dc864..7666a29df 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -12,7 +12,7 @@ <h1><big><font color="#3c34ec"> <i>NuttX RTOS Porting Guide</i> </font></big></h1> - <p>Last Updated: September 10, 2010</p> + <p>Last Updated: September 11, 2010</p> </td> </tr> </table> @@ -2596,16 +2596,21 @@ build <li> <code>CONFIG_PAGING_M25PX</code>: Use the m25px.c FLASH driver. - If this is selected, then the MTD interface to the M25Px device will be used to support paging. + If this is selected, then the MTD interface to the M25Px device will be used to support paging. </li> <li> - <code>CONFIG_PAGING_M25PX_BINOFFSET</code>: - If CONFIG_PAGING_M25PX is defined then CONFIG_PAGING_M25PX_BINOFFSET will be used to specify the offset in bytes into the FLASH device where the NuttX binary image is located. + <code>CONFIG_PAGING_AT45DB</code>: + Use the at45db.c FLASH driver. + If this is selected, then the MTD interface to the Atmel AT45DB device will be used to support paging. + </li> + <li> + <code>CONFIG_PAGING_BINOFFSET</code>: + If CONFIG_PAGING_M25PX or CONFIG_PAGING_AT45DB is defined then CONFIG_PAGING_BINOFFSET will be used to specify the offset in bytes into the FLASH device where the NuttX binary image is located. Default: 0 </li> <li> - <code>CONFIG_PAGING_M25PX_SPIPORT</code>: - If CONFIG_PAGING_M25PX is defined and the device has multiple SPI busses (ports), then this configuration should be set to indicate which SPI port the M25Px device is connected. + <code>CONFIG_PAGING_SPIPORT</code>: + If CONFIG_PAGING_M25PX or CONFIG_PAGING_AT45DB is defined and the device has multiple SPI busses (ports), then this configuration should be set to indicate which SPI port the device is connected. Default: 0 </li> </ul> diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 66111d791..8f0e02ea2 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -423,14 +423,17 @@ defconfig -- This is a configuration file similar to the Linux CONFIG_PAGING_M25PX - Use the m25px.c FLASH driver. If this is selected, then the MTD interface to the M25Px device will be used to support paging. - CONFIG_PAGING_M25PX_BINOFFSET - If CONFIG_PAGING_M25PX is defined then - CONFIG_PAGING_M25PX_BINOFFSET will be used to specify the offset + CONFIG_PAGING_AT45DB - Use the at45db.c FLASH driver. If this is selected, + then the MTD interface to the Atmel AT45DB device will be used to support + paging. + CONFIG_PAGING_BINOFFSET - If CONFIG_PAGING_M25PX or is CONFIG_PAGING_AT45DB + defined then CONFIG_PAGING_BINOFFSET will be used to specify the offset in bytes into the FLASH device where the NuttX binary image is located. Default: 0 - CONFIG_PAGING_M25PX_SPIPORT - If CONFIG_PAGING_M25PX is defined and - the device has multiple SPI busses (ports), then this configuration - should be set to indicate which SPI port the M25Px device is connected. - Default: 0 + CONFIG_PAGING_SPIPORT - If CONFIG_PAGING_M25PX CONFIG_PAGING_AT45DB is + defined and the device has multiple SPI busses (ports), then this + configuration should be set to indicate which SPI port the device is + connected. Default: 0 The following can be used to disable categories of APIs supported by the OS. If the compiler supports weak functions, then it diff --git a/nuttx/configs/ea3131/pgnsh/defconfig b/nuttx/configs/ea3131/pgnsh/defconfig index 17e8ae075..e1c9b0871 100755 --- a/nuttx/configs/ea3131/pgnsh/defconfig +++ b/nuttx/configs/ea3131/pgnsh/defconfig @@ -427,14 +427,17 @@ CONFIG_SIG_SIGWORK=4 # CONFIG_PAGING_M25PX - Use the m25px.c FLASH driver. If this is selected, # then the MTD interface to the M25Px device will be used to support # paging. -# CONFIG_PAGING_M25PX_BINOFFSET - If CONFIG_PAGING_M25PX is defined then -# CONFIG_PAGING_M25PX_BINOFFSET will be used to specify the offset +# CONFIG_PAGING_AT45DB - Use the at45db.c FLASH driver. If this is selected, +# then the MTD interface to the Atmel AT45DB device will be used to support +# paging. +# CONFIG_PAGING_BINOFFSET - If CONFIG_PAGING_M25PX or CONFIG_PAGING_AT45DB +# is defined then CONFIG_PAGING_BINOFFSET will be used to specify the offset # in bytes into the FLASH device where the NuttX binary image is located. # Default: 0 -# CONFIG_PAGING_M25PX_SPIPORT - If CONFIG_PAGING_M25PX is defined and -# the device has multiple SPI busses (ports), then this configuration -# should be set to indicate which SPI port the M25Px device is connected. -# Default: 0 +# CONFIG_PAGING_SPIPORT - If CONFIG_PAGING_M25PX or CONFIG_PAGING_AT45DB +# is defined and the device has multiple SPI busses (ports), then this +# configuration should be set to indicate which SPI port the device is +# connected. Default: 0 # CONFIG_PAGING=y CONFIG_PAGING_PAGESIZE=1024 @@ -457,8 +460,9 @@ CONFIG_PAGING_MOUNTPT="/mnt/pgsrc" CONFIG_PAGING_MINOR=0 CONFIG_PAGING_SDSLOT=0 CONFIG_PAGING_M25PX=n -CONFIG_PAGING_M25PX_BINOFFSET=0 -CONFIG_PAGING_M25PX_SPIPORT=0 +CONFIG_PAGING_AT45DB=n +CONFIG_PAGING_BINOFFSET=0 +CONFIG_PAGING_SPIPORT=0 # # The following can be used to disable categories of diff --git a/nuttx/configs/ea3131/src/up_fillpage.c b/nuttx/configs/ea3131/src/up_fillpage.c index 6058095d3..156f89ab8 100755 --- a/nuttx/configs/ea3131/src/up_fillpage.c +++ b/nuttx/configs/ea3131/src/up_fillpage.c @@ -62,7 +62,7 @@ # endif #endif -#ifdef CONFIG_PAGING_M25PX +#if defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) # include <sys/ioctl.h> # include <nuttx/ioctl.h> # include <nuttx/spi.h> @@ -94,10 +94,18 @@ /* Sanity check: We can only perform paging using a single source device */ +#if defined(CONFIG_PAGING_M25PX) && defined(CONFIG_PAGING_AT45DB) +# error "Both CONFIG_PAGING_M25PX and CONFIG_PAGING_AT45DB are defined" +# undef CONFIG_PAGING_M25PX +#endif #if defined(CONFIG_PAGING_BINPATH) && defined(CONFIG_PAGING_M25PX) # error "Both CONFIG_PAGING_BINPATH and CONFIG_PAGING_M25PX are defined" # undef CONFIG_PAGING_BINPATH #endif +#if defined(CONFIG_PAGING_BINPATH) && defined(CONFIG_PAGING_AT45DB) +# error "Both CONFIG_PAGING_BINPATH and CONFIG_PAGING_AT45DB are defined" +# undef CONFIG_PAGING_BINPATH +#endif /* Are we accessing the page source data through a file path? */ @@ -140,7 +148,7 @@ /* Are we accessing the page source data through the M25P* MTD device? */ -#ifdef CONFIG_PAGING_M25PX +#if defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) /* Verify that SPI support is enabld */ @@ -152,14 +160,14 @@ * of the NuttX binary image. */ -# ifndef CONFIG_PAGING_M25PX_BINOFFSET -# define CONFIG_PAGING_M25PX_BINOFFSET 0 +# ifndef CONFIG_PAGING_BINOFFSET +# define CONFIG_PAGING_BINOFFSET 0 # endif /* Make sure that some value is defined for the SPI port number */ -# ifndef CONFIG_PAGING_M25PX_SPIPORT -# define CONFIG_PAGING_M25PX_SPIPORT 0 +# ifndef CONFIG_PAGING_SPIPORT +# define CONFIG_PAGING_SPIPORT 0 # endif #endif @@ -179,7 +187,7 @@ struct pg_source_s /* State structured needd to support paging through the M25P* MTD interface. */ -#ifdef CONFIG_PAGING_M25PX +#if defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) struct pg_source_s { /* If interrupts or DMA are used, then we will have to defer initialization */ @@ -204,7 +212,7 @@ struct pg_source_s * Private Data ****************************************************************************/ -#if defined(CONFIG_PAGING_BINPATH) || defined(CONFIG_PAGING_M25PX) +#if defined(CONFIG_PAGING_BINPATH) || defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) static struct pg_source_s g_pgsrc; #endif @@ -277,7 +285,7 @@ static inline void lpc313x_initsrc(void) } } -#elif defined(CONFIG_PAGING_M25PX) +#elif defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) static inline void lpc313x_initsrc(void) { #ifdef CONFIG_DEBUG @@ -295,12 +303,16 @@ static inline void lpc313x_initsrc(void) /* First get an instance of the SPI device interface */ - FAR struct spi_dev_s *spi = up_spiinitialize(CONFIG_PAGING_M25PX_SPIPORT); + FAR struct spi_dev_s *spi = up_spiinitialize(CONFIG_PAGING_SPIPORT); DEBUGASSERT(spi != NULL); - /* Then bind the SPI interface to the M25Px MTD driver */ + /* Then bind the SPI interface to the MTD driver */ +#ifdef CONFIG_PAGING_M25PX g_pgsrc.mtd = m25p_initialize(spi); +#else + g_pgsrc.mtd = at45db_initialize(spi); +#endif DEBUGASSERT(g_pgsrc.mtd != NULL); /* Verify that we can use the device */ @@ -315,7 +327,7 @@ static inline void lpc313x_initsrc(void) DEBUGASSERT(ret >= 0); capacity = g_pgsrc.geo.erasesize*g_pgsrc.geo.neraseblocks; pgllvdbg("capacity: %d\n", capacity); - DEBUGASSERT(capacity >= (CONFIG_PAGING_M25PX_BINOFFSET + PG_TEXT_VSIZE)); + DEBUGASSERT(capacity >= (CONFIG_PAGING_BINOFFSET + PG_TEXT_VSIZE)); #endif #if defined(CONFIG_LPC313x_SPI_INTERRUPTS) || defined(CONFIG_LPC313x_SPI_DMA) @@ -394,7 +406,7 @@ int up_fillpage(FAR _TCB *tcb, FAR void *vpage) ssize_t nbytes; off_t offset; off_t pos; -#elif defined(CONFIG_PAGING_M25PX) +#elif defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) ssize_t nbytes; off_t offset; #endif @@ -432,11 +444,11 @@ int up_fillpage(FAR _TCB *tcb, FAR void *vpage) DEBUGASSERT(nbytes == PAGESIZE); return OK; -#elif defined(CONFIG_PAGING_M25PX) /* !CONFIG_PAGING_BINPATH */ +#elif defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) /* !CONFIG_PAGING_BINPATH */ - /* If CONFIG_PAGING_M25PX is defined, use the m25px.c FLASH driver. If this - * is selected, then the MTD interface to the M25Px device will be used to - * support paging. + /* If CONFIG_PAGING_M25PX or CONFIG_PAGING_AT45DB is defined, use the + * SPI corresponding FLASH driver. If either are selected, then the + * MTD interface to the device will be used to support paging. * * If the driver is configured to use interrupts or DMA, then it must be * initialized in this context. @@ -450,7 +462,7 @@ int up_fillpage(FAR _TCB *tcb, FAR void *vpage) * virtual address. File offset 0 corresponds to PG_LOCKED_VBASE. */ - offset = (off_t)tcb->xcp.far - PG_LOCKED_VBASE + CONFIG_PAGING_M25PX_BINOFFSET; + offset = (off_t)tcb->xcp.far - PG_LOCKED_VBASE + CONFIG_PAGING_BINOFFSET; /* Read the page at the correct offset into the SPI FLASH device */ @@ -458,12 +470,12 @@ int up_fillpage(FAR _TCB *tcb, FAR void *vpage) DEBUGASSERT(nbytes == PAGESIZE); return OK; -#else /* !CONFIG_PAGING_BINPATH && !CONFIG_PAGING_M25PX */ +#else /* !CONFIG_PAGING_BINPATH && !CONFIG_PAGING_M25PX && !CONFIG_PAGING_AT45DB */ # warning "Not implemented" return -ENOSYS; -#endif /* !CONFIG_PAGING_BINPATH && !CONFIG_PAGING_M25PX */ +#endif /* !CONFIG_PAGING_BINPATH && !CONFIG_PAGING_M25PX && !CONFIG_PAGING_AT45DB */ } #else /* CONFIG_PAGING_BLOCKINGFILL */ @@ -477,7 +489,7 @@ int up_fillpage(FAR _TCB *tcb, FAR void *vpage, up_pgcallback_t pg_callback) #if defined(CONFIG_PAGING_BINPATH) # error "File system-based paging must always be implemented with blocking calls" -#elif defined(CONFIG_PAGING_M25PX) +#elif defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) # error "SPI FLASH paging must always be implemented with blocking calls" #else # warning "Not implemented" @@ -521,11 +533,11 @@ void weak_function lpc313x_pginitialize(void) * time that up_fillpage() is called. */ -#elif defined(CONFIG_PAGING_M25PX) +#elif defined(CONFIG_PAGING_M25PX) || defined(CONFIG_PAGING_AT45DB) - /* If CONFIG_PAGING_M25PX is defined, use the m25px.c FLASH driver. If this - * is selected, then the MTD interface to the M25Px device will be used to - * support paging. + /* If CONFIG_PAGING_M25PX or CONFIG_PAGING_AT45DB is defined, use the corresponding + * FLASH driver. If either is selected, then the MTD interface to the device + * will be used to support paging. * * If the driver is not configured to use interrupts or DMA, then it is * probably safe to initialize it in this context. diff --git a/nuttx/drivers/mtd/Make.defs b/nuttx/drivers/mtd/Make.defs index 9fb584658..188cdfe1c 100644 --- a/nuttx/drivers/mtd/Make.defs +++ b/nuttx/drivers/mtd/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # drivers/mtd/Make.defs # -# Copyright (C) 2009 Gregory Nutt. All rights reserved. +# Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. # Author: Gregory Nutt <spudmonkey@racsa.co.cr> # # Redistribution and use in source and binary forms, with or without @@ -34,5 +34,5 @@ ############################################################################ MTD_ASRCS = -MTD_CSRCS = ftl.c m25px.c +MTD_CSRCS = ftl.c m25px.c at45db.c diff --git a/nuttx/drivers/mtd/at45db.c b/nuttx/drivers/mtd/at45db.c new file mode 100644 index 000000000..f84db48ad --- /dev/null +++ b/nuttx/drivers/mtd/at45db.c @@ -0,0 +1,779 @@ +/************************************************************************************ + * drivers/mtd/at45db.c + * Driver for SPI-based AT45DB161D (16Mbit) + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* Ordering Code Detail: + * + * AT 45DB 16 1 D – SS U + * | | | | | | `- Device grade + * | | | | | `- Package Option + * | | | | `- Device revision + * | | | `- Interface: 1=serial + * | | `- Capacity: 16=16Mbit + * | `- Product family + * `- Atmel designator + */ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <stdlib.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <nuttx/ioctl.h> +#include <nuttx/spi.h> +#include <nuttx/mtd.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ + +#ifndef CONFIG_AT45DB_FREQUENCY +# define CONFIG_AT45DB_FREQUENCY 1000000 +#endif + +/* SPI Commands *********************************************************************/ + +/* Read commands */ + +#define AT45DB_RDMN 0xd2 /* Main Memory Page Read */ +#define AT45DB_RDARRY 0xe8 /* Continuous Array Read (Legacy Command) */ +#define AT45DB_RDARRAYLF 0x03 /* Continuous Array Read (Low Frequency) */ +#define AT45DB_RDARRAYHF 0x0b /* Continuous Array Read (High Frequency) */ +#define AT45DB_RDBF1LF 0xd1 /* Buffer 1 Read (Low Frequency) */ +#define AT45DB_RDBF2LF 0xd3 /* Buffer 2 Read (Low Frequency) */ +#define AT45DB_RDBF1 0xd4 /* Buffer 1 Read */ +#define AT45DB_RDBF2 0xd6 /* Buffer 2 Read */ + +/* Program and Erase Commands */ + +#define AT45DB_WRBF1 0x84 /* Buffer 1 Write */ +#define AT45DB_WRBF2 0x87 /* Buffer 2 Write */ +#define AT45DB_BF1TOMNE 0x83 /* Buffer 1 to Main Memory Page Program with Built-in Erase */ +#define AT45DB_BF2TOMNE 0x86 /* Buffer 2 to Main Memory Page Program with Built-in Erase */ +#define AT45DB_BF1TOMN 0x88 /* Buffer 1 to Main Memory Page Program without Built-in Erase */ +#define AT45DB_BF2TOMN 0x89 /* Buffer 2 to Main Memory Page Program without Built-in Erase */ +#define AT45DB_PGERASE 0x81 /* Page Erase */ +#define AT45DB_BLKERASE 0x50 /* Block Erase */ +#define AT45DB_SECTERASE 0x7c /* Sector Erase */ +#define AT45DB_CHIPERASE1 0xc7 /* Chip Erase - byte 1 */ +# define AT45DB_CHIPERASE2 0x94 /* Chip Erase - byte 2 */ +# define AT45DB_CHIPERASE3 0x80 /* Chip Erase - byte 3 */ +# define AT45DB_CHIPERASE4 0x9a /* Chip Erase - byte 4 */ +#define AT45DB_MNTHRUBF1 0x82 /* Main Memory Page Program Through Buffer 1 */ +#define AT45DB_MNTHRUBF2 0x85 /* Main Memory Page Program Through Buffer 2 */ + +/* Protection and Security Commands */ + +#define AT45DB_ENABPROT1 0x3d /* Enable Sector Protection - byte 1 */ +# define AT45DB_ENABPROT2 0x2a /* Enable Sector Protection - byte 2 */ +# define AT45DB_ENABPROT3 0x7f /* Enable Sector Protection - byte 3 */ +# define AT45DB_ENABPROT4 0xa9 /* Enable Sector Protection - byte 4 */ +#define AT45DB_DISABPROT1 0x3d /* Disable Sector Protection - byte 1 */ +# define AT45DB_DISABPROT2 0x2a /* Disable Sector Protection - byte 2 */ +# define AT45DB_DISABPROT3 0x7f /* Disable Sector Protection - byte 3 */ +# define AT45DB_DISABPROT4 0x9a /* Disable Sector Protection - byte 4 */ +#define AT45DB_ERASEPROT1 0x3d /* Erase Sector Protection Register - byte 1 */ +# define AT45DB_ERASEPROT2 0x2a /* Erase Sector Protection Register - byte 2 */ +# define AT45DB_ERASEPROT3 0x7f /* Erase Sector Protection Register - byte 3 */ +# define AT45DB_ERASEPROT4 0xcf /* Erase Sector Protection Register - byte 4 */ +#define AT45DB_PROGPROT1 0x3d /* Program Sector Protection Register - byte 1 */ +# define AT45DB_PROGPROT2 0x2a /* Program Sector Protection Register - byte 2 */ +# define AT45DB_PROGPROT3 0x7f /* Program Sector Protection Register - byte 3 */ +# define AT45DB_PROGPROT4 0xfc /* Program Sector Protection Register - byte 4 */ +#define AT45DB_RDPROT 0x32 /* Read Sector Protection Register */ +#define AT45DB_LOCKDOWN1 0x3d /* Sector Lockdown - byte 1 */ +# define AT45DB_LOCKDOWN2 0x2a /* Sector Lockdown - byte 2 */ +# define AT45DB_LOCKDOWN3 0x7f /* Sector Lockdown - byte 3 */ +# define AT45DB_LOCKDOWN4 0x30 /* Sector Lockdown - byte 4 */ +#define AT45DB_RDLOCKDOWN 0x35 /* Read Sector Lockdown Register */ +#define AT45DB_PROGSEC1 0x9b /* Program Security Register - byte 1 */ +# define AT45DB_PROGSEC2 0x00 /* Program Security Register - byte 2 */ +# define AT45DB_PROGSEC3 0x00 /* Program Security Register - byte 3 */ +# define AT45DB_PROGSEC4 0x00 /* Program Security Register - byte 4 */ +#define AT45DB_RDSEC 0x77 /* Read Security Register */ + +/* Additional commands */ + +#define AT45DB_MNTOBF1XFR 0x53 /* Main Memory Page to Buffer 1 Transfer */ +#define AT45DB_MNTOBF2XFR 0x55 /* Main Memory Page to Buffer 2 Transfer */ +#define AT45DB_MNBF1CMP 0x60 /* Main Memory Page to Buffer 1 Compare */ +#define AT45DB_MNBF2CMP 0x61 /* Main Memory Page to Buffer 2 Compare */ +#define AT45DB_AUTOWRBF1 0x58 /* Auto Page Rewrite through Buffer 1 */ +#define AT45DB_AUTOWRBF2 0x59 /* Auto Page Rewrite through Buffer 2 */ +#define AT45DB_PWRDOWN 0xb9 /* Deep Power-down */ +#define AT45DB_RESUME 0xab /* Resume from Deep Power-down */ +#define AT45DB_RDSR 0xd7 /* Status Register Read */ +#define AT45DB_RDDEVID 0x9f /* Manufacturer and Device ID Read */ + +#define AT45DB_MANUFACTURER 0x1f /* Manufacturer ID: Atmel */ +#define AT45DB_DEVID1_CAPMSK 0x1f /* Bits 0-4: Capacity */ +#define AT45DB_DEVID1_16MBIT 0x06 /* xxx0 0110 = 16Mbit */ +#define AT45DB_DEVID1_FAMMSK 0xe0 /* Bits 5-7: Family */ +#define AT45DB_DEVID1_DFLASH 0x20 /* 001x xxxx = Dataflash */ +#define AT45DB_DEVID2_VERMSK 0x1f /* Bits 0-4: MLC mask */ +#define AT45DB_DEVID2_MLCMSK 0xe0 /* Bits 5-7: MLC mask */ + +/* Status register bit definitions */ + +#define AT45DB_SR_RDY (1 << 7) /* Bit 7: RDY/ Not BUSY */ +#define AT45DB_SR_COMP (1 << 6) /* Bit 6: COMP */ +#define AT45DB_SR_PROTECT (1 << 1) /* Bit 1: PROTECT */ +#define AT45DB_SR_PGSIZE (1 << 0) /* Bit 0: PAGE_SIZE */ + +/* 1 Block = 16 pages; 1 sector = 256 pages */ + +#define PG_PER_BLOCK (16) +#define PG_PER_SECTOR (256) + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* This type represents the state of the MTD device. The struct mtd_dev_s + * must appear at the beginning of the definition so that you can freely + * cast between pointers to struct mtd_dev_s and struct at45db_dev_s. + */ + +struct at45db_dev_s +{ + struct mtd_dev_s mtd; /* MTD interface */ + FAR struct spi_dev_s *spi; /* Saved SPI interface instance */ + uint8_t pageshift; /* log2 of the page size (eg. 1 << 9 = 512) */ + uint32_t npages; /* Number of pages in the device */ +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +/* Helpers */ + +static void at45db_lock(struct at45db_dev_s *priv); +static inline void at45db_unlock(struct at45db_dev_s *priv); +static void at45db_pwrdown(struct at45db_dev_s *priv); +static void at45db_resume(struct at45db_dev_s *priv); +static inline int at45db_rdid(struct at45db_dev_s *priv); +static inline uint8_t at45db_rdsr(struct at45db_dev_s *priv); +static uint8_t at45db_waitbusy(struct at45db_dev_s *priv); +static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t offset); +static inline int at32db_chiperase(struct at45db_dev_s *priv); +static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *buffer, + off_t offset); + +/* MTD driver methods */ + +static int at45db_erase(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks); +static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock, + size_t nblocks, FAR uint8_t *buf); +static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock, + size_t nblocks, FAR const uint8_t *buf); +static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbytes, + FAR uint8_t *buffer); +static int at45db_ioctl(FAR struct mtd_dev_s *mtd, int cmd, unsigned long arg); + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* Chip erase sequence */ + +#define CHIP_ERASE_SIZE 4 +static const uint8_t g_chiperase[CHIP_ERASE_SIZE] = {0xc7, 0x94, 0x80, 0x9a}; + +/* Sequence to program the device to 512 page size */ + +#define CFG512_SIZE 4 +static const uint8_t g_cfg512[CFG512_SIZE] = {0x3d, 0x2a, 0x80, 0xa6}; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: at45db_lock + ************************************************************************************/ + +static void at45db_lock(struct at45db_dev_s *priv) +{ + /* On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. + * + * This is a blocking call and will not return until we have exclusiv access to + * the SPI buss. We will retain that exclusive access until the bus is unlocked. + */ + + (void)SPI_LOCK(priv->spi, true); + + /* After locking the SPI bus, the we also need call the setfrequency, setbits, and + * setmode methods to make sure that the SPI is properly configured for the device. + * If the SPI buss is being shared, then it may have been left in an incompatible + * state. + */ + + SPI_SETMODE(priv->spi, SPIDEV_MODE3); + SPI_SETBITS(priv->spi, 8); + (void)SPI_SETFREQUENCY(priv->spi, CONFIG_AT45DB_FREQUENCY); +} + +/************************************************************************************ + * Name: at45db_unlock + ************************************************************************************/ + +static inline void at45db_unlock(struct at45db_dev_s *priv) +{ + (void)SPI_LOCK(priv->spi, false); +} + + +/************************************************************************************ + * Name: at45db_pwrdown + ************************************************************************************/ + +static void at45db_pwrdown(struct at45db_dev_s *priv) +{ + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SEND(priv->spi, AT45DB_PWRDOWN); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); +} + +/************************************************************************************ + * Name: at45db_resume + ************************************************************************************/ + +static void at45db_resume(struct at45db_dev_s *priv) +{ + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SEND(priv->spi, AT45DB_RESUME); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + up_udelay(50); +} + +/************************************************************************************ + * Name: at45db_rdid + ************************************************************************************/ + +static inline int at45db_rdid(struct at45db_dev_s *priv) +{ + uint16_t manufacturer; + uint16_t devid1; + uint16_t devid2; + uint16_t capacity; + + fvdbg("priv: %p\n", priv); + + /* Lock the SPI bus, configure the bus, and select this FLASH part. */ + + at45db_lock(priv); + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + + /* Send the " Manufacturer and Device ID Read" command and read the first three + * ID bytes + */ + + (void)SPI_SEND(priv->spi, AT45DB_RDDEVID); + manufacturer = SPI_SEND(priv->spi, 0xff); + devid1 = SPI_SEND(priv->spi, 0xff); + devid2 = SPI_SEND(priv->spi, 0xff); + + /* Deselect the FLASH and unlock the bus */ + + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + at45db_unlock(priv); + + fvdbg("manufacturer: %02x devid1: %02x devid2: %02x\n", + manufacturer, devid1, devid2); + + /* Check for a valid manufacturer and memory family */ + + if (manufacturer == AT45DB_MANUFACTURER && + (devid1 & AT45DB_DEVID1_FAMMSK) == AT45DB_DEVID1_DFLASH) + { + /* Okay.. is it a FLASH capacity that we understand? */ + + capacity = devid1 & AT45DB_DEVID1_CAPMSK; + + if (capacity == AT45DB_DEVID1_16MBIT) + { + /* Save the FLASH geometry for the 16Mbit AT45DB161 */ + + priv->pageshift = 9; /* Page size = 512 bytes */ + priv->npages = 4096; /* 4096 pages */ + return OK; + } +# if 0 /* Add support for other at45db FLASH parts here */ + else if (capacity == ) + { + /* Save the FLASH geometry */ + + priv->pageshift = ; + priv->npages = ; + return OK; + } +#endif + } + + return -ENODEV; +} + +/************************************************************************************ + * Name: at45db_rdsr + ************************************************************************************/ + +static inline uint8_t at45db_rdsr(struct at45db_dev_s *priv) +{ + uint8_t retval; + + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SEND(priv->spi, AT45DB_RDSR); + retval = SPI_SEND(priv->spi, 0xff); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + return retval; +} + +/************************************************************************************ + * Name: at45db_waitbusy + ************************************************************************************/ + +static uint8_t at45db_waitbusy(struct at45db_dev_s *priv) +{ + uint8_t sr; + + /* Poll the device, waiting for it to report that it is ready */ + + do + { + up_udelay(10); + sr = (uint8_t)at45db_rdsr(priv); + } + while ((sr & AT45DB_SR_RDY) == 0); + return sr; +} + +/************************************************************************************ + * Name: at45db_pgerase + ************************************************************************************/ + +static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector) +{ + uint8_t erasecmd[4]; + off_t offset = sector << priv->pageshift; + + fvdbg("sector: %08lx\n", (long)sector); + + /* The Page Erase command can be used to individually erase any page in the main + * memory array allowing the Buffer to Main Memory Page Program to be utilized at a + * later time. ... To perform a page erase in the binary page size (512 bytes), the + * opcode 81H must be loaded into the device, followed by three address bytes + * consist of 3 don’t care bits, 12 page address bits (A20 - A9) that specify the + * page in the main memory to be erased and 9 don’t care bits. When a low-to-high + * transition occurs on the CS pin, the part will erase the selected page (the + * erased state is a logical 1). ... the status register and the RDY/BUSY pin will + * indicate that the part is busy. + */ + + erasecmd[0] = AT45DB_PGERASE; /* Page erase command */ + erasecmd[1] = (offset >> 16) & 0xff; /* 24-bit offset MS bytes */ + erasecmd[2] = (offset >> 8) & 0xff; /* 24-bit offset middle bytes */ + erasecmd[3] = offset & 0xff; /* 24-bit offset LS bytes */ + + /* Erase the page */ + + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SNDBLOCK(priv->spi, erasecmd, 4); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + + /* Wait for any erase to complete */ + + at45db_waitbusy(priv); + fvdbg("Erased\n"); +} + +/************************************************************************************ + * Name: at32db_chiperase + ************************************************************************************/ + +static inline int at32db_chiperase(struct at45db_dev_s *priv) +{ + fvdbg("priv: %p\n", priv); + + /* "The entire main memory can be erased at one time by using the Chip Erase + * command. To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, + * 80H and 9AH must be clocked into the device. ... After the last bit of the opcode + * sequence has been clocked in, the CS pin can be deasserted to start the erase + * process. ... the Status Register will indicate that the device is busy. The Chip + * Erase command will not affect sectors that are protected or locked down... + */ + + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SNDBLOCK(priv->spi, g_chiperase, CHIP_ERASE_SIZE); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + + /* Wait for any erase to complete */ + + at45db_waitbusy(priv); + return OK; +} + +/************************************************************************************ + * Name: at45db_pgwrite + ************************************************************************************/ + +static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *buffer, + off_t page) +{ + uint8_t wrcmd [4]; + off_t offset = page << priv->pageshift; + + fvdbg("page: %08lx offset: %08lx\n", (long)page, (long)offset); + + /* We assume that sectors are not write protected */ + + wrcmd[0] = AT45DB_MNTHRUBF1; /* To main memory through buffer 1 */ + wrcmd[1] = (offset >> 16) & 0xff; /* 24-bit address MS byte */ + wrcmd[2] = (offset >> 8) & 0xff; /* 24-bit address middle byte */ + wrcmd[3] = offset & 0xff; /* 24-bit address LS byte */ + + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SNDBLOCK(priv->spi, wrcmd, 4); + SPI_SNDBLOCK(priv->spi, buffer, 1 << priv->pageshift); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + + /* Wait for any write to complete */ + + at45db_waitbusy(priv); + fvdbg("Written\n"); +} + +/************************************************************************************ + * Name: at45db_erase + ************************************************************************************/ + +static int at45db_erase(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks) +{ + FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd; + size_t pgsleft = nblocks; + + fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + /* Take the lock so that we have exclusive access to the bus, then power up the + * FLASH device. + */ + + at45db_lock(priv); + at45db_resume(priv); + + /* Then erase each page */ + + while (pgsleft-- > 0) + { + /* Erase each sector */ + + at45db_pgerase(priv, startblock); + startblock++; + } + + at45db_pwrdown(priv); + at45db_unlock(priv); + return (int)nblocks; +} + +/************************************************************************************ + * Name: at45db_bread + ************************************************************************************/ + +static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks, + FAR uint8_t *buffer) +{ + FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd; + ssize_t nbytes; + + /* On this device, we can handle the block read just like the byte-oriented read */ + + nbytes = at45db_read(mtd, startblock << priv->pageshift, nblocks << priv->pageshift, buffer); + if (nbytes > 0) + { + return nbytes >> priv->pageshift; + } + return nbytes; +} + +/************************************************************************************ + * Name: at45db_bwrite + ************************************************************************************/ + +static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks, + FAR const uint8_t *buffer) +{ + FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd; + size_t pgsleft = nblocks; + + fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + /* Take the lock so that we have exclusive access to the bus, then power up the + * FLASH device. + */ + + at45db_lock(priv); + at45db_resume(priv); + + /* Write each page to FLASH */ + + at45db_lock(priv); + while (pgsleft-- > 0) + { + at45db_pgwrite(priv, buffer, startblock); + startblock++; + } + at45db_unlock(priv); + + return nblocks; +} + +/************************************************************************************ + * Name: at45db_read + ************************************************************************************/ + +static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbytes, + FAR uint8_t *buffer) +{ + FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd; + uint8_t rdcmd [5]; + + fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes); + + /* Set up for the read */ + + rdcmd[0] = AT45DB_RDARRAYHF; /* FAST_READ is safe at all supported SPI speeds. */ + rdcmd[1] = (offset >> 16) & 0xff; /* 24-bit address upper byte */ + rdcmd[2] = (offset >> 8) & 0xff; /* 24-bit address middle byte */ + rdcmd[3] = offset & 0xff; /* 24-bit address least significant byte */ + rdcmd[4] = 0; /* Dummy byte */ + + /* Take the lock so that we have exclusive access to the bus, then power up the + * FLASH device. + */ + + at45db_lock(priv); + at45db_resume(priv); + + /* Perform the read */ + + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SNDBLOCK(priv->spi, rdcmd, 5); + SPI_RECVBLOCK(priv->spi, buffer, nbytes); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + + at45db_pwrdown(priv); + at45db_unlock(priv); + fvdbg("return nbytes: %d\n", (int)nbytes); + return nbytes; +} + +/************************************************************************************ + * Name: at45db_ioctl + ************************************************************************************/ + +static int at45db_ioctl(FAR struct mtd_dev_s *mtd, int cmd, unsigned long arg) +{ + FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd; + int ret = -EINVAL; /* Assume good command with bad parameters */ + + fvdbg("cmd: %d \n", cmd); + + switch (cmd) + { + case MTDIOC_GEOMETRY: + { + FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg); + if (geo) + { + /* Populate the geometry structure with information need to know + * the capacity and how to access the device. + * + * NOTE: that the device is treated as though it where just an array + * of fixed size blocks. That is most likely not true, but the client + * will expect the device logic to do whatever is necessary to make it + * appear so. + */ + + geo->blocksize = (1 << priv->pageshift); + geo->erasesize = geo->blocksize; + geo->neraseblocks = priv->npages; + ret = OK; + + fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n", + geo->blocksize, geo->erasesize, geo->neraseblocks); + } + } + break; + + case MTDIOC_BULKERASE: + { + /* Take the lock so that we have exclusive access to the bus, then + * power up the FLASH device. + */ + + at45db_lock(priv); + at45db_resume(priv); + + /* Erase the entire device */ + + ret = at32db_chiperase(priv); + at45db_pwrdown(priv); + at45db_unlock(priv); + } + break; + + case MTDIOC_XIPBASE: + default: + ret = -ENOTTY; /* Bad command */ + break; + } + + fvdbg("return %d\n", ret); + return ret; +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: at45db_initialize + * + * Description: + * Create an initialize MTD device instance. MTD devices are not registered + * in the file system, but are created as instances that can be bound to + * other functions (such as a block or character driver front end). + * + ************************************************************************************/ + +FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *spi) +{ + FAR struct at45db_dev_s *priv; + uint8_t sr; + int ret; + + fvdbg("spi: %p\n", spi); + + /* Allocate a state structure (we allocate the structure instead of using + * a fixed, static allocation so that we can handle multiple FLASH devices. + * The current implementation would handle only one FLASH part per SPI + * device (only because of the SPIDEV_FLASH definition) and so would have + * to be extended to handle multiple FLASH parts on the same SPI bus. + */ + + priv = (FAR struct at45db_dev_s *)malloc(sizeof(struct at45db_dev_s)); + if (priv) + { + /* Initialize the allocated structure */ + + priv->mtd.erase = at45db_erase; + priv->mtd.bread = at45db_bread; + priv->mtd.bwrite = at45db_bwrite; + priv->mtd.read = at45db_read; + priv->mtd.ioctl = at45db_ioctl; + priv->spi = spi; + + /* Deselect the FLASH */ + + SPI_SELECT(spi, SPIDEV_FLASH, false); + + /* Lock and configure the SPI bus. */ + + at45db_lock(priv); + + /* Identify the FLASH chip and get its capacity */ + + at45db_resume(priv); + ret = at45db_rdid(priv); + if (ret != OK) + { + /* Unrecognized! Discard all of that work we just did and return NULL */ + + fdbg("Unrecognized\n"); + goto errout; + } + + /* Get the value of the status register (as soon as the device is ready) */ + + sr = at45db_waitbusy(priv); + + /* Check if the device is configured as 512 page device */ + + if ((sr & AT45DB_SR_PGSIZE) == 0) + { + /* No, re-program it for 512 byte pages. NOTE: A power cycle + * is required after the device has be re-programmed. + */ + + fdbg("Reprogramming page size\n"); + SPI_SELECT(priv->spi, SPIDEV_FLASH, true); + SPI_SNDBLOCK(priv->spi, g_cfg512, CFG512_SIZE); + SPI_SELECT(priv->spi, SPIDEV_FLASH, false); + goto errout; + } + + /* Release the lock and power down the device */ + + at45db_pwrdown(priv); + at45db_unlock(priv); + } + + fvdbg("Return %p\n", priv); + return (FAR struct mtd_dev_s *)priv; + +/* On any failure, we need free memory allocations and release the lock that + * we hold on the SPI bus. On failures, assume that we cannot talk to the + * device to do any more. + */ + +errout: + at45db_unlock(priv); + free(priv); + return NULL; +} diff --git a/nuttx/include/nuttx/mtd.h b/nuttx/include/nuttx/mtd.h index c8e6f1fdc..d9beb082c 100644 --- a/nuttx/include/nuttx/mtd.h +++ b/nuttx/include/nuttx/mtd.h @@ -2,7 +2,7 @@ * include/nuttx/mtd.h * Memory Technology Device (MTD) interface * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -154,6 +154,18 @@ EXTERN int ftl_initialize(int minor, uint8_t *buffer, FAR struct mtd_dev_s *mtd) EXTERN FAR struct mtd_dev_s *m25p_initialize(FAR struct spi_dev_s *dev); +/************************************************************************************ + * Name: at45db_initialize + * + * Description: + * Create an initialize MTD device instance. MTD devices are not registered + * in the file system, but are created as instances that can be bound to + * other functions (such as a block or character driver front end). + * + ************************************************************************************/ + +EXTERN FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *dev); + #undef EXTERN #ifdef __cplusplus } |