Add mpmc initialization

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2459 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 284 insertions, 195 deletions

diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h b/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
index c2b8e12a1..ffd2899d2 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
@@ -213,157 +213,157 @@
 /* SYSCREG register (virtual) addresses *****************************************************************/
 /* Miscellaneous system configuration registers, part1 */
 
-define LPC313X_SYSCREG_EBIMPMCPRIO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIMPMCPRIO_OFFSET)
-define LPC313X_SYSCREG_EBNANDCPRIO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBNANDCPRIO_OFFSET)
-define LPC313X_SYSCREG_EBIUNUSEDPRIO             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIUNUSEDPRIO_OFFSET)
-define LPC313X_SYSCREG_RINGOSCCFG                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_RINGOSCCFG_OFFSET)
-define LPC313X_SYSCREG_ADCPDADC10BITS            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ADCPDADC10BITS_OFFSET)
-define LPC313X_SYSCREG_ABCCFG                    (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ABCCFG_OFFSET)
-define LPC313X_SYSCREG_SDMMCCFG                  (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_SDMMCCFG_OFFSET)
-define LPC313X_SYSCREG_MCIDELAYMODES             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MCIDELAYMODES_OFFSET)
+#define LPC313X_SYSCREG_EBIMPMCPRIO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIMPMCPRIO_OFFSET)
+#define LPC313X_SYSCREG_EBNANDCPRIO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBNANDCPRIO_OFFSET)
+#define LPC313X_SYSCREG_EBIUNUSEDPRIO            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIUNUSEDPRIO_OFFSET)
+#define LPC313X_SYSCREG_RINGOSCCFG               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_RINGOSCCFG_OFFSET)
+#define LPC313X_SYSCREG_ADCPDADC10BITS           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ADCPDADC10BITS_OFFSET)
+#define LPC313X_SYSCREG_ABCCFG                   (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ABCCFG_OFFSET)
+#define LPC313X_SYSCREG_SDMMCCFG                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_SDMMCCFG_OFFSET)
+#define LPC313X_SYSCREG_MCIDELAYMODES            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MCIDELAYMODES_OFFSET)
 
 /* USB configuration registers */
 
-define LPC313X_SYSCREG_USB_ATXPLLPDREG           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_ATXPLLPDREG_OFFSET)
-define LPC313X_SYSCREG_USB_OTGCFG                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGCFG_OFFSET)
-define LPC313X_SYSCREG_USB_OTGPORTINDCTL         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGPORTINDCTL_OFFSET)
-define LPC313X_SYSCREG_USB_PLLNDEC               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLNDEC_OFFSET)
-define LPC313X_SYSCREG_USB_PLLMDEC               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLMDEC_OFFSET)
-define LPC313X_SYSCREG_USB_PLLPDEC               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLPDEC_OFFSET)
-define LPC313X_SYSCREG_USB_PLLSELR               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELR_OFFSET)
-define LPC313X_SYSCREG_USB_PLLSELI               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELI_OFFSET)
-define LPC313X_SYSCREG_USB_PLLSELP               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELP_OFFSET)
+#define LPC313X_SYSCREG_USB_ATXPLLPDREG          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_ATXPLLPDREG_OFFSET)
+#define LPC313X_SYSCREG_USB_OTGCFG               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGCFG_OFFSET)
+#define LPC313X_SYSCREG_USB_OTGPORTINDCTL        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGPORTINDCTL_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLNDEC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLNDEC_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLMDEC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLMDEC_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLPDEC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLPDEC_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLSELR              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELR_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLSELI              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELI_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLSELP              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELP_OFFSET)
 
 /* ISRAM/ISROM configuration registers */
 
-define LPC313X_SYSCREG_ISRAM0_LATENCYCFG         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM0_LATENCYCFG_OFFSET)
-define LPC313X_SYSCREG_ISRAM1_LATENCYCFG         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM1_LATENCYCFG_OFFSET)
-define LPC313X_SYSCREG_ISROM_LATENCYCFG          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISROM_LATENCYCFG_OFFSET)
+#define LPC313X_SYSCREG_ISRAM0_LATENCYCFG        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM0_LATENCYCFG_OFFSET)
+#define LPC313X_SYSCREG_ISRAM1_LATENCYCFG        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM1_LATENCYCFG_OFFSET)
+#define LPC313X_SYSCREG_ISROM_LATENCYCFG         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISROM_LATENCYCFG_OFFSET)
 
 /* MPMC configuration registers */
 
-define LPC313X_SYSCREG_MPMC_AHBMISC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_AHBMISC_OFFSET)
-define LPC313X_SYSCREG_MPMC_DELAYMODES           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_DELAYMODES_OFFSET)
-define LPC313X_SYSCREG_MPMC_WAITRD0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD0_OFFSET)
-define LPC313X_SYSCREG_MPMC_WAITRD1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD1_OFFSET)
-define LPC313X_SYSCREG_MPMC_WIREEBIMSZ           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WIREEBIMSZ_OFFSET)
-define LPC313X_SYSCREG_MPMC_TESTMODE0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE0_OFFSET)
-define LPC313X_SYSCREG_MPMC_TESTMODE1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE1_OFFSET)
+#define LPC313X_SYSCREG_MPMC_AHBMISC             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_AHBMISC_OFFSET)
+#define LPC313X_SYSCREG_MPMC_DELAYMODES          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_DELAYMODES_OFFSET)
+#define LPC313X_SYSCREG_MPMC_WAITRD0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD0_OFFSET)
+#define LPC313X_SYSCREG_MPMC_WAITRD1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD1_OFFSET)
+#define LPC313X_SYSCREG_MPMC_WIREEBIMSZ          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WIREEBIMSZ_OFFSET)
+#define LPC313X_SYSCREG_MPMC_TESTMODE0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE0_OFFSET)
+#define LPC313X_SYSCREG_MPMC_TESTMODE1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE1_OFFSET)
 
 /* Miscellaneous system configuration registers, part 2 */
 
-define LPC313X_SYSCREG_AHB0EXTPRIO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_AHB0EXTPRIO_OFFSET)
-define LPC313X_SYSCREG_ARM926SHADOWPTR           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ARM926SHADOWPTR_OFFSET)
+#define LPC313X_SYSCREG_AHB0EXTPRIO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_AHB0EXTPRIO_OFFSET)
+#define LPC313X_SYSCREG_ARM926SHADOWPTR          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ARM926SHADOWPTR_OFFSET)
 
 /* Pin multiplexing control registers */
 
-define LPC313X_SYSCREG_MUX_LCDEBISEL             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_LCDEBISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_GPIOMCISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_GPIOMCISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_NANDMCISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_NANDMCISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_UARTSPISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_UARTSPISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_I2STXPCMSEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_I2STXPCMSEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_LCDEBISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_LCDEBISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_GPIOMCISEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_GPIOMCISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_NANDMCISEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_NANDMCISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_UARTSPISEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_UARTSPISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_I2STXPCMSEL          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_I2STXPCMSEL_OFFSET)
 
 /* Pad configuration registers */
 
-define LPC313X_SYSCREG_PAD_EBID9                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID9_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID10                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID10_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID11                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID11_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID12                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID12_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID13                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID13_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID14                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID14_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXBCK0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK0_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO9                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO9_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO6                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO6_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB7               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB7_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB4               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB4_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB2               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB2_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN0_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO1                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO1_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID4                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID4_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXCLK0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXCLK0_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXBCK0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXBCK0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBIA1CLE              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA1CLE_OFFSET)
-define LPC313X_SYSCREG_PAD_EBINCASBLOUT0         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINCASBLOUT0_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS3              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS3_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB0               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBIDQM0NOE            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIDQM0NOE_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID0                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID1                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID1_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID2                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID2_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID3                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID3_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID5                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID5_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID6                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID6_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID7                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID7_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID8                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID8_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID15                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID15_OFFSET)
-define LPC313X_SYSCREG_PAD_I2STXDATA1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXDATA1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2STXBCK1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXBCK1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2STXWS1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXWS1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXDATA0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA0_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXWS0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS0_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXDATA1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXBCK1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXWS1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS1_OFFSET)
-define LPC313X_SYSCREG_PAD_SYSCLKO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SYSCLKO_OFFSET)
-define LPC313X_SYSCREG_PAD_PWMDATA               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_PWMDATA_OFFSET)
-define LPC313X_SYSCREG_PAD_UARTRXD               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTRXD_OFFSET)
-define LPC313X_SYSCREG_PAD_UARTTXD               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTTXD_OFFSET)
-define LPC313X_SYSCREG_PAD_I2CSDA1               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSDA1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2CSCL1               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSCL1_OFFSET)
-define LPC313X_SYSCREG_PAD_CLK256FSO             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_CLK256FSO_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO0                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO0_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO2                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO2_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO3                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO3_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO4                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO4_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO11                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO11_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO12                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO12_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO13                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO13_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO14                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO14_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO15                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO15_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO16                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO16_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO17                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO17_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO18                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO18_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO19                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO19_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO20                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO20_OFFSET)
-define LPC313X_SYSCREG_PAD_SPIMISO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMISO_OFFSET)
-define LPC313X_SYSCREG_PAD_SPIMOSI               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMOSI_OFFSET)
-define LPC313X_SYSCREG_PAD_SPICSIN               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSIN_OFFSET)
-define LPC313X_SYSCREG_PAD_SPISCK                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPISCK_OFFSET)
-define LPC313X_SYSCREG_PAD_SPICSOUT0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSOUT0_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS0_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS1_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS2              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS2_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDCSB               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDCSB_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB1               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB1_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDERD               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDERD_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDRS                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRS_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDRWWR              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRWWR_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB3               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB3_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB5               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB5_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB6               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB6_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB8               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB8_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB9               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB9_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB10              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB10_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB11              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB11_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB12              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB12_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB13              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB13_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB14              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB14_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB15              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB15_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO5                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO5_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO7                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO7_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO8                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO8_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO10               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO10_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN1_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN2            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN2_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN3            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN3_OFFSET)
-define LPC313X_SYSCREG_PAD_MUARTCTSN             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MUARTCTSN_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXDATA0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXDATA0_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXWS0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXWS0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBINRASBLOUT1         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINRASBLOUT1_OFFSET)
-define LPC313X_SYSCREG_PAD_EBIA0ALE              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA0ALE_OFFSET)
-define LPC313X_SYSCREG_PAD_EBINWE                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINWE_OFFSET)
-define LPC313X_SYSCREG_PAD_ESHCTRLSUP4           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP4_OFFSET)
-define LPC313X_SYSCREG_PAD_ESHCTRLSUP8           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP8_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID9                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID9_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID10               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID10_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID11               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID11_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID12               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID12_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID13               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID13_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID14               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID14_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXBCK0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK0_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO9               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO9_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO6               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO6_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB7              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB7_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB4              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB4_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB2              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB2_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN0_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO1                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO1_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID4                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID4_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXCLK0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXCLK0_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXBCK0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXBCK0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBIA1CLE             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA1CLE_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBINCASBLOUT0        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINCASBLOUT0_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS3             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS3_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBIDQM0NOE           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIDQM0NOE_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID0                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID1                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID1_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID2                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID2_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID3                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID3_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID5                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID5_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID6                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID6_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID7                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID7_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID8                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID8_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID15               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID15_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2STXDATA1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXDATA1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2STXBCK1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXBCK1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2STXWS1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXWS1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXDATA0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA0_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXWS0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS0_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXDATA1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXBCK1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXWS1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS1_OFFSET)
+#define LPC313X_SYSCREG_PAD_SYSCLKO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SYSCLKO_OFFSET)
+#define LPC313X_SYSCREG_PAD_PWMDATA              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_PWMDATA_OFFSET)
+#define LPC313X_SYSCREG_PAD_UARTRXD              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTRXD_OFFSET)
+#define LPC313X_SYSCREG_PAD_UARTTXD              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTTXD_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2CSDA1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSDA1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2CSCL1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSCL1_OFFSET)
+#define LPC313X_SYSCREG_PAD_CLK256FSO            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_CLK256FSO_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO0                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO0_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO2                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO2_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO3                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO3_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO4                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO4_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO11               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO11_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO12               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO12_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO13               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO13_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO14               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO14_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO15               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO15_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO16               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO16_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO17               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO17_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO18               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO18_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO19               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO19_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO20               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO20_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPIMISO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMISO_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPIMOSI              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMOSI_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPICSIN              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSIN_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPISCK               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPISCK_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPICSOUT0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSOUT0_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS0_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS1_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS2             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS2_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDCSB              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDCSB_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB1_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDERD              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDERD_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDRS               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRS_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDRWWR             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRWWR_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB3              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB3_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB5              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB5_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB6              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB6_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB8              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB8_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB9              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB9_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB10             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB10_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB11             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB11_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB12             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB12_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB13             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB13_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB14             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB14_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB15             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB15_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO5               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO5_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO7               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO7_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO8               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO8_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO10              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO10_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN1_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN2           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN2_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN3           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN3_OFFSET)
+#define LPC313X_SYSCREG_PAD_MUARTCTSN            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MUARTCTSN_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXDATA0          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXDATA0_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXWS0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXWS0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBINRASBLOUT1        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINRASBLOUT1_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBIA0ALE             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA0ALE_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBINWE               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINWE_OFFSET)
+#define LPC313X_SYSCREG_PAD_ESHCTRLSUP4          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP4_OFFSET)
+#define LPC313X_SYSCREG_PAD_ESHCTRLSUP8          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP8_OFFSET)
 
 /* SYSCREG register bit definitions *********************************************************************/
 /* Miscellaneous system configuration registers, part1 */
@@ -409,14 +409,14 @@ define LPC313X_SYSCREG_PAD_ESHCTRLSUP8           (LPC313X_SYSCREG_VBASE+LPC313X_
 #  define SYSCREG_ABCCFG_ARM926EJSI_EXT32        (7 << SYSCREG_ABCCFG_ARM926EJSI_SHIFT) /* extend to 32-beat */
 #define SYSCREG_ABCCFG_ARM926EJSD_SHIFT          (3)       /* Bits 3-5: ARM926EJS data AHB bus bandwidth control */
 #define SYSCREG_ABCCFG_ARM926EJSD_MASK           (7 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT)
-#  define SYSCREG_ABCCFG_ARM926EJSI_NORMAL       (0 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Normal mode */
-#  define SYSCREG_ABCCFG_ARM926EJSI_NONSEQ       (1 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Make non-sequential */
-#  define SYSCREG_ABCCFG_ARM926EJSI_SPLIT4       (2 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_SPLIT8       (3 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 8-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_EXT8         (4 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 8-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_EXT16        (5 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 16-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_SPLIT4W      (6 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_EXT32        (7 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* extend to 32-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_NORMAL       (0 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Normal mode */
+#  define SYSCREG_ABCCFG_ARM926EJSD_NONSEQ       (1 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Make non-sequential */
+#  define SYSCREG_ABCCFG_ARM926EJSD_SPLIT4       (2 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_SPLIT8       (3 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 8-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_EXT8         (4 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 8-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_EXT16        (5 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 16-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_SPLIT4W      (6 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_EXT32        (7 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* extend to 32-beat */
 #define SYSCREG_ABCCFG_DMA_SHIFT                 (0)       /* Bits 0-2: 2:0 DMA AHB bus bandwidth control */
 #define SYSCREG_ABCCFG_DMA_MASK                  (7 << SYSCREG_ABCCFG_DMA_SHIFT)
 #  define SYSCREG_ABCCFG_DMA_NORMAL              (0 << SYSCREG_ABCCFG_DMA_SHIFT)        /* Normal mode */
diff --git a/nuttx/configs/ea3131/src/Makefile b/nuttx/configs/ea3131/src/Makefile
index 410597cb9..49b0126df 100755
--- a/nuttx/configs/ea3131/src/Makefile
+++ b/nuttx/configs/ea3131/src/Makefile
@@ -40,7 +40,7 @@ CFLAGS		+= -I$(TOPDIR)/sched
 ASRCS		= 
 AOBJS		= $(ASRCS:.S=$(OBJEXT))
 
-CSRCS		= up_boot.c up_buttons.c up_leds.c up_sdram.c up_spi.c
+CSRCS		= up_boot.c up_buttons.c up_leds.c up_mem.c up_spi.c
 ifeq ($(CONFIG_EXAMPLES_NSH_ARCHINIT),y)
 CSRCS		+= up_nsh.c
 endif
diff --git a/nuttx/configs/ea3131/src/ea3131_internal.h b/nuttx/configs/ea3131/src/ea3131_internal.h
index 36b83ea14..58fef3f06 100755
--- a/nuttx/configs/ea3131/src/ea3131_internal.h
+++ b/nuttx/configs/ea3131/src/ea3131_internal.h
@@ -74,16 +74,16 @@
  * Public Functions

  ************************************************************************************/

 

-/****************************************************************************

- * Name: lpc313x_sdraminitialize

+/************************************************************************************

+ * Name: lpc313x_meminitialize

  *

  * Description:

- *   Configure Micron MT48LC32M16A2 SDRAM on the EA3131 board

+ *   Initialize external memory resources

  *

- ****************************************************************************/

+ ************************************************************************************/

 

 #ifdef CONFIG_LPC313X_EXTSDRAM

-extern void lpc313x_sdraminitialize(void);

+extern void lpc313x_meminitialize(void);

 #endif

 

 /************************************************************************************

diff --git a/nuttx/configs/ea3131/src/up_boot.c b/nuttx/configs/ea3131/src/up_boot.c
index 5e2e44751..fc37a7ea9 100755
--- a/nuttx/configs/ea3131/src/up_boot.c
+++ b/nuttx/configs/ea3131/src/up_boot.c
@@ -73,10 +73,10 @@
 

 void lpc313x_boardinitialize(void)

 {

-  /* Configure Micron MT48LC32M16A2 SDRAM on the EA3131 board */

+  /* Initialize configured, external memory resources */

 

 #ifdef CONFIG_LPC313X_EXTSDRAM

-  lpc313x_sdraminitialize();

+  lpc313x_meminitialize();

 #endif

 

   /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function

diff --git a/nuttx/configs/ea3131/src/up_sdram.c b/nuttx/configs/ea3131/src/up_mem.c
index 3206cf6c3..899e3d684 100755
--- a/nuttx/configs/ea3131/src/up_sdram.c
+++ b/nuttx/configs/ea3131/src/up_mem.c
@@ -1,11 +1,12 @@
 /****************************************************************************
- * configs/ea3131/src/up_sdram.c
- * arch/arm/src/board/up_sdram.c
+ * configs/ea3131/src/up_mem.c
+ * arch/arm/src/board/up_mem.c
  *
  *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * References:
+ *   - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
  *   - NXP lpc313x.cdl.drivers.zip example driver code
  *
  * Redistribution and use in source and binary forms, with or without
@@ -44,36 +45,31 @@
 #include <nuttx/config.h>
 
 #include <stdint.h>
+#include <stdbool.h>
 #include <debug.h>
 
 #include <nuttx/arch.h>
+#include <arch/board/board.h>
 
 #include "chip.h"
 #include "up_arch.h"
 
-#include "lpc313x_mpmc.h"
+#include "lpc313x_syscreg.h"
 #include "lpc313x_cgudrvr.h"
+#include "lpc313x_mpmc.h"
 #include "ea3131_internal.h"
 
 #ifdef CONFIG_LPC313X_EXTSDRAM
 
 /****************************************************************************
- * Definitions
+ * Pre-processor Definitions
  ****************************************************************************/
 
-/* Enables debug output from this file (needs CONFIG_DEBUG with
- * CONFIG_DEBUG_VERBOSE too)
+/* The MPMC delay based on trace lengths between SDRAM and the chip and on
+ * the delay strategy used for SDRAM.
  */
 
-#undef SDRAM_DEBUG  /* Define to enable debug */
-
-#ifdef SDRAM_DEBUG
-#  define sdramdbg  lldbg
-#  define sdramvdbg llvdbg
-#else
-#  define sdramdbg(x...)
-#  define sdramvdbg(x...)
-#endif
+#define EA3131_MPMC_DELAY           0x824
 
 /*Delay constants in nanosecondss for MT48LC32M16LF SDRAM on board */
 
@@ -107,10 +103,6 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
  * Name: lpc313x_sdraminitialize
  *
  * Description:
@@ -163,7 +155,7 @@
  *
  ****************************************************************************/
 
-void lpc313x_sdraminitialize(void)
+static void lpc313x_sdraminitialize(void)
 {
   uint32_t tmp;
   uint32_t regval;
@@ -179,7 +171,7 @@ void lpc313x_sdraminitialize(void)
 # define HCLK hclk
 #endif
 
-  /* Check RTL for divide by 2 possible. If so change then enable the following logic */
+  /* Check RTL for divide by 2 possible. If so change then enable the followng logic */
 #if 0
   uint32_t hclk2 = hclk;
 
@@ -199,27 +191,41 @@ void lpc313x_sdraminitialize(void)
 
   /* Configure device config register nSDCE0 for proper width SDRAM */
 
-  putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16), LPC313X_MPMC_DYNCONFIG0);
-  putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK), LPC313X_MPMC_DYNRASCAS0);
+  putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16),
+           LPC313X_MPMC_DYNCONFIG0);
+  putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK),
+           LPC313X_MPMC_DYNRASCAS0);
 
   /* Min 20ns program 1 so that at least 2 HCLKs are used */
 
-  putreg32(NS2HCLKS(EA3131_SDRAM_TRP,  HCLK2, MPMC_DYNTRP_MASK),   LPC313X_MPMC_DYNTRP);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TRAS, HCLK2, MPMC_DYNTRAS_MASK),  LPC313X_MPMC_DYNTRAS);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TREX, HCLK2, MPMC_DYNTSREX_MASK), LPC313X_MPMC_DYNTSREX);
-  putreg32(EA3131_SDRAM_TARP,                                      LPC313X_MPMC_DYNTAPR);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TDAL, HCLK2, MPMC_DYNTDAL_MASK),  LPC313X_MPMC_DYNTDAL);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TWR,  HCLK2, MPMC_DYNTWR_MASK),   LPC313X_MPMC_DYNTWR);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TRC,  HCLK2, MPMC_DYNTRC_MASK),   LPC313X_MPMC_DYNTRC);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TRFC, HCLK2, MPMC_DYNTRFC_MASK),  LPC313X_MPMC_DYNTRFC);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TXSR, HCLK2, MPMC_DYNTXSR_MASK),  LPC313X_MPMC_DYNTXSR);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TRRD, HCLK2, MPMC_DYNTRRD_MASK),  LPC313X_MPMC_DYNTRRD);
-  putreg32(NS2HCLKS(EA3131_SDRAM_TMRD, HCLK2, MPMC_DYNTMRD_MASK),  LPC313X_MPMC_DYNTMRD);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TRP,  HCLK2, MPMC_DYNTRP_MASK),
+           LPC313X_MPMC_DYNTRP);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TRAS, HCLK2, MPMC_DYNTRAS_MASK),
+           LPC313X_MPMC_DYNTRAS);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TREX, HCLK2, MPMC_DYNTSREX_MASK),
+           LPC313X_MPMC_DYNTSREX);
+  putreg32(EA3131_SDRAM_TARP,
+           LPC313X_MPMC_DYNTAPR);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TDAL, HCLK2, MPMC_DYNTDAL_MASK),
+           LPC313X_MPMC_DYNTDAL);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TWR,  HCLK2, MPMC_DYNTWR_MASK),
+           LPC313X_MPMC_DYNTWR);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TRC,  HCLK2, MPMC_DYNTRC_MASK),
+           LPC313X_MPMC_DYNTRC);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TRFC, HCLK2, MPMC_DYNTRFC_MASK),
+           LPC313X_MPMC_DYNTRFC);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TXSR, HCLK2, MPMC_DYNTXSR_MASK),
+           LPC313X_MPMC_DYNTXSR);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TRRD, HCLK2, MPMC_DYNTRRD_MASK),
+           LPC313X_MPMC_DYNTRRD);
+  putreg32(NS2HCLKS(EA3131_SDRAM_TMRD, HCLK2, MPMC_DYNTMRD_MASK),
+           LPC313X_MPMC_DYNTMRD);
   up_udelay(100);
   
   /* Issue continuous NOP commands  */
 
-  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INOP), LPC313X_MPMC_DYNCONTROL);
+  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INOP),
+           LPC313X_MPMC_DYNCONTROL);
 
   /* Load ~200us delay value to timer1 */
 
@@ -227,37 +233,50 @@ void lpc313x_sdraminitialize(void)
   
   /* Issue a "pre-charge all" command */
 
-  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IPALL), LPC313X_MPMC_DYNCONTROL);
+  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IPALL),
+           LPC313X_MPMC_DYNCONTROL);
 
-  /* Minimum refresh pulse interval (tRFC) for MT48LC32M16A2=80nsec, 100nsec provides more than adequate interval.
+  /* Minimum refresh pulse interval (tRFC) for MT48LC32M16A2=80nsec,
+   * 100nsec provides more than adequate interval.
    */
 
-  putreg32(NS2HCLKS(EA3131_SDRAM_REFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK), LPC313X_MPMC_DYNREFRESH);
+  putreg32(NS2HCLKS(EA3131_SDRAM_REFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK),
+           LPC313X_MPMC_DYNREFRESH);
 
   /* Load ~250us delay value to timer1 */
 
   up_udelay(250);
   
-  /* Recommended refresh interval for normal operation of the Micron MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) = refresh counter interval rate, (subtract one for safety margin).
+  /* Recommended refresh interval for normal operation of the Micron
+   * MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) =
+    * refresh counter interval rate, (subtract one for safety margin).
    */
 
-  putreg32(NS2HCLKS(EA3131_SDRAM_OPERREFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK), LPC313X_MPMC_DYNREFRESH);
+  putreg32(NS2HCLKS(EA3131_SDRAM_OPERREFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK),
+           LPC313X_MPMC_DYNREFRESH);
 
   /* Select mode register update mode */
 
-  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IMODE), LPC313X_MPMC_DYNCONTROL);
+  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IMODE),
+           LPC313X_MPMC_DYNCONTROL);
 
-  /* Program the SDRAM internal mode registers on bank nSDCE0 and reconfigure the SDRAM chips.  Bus speeds up to 90MHz requires use of a CAS latency = 2. To get correct value on address bus CAS cycle, requires a shift by 13 for 16bit mode
+  /* Program the SDRAM internal mode registers on bank nSDCE0 and reconfigure
+   * the SDRAM chips.  Bus speeds up to 90MHz requires use of a CAS latency = 2.
+   * To get correct value on address bus CAS cycle, requires a shift by 13 for
+   * 16bit mode
    */
 
   tmp = getreg32(LPC313X_EXTSDRAM0_VSECTION | (0x23 << 13));
   
-  putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16), LPC313X_MPMC_DYNCONFIG0);
-  putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK), LPC313X_MPMC_DYNRASCAS0);
+  putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16),
+           LPC313X_MPMC_DYNCONFIG0);
+  putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK),
+           LPC313X_MPMC_DYNRASCAS0);
 
   /* Select normal operating mode */
 
-  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INORMAL), LPC313X_MPMC_DYNCONTROL);
+  putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INORMAL),
+           LPC313X_MPMC_DYNCONTROL);
 
   /* Enable buffers */
 
@@ -265,6 +284,76 @@ void lpc313x_sdraminitialize(void)
   regval |= MPMC_DYNCONFIG0_B;
   putreg32(regval, LPC313X_MPMC_DYNCONFIG0);
 
-  putreg32((MPMC_DYNCONTROL_INORMAL|MPMC_DYNCONTROL_CS), LPC313X_MPMC_DYNCONTROL);
+  putreg32((MPMC_DYNCONTROL_INORMAL|MPMC_DYNCONTROL_CS),
+           LPC313X_MPMC_DYNCONTROL);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc313x_meminitialize
+ *
+ * Description:
+ *   Initialize memory
+ *
+ ****************************************************************************/
+
+void lpc313x_meminitialize(void)
+{
+  /* Configure the LCD pins in external bus interface (EBI/MPMC) memory mode.
+   * 
+   * LCD_CSB   -> MPMC_NSTCS_0
+   * LCD_DB_1  -> MPMC_NSTCS_1
+   * LCD_DB_0  -> MPMC_CLKOUT
+   * LCD_E_RD  -> MPMC_CKE
+   * LCD_RS    -> MPMC_NDYCS
+   * LCD_RW_WR -> MPMC_DQM_1
+   * LCD_DB_2  -> EBI_A_2
+   * LCD_DB_3  -> EBI_A_3 l
+   * LCD_DB_4  -> EBI_A_4 l
+   * LCD_DB_5  -> EBI_A_5 l
+   * LCD_DB_6  -> EBI_A_6
+   * LCD_DB_7  -> EBI_A_7
+   * LCD_DB_8  -> EBI_A_8
+   * LCD_DB_9  -> EBI_A_9
+   * LCD_DB_10 -> EBI_A_10
+   * LCD_DB_11 -> EBI_A_11
+   * LCD_DB_12 -> EBI_A_12
+   * LCD_DB_13 -> EBI_A_13
+   * LCD_DB_14 -> EBI_A_14
+   * LCD_DB_15 -> EBI_A_15
+   */
+
+  putreg32(SYSCREG_MUX_LCDEBISEL_EBIMPMC, LPC313X_SYSCREG_MUX_LCDEBISEL);
+
+  /* Enable EBI clock */
+
+  lpc313x_enableclock(CLKID_EBICLK);
+  
+  /* Enable MPMC controller clocks */
+
+  lpc313x_enableclock(CLKID_MPMCCFGCLK);
+  lpc313x_enableclock(CLKID_MPMCCFGCLK2);
+  lpc313x_enableclock(CLKID_MPMCCFGCLK3);
+
+  /* Enable the external memory controller */
+
+  putreg32(MPMC_CONTROL_E, LPC313X_MPMC_CONTROL);
+
+  /* Force HCLK to MPMC_CLK to 1:1 ratio, little-endian mode */
+
+  putreg32(0, LPC313X_MPMC_CONFIG);
+
+  /* Set MPMC delay based on trace lengths between SDRAM and the chip
+   * and on the delay strategy used for SDRAM.
+   */
+
+  putreg32(EA3131_MPMC_DELAY, LPC313X_SYSCREG_MPMC_DELAYMODES);
+  
+  /* Configure Micron MT48LC32M16A2 SDRAM on the EA3131 board */
+
+  lpc313x_sdraminitialize();
 }
 #endif /* CONFIG_LPC313X_EXTSDRAM */