diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-03-08 23:05:03 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-03-08 23:05:03 +0000 |
| commit | 75d794ffc49c837547489255f8f0f5d79ec84498 (patch) | |
| tree | 2b09280a26d4fdaecc9e9cf51ae9740491e50c00 | |
| parent | 6d8de0bdc5d9d895f7d65565bdb81f1b313655b0 (diff) | |
| download | px4-nuttx-75d794ffc49c837547489255f8f0f5d79ec84498.tar.gz px4-nuttx-75d794ffc49c837547489255f8f0f5d79ec84498.tar.bz2 px4-nuttx-75d794ffc49c837547489255f8f0f5d79ec84498.zip | |
Update PIC32 Ethernet driver from debugging (still does not work
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4465 42af7a65-404d-4744-a932-0658087f49c3
| -rwxr-xr-x | nuttx/arch/mips/src/common/up_etherstub.c | 6 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mx/Make.defs | 3 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mx/pic32mx-bmx.h | 332 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mx/pic32mx-config.h | 4 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c | 78 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h | 228 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h | 610 | ||||
| -rw-r--r-- | nuttx/configs/pic32-starterkit/README.txt | 36 | ||||
| -rw-r--r-- | nuttx/configs/pic32-starterkit/nsh/appconfig | 38 | ||||
| -rw-r--r-- | nuttx/configs/pic32-starterkit/nsh/defconfig | 310 | ||||
| -rw-r--r-- | nuttx/configs/pic32-starterkit/ostest/defconfig | 307 | ||||
| -rw-r--r-- | nuttx/include/nuttx/net/mii.h | 31 | ||||
| -rw-r--r-- | nuttx/net/getsockname.c | 2 |
13 files changed, 1345 insertions, 640 deletions
diff --git a/nuttx/arch/mips/src/common/up_etherstub.c b/nuttx/arch/mips/src/common/up_etherstub.c index df9a418dd..1781c8c80 100755 --- a/nuttx/arch/mips/src/common/up_etherstub.c +++ b/nuttx/arch/mips/src/common/up_etherstub.c @@ -1,8 +1,8 @@ /**************************************************************************** * arch/mips/src/common/up_etherstub.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -73,7 +73,7 @@ * In this case, up_initialize will still try to call up_netinitialize() * when one does not exist. This cornercase would occur if, for example, * only a USB network interface is being used or perhaps if a SLIP is - * being used). + * being used). In those cases, the initialization path is very different. * * In the long run, it might be better to have some kind of CONFIG_NO_ETHERNET * to suppress the call to up_netinitialize() in up_initialize(). Then diff --git a/nuttx/arch/mips/src/pic32mx/Make.defs b/nuttx/arch/mips/src/pic32mx/Make.defs index 44469b927..46fef84dc 100644 --- a/nuttx/arch/mips/src/pic32mx/Make.defs +++ b/nuttx/arch/mips/src/pic32mx/Make.defs @@ -50,9 +50,11 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ # Configuration dependent common files +ifneq ($(CONFIG_PIC32MX_ETHERNET),y) ifeq ($(CONFIG_NET),y) CMN_CSRCS += up_etherstub.c endif +endif ifeq ($(CONFIG_ARCH_STACKDUMP),y) CMN_CSRCS += up_dumpstate.c @@ -78,3 +80,4 @@ endif ifeq ($(CONFIG_PIC32MX_ETHERNET),y) CHIP_CSRCS += pic32mx-ethernet.c endif + diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-bmx.h b/nuttx/arch/mips/src/pic32mx/pic32mx-bmx.h index 42a5dcff1..2f65ac5ba 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-bmx.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-bmx.h @@ -1,166 +1,166 @@ -/********************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-bmx.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
-
-/********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
-/********************************************************************************************
- * Pre-Processor Definitions
- ********************************************************************************************/
-/* Register Offsets *************************************************************************/
-
-#define PIC32MX_BMX_CON_OFFSET 0x0000 /* Configuration Register */
-#define PIC32MX_BMX_CONCLR_OFFSET 0x0000 /* Configuration Clear Register */
-#define PIC32MX_BMX_CONSET_OFFSET 0x0004 /* Configuration Set Register */
-#define PIC32MX_BMX_CONINV_OFFSET 0x0008 /* Configuration Invert Register */
-#define PIC32MX_BMX_DKPBA_OFFSET 0x001c /* Data RAM Kernel Program Base Address Register */
-#define PIC32MX_BMX_DKPBACLR_OFFSET 0x0010 /* Data RAM Kernel Program Base Address Clear Register */
-#define PIC32MX_BMX_DKPBASET_OFFSET 0x0014 /* Data RAM Kernel Program Base Address Set Register */
-#define PIC32MX_BMX_DKPBAINV_OFFSET 0x0018 /* Data RAM Kernel Program Base Address Invert Register */
-#define PIC32MX_BMX_DUDBA_OFFSET 0x002c /* Data RAM User Data Base Address Register */
-#define PIC32MX_BMX_DUDBACLR_OFFSET 0x0020 /* Data RAM User Data Base Address Clear Register */
-#define PIC32MX_BMX_DUDBASET_OFFSET 0x0024 /* Data RAM User Data Base Address Set Register */
-#define PIC32MX_BMX_DUDBAINV_OFFSET 0x0028 /* Data RAM User Data Base Address Invert Register */
-#define PIC32MX_BMX_DUPBA_OFFSET 0x003c /* Data RAM User Program Base Address Register */
-#define PIC32MX_BMX_DUPBACLR_OFFSET 0x0030 /* Data RAM User Program Base Address Clear Register */
-#define PIC32MX_BMX_DUPBASET_OFFSET 0x0034 /* Data RAM User Program Base Address Set Register */
-#define PIC32MX_BMX_DUPBAINV_OFFSET 0x0038 /* Data RAM User Program Base Address Invert Register */
-#define PIC32MX_BMX_DRMSZ_OFFSET 0x0040 /* Data RAM Size Register */
-#define PIC32MX_BMX_PUPBA_OFFSET 0x0050 /* Program Flash (PFM) User Program Base Address Register */
-#define PIC32MX_BMX_PUPBACLR_OFFSET 0x0054 /* Program Flash (PFM) User Program Base Address Clear Register */
-#define PIC32MX_BMX_PUPBASET_OFFSET 0x0058 /* Program Flash (PFM) User Program Base Address Set Register */
-#define PIC32MX_BMX_PUPBINVA_OFFSET 0x005c /* Program Flash (PFM) User Program Base Address Invert Register */
-#define PIC32MX_BMX_PFMSZ_OFFSET 0x0060 /* Program Flash Size Register */
-#define PIC32MX_BMX_BOOTSZ_OFFSET 0x0070 /* Boot Flash Size Register */
-
-/* Register Addresses ***********************************************************************/
-
-#define PIC32MX_BMX_CON (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CON_OFFSET)
-#define PIC32MX_BMX_CONCLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONCLR_OFFSET)
-#define PIC32MX_BMX_CONSET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONSET_OFFSET)
-#define PIC32MX_BMX_CONINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONINV_OFFSET)
-#define PIC32MX_BMX_DKPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBA_OFFSET)
-#define PIC32MX_BMX_DKPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBACLR_OFFSET)
-#define PIC32MX_BMX_DKPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBASET_OFFSET)
-#define PIC32MX_BMX_DKPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBAINV_OFFSET)
-#define PIC32MX_BMX_DUDBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBA_OFFSET)
-#define PIC32MX_BMX_DUDBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBACLR_OFFSET)
-#define PIC32MX_BMX_DUDBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBASET_OFFSET)
-#define PIC32MX_BMX_DUDBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBAINV_OFFSET)
-#define PIC32MX_BMX_DUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBA_OFFSET)
-#define PIC32MX_BMX_DUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBACLR_OFFSET)
-#define PIC32MX_BMX_DUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBASET_OFFSET)
-#define PIC32MX_BMX_DUPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBAINV_OFFSET)
-#define PIC32MX_BMX_DRMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DRMSZ_OFFSET)
-#define PIC32MX_BMX_PUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBA_OFFSET)
-#define PIC32MX_BMX_PUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBACLR_OFFSET)
-#define PIC32MX_BMX_PUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBASET_OFFSET)
-#define PIC32MX_BMX_PUPBINVA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBINVA_OFFSET)
-#define PIC32MX_BMX_PFMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PFMSZ_OFFSET)
-#define PIC32MX_BMX_BOOTSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_BOOTSZ_OFFSET)
-
-/* Register Bit-Field Definitions ***********************************************************/
-
-/* Configuration Register */
-
-#define BMX_CON_BMXARB_SHIFT (0) /* Bits 0-2: : Bus matrix arbitration mode */
-#define BMX_CON_BMXARB_MASK (7 << BMX_CON_BMXARB_SHIFT)
-# define BMX_CON_BMXARB(n) ((n) << BMX_CON_BMXARB_SHIFT) /* Mode n, n=0,1,2 */
-#define BMX_CON_BMXWSDRM (1 << 6) /* Bit 6: CPU Instruction or data access from data RAM wait state */
-#define BMX_CON_BMXERRIS (1 << 16) /* Bit 16: Bus error from CPU instruction access */
-#define BMX_CON_BMXERRDS (1 << 17) /* Bit 17: Bus error from CPU data access */
-#define BMX_CON_BMXERRDMA (1 << 18) /* Bit 18: Bus error from DMA */
-#define BMX_CON_BMXERRICD (1 << 19) /* Bit 19: Enable bus error from ICD debug unit */
-#define BMX_CON_BMXERRIXI (1 << 20) /* Bit 20: Enable bus error from IXI */
-#define BMX_CON_BMXCHEDMA (1 << 26) /* Bit 26: BMX PFM cacheability for DMA accesses */
-
-/* Data RAM Kernel Program Base Address Register */
-
-#define BMX_DKPBA_MASK 0x0000ffff /* Bits 0-15 */
-
-/* Data RAM User Data Base Address Register */
-
-#define BMX_DUDBA_MASK 0x0000ffff /* Bits 0-15 */
-
-/* Data RAM User Program Base Address Register */
-
-#define BMX_DUPBA_MASK 0x0000ffff /* Bits 0-15 */
-
-/* Data RAM Size Register -- 32-bit size value */
-
-/* Program Flash (PFM) User Program Base Address Register */
-
-#define BMX_PUPBA_MASK 0x000fffff /* Bits 0-19 */
-
-/* Program Flash Size Register -- 32-bit size value */
-
-/* Boot Flash Size Register -- 32-bit size value */
-
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/********************************************************************************************
- * Inline Functions
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Function Prototypes
- ********************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H */
+/******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-bmx.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ + +#define PIC32MX_BMX_CON_OFFSET 0x0000 /* Configuration Register */ +#define PIC32MX_BMX_CONCLR_OFFSET 0x0004 /* Configuration Clear Register */ +#define PIC32MX_BMX_CONSET_OFFSET 0x0008 /* Configuration Set Register */ +#define PIC32MX_BMX_CONINV_OFFSET 0x000c /* Configuration Invert Register */ +#define PIC32MX_BMX_DKPBA_OFFSET 0x0010 /* Data RAM Kernel Program Base Address Register */ +#define PIC32MX_BMX_DKPBACLR_OFFSET 0x0014 /* Data RAM Kernel Program Base Address Clear Register */ +#define PIC32MX_BMX_DKPBASET_OFFSET 0x0018 /* Data RAM Kernel Program Base Address Set Register */ +#define PIC32MX_BMX_DKPBAINV_OFFSET 0x001c /* Data RAM Kernel Program Base Address Invert Register */ +#define PIC32MX_BMX_DUDBA_OFFSET 0x0020 /* Data RAM User Data Base Address Register */ +#define PIC32MX_BMX_DUDBACLR_OFFSET 0x0024 /* Data RAM User Data Base Address Clear Register */ +#define PIC32MX_BMX_DUDBASET_OFFSET 0x0028 /* Data RAM User Data Base Address Set Register */ +#define PIC32MX_BMX_DUDBAINV_OFFSET 0x002c /* Data RAM User Data Base Address Invert Register */ +#define PIC32MX_BMX_DUPBA_OFFSET 0x0030 /* Data RAM User Program Base Address Register */ +#define PIC32MX_BMX_DUPBACLR_OFFSET 0x0034 /* Data RAM User Program Base Address Clear Register */ +#define PIC32MX_BMX_DUPBASET_OFFSET 0x0038 /* Data RAM User Program Base Address Set Register */ +#define PIC32MX_BMX_DUPBAINV_OFFSET 0x003c /* Data RAM User Program Base Address Invert Register */ +#define PIC32MX_BMX_DRMSZ_OFFSET 0x0040 /* Data RAM Size Register */ +#define PIC32MX_BMX_PUPBA_OFFSET 0x0050 /* Program Flash (PFM) User Program Base Address Register */ +#define PIC32MX_BMX_PUPBACLR_OFFSET 0x0054 /* Program Flash (PFM) User Program Base Address Clear Register */ +#define PIC32MX_BMX_PUPBASET_OFFSET 0x0058 /* Program Flash (PFM) User Program Base Address Set Register */ +#define PIC32MX_BMX_PUPBINVA_OFFSET 0x005c /* Program Flash (PFM) User Program Base Address Invert Register */ +#define PIC32MX_BMX_PFMSZ_OFFSET 0x0060 /* Program Flash Size Register */ +#define PIC32MX_BMX_BOOTSZ_OFFSET 0x0070 /* Boot Flash Size Register */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_BMX_CON (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CON_OFFSET) +#define PIC32MX_BMX_CONCLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONCLR_OFFSET) +#define PIC32MX_BMX_CONSET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONSET_OFFSET) +#define PIC32MX_BMX_CONINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONINV_OFFSET) +#define PIC32MX_BMX_DKPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBA_OFFSET) +#define PIC32MX_BMX_DKPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBACLR_OFFSET) +#define PIC32MX_BMX_DKPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBASET_OFFSET) +#define PIC32MX_BMX_DKPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBAINV_OFFSET) +#define PIC32MX_BMX_DUDBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBA_OFFSET) +#define PIC32MX_BMX_DUDBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBACLR_OFFSET) +#define PIC32MX_BMX_DUDBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBASET_OFFSET) +#define PIC32MX_BMX_DUDBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBAINV_OFFSET) +#define PIC32MX_BMX_DUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBA_OFFSET) +#define PIC32MX_BMX_DUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBACLR_OFFSET) +#define PIC32MX_BMX_DUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBASET_OFFSET) +#define PIC32MX_BMX_DUPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBAINV_OFFSET) +#define PIC32MX_BMX_DRMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DRMSZ_OFFSET) +#define PIC32MX_BMX_PUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBA_OFFSET) +#define PIC32MX_BMX_PUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBACLR_OFFSET) +#define PIC32MX_BMX_PUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBASET_OFFSET) +#define PIC32MX_BMX_PUPBINVA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBINVA_OFFSET) +#define PIC32MX_BMX_PFMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PFMSZ_OFFSET) +#define PIC32MX_BMX_BOOTSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_BOOTSZ_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* Configuration Register */ + +#define BMX_CON_BMXARB_SHIFT (0) /* Bits 0-2: : Bus matrix arbitration mode */ +#define BMX_CON_BMXARB_MASK (7 << BMX_CON_BMXARB_SHIFT) +# define BMX_CON_BMXARB(n) ((n) << BMX_CON_BMXARB_SHIFT) /* Mode n, n=0,1,2 */ +#define BMX_CON_BMXWSDRM (1 << 6) /* Bit 6: CPU Instruction or data access from data RAM wait state */ +#define BMX_CON_BMXERRIS (1 << 16) /* Bit 16: Bus error from CPU instruction access */ +#define BMX_CON_BMXERRDS (1 << 17) /* Bit 17: Bus error from CPU data access */ +#define BMX_CON_BMXERRDMA (1 << 18) /* Bit 18: Bus error from DMA */ +#define BMX_CON_BMXERRICD (1 << 19) /* Bit 19: Enable bus error from ICD debug unit */ +#define BMX_CON_BMXERRIXI (1 << 20) /* Bit 20: Enable bus error from IXI */ +#define BMX_CON_BMXCHEDMA (1 << 26) /* Bit 26: BMX PFM cacheability for DMA accesses */ + +/* Data RAM Kernel Program Base Address Register */ + +#define BMX_DKPBA_MASK 0x0000ffff /* Bits 0-15 */ + +/* Data RAM User Data Base Address Register */ + +#define BMX_DUDBA_MASK 0x0000ffff /* Bits 0-15 */ + +/* Data RAM User Program Base Address Register */ + +#define BMX_DUPBA_MASK 0x0000ffff /* Bits 0-15 */ + +/* Data RAM Size Register -- 32-bit size value */ + +/* Program Flash (PFM) User Program Base Address Register */ + +#define BMX_PUPBA_MASK 0x000fffff /* Bits 0-19 */ + +/* Program Flash Size Register -- 32-bit size value */ + +/* Boot Flash Size Register -- 32-bit size value */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-config.h b/nuttx/arch/mips/src/pic32mx/pic32mx-config.h index 990ebd09e..58b44017f 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-config.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-config.h @@ -607,11 +607,11 @@ /* Unless overridden in the .config file, all pins are in the default setting */ -#ifndef CONFIG_PIC32MX_FMIIEN /* Ethernet MII enable */ +#ifndef CONFIG_PIC32MX_FMIIEN /* Ethernet MII enable: 0=RMII 1=MII */ # define CONFIG_PIC32MX_FMIIEN 1 /* MII enabled */ #endif -#ifndef CONFIG_PIC32MX_FETHIO /* SCM1 pin C selection */ +#ifndef CONFIG_PIC32MX_FETHIO /* Ethernet I/O Pins 0=alternate 1=default */ # define CONFIG_PIC32MX_FETHIO 1 /* Default Ethernet I/O Pins */ #endif diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c index d4dee038c..4438b369a 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -156,6 +156,10 @@ #define PIC32MX_TXTIMEOUT (60*CLK_TCK) +/* PHY timout = 1 minute */ + +#define PIC32MX_MIITIMEOUT (666666) + /* Ethernet MII clocking. * * The clock divider used to create the MII Management Clock (MDC). The MIIM @@ -219,8 +223,6 @@ # undef PIC32MX_HAVE_PHY #endif -#define MII_BIG_TIMEOUT 666666 - /* These definitions are used to remember the speed/duplex settings */ #define PIC32MX_SPEED_MASK 0x01 @@ -415,7 +417,7 @@ static void pic32mx_showmii(uint8_t phyaddr, const char *msg); # endif static void pic32mx_phywrite(uint8_t phyaddr, uint8_t regaddr, - uint16_t phydata); + uint16_t phydata); static uint16_t pic32mx_phyread(uint8_t phyaddr, uint8_t regaddr); static inline int pic32mx_phyreset(uint8_t phyaddr); # ifdef CONFIG_PHY_AUTONEG @@ -1682,7 +1684,8 @@ static int pic32mx_ifup(struct uip_driver_s *dev) */ #if CONFIG_PIC32MX_FMIIEN == 0 -# warning "Missing logic" + pic32mx_putreg(EMAC1_SUPP_RESETRMII, PIC32MX_EMAC1_SUPPSET); + pic32mx_putreg((EMAC1_SUPP_RESETRMII | EMAC1_SUPP_SPEEDRMII), PIC32MX_EMAC1_SUPPCLR); #endif /* Issue an MIIM block reset, by setting the RESETMGMT (EMAC1MCFG:15) bit, @@ -1721,7 +1724,6 @@ static int pic32mx_ifup(struct uip_driver_s *dev) /* Set other misc configuration-related registers to default values */ pic32mx_putreg(0, PIC32MX_EMAC1_CFG2); - pic32mx_putreg(0, PIC32MX_EMAC1_SUPP); pic32mx_putreg(0, PIC32MX_EMAC1_TEST); /* Having available the Duplex and Speed settings, configure the MAC @@ -1732,7 +1734,7 @@ static int pic32mx_ifup(struct uip_driver_s *dev) */ pic32mx_putreg(EMAC1_CFG1_RXEN | EMAC1_CFG1_RXPAUSE | EMAC1_CFG1_TXPAUSE, - PIC32MX_EMAC1_MCFGSET); + PIC32MX_EMAC1_CFG1SET); /* Select the desired auto-padding and CRC capabilities, and the enabling * of the huge frames and the Duplex type in the EMAC1CFG2 register. @@ -1850,7 +1852,7 @@ static int pic32mx_ifup(struct uip_driver_s *dev) /* Configure to pass all received frames */ - regval = pic32mx_getreg(PIC32MX_EMAC1_CFG1); + regval = pic32mx_getreg(PIC32MX_EMAC1_CFG1); regval |= EMAC1_CFG1_PASSALL; pic32mx_putreg(regval, PIC32MX_EMAC1_CFG1); @@ -2207,7 +2209,7 @@ static uint16_t pic32mx_phyread(uint8_t phyaddr, uint8_t regaddr) #ifdef PIC32MX_HAVE_PHY static inline int pic32mx_phyreset(uint8_t phyaddr) { - int32_t timeout; + int32_t timeout; uint16_t phyreg; /* Reset the PHY. Needs a minimal 50uS delay after reset. */ @@ -2222,7 +2224,7 @@ static inline int pic32mx_phyreset(uint8_t phyaddr) * that the reset is complete. */ - for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--) + for (timeout = PIC32MX_MIITIMEOUT; timeout > 0; timeout--) { phyreg = pic32mx_phyread(phyaddr, MII_MCR); if ((phyreg & MII_MCR_RESET) == 0) @@ -2265,7 +2267,7 @@ static inline int pic32mx_phyautoneg(uint8_t phyaddr) /* Wait for autonegotiation to complete */ - for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--) + for (timeout = PIC32MX_MIITIMEOUT; timeout > 0; timeout--) { /* Check if auto-negotiation has completed */ @@ -2336,7 +2338,7 @@ static int pic32mx_phymode(uint8_t phyaddr, uint8_t mode) /* Then wait for the link to be established */ - for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--) + for (timeout = PIC32MX_MIITIMEOUT; timeout > 0; timeout--) { #ifdef CONFIG_PHY_DP83848C phyreg = pic32mx_phyread(phyaddr, MII_DP83848C_STS); @@ -2387,9 +2389,28 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) uint32_t regval; int ret; - /* Clear any ongoing PHY command bits */ +#if CONFIG_PIC32MX_FMIIEN == 0 + /* Set the RMII operation mode. This usually requires access to a vendor + * specific control register. + */ - pic32mx_putreg(0, PIC32MX_EMAC1_MCMD); +#ifdef CONFIG_PHY_DP83848C + /* The RMII/MII of operation can be selected by strap options or register + * control (using the RBR register). For RMII mode, it is required to use the + * strap option, since it requires a 50 MHz clock instead of the normal 25 MHz. + */ +#endif + +#else + /* Set the MII/ operation mode. This usually requires access to a vendor- + * specific control register. + */ + +#ifdef CONFIG_PHY_DP83848C +# warning "Missing logic" +#endif + +#endif /* Find PHY Address. Because the controller has a pull-up and the * PHY has pull-down resistors on RXD lines some times the PHY @@ -2398,9 +2419,26 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) for (phyaddr = 1; phyaddr < 32; phyaddr++) { - /* Check if we can see the selected device ID at this - * PHY address. - */ + /* Clear any ongoing PHY command bits */ + + pic32mx_putreg(0, PIC32MX_EMAC1_MCMD); + + /* Reset the PHY (use Control Register 0). */ + + ret = pic32mx_phyreset(phyaddr); + if (ret < 0) + { + ndbg("Failed to reset PHY at address %d\n"); + continue; + } + + /* Set the normal, swapped or auto (preferred) MDIX. This usually + * requires access to a vendor-specific control register. + */ + + /* Check if we can see the selected device ID at this + * PHY address. + */ phyreg = (unsigned int)pic32mx_phyread(phyaddr, MII_PHYID1); nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg); @@ -2410,7 +2448,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) phyreg = pic32mx_phyread(phyaddr, MII_PHYID2); nvdbg("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg); - if (phyreg == PIC32MX_PHYID2) + if (phyreg == PIC32MX_PHYID2) { break; } @@ -2667,8 +2705,9 @@ static void pic32mx_macmode(uint8_t mode) pic32mx_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), PIC32MX_EMAC1_CFG2SET); } - /* Set the MAC speed. */ + /* Set the RMII MAC speed. */ +#if CONFIG_PIC32MX_FMIIEN == 0 if ((mode & PIC32MX_SPEED_MASK) == PIC32MX_SPEED_100) { pic32mx_putreg(EMAC1_SUPP_SPEEDRMII, PIC32MX_EMAC1_SUPPSET); @@ -2677,6 +2716,7 @@ static void pic32mx_macmode(uint8_t mode) { pic32mx_putreg(EMAC1_SUPP_SPEEDRMII, PIC32MX_EMAC1_SUPPCLR); } +#endif } #endif @@ -2738,7 +2778,7 @@ static void pic32mx_ethreset(struct pic32mx_driver_s *priv) /* Clear the TX and RX start addresses by using ETHTXSTCLR and ETHRXSTCLR */ pic32mx_putreg(0xffffffff, PIC32MX_ETH_TXSTCLR); - pic32mx_putreg(0xffffffff, PIC32MX_ETH_RXSTSET); + pic32mx_putreg(0xffffffff, PIC32MX_ETH_RXSTCLR); /* MAC Initialization *****************************************************/ /* Put the MAC into the reset state */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h index 5b7a8a152..f8232c6d3 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ethernet.h @@ -52,175 +52,175 @@ /* Controller and DMA Engine Configuration/Status Registers */ #define PIC32MX_ETH_CON1_OFFSET 0x0000 /* Ethernet Controller Control 1 Register */ -#define PIC32MX_ETH_CON1SET_OFFSET 0x0004 -#define PIC32MX_ETH_CON1CLR_OFFSET 0x0008 +#define PIC32MX_ETH_CON1CLR_OFFSET 0x0004 +#define PIC32MX_ETH_CON1SET_OFFSET 0x0008 #define PIC32MX_ETH_CON1INV_OFFSET 0x000c #define PIC32MX_ETH_CON2_OFFSET 0x0010 /* Ethernet Controller Control 2 Register */ -#define PIC32MX_ETH_CON2SET_OFFSET 0x0014 -#define PIC32MX_ETH_CON2CLR_OFFSET 0x0018 +#define PIC32MX_ETH_CON2CLR_OFFSET 0x0014 +#define PIC32MX_ETH_CON2SET_OFFSET 0x0018 #define PIC32MX_ETH_CON2INV_OFFSET 0x001c #define PIC32MX_ETH_TXST_OFFSET 0x0020 /* Ethernet Controller TX Packet Descriptor Start Address Register */ -#define PIC32MX_ETH_TXSTSET_OFFSET 0x0024 -#define PIC32MX_ETH_TXSTCLR_OFFSET 0x0028 +#define PIC32MX_ETH_TXSTCLR_OFFSET 0x0024 +#define PIC32MX_ETH_TXSTSET_OFFSET 0x0028 #define PIC32MX_ETH_TXSTINV_OFFSET 0x002c #define PIC32MX_ETH_RXST_OFFSET 0x0030 /* Ethernet Controller RX Packet Descriptor Start Address Register */ -#define PIC32MX_ETH_RXSTSET_OFFSET 0x0034 -#define PIC32MX_ETH_RXSTCLR_OFFSET 0x0038 +#define PIC32MX_ETH_RXSTCLR_OFFSET 0x0034 +#define PIC32MX_ETH_RXSTSET_OFFSET 0x0038 #define PIC32MX_ETH_RXSTINV_OFFSET 0x003c #define PIC32MX_ETH_IEN_OFFSET 0x00c0 /* Ethernet Controller Interrupt Enable Register */ -#define PIC32MX_ETH_IENSET_OFFSET 0x00c4 -#define PIC32MX_ETH_IENCLR_OFFSET 0x00c8 +#define PIC32MX_ETH_IENCLR_OFFSET 0x00c4 +#define PIC32MX_ETH_IENSET_OFFSET 0x00c8 #define PIC32MX_ETH_IENINV_OFFSET 0x00cc #define PIC32MX_ETH_IRQ_OFFSET 0x00d0 /* Ethernet Controller Interrupt Request Register */ -#define PIC32MX_ETH_IRQSET_OFFSET 0x00d4 -#define PIC32MX_ETH_IRQCLR_OFFSET 0x00d8 +#define PIC32MX_ETH_IRQCLR_OFFSET 0x00d4 +#define PIC32MX_ETH_IRQSET_OFFSET 0x00d8 #define PIC32MX_ETH_IRQINV_OFFSET 0x00dc #define PIC32MX_ETH_STAT_OFFSET 0x00e0 /* Ethernet Controller Status Register */ /* RX Filtering Configuration Registers */ #define PIC32MX_ETH_RXFC_OFFSET 0x00a0 /* Ethernet Controller Receive Filter Configuration Register */ -#define PIC32MX_ETH_RXFCSET_OFFSET 0x00a4 -#define PIC32MX_ETH_RXFCCLR_OFFSET 0x00a8 +#define PIC32MX_ETH_RXFCCLR_OFFSET 0x00a4 +#define PIC32MX_ETH_RXFCSET_OFFSET 0x00a8 #define PIC32MX_ETH_RXFCINV_OFFSET 0x00ac #define PIC32MX_ETH_HT0_OFFSET 0x0040 /* Ethernet Controller Hash Table 0 Register */ -#define PIC32MX_ETH_HT0SET_OFFSET 0x0044 -#define PIC32MX_ETH_HT0CLR_OFFSET 0x0048 +#define PIC32MX_ETH_HT0CLR_OFFSET 0x0044 +#define PIC32MX_ETH_HT0SET_OFFSET 0x0048 #define PIC32MX_ETH_HT0INV_OFFSET 0x004c #define PIC32MX_ETH_HT1_OFFSET 0x0050 /* Ethernet Controller Hash Table 1 Register */ -#define PIC32MX_ETH_HT1SET_OFFSET 0x0054 -#define PIC32MX_ETH_HT1CLR_OFFSET 0x0058 +#define PIC32MX_ETH_HT1CLR_OFFSET 0x0054 +#define PIC32MX_ETH_HT1SET_OFFSET 0x0058 #define PIC32MX_ETH_HT1INV_OFFSET 0x005c #define PIC32MX_ETH_PMM0_OFFSET 0x0060 /* Ethernet Controller Pattern Match Mask 0 Register */ -#define PIC32MX_ETH_PMM0SET_OFFSET 0x0064 -#define PIC32MX_ETH_PMM0CLR_OFFSET 0x0068 +#define PIC32MX_ETH_PMM0CLR_OFFSET 0x0064 +#define PIC32MX_ETH_PMM0SET_OFFSET 0x0068 #define PIC32MX_ETH_PMM0INV_OFFSET 0x006c #define PIC32MX_ETH_PMM1_OFFSET 0x0070 /* Ethernet Controller Pattern Match Mask 1 Register */ -#define PIC32MX_ETH_PMM1SET_OFFSET 0x0074 -#define PIC32MX_ETH_PMM1CLR_OFFSET 0x0078 +#define PIC32MX_ETH_PMM1CLR_OFFSET 0x0074 +#define PIC32MX_ETH_PMM1SET_OFFSET 0x0078 #define PIC32MX_ETH_PMM1INV_OFFSET 0x007c #define PIC32MX_ETH_PMCS_OFFSET 0x0080 /* Ethernet Controller Pattern Match Checksum Register */ -#define PIC32MX_ETH_PMCSSET_OFFSET 0x0084 -#define PIC32MX_ETH_PMCSCLR_OFFSET 0x0088 +#define PIC32MX_ETH_PMCSCLR_OFFSET 0x0084 +#define PIC32MX_ETH_PMCSSET_OFFSET 0x0088 #define PIC32MX_ETH_PMCSINV_OFFSET 0x008c #define PIC32MX_ETH_PMO_OFFSET 0x0090 /* Ethernet Controller Pattern Match Offset Register */ -#define PIC32MX_ETH_PMOSET_OFFSET 0x0094 -#define PIC32MX_ETH_PMOCLR_OFFSET 0x0098 +#define PIC32MX_ETH_PMOCLR_OFFSET 0x0094 +#define PIC32MX_ETH_PMOSET_OFFSET 0x0098 #define PIC32MX_ETH_PMOINV_OFFSET 0x009c /* Flow Control Configuring Register */ #define PIC32MX_ETH_RXWM_OFFSET 0x00b0 /* Ethernet Controller Receive Watermarks Register */ -#define PIC32MX_ETH_RXWMSET_OFFSET 0x00b4 -#define PIC32MX_ETH_RXWMCLR_OFFSET 0x00b8 +#define PIC32MX_ETH_RXWMCLR_OFFSET 0x00b4 +#define PIC32MX_ETH_RXWMSET_OFFSET 0x00b8 #define PIC32MX_ETH_RXWMINV_OFFSET 0x00bc /* Ethernet Statistics Registers */ #define PIC32MX_ETH_RXOVFLOW_OFFSET 0x0100 /* Ethernet Controller Receive Overflow Statistics Register */ -#define PIC32MX_ETH_RXOVFLOWSET_OFFSET 0x0104 -#define PIC32MX_ETH_RXOVFLOWCLR_OFFSET 0x0108 +#define PIC32MX_ETH_RXOVFLOWCLR_OFFSET 0x0104 +#define PIC32MX_ETH_RXOVFLOWSET_OFFSET 0x0108 #define PIC32MX_ETH_RXOVFLOWINV_OFFSET 0x010c #define PIC32MX_ETH_FRMTXOK_OFFSET 0x0110 /* Ethernet Controller Frames Transmitted OK Statistics Register */ -#define PIC32MX_ETH_FRMTXOKSET_OFFSET 0x0114 -#define PIC32MX_ETH_FRMTXOKCLR_OFFSET 0x0118 +#define PIC32MX_ETH_FRMTXOKCLR_OFFSET 0x0114 +#define PIC32MX_ETH_FRMTXOKSET_OFFSET 0x0118 #define PIC32MX_ETH_FRMTXOKINV_OFFSET 0x011c #define PIC32MX_ETH_SCOLFRM_OFFSET 0x0120 /* Ethernet Controller Single Collision Frames Statistics Register */ -#define PIC32MX_ETH_SCOLFRMSET_OFFSET 0x0124 -#define PIC32MX_ETH_SCOLFRMCLR_OFFSET 0x0128 +#define PIC32MX_ETH_SCOLFRMCLR_OFFSET 0x0124 +#define PIC32MX_ETH_SCOLFRMSET_OFFSET 0x0128 #define PIC32MX_ETH_SCOLFRMINV_OFFSET 0x012c #define PIC32MX_ETH_MCOLFRM_OFFSET 0x0130 /* Ethernet Controller Multiple Collision Frames Statistics Register */ -#define PIC32MX_ETH_MCOLFRMSET_OFFSET 0x0134 -#define PIC32MX_ETH_MCOLFRMCLR_OFFSET 0x0138 +#define PIC32MX_ETH_MCOLFRMCLR_OFFSET 0x0134 +#define PIC32MX_ETH_MCOLFRMSET_OFFSET 0x0138 #define PIC32MX_ETH_MCOLFRMINV_OFFSET 0x013c #define PIC32MX_ETH_FRMRXOK_OFFSET 0x0140 /* Ethernet Controller Frames Received OK Statistics Register */ -#define PIC32MX_ETH_FRMRXOKSET_OFFSET 0x0144 -#define PIC32MX_ETH_FRMRXOKCLR_OFFSET 0x0148 +#define PIC32MX_ETH_FRMRXOKCLR_OFFSET 0x0144 +#define PIC32MX_ETH_FRMRXOKSET_OFFSET 0x0148 #define PIC32MX_ETH_FRMRXOKINV_OFFSET 0x014c #define PIC32MX_ETH_FCSERR_OFFSET 0x0150 /* Ethernet Controller Frame Check Sequence Error Statistics Register */ -#define PIC32MX_ETH_FCSERRSET_OFFSET 0x0154 -#define PIC32MX_ETH_FCSERRCLR_OFFSET 0x0158 +#define PIC32MX_ETH_FCSERRCLR_OFFSET 0x0154 +#define PIC32MX_ETH_FCSERRSET_OFFSET 0x0158 #define PIC32MX_ETH_FCSERRINV_OFFSET 0x015c #define PIC32MX_ETH_ALGNERR_OFFSET 0x0160 /* Ethernet Controller Alignment Errors Statistics Register */ -#define PIC32MX_ETH_ALGNERRSET_OFFSET 0x0164 -#define PIC32MX_ETH_ALGNERRCLR_OFFSET 0x0168 +#define PIC32MX_ETH_ALGNERRCLR_OFFSET 0x0164 +#define PIC32MX_ETH_ALGNERRSET_OFFSET 0x0168 #define PIC32MX_ETH_ALGNERRINV_OFFSET 0x016c /* MAC Configuration Registers */ #define PIC32MX_EMAC1_CFG1_OFFSET 0x0200 /* Ethernet Controller MAC Configuration 1 Register */ -#define PIC32MX_EMAC1_CFG1SET_OFFSET 0x0204 -#define PIC32MX_EMAC1_CFG1CLR_OFFSET 0x0208 +#define PIC32MX_EMAC1_CFG1CLR_OFFSET 0x0204 +#define PIC32MX_EMAC1_CFG1SET_OFFSET 0x0208 #define PIC32MX_EMAC1_CFG1INV_OFFSET 0x020c #define PIC32MX_EMAC1_CFG2_OFFSET 0x0210 /* Ethernet Controller MAC Configuration 2 Register */ -#define PIC32MX_EMAC1_CFG2SET_OFFSET 0x0214 -#define PIC32MX_EMAC1_CFG2CLR_OFFSET 0x0218 +#define PIC32MX_EMAC1_CFG2CLR_OFFSET 0x0214 +#define PIC32MX_EMAC1_CFG2SET_OFFSET 0x0218 #define PIC32MX_EMAC1_CFG2INV_OFFSET 0x021c #define PIC32MX_EMAC1_IPGT_OFFSET 0x0220 /* Ethernet Controller MAC Back-to-Back Interpacket Gap Register */ -#define PIC32MX_EMAC1_IPGTSET_OFFSET 0x0224 -#define PIC32MX_EMAC1_IPGTCLR_OFFSET 0x0228 +#define PIC32MX_EMAC1_IPGTCLR_OFFSET 0x0224 +#define PIC32MX_EMAC1_IPGTSET_OFFSET 0x0228 #define PIC32MX_EMAC1_IPGTINV_OFFSET 0x022c #define PIC32MX_EMAC1_IPGR_OFFSET 0x0230 /* Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register */ -#define PIC32MX_EMAC1_IPGRSET_OFFSET 0x0234 -#define PIC32MX_EMAC1_IPGRCLR_OFFSET 0x0238 +#define PIC32MX_EMAC1_IPGRCLR_OFFSET 0x0234 +#define PIC32MX_EMAC1_IPGRSET_OFFSET 0x0238 #define PIC32MX_EMAC1_IPGRINV_OFFSET 0x023c #define PIC32MX_EMAC1_CLRT_OFFSET 0x0240 /* Ethernet Controller MAC Collision Window/Retry Limit Register */ -#define PIC32MX_EMAC1_CLRTSET_OFFSET 0x0244 -#define PIC32MX_EMAC1_CLRTCLR_OFFSET 0x0248 +#define PIC32MX_EMAC1_CLRTCLR_OFFSET 0x0244 +#define PIC32MX_EMAC1_CLRTSET_OFFSET 0x0248 #define PIC32MX_EMAC1_CLRTINV_OFFSET 0x024c #define PIC32MX_EMAC1_MAXF_OFFSET 0x0250 /* Ethernet Controller MAC Maximum Frame Length Register */ -#define PIC32MX_EMAC1_MAXFSET_OFFSET 0x0254 -#define PIC32MX_EMAC1_MAXFCLR_OFFSET 0x0258 +#define PIC32MX_EMAC1_MAXFCLR_OFFSET 0x0254 +#define PIC32MX_EMAC1_MAXFSET_OFFSET 0x0258 #define PIC32MX_EMAC1_MAXFINV_OFFSET 0x025c #define PIC32MX_EMAC1_SUPP_OFFSET 0x0260 /* Ethernet Controller MAC PHY Support Register */ -#define PIC32MX_EMAC1_SUPPSET_OFFSET 0x0264 -#define PIC32MX_EMAC1_SUPPCLR_OFFSET 0x0268 +#define PIC32MX_EMAC1_SUPPCLR_OFFSET 0x0264 +#define PIC32MX_EMAC1_SUPPSET_OFFSET 0x0268 #define PIC32MX_EMAC1_SUPPINV_OFFSET 0x026c #define PIC32MX_EMAC1_TEST_OFFSET 0x0270 /* Ethernet Controller MAC Test Register */ -#define PIC32MX_EMAC1_TESTSET_OFFSET 0x0274 -#define PIC32MX_EMAC1_TESTCLR_OFFSET 0x0278 +#define PIC32MX_EMAC1_TESTCLR_OFFSET 0x0274 +#define PIC32MX_EMAC1_TESTSET_OFFSET 0x0278 #define PIC32MX_EMAC1_TESTINV_OFFSET 0x027c #define PIC32MX_EMAC1_SA0_OFFSET 0x0300 /* Ethernet Controller MAC Station Address 0 Register */ -#define PIC32MX_EMAC1_SA0SET_OFFSET 0x0304 -#define PIC32MX_EMAC1_SA0CLR_OFFSET 0x0308 +#define PIC32MX_EMAC1_SA0CLR_OFFSET 0x0304 +#define PIC32MX_EMAC1_SA0SET_OFFSET 0x0308 #define PIC32MX_EMAC1_SA0INV_OFFSET 0x030c #define PIC32MX_EMAC1_SA1_OFFSET 0x0310 /* Ethernet Controller MAC Station Address 1 Register */ -#define PIC32MX_EMAC1_SA1SET_OFFSET 0x0314 -#define PIC32MX_EMAC1_SA1CLR_OFFSET 0x0318 +#define PIC32MX_EMAC1_SA1CLR_OFFSET 0x0314 +#define PIC32MX_EMAC1_SA1SET_OFFSET 0x0318 #define PIC32MX_EMAC1_SA1INV_OFFSET 0x031c #define PIC32MX_EMAC1_SA2_OFFSET 0x0320 /* Ethernet Controller MAC Station Address 2 Register */ -#define PIC32MX_EMAC1_SA2SET_OFFSET 0x0324 -#define PIC32MX_EMAC1_SA2CLR_OFFSET 0x0328 +#define PIC32MX_EMAC1_SA2CLR_OFFSET 0x0324 +#define PIC32MX_EMAC1_SA2SET_OFFSET 0x0328 #define PIC32MX_EMAC1_SA2INV_OFFSET 0x032c /* MII Management Registers */ #define PIC32MX_EMAC1_MCFG_OFFSET 0x0280 /* Ethernet Controller MAC MII Management Configuration Register */ -#define PIC32MX_EMAC1_MCFGSET_OFFSET 0x0284 -#define PIC32MX_EMAC1_MCFGCLR_OFFSET 0x0288 +#define PIC32MX_EMAC1_MCFGCLR_OFFSET 0x0284 +#define PIC32MX_EMAC1_MCFGSET_OFFSET 0x0288 #define PIC32MX_EMAC1_MCFGINV_OFFSET 0x028c #define PIC32MX_EMAC1_MCMD_OFFSET 0x0290 /* Ethernet Controller MAC MII Management Command Register */ -#define PIC32MX_EMAC1_MCMDSET_OFFSET 0x0294 -#define PIC32MX_EMAC1_MCMDCLR_OFFSET 0x0298 +#define PIC32MX_EMAC1_MCMDCLR_OFFSET 0x0294 +#define PIC32MX_EMAC1_MCMDSET_OFFSET 0x0298 #define PIC32MX_EMAC1_MCMDINV_OFFSET 0x029c #define PIC32MX_EMAC1_MADR_OFFSET 0x02a0 /* Ethernet Controller MAC MII Management Address Register */ -#define PIC32MX_EMAC1_MADRSET_OFFSET 0x02a4 -#define PIC32MX_EMAC1_MADRCLR_OFFSET 0x02a8 +#define PIC32MX_EMAC1_MADRCLR_OFFSET 0x02a4 +#define PIC32MX_EMAC1_MADRSET_OFFSET 0x02a8 #define PIC32MX_EMAC1_MADRINV_OFFSET 0x02ac #define PIC32MX_EMAC1_MWTD_OFFSET 0x02b0 /* Ethernet Controller MAC MII Management Write Data Register */ -#define PIC32MX_EMAC1_MWTDSET_OFFSET 0x02b4 -#define PIC32MX_EMAC1_MWTDCLR_OFFSET 0x02b8 +#define PIC32MX_EMAC1_MWTDCLR_OFFSET 0x02b4 +#define PIC32MX_EMAC1_MWTDSET_OFFSET 0x02b8 #define PIC32MX_EMAC1_MWTDINV_OFFSET 0x02bc #define PIC32MX_EMAC1_MRDD_OFFSET 0x02c0 /* Ethernet Controller MAC MII Management Read Data Register */ -#define PIC32MX_EMAC1_MRDDSET_OFFSET 0x02c4 -#define PIC32MX_EMAC1_MRDDCLR_OFFSET 0x02c8 +#define PIC32MX_EMAC1_MRDDCLR_OFFSET 0x02c4 +#define PIC32MX_EMAC1_MRDDSET_OFFSET 0x02c8 #define PIC32MX_EMAC1_MRDDINV_OFFSET 0x02cc #define PIC32MX_EMAC1_MIND_OFFSET 0x02d0 /* Ethernet Controller MAC MII Management Indicators Register */ -#define PIC32MX_EMAC1_MINDSET_OFFSET 0x02d4 -#define PIC32MX_EMAC1_MINDCLR_OFFSET 0x02d8 +#define PIC32MX_EMAC1_MINDCLR_OFFSET 0x02d4 +#define PIC32MX_EMAC1_MINDSET_OFFSET 0x02d8 #define PIC32MX_EMAC1_MINDINV_OFFSET 0x02dc /* Register Addresses ***********************************************************************/ @@ -228,172 +228,172 @@ /* Controller and DMA Engine Configuration/Status Registers */ #define PIC32MX_ETH_CON1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1_OFFSET) -#define PIC32MX_ETH_CON1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1SET_OFFSET) #define PIC32MX_ETH_CON1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1CLR_OFFSET) +#define PIC32MX_ETH_CON1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1SET_OFFSET) #define PIC32MX_ETH_CON1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1INV_OFFSET) #define PIC32MX_ETH_CON2 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2_OFFSET) -#define PIC32MX_ETH_CON2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2SET_OFFSET) #define PIC32MX_ETH_CON2CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2CLR_OFFSET) +#define PIC32MX_ETH_CON2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2SET_OFFSET) #define PIC32MX_ETH_CON2INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2INV_OFFSET) #define PIC32MX_ETH_TXST (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXST_OFFSET) -#define PIC32MX_ETH_TXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTSET_OFFSET) #define PIC32MX_ETH_TXSTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTCLR_OFFSET) +#define PIC32MX_ETH_TXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTSET_OFFSET) #define PIC32MX_ETH_TXSTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTINV_OFFSET) #define PIC32MX_ETH_RXST (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXST_OFFSET) -#define PIC32MX_ETH_RXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTSET_OFFSET) #define PIC32MX_ETH_RXSTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTCLR_OFFSET) +#define PIC32MX_ETH_RXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTSET_OFFSET) #define PIC32MX_ETH_RXSTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTINV_OFFSET) #define PIC32MX_ETH_IEN (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IEN_OFFSET) -#define PIC32MX_ETH_IENSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENSET_OFFSET) #define PIC32MX_ETH_IENCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENCLR_OFFSET) +#define PIC32MX_ETH_IENSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENSET_OFFSET) #define PIC32MX_ETH_IENINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENINV_OFFSET) #define PIC32MX_ETH_IRQ (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQ_OFFSET) -#define PIC32MX_ETH_IRQSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQSET_OFFSET) #define PIC32MX_ETH_IRQCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQCLR_OFFSET) +#define PIC32MX_ETH_IRQSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQSET_OFFSET) #define PIC32MX_ETH_IRQINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQINV_OFFSET) #define PIC32MX_ETH_STAT (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_STAT_OFFSET) /* RX Filtering Configuration Registers */ #define PIC32MX_ETH_RXFC (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFC_OFFSET) -#define PIC32MX_ETH_RXFCSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCSET_OFFSET) #define PIC32MX_ETH_RXFCCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCCLR_OFFSET) +#define PIC32MX_ETH_RXFCSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCSET_OFFSET) #define PIC32MX_ETH_RXFCINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCINV_OFFSET) #define PIC32MX_ETH_HT0 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0_OFFSET) -#define PIC32MX_ETH_HT0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0SET_OFFSET) #define PIC32MX_ETH_HT0CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0CLR_OFFSET) +#define PIC32MX_ETH_HT0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0SET_OFFSET) #define PIC32MX_ETH_HT0INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0INV_OFFSET) #define PIC32MX_ETH_HT1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1_OFFSET) -#define PIC32MX_ETH_HT1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1SET_OFFSET) #define PIC32MX_ETH_HT1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1CLR_OFFSET) +#define PIC32MX_ETH_HT1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1SET_OFFSET) #define PIC32MX_ETH_HT1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1INV_OFFSET) #define PIC32MX_ETH_PMM0 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0_OFFSET) -#define PIC32MX_ETH_PMM0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0SET_OFFSET) #define PIC32MX_ETH_PMM0CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0CLR_OFFSET) +#define PIC32MX_ETH_PMM0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0SET_OFFSET) #define PIC32MX_ETH_PMM0INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0INV_OFFSET) #define PIC32MX_ETH_PMM1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1_OFFSET) -#define PIC32MX_ETH_PMM1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1SET_OFFSET) #define PIC32MX_ETH_PMM1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1CLR_OFFSET) +#define PIC32MX_ETH_PMM1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1SET_OFFSET) #define PIC32MX_ETH_PMM1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1INV_OFFSET) #define PIC32MX_ETH_PMCS (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCS_OFFSET) -#define PIC32MX_ETH_PMCSSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSSET_OFFSET) #define PIC32MX_ETH_PMCSCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSCLR_OFFSET) +#define PIC32MX_ETH_PMCSSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSSET_OFFSET) #define PIC32MX_ETH_PMCSINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSINV_OFFSET) #define PIC32MX_ETH_PMO (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMO_OFFSET) -#define PIC32MX_ETH_PMOSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOSET_OFFSET) #define PIC32MX_ETH_PMOCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOCLR_OFFSET) +#define PIC32MX_ETH_PMOSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOSET_OFFSET) #define PIC32MX_ETH_PMOINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOINV_OFFSET) /* Flow Control Configuring Register */ #define PIC32MX_ETH_RXWM (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWM_OFFSET) -#define PIC32MX_ETH_RXWMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMSET_OFFSET) #define PIC32MX_ETH_RXWMCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMCLR_OFFSET) +#define PIC32MX_ETH_RXWMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMSET_OFFSET) #define PIC32MX_ETH_RXWMINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMINV_OFFSET) /* Ethernet Statistics Registers */ #define PIC32MX_ETH_RXOVFLOW (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOW_OFFSET) -#define PIC32MX_ETH_RXOVFLOWSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWSET_OFFSET) #define PIC32MX_ETH_RXOVFLOWCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWCLR_OFFSET) +#define PIC32MX_ETH_RXOVFLOWSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWSET_OFFSET) #define PIC32MX_ETH_RXOVFLOWINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWINV_OFFSET) #define PIC32MX_ETH_FRMTXOK (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOK_OFFSET) -#define PIC32MX_ETH_FRMTXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKSET_OFFSET) #define PIC32MX_ETH_FRMTXOKCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKCLR_OFFSET) +#define PIC32MX_ETH_FRMTXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKSET_OFFSET) #define PIC32MX_ETH_FRMTXOKINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKINV_OFFSET) #define PIC32MX_ETH_SCOLFRM (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRM_OFFSET) -#define PIC32MX_ETH_SCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMSET_OFFSET) #define PIC32MX_ETH_SCOLFRMCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMCLR_OFFSET) +#define PIC32MX_ETH_SCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMSET_OFFSET) #define PIC32MX_ETH_SCOLFRMINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMINV_OFFSET) #define PIC32MX_ETH_MCOLFRM (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRM_OFFSET) -#define PIC32MX_ETH_MCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMSET_OFFSET) #define PIC32MX_ETH_MCOLFRMCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMCLR_OFFSET) +#define PIC32MX_ETH_MCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMSET_OFFSET) #define PIC32MX_ETH_MCOLFRMINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMINV_OFFSET) #define PIC32MX_ETH_FRMRXOK (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOK_OFFSET) -#define PIC32MX_ETH_FRMRXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKSET_OFFSET) #define PIC32MX_ETH_FRMRXOKCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKCLR_OFFSET) +#define PIC32MX_ETH_FRMRXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKSET_OFFSET) #define PIC32MX_ETH_FRMRXOKINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKINV_OFFSET) #define PIC32MX_ETH_FCSERR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERR_OFFSET) -#define PIC32MX_ETH_FCSERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRSET_OFFSET) #define PIC32MX_ETH_FCSERRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRCLR_OFFSET) +#define PIC32MX_ETH_FCSERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRSET_OFFSET) #define PIC32MX_ETH_FCSERRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRINV_OFFSET) #define PIC32MX_ETH_ALGNERR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERR_OFFSET) -#define PIC32MX_ETH_ALGNERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRSET_OFFSET) #define PIC32MX_ETH_ALGNERRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRCLR_OFFSET) +#define PIC32MX_ETH_ALGNERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRSET_OFFSET) #define PIC32MX_ETH_ALGNERRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRINV_OFFSET) /* MAC Configuration Registers */ #define PIC32MX_EMAC1_CFG1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1_OFFSET) -#define PIC32MX_EMAC1_CFG1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1SET_OFFSET) #define PIC32MX_EMAC1_CFG1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1CLR_OFFSET) +#define PIC32MX_EMAC1_CFG1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1SET_OFFSET) #define PIC32MX_EMAC1_CFG1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1INV_OFFSET) #define PIC32MX_EMAC1_CFG2 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2_OFFSET) -#define PIC32MX_EMAC1_CFG2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2SET_OFFSET) #define PIC32MX_EMAC1_CFG2CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2CLR_OFFSET) +#define PIC32MX_EMAC1_CFG2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2SET_OFFSET) #define PIC32MX_EMAC1_CFG2INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2INV_OFFSET) #define PIC32MX_EMAC1_IPGT (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGT_OFFSET) -#define PIC32MX_EMAC1_IPGTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTSET_OFFSET) #define PIC32MX_EMAC1_IPGTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTCLR_OFFSET) +#define PIC32MX_EMAC1_IPGTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTSET_OFFSET) #define PIC32MX_EMAC1_IPGTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTINV_OFFSET) #define PIC32MX_EMAC1_IPGR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGR_OFFSET) -#define PIC32MX_EMAC1_IPGRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRSET_OFFSET) #define PIC32MX_EMAC1_IPGRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRCLR_OFFSET) +#define PIC32MX_EMAC1_IPGRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRSET_OFFSET) #define PIC32MX_EMAC1_IPGRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRINV_OFFSET) #define PIC32MX_EMAC1_CLRT (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRT_OFFSET) -#define PIC32MX_EMAC1_CLRTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTSET_OFFSET) #define PIC32MX_EMAC1_CLRTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTCLR_OFFSET) +#define PIC32MX_EMAC1_CLRTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTSET_OFFSET) #define PIC32MX_EMAC1_CLRTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTINV_OFFSET) #define PIC32MX_EMAC1_MAXF (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXF_OFFSET) -#define PIC32MX_EMAC1_MAXFSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFSET_OFFSET) #define PIC32MX_EMAC1_MAXFCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFCLR_OFFSET) +#define PIC32MX_EMAC1_MAXFSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFSET_OFFSET) #define PIC32MX_EMAC1_MAXFINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFINV_OFFSET) #define PIC32MX_EMAC1_SUPP (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPP_OFFSET) -#define PIC32MX_EMAC1_SUPPSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPSET_OFFSET) #define PIC32MX_EMAC1_SUPPCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPCLR_OFFSET) +#define PIC32MX_EMAC1_SUPPSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPSET_OFFSET) #define PIC32MX_EMAC1_SUPPINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPINV_OFFSET) #define PIC32MX_EMAC1_TEST (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TEST_OFFSET) -#define PIC32MX_EMAC1_TESTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTSET_OFFSET) #define PIC32MX_EMAC1_TESTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTCLR_OFFSET) +#define PIC32MX_EMAC1_TESTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTSET_OFFSET) #define PIC32MX_EMAC1_TESTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTINV_OFFSET) #define PIC32MX_EMAC1_SA0 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0_OFFSET) -#define PIC32MX_EMAC1_SA0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0SET_OFFSET) #define PIC32MX_EMAC1_SA0CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0CLR_OFFSET) +#define PIC32MX_EMAC1_SA0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0SET_OFFSET) #define PIC32MX_EMAC1_SA0INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0INV_OFFSET) #define PIC32MX_EMAC1_SA1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1_OFFSET) -#define PIC32MX_EMAC1_SA1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1SET_OFFSET) #define PIC32MX_EMAC1_SA1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1CLR_OFFSET) +#define PIC32MX_EMAC1_SA1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1SET_OFFSET) #define PIC32MX_EMAC1_SA1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1INV_OFFSET) #define PIC32MX_EMAC1_SA2 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2_OFFSET) -#define PIC32MX_EMAC1_SA2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2SET_OFFSET) #define PIC32MX_EMAC1_SA2CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2CLR_OFFSET) +#define PIC32MX_EMAC1_SA2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2SET_OFFSET) #define PIC32MX_EMAC1_SA2INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2INV_OFFSET) /* MII Management Registers */ #define PIC32MX_EMAC1_MCFG (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFG_OFFSET) -#define PIC32MX_EMAC1_MCFGSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGSET_OFFSET) #define PIC32MX_EMAC1_MCFGCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGCLR_OFFSET) +#define PIC32MX_EMAC1_MCFGSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGSET_OFFSET) #define PIC32MX_EMAC1_MCFGINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGINV_OFFSET) #define PIC32MX_EMAC1_MCMD (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMD_OFFSET) -#define PIC32MX_EMAC1_MCMDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDSET_OFFSET) #define PIC32MX_EMAC1_MCMDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDCLR_OFFSET) +#define PIC32MX_EMAC1_MCMDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDSET_OFFSET) #define PIC32MX_EMAC1_MCMDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDINV_OFFSET) #define PIC32MX_EMAC1_MADR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADR_OFFSET) -#define PIC32MX_EMAC1_MADRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRSET_OFFSET) #define PIC32MX_EMAC1_MADRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRCLR_OFFSET) +#define PIC32MX_EMAC1_MADRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRSET_OFFSET) #define PIC32MX_EMAC1_MADRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRINV_OFFSET) #define PIC32MX_EMAC1_MWTD (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTD_OFFSET) -#define PIC32MX_EMAC1_MWTDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDSET_OFFSET) #define PIC32MX_EMAC1_MWTDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDCLR_OFFSET) +#define PIC32MX_EMAC1_MWTDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDSET_OFFSET) #define PIC32MX_EMAC1_MWTDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDINV_OFFSET) #define PIC32MX_EMAC1_MRDD (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDD_OFFSET) -#define PIC32MX_EMAC1_MRDDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDSET_OFFSET) #define PIC32MX_EMAC1_MRDDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDCLR_OFFSET) +#define PIC32MX_EMAC1_MRDDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDSET_OFFSET) #define PIC32MX_EMAC1_MRDDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDINV_OFFSET ) #define PIC32MX_EMAC1_MIND (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MIND_OFFSET) -#define PIC32MX_EMAC1_MINDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDSET_OFFSET) #define PIC32MX_EMAC1_MINDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDCLR_OFFSET) +#define PIC32MX_EMAC1_MINDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDSET_OFFSET) #define PIC32MX_EMAC1_MINDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDINV_OFFSET) /* Register Bit-Field Definitions ***********************************************************/ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h b/nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h index 768f71349..544b0e37b 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h @@ -1,305 +1,305 @@ -/************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-i2c.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "pic32mx-memorymap.h"
-
-/************************************************************************************
- * Pre-Processor Definitions
- ************************************************************************************/
-/* Register Offsets *****************************************************************/
-
-#define PIC32MX_I2C_CON_OFFSET 0x0000 /* I2C control register */
-#define PIC32MX_I2C_CONCLR_OFFSET 0x0004 /* I2C control clear register */
-#define PIC32MX_I2C_CONSET_OFFSET 0x0008 /* I2C control set register */
-#define PIC32MX_I2C_CONINV_OFFSET 0x000c /* I2C control invert register */
-#define PIC32MX_I2C_STAT_OFFSET 0x0010 /* I2C status register */
-#define PIC32MX_I2C_STATCLR_OFFSET 0x0014 /* I2C status clear register */
-#define PIC32MX_I2C_STATSET_OFFSET 0x0018 /* I2C status set register */
-#define PIC32MX_I2C_STATINV_OFFSET 0x001c /* I2C status invert register */
-#define PIC32MX_I2C_ADD_OFFSET 0x0020 /* I2C address register */
-#define PIC32MX_I2C_ADDCLR_OFFSET 0x0024 /* I2C address clear register */
-#define PIC32MX_I2C_ADDSET_OFFSET 0x0028 /* I2C address set register */
-#define PIC32MX_I2C_ADDINV_OFFSET 0x002c /* I2C address invert register */
-#define PIC32MX_I2C_MSK_OFFSET 0x0030 /* I2C address mask register */
-#define PIC32MX_I2C_MSKCLR_OFFSET 0x0034 /* I2C address mask clear register */
-#define PIC32MX_I2C_MSKSET_OFFSET 0x0038 /* I2C address mask set register */
-#define PIC32MX_I2C_MSKINV_OFFSET 0x003c /* I2C address mask invert register */
-#define PIC32MX_I2C_BRG_OFFSET 0x0040 /* Baud rate generator reload register */
-#define PIC32MX_I2C_BRGSET_OFFSET 0x0044 /* Baud rate generator reload clear register */
-#define PIC32MX_I2C_BRGCLR_OFFSET 0x0048 /* Baud rate generator reload set register */
-#define PIC32MX_I2C_BRGINV_OFFSET 0x004c /* Baud rate generator reload invert register */
-#define PIC32MX_I2C_TRN_OFFSET 0x0050 /* I2C transmit register */
-#define PIC32MX_I2C_TRNCLR_OFFSET 0x0054 /* I2C transmit clear register */
-#define PIC32MX_I2C_TRNSET_OFFSET 0x0058 /* I2C transmit set register */
-#define PIC32MX_I2C_TRNINV_OFFSET 0x005c /* I2C transmit invert register */
-#define PIC32MX_I2C_RCV_OFFSET 0x0060 /* I2C receive buffer register */
-
-/* Register Addresses ***************************************************************/
-
-#if CHIP_NI2C > 0
-# define PIC32MX_I2C1_CON (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CON_OFFSET)
-# define PIC32MX_I2C1_CONCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
-# define PIC32MX_I2C1_CONSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
-# define PIC32MX_I2C1_CONINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
-# define PIC32MX_I2C1_STAT (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STAT_OFFSET)
-# define PIC32MX_I2C1_STATCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
-# define PIC32MX_I2C1_STATSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
-# define PIC32MX_I2C1_STATINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
-# define PIC32MX_I2C1_ADD (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADD_OFFSET)
-# define PIC32MX_I2C1_ADDCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
-# define PIC32MX_I2C1_ADDSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
-# define PIC32MX_I2C1_ADDINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
-# define PIC32MX_I2C1_MSK (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSK_OFFSET)
-# define PIC32MX_I2C1_MSKCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
-# define PIC32MX_I2C1_MSKSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
-# define PIC32MX_I2C1_MSKINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
-# define PIC32MX_I2C1_BRG (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRG_OFFSET)
-# define PIC32MX_I2C1_BRGSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
-# define PIC32MX_I2C1_BRGCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
-# define PIC32MX_I2C1_BRGINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
-# define PIC32MX_I2C1_TRN (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRN_OFFSET)
-# define PIC32MX_I2C1_TRNCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
-# define PIC32MX_I2C1_TRNSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
-# define PIC32MX_I2C1_TRNINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
-# define PIC32MX_I2C1_RCV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_RCV_OFFSET)
-#endif
-
-#if CHIP_NI2C > 1
-# define PIC32MX_I2C2_CON (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CON_OFFSET)
-# define PIC32MX_I2C2_CONCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
-# define PIC32MX_I2C2_CONSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
-# define PIC32MX_I2C2_CONINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
-# define PIC32MX_I2C2_STAT (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STAT_OFFSET)
-# define PIC32MX_I2C2_STATCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
-# define PIC32MX_I2C2_STATSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
-# define PIC32MX_I2C2_STATINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
-# define PIC32MX_I2C2_ADD (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADD_OFFSET)
-# define PIC32MX_I2C2_ADDCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
-# define PIC32MX_I2C2_ADDSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
-# define PIC32MX_I2C2_ADDINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
-# define PIC32MX_I2C2_MSK (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSK_OFFSET)
-# define PIC32MX_I2C2_MSKCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
-# define PIC32MX_I2C2_MSKSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
-# define PIC32MX_I2C2_MSKINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
-# define PIC32MX_I2C2_BRG (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRG_OFFSET)
-# define PIC32MX_I2C2_BRGSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
-# define PIC32MX_I2C2_BRGCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
-# define PIC32MX_I2C2_BRGINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
-# define PIC32MX_I2C2_TRN (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRN_OFFSET)
-# define PIC32MX_I2C2_TRNCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
-# define PIC32MX_I2C2_TRNSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
-# define PIC32MX_I2C2_TRNINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
-# define PIC32MX_I2C2_RCV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_RCV_OFFSET)
-#endif
-
-#if CHIP_NI2C > 2
-# define PIC32MX_I2C3_CON (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CON_OFFSET)
-# define PIC32MX_I2C3_CONCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
-# define PIC32MX_I2C3_CONSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
-# define PIC32MX_I2C3_CONINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
-# define PIC32MX_I2C3_STAT (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STAT_OFFSET)
-# define PIC32MX_I2C3_STATCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
-# define PIC32MX_I2C3_STATSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
-# define PIC32MX_I2C3_STATINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
-# define PIC32MX_I2C3_ADD (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADD_OFFSET)
-# define PIC32MX_I2C3_ADDCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
-# define PIC32MX_I2C3_ADDSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
-# define PIC32MX_I2C3_ADDINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
-# define PIC32MX_I2C3_MSK (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSK_OFFSET)
-# define PIC32MX_I2C3_MSKCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
-# define PIC32MX_I2C3_MSKSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
-# define PIC32MX_I2C3_MSKINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
-# define PIC32MX_I2C3_BRG (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRG_OFFSET)
-# define PIC32MX_I2C3_BRGSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
-# define PIC32MX_I2C3_BRGCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
-# define PIC32MX_I2C3_BRGINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
-# define PIC32MX_I2C3_TRN (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRN_OFFSET)
-# define PIC32MX_I2C3_TRNCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
-# define PIC32MX_I2C3_TRNSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
-# define PIC32MX_I2C3_TRNINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
-# define PIC32MX_I2C3_RCV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_RCV_OFFSET)
-#endif
-
-#if CHIP_NI2C > 3
-# define PIC32MX_I2C4_CON (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CON_OFFSET)
-# define PIC32MX_I2C4_CONCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
-# define PIC32MX_I2C4_CONSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
-# define PIC32MX_I2C4_CONINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
-# define PIC32MX_I2C4_STAT (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STAT_OFFSET)
-# define PIC32MX_I2C4_STATCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
-# define PIC32MX_I2C4_STATSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
-# define PIC32MX_I2C4_STATINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
-# define PIC32MX_I2C4_ADD (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADD_OFFSET)
-# define PIC32MX_I2C4_ADDCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
-# define PIC32MX_I2C4_ADDSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
-# define PIC32MX_I2C4_ADDINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
-# define PIC32MX_I2C4_MSK (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSK_OFFSET)
-# define PIC32MX_I2C4_MSKCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
-# define PIC32MX_I2C4_MSKSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
-# define PIC32MX_I2C4_MSKINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
-# define PIC32MX_I2C4_BRG (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRG_OFFSET)
-# define PIC32MX_I2C4_BRGSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
-# define PIC32MX_I2C4_BRGCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
-# define PIC32MX_I2C4_BRGINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
-# define PIC32MX_I2C4_TRN (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRN_OFFSET)
-# define PIC32MX_I2C4_TRNCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
-# define PIC32MX_I2C4_TRNSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
-# define PIC32MX_I2C4_TRNINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
-# define PIC32MX_I2C4_RCV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_RCV_OFFSET)
-#endif
-
-#if CHIP_NI2C > 4
-# define PIC32MX_I2C5_CON (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CON_OFFSET)
-# define PIC32MX_I2C5_CONCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
-# define PIC32MX_I2C5_CONSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
-# define PIC32MX_I2C5_CONINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
-# define PIC32MX_I2C5_STAT (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STAT_OFFSET)
-# define PIC32MX_I2C5_STATCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
-# define PIC32MX_I2C5_STATSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
-# define PIC32MX_I2C5_STATINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
-# define PIC32MX_I2C5_ADD (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADD_OFFSET)
-# define PIC32MX_I2C5_ADDCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
-# define PIC32MX_I2C5_ADDSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
-# define PIC32MX_I2C5_ADDINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
-# define PIC32MX_I2C5_MSK (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSK_OFFSET)
-# define PIC32MX_I2C5_MSKCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
-# define PIC32MX_I2C5_MSKSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
-# define PIC32MX_I2C5_MSKINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
-# define PIC32MX_I2C5_BRG (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRG_OFFSET)
-# define PIC32MX_I2C5_BRGSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
-# define PIC32MX_I2C5_BRGCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
-# define PIC32MX_I2C5_BRGINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
-# define PIC32MX_I2C5_TRN (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRN_OFFSET)
-# define PIC32MX_I2C5_TRNCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
-# define PIC32MX_I2C5_TRNSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
-# define PIC32MX_I2C5_TRNINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
-# define PIC32MX_I2C5_RCV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_RCV_OFFSET)
-#endif
-
-/* Register Bit-Field Definitions ***************************************************/
-
-/* I2C control register */
-
-#define I2C_CON_SEN (1 << 0) /* Bit 0: Start condition enable */
-#define I2C_CON_RSEN (1 << 1) /* Bit 1: Restart condition enable */
-#define I2C_CON_PEN (1 << 2) /* Bit 2: Stop condition enable */
-#define I2C_CON_RCEN (1 << 3) /* Bit 3: Receive enable */
-#define I2C_CON_ACKEN (1 << 4) /* Bit 4: Acknowledge sequence enable */
-#define I2C_CON_ACKDT (1 << 5) /* Bit 5: Acknowledge data */
-#define I2C_CON_STREN (1 << 6) /* Bit 6: SCL clock stretch enable */
-#define I2C_CON_GCEN (1 << 7) /* Bit 7: General call enable */
-#define I2C_CON_SMEN (1 << 8) /* Bit 8: SMBus input levels disable */
-#define I2C_CON_DISSLW (1 << 9) /* Bit 9: Slew rate control disable */
-#define I2C_CON_A10M (1 << 10) /* Bit 10: 10-bit slave addrewss flag */
-#define I2C_CON_STRICT (1 << 11) /* Bit 11: Strict I2C reserved address rules enable */
-#define I2C_CON_SCLREL (1 << 12) /* Bit 12: SCL release control */
-#define I2C_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
-#define I2C_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug mode control */
-#define I2C_CON_ON (1 << 15) /* Bit 15: I2C enable */
-
-/* I2C status register */
-
-#define I2C_STAT_TBF (1 << 0) /* Bit 0: Transmit buffer full */
-#define I2C_STAT_RBF (1 << 1) /* Bit 1: Receive buffer full */
-#define I2C_STAT_RW (1 << 2) /* Bit 2: Read/write information */
-#define I2C_STAT_S (1 << 3) /* Bit 3: Start */
-#define I2C_STAT_P (1 << 4) /* Bit 4: Stop */
-#define I2C_STAT_DA (1 << 5) /* Bit 5: Data/address */
-#define I2C_STAT_I2COV (1 << 6) /* Bit 6: I2C overflow status */
-#define I2C_STAT_IWCOL (1 << 7) /* Bit 7: Write collision detect */
-#define I2C_STAT_ADD10 (1 << 8) /* Bit 8: 10-bit address status */
-#define I2C_STAT_GCSTAT (1 << 9) /* Bit 9: General call status */
-#define I2C_STAT_BCL (1 << 10) /* Bit 10: Master bus collision detect */
-#define I2C_STAT_TRSTAT (1 << 14) /* Bit 14: Transmit status */
-#define I2C_STAT_ACKSTAT (1 << 15) /* Bit 15: Acknowledge status */
-
-/* I2C address register */
-
-#define I2C_ADD_MASK 0x3ff /* 10-bit I2C address */
-
-/* I2C address mask register */
-
-#define I2C_MSK_MASK 0x3ff /* 10-bit I2C address mask */
-
-/* Baud rate generator reload register */
-
-#define I2C_BRG_MASK 0xfff /* 12-bit I2C BRG value */
-
-/* I2C transmit register */
-
-#define I2C_TRN_MASK 0xff /* 8-bit transmit data */
-
-/* I2C receive buffer register */
-
-#define I2C_RCV_MASK 0xff /* 8-bit receive data */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H */
+/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-i2c.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "pic32mx-memorymap.h" + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_I2C_CON_OFFSET 0x0000 /* I2C control register */ +#define PIC32MX_I2C_CONCLR_OFFSET 0x0004 /* I2C control clear register */ +#define PIC32MX_I2C_CONSET_OFFSET 0x0008 /* I2C control set register */ +#define PIC32MX_I2C_CONINV_OFFSET 0x000c /* I2C control invert register */ +#define PIC32MX_I2C_STAT_OFFSET 0x0010 /* I2C status register */ +#define PIC32MX_I2C_STATCLR_OFFSET 0x0014 /* I2C status clear register */ +#define PIC32MX_I2C_STATSET_OFFSET 0x0018 /* I2C status set register */ +#define PIC32MX_I2C_STATINV_OFFSET 0x001c /* I2C status invert register */ +#define PIC32MX_I2C_ADD_OFFSET 0x0020 /* I2C address register */ +#define PIC32MX_I2C_ADDCLR_OFFSET 0x0024 /* I2C address clear register */ +#define PIC32MX_I2C_ADDSET_OFFSET 0x0028 /* I2C address set register */ +#define PIC32MX_I2C_ADDINV_OFFSET 0x002c /* I2C address invert register */ +#define PIC32MX_I2C_MSK_OFFSET 0x0030 /* I2C address mask register */ +#define PIC32MX_I2C_MSKCLR_OFFSET 0x0034 /* I2C address mask clear register */ +#define PIC32MX_I2C_MSKSET_OFFSET 0x0038 /* I2C address mask set register */ +#define PIC32MX_I2C_MSKINV_OFFSET 0x003c /* I2C address mask invert register */ +#define PIC32MX_I2C_BRG_OFFSET 0x0040 /* Baud rate generator reload register */ +#define PIC32MX_I2C_BRGCLR_OFFSET 0x0044 /* Baud rate generator reload set register */ +#define PIC32MX_I2C_BRGSET_OFFSET 0x0048 /* Baud rate generator reload clear register */ +#define PIC32MX_I2C_BRGINV_OFFSET 0x004c /* Baud rate generator reload invert register */ +#define PIC32MX_I2C_TRN_OFFSET 0x0050 /* I2C transmit register */ +#define PIC32MX_I2C_TRNCLR_OFFSET 0x0054 /* I2C transmit clear register */ +#define PIC32MX_I2C_TRNSET_OFFSET 0x0058 /* I2C transmit set register */ +#define PIC32MX_I2C_TRNINV_OFFSET 0x005c /* I2C transmit invert register */ +#define PIC32MX_I2C_RCV_OFFSET 0x0060 /* I2C receive buffer register */ + +/* Register Addresses ***************************************************************/ + +#if CHIP_NI2C > 0 +# define PIC32MX_I2C1_CON (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CON_OFFSET) +# define PIC32MX_I2C1_CONCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONCLR_OFFSET) +# define PIC32MX_I2C1_CONSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONSET_OFFSET) +# define PIC32MX_I2C1_CONINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONINV_OFFSET) +# define PIC32MX_I2C1_STAT (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STAT_OFFSET) +# define PIC32MX_I2C1_STATCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATCLR_OFFSET) +# define PIC32MX_I2C1_STATSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATSET_OFFSET) +# define PIC32MX_I2C1_STATINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATINV_OFFSET) +# define PIC32MX_I2C1_ADD (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADD_OFFSET) +# define PIC32MX_I2C1_ADDCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET) +# define PIC32MX_I2C1_ADDSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDSET_OFFSET) +# define PIC32MX_I2C1_ADDINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDINV_OFFSET) +# define PIC32MX_I2C1_MSK (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSK_OFFSET) +# define PIC32MX_I2C1_MSKCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET) +# define PIC32MX_I2C1_MSKSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKSET_OFFSET) +# define PIC32MX_I2C1_MSKINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKINV_OFFSET) +# define PIC32MX_I2C1_BRG (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRG_OFFSET) +# define PIC32MX_I2C1_BRGSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGSET_OFFSET) +# define PIC32MX_I2C1_BRGCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET) +# define PIC32MX_I2C1_BRGINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGINV_OFFSET) +# define PIC32MX_I2C1_TRN (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRN_OFFSET) +# define PIC32MX_I2C1_TRNCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET) +# define PIC32MX_I2C1_TRNSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNSET_OFFSET) +# define PIC32MX_I2C1_TRNINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNINV_OFFSET) +# define PIC32MX_I2C1_RCV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_RCV_OFFSET) +#endif + +#if CHIP_NI2C > 1 +# define PIC32MX_I2C2_CON (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CON_OFFSET) +# define PIC32MX_I2C2_CONCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONCLR_OFFSET) +# define PIC32MX_I2C2_CONSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONSET_OFFSET) +# define PIC32MX_I2C2_CONINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONINV_OFFSET) +# define PIC32MX_I2C2_STAT (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STAT_OFFSET) +# define PIC32MX_I2C2_STATCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATCLR_OFFSET) +# define PIC32MX_I2C2_STATSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATSET_OFFSET) +# define PIC32MX_I2C2_STATINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATINV_OFFSET) +# define PIC32MX_I2C2_ADD (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADD_OFFSET) +# define PIC32MX_I2C2_ADDCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET) +# define PIC32MX_I2C2_ADDSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDSET_OFFSET) +# define PIC32MX_I2C2_ADDINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDINV_OFFSET) +# define PIC32MX_I2C2_MSK (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSK_OFFSET) +# define PIC32MX_I2C2_MSKCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET) +# define PIC32MX_I2C2_MSKSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKSET_OFFSET) +# define PIC32MX_I2C2_MSKINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKINV_OFFSET) +# define PIC32MX_I2C2_BRG (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRG_OFFSET) +# define PIC32MX_I2C2_BRGSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGSET_OFFSET) +# define PIC32MX_I2C2_BRGCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET) +# define PIC32MX_I2C2_BRGINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGINV_OFFSET) +# define PIC32MX_I2C2_TRN (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRN_OFFSET) +# define PIC32MX_I2C2_TRNCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET) +# define PIC32MX_I2C2_TRNSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNSET_OFFSET) +# define PIC32MX_I2C2_TRNINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNINV_OFFSET) +# define PIC32MX_I2C2_RCV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_RCV_OFFSET) +#endif + +#if CHIP_NI2C > 2 +# define PIC32MX_I2C3_CON (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CON_OFFSET) +# define PIC32MX_I2C3_CONCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONCLR_OFFSET) +# define PIC32MX_I2C3_CONSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONSET_OFFSET) +# define PIC32MX_I2C3_CONINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONINV_OFFSET) +# define PIC32MX_I2C3_STAT (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STAT_OFFSET) +# define PIC32MX_I2C3_STATCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATCLR_OFFSET) +# define PIC32MX_I2C3_STATSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATSET_OFFSET) +# define PIC32MX_I2C3_STATINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATINV_OFFSET) +# define PIC32MX_I2C3_ADD (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADD_OFFSET) +# define PIC32MX_I2C3_ADDCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET) +# define PIC32MX_I2C3_ADDSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDSET_OFFSET) +# define PIC32MX_I2C3_ADDINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDINV_OFFSET) +# define PIC32MX_I2C3_MSK (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSK_OFFSET) +# define PIC32MX_I2C3_MSKCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET) +# define PIC32MX_I2C3_MSKSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKSET_OFFSET) +# define PIC32MX_I2C3_MSKINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKINV_OFFSET) +# define PIC32MX_I2C3_BRG (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRG_OFFSET) +# define PIC32MX_I2C3_BRGSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGSET_OFFSET) +# define PIC32MX_I2C3_BRGCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET) +# define PIC32MX_I2C3_BRGINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGINV_OFFSET) +# define PIC32MX_I2C3_TRN (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRN_OFFSET) +# define PIC32MX_I2C3_TRNCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET) +# define PIC32MX_I2C3_TRNSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNSET_OFFSET) +# define PIC32MX_I2C3_TRNINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNINV_OFFSET) +# define PIC32MX_I2C3_RCV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_RCV_OFFSET) +#endif + +#if CHIP_NI2C > 3 +# define PIC32MX_I2C4_CON (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CON_OFFSET) +# define PIC32MX_I2C4_CONCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONCLR_OFFSET) +# define PIC32MX_I2C4_CONSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONSET_OFFSET) +# define PIC32MX_I2C4_CONINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONINV_OFFSET) +# define PIC32MX_I2C4_STAT (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STAT_OFFSET) +# define PIC32MX_I2C4_STATCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATCLR_OFFSET) +# define PIC32MX_I2C4_STATSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATSET_OFFSET) +# define PIC32MX_I2C4_STATINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATINV_OFFSET) +# define PIC32MX_I2C4_ADD (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADD_OFFSET) +# define PIC32MX_I2C4_ADDCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET) +# define PIC32MX_I2C4_ADDSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDSET_OFFSET) +# define PIC32MX_I2C4_ADDINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDINV_OFFSET) +# define PIC32MX_I2C4_MSK (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSK_OFFSET) +# define PIC32MX_I2C4_MSKCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET) +# define PIC32MX_I2C4_MSKSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKSET_OFFSET) +# define PIC32MX_I2C4_MSKINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKINV_OFFSET) +# define PIC32MX_I2C4_BRG (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRG_OFFSET) +# define PIC32MX_I2C4_BRGSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGSET_OFFSET) +# define PIC32MX_I2C4_BRGCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET) +# define PIC32MX_I2C4_BRGINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGINV_OFFSET) +# define PIC32MX_I2C4_TRN (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRN_OFFSET) +# define PIC32MX_I2C4_TRNCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET) +# define PIC32MX_I2C4_TRNSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNSET_OFFSET) +# define PIC32MX_I2C4_TRNINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNINV_OFFSET) +# define PIC32MX_I2C4_RCV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_RCV_OFFSET) +#endif + +#if CHIP_NI2C > 4 +# define PIC32MX_I2C5_CON (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CON_OFFSET) +# define PIC32MX_I2C5_CONCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONCLR_OFFSET) +# define PIC32MX_I2C5_CONSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONSET_OFFSET) +# define PIC32MX_I2C5_CONINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONINV_OFFSET) +# define PIC32MX_I2C5_STAT (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STAT_OFFSET) +# define PIC32MX_I2C5_STATCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATCLR_OFFSET) +# define PIC32MX_I2C5_STATSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATSET_OFFSET) +# define PIC32MX_I2C5_STATINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATINV_OFFSET) +# define PIC32MX_I2C5_ADD (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADD_OFFSET) +# define PIC32MX_I2C5_ADDCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET) +# define PIC32MX_I2C5_ADDSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDSET_OFFSET) +# define PIC32MX_I2C5_ADDINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDINV_OFFSET) +# define PIC32MX_I2C5_MSK (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSK_OFFSET) +# define PIC32MX_I2C5_MSKCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET) +# define PIC32MX_I2C5_MSKSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKSET_OFFSET) +# define PIC32MX_I2C5_MSKINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKINV_OFFSET) +# define PIC32MX_I2C5_BRG (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRG_OFFSET) +# define PIC32MX_I2C5_BRGSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGSET_OFFSET) +# define PIC32MX_I2C5_BRGCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET) +# define PIC32MX_I2C5_BRGINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGINV_OFFSET) +# define PIC32MX_I2C5_TRN (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRN_OFFSET) +# define PIC32MX_I2C5_TRNCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET) +# define PIC32MX_I2C5_TRNSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNSET_OFFSET) +# define PIC32MX_I2C5_TRNINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNINV_OFFSET) +# define PIC32MX_I2C5_RCV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_RCV_OFFSET) +#endif + +/* Register Bit-Field Definitions ***************************************************/ + +/* I2C control register */ + +#define I2C_CON_SEN (1 << 0) /* Bit 0: Start condition enable */ +#define I2C_CON_RSEN (1 << 1) /* Bit 1: Restart condition enable */ +#define I2C_CON_PEN (1 << 2) /* Bit 2: Stop condition enable */ +#define I2C_CON_RCEN (1 << 3) /* Bit 3: Receive enable */ +#define I2C_CON_ACKEN (1 << 4) /* Bit 4: Acknowledge sequence enable */ +#define I2C_CON_ACKDT (1 << 5) /* Bit 5: Acknowledge data */ +#define I2C_CON_STREN (1 << 6) /* Bit 6: SCL clock stretch enable */ +#define I2C_CON_GCEN (1 << 7) /* Bit 7: General call enable */ +#define I2C_CON_SMEN (1 << 8) /* Bit 8: SMBus input levels disable */ +#define I2C_CON_DISSLW (1 << 9) /* Bit 9: Slew rate control disable */ +#define I2C_CON_A10M (1 << 10) /* Bit 10: 10-bit slave addrewss flag */ +#define I2C_CON_STRICT (1 << 11) /* Bit 11: Strict I2C reserved address rules enable */ +#define I2C_CON_SCLREL (1 << 12) /* Bit 12: SCL release control */ +#define I2C_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +#define I2C_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug mode control */ +#define I2C_CON_ON (1 << 15) /* Bit 15: I2C enable */ + +/* I2C status register */ + +#define I2C_STAT_TBF (1 << 0) /* Bit 0: Transmit buffer full */ +#define I2C_STAT_RBF (1 << 1) /* Bit 1: Receive buffer full */ +#define I2C_STAT_RW (1 << 2) /* Bit 2: Read/write information */ +#define I2C_STAT_S (1 << 3) /* Bit 3: Start */ +#define I2C_STAT_P (1 << 4) /* Bit 4: Stop */ +#define I2C_STAT_DA (1 << 5) /* Bit 5: Data/address */ +#define I2C_STAT_I2COV (1 << 6) /* Bit 6: I2C overflow status */ +#define I2C_STAT_IWCOL (1 << 7) /* Bit 7: Write collision detect */ +#define I2C_STAT_ADD10 (1 << 8) /* Bit 8: 10-bit address status */ +#define I2C_STAT_GCSTAT (1 << 9) /* Bit 9: General call status */ +#define I2C_STAT_BCL (1 << 10) /* Bit 10: Master bus collision detect */ +#define I2C_STAT_TRSTAT (1 << 14) /* Bit 14: Transmit status */ +#define I2C_STAT_ACKSTAT (1 << 15) /* Bit 15: Acknowledge status */ + +/* I2C address register */ + +#define I2C_ADD_MASK 0x3ff /* 10-bit I2C address */ + +/* I2C address mask register */ + +#define I2C_MSK_MASK 0x3ff /* 10-bit I2C address mask */ + +/* Baud rate generator reload register */ + +#define I2C_BRG_MASK 0xfff /* 12-bit I2C BRG value */ + +/* I2C transmit register */ + +#define I2C_TRN_MASK 0xff /* 8-bit transmit data */ + +/* I2C receive buffer register */ + +#define I2C_RCV_MASK 0xff /* 8-bit receive data */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H */ diff --git a/nuttx/configs/pic32-starterkit/README.txt b/nuttx/configs/pic32-starterkit/README.txt index a27deecce..3fe6c9e79 100644 --- a/nuttx/configs/pic32-starterkit/README.txt +++ b/nuttx/configs/pic32-starterkit/README.txt @@ -1037,3 +1037,39 @@ Where <subdir> is one of the following: examples/usbstorage - There are some hooks in the appconfig file to enable the USB mass storage device. However, this device cannot work until support for the SD card is also incorporated. + + Networking Configuations. + ------------------------- + Several Networking configurations can be enabled and included + as NSH built-in built in functions. The following additional + configuration settings are required: + + CONFIG_NET=y : Enable networking support + CONFIG_PIC32MX_ETHERNET=y : Enable the PIC32 Ethernet driver + CONFIG_NSH_TELNET=y : Enable the Telnet NSH console (optional) + + NOTES: + 1. This logic will assume that a network is connected. During its + initialization, it will try to negotiate the link speed. If you have + no network connected when you reset the board, there will be a long + delay (maybe 30 seconds?) before anything happens. That is the timeout + before the networking finally gives up and decides that no network is + available. + + 2. This example can support an FTP client. In order to build in FTP client + support simply uncomment the following lines in the appconfig file (before + configuring) or in the apps/.config file (after configuring): + + #CONFIGURED_APPS += netutils/ftpc + #CONFIGURED_APPS += examples/ftpc + + 3. This example can support an FTP server. In order to build in FTP server + support simply uncomment the following lines in the appconfig file (before + configuring) or in the apps/.config file (after configuring): + + #CONFIGURED_APPS += netutils/ftpd + #CONFIGURED_APPS += examples/ftpd + + And enable poll() support in the NuttX configuration file: + + CONFIG_DISABLE_POLL=n diff --git a/nuttx/configs/pic32-starterkit/nsh/appconfig b/nuttx/configs/pic32-starterkit/nsh/appconfig index bd8aabb47..6fd17ae0c 100644 --- a/nuttx/configs/pic32-starterkit/nsh/appconfig +++ b/nuttx/configs/pic32-starterkit/nsh/appconfig @@ -75,3 +75,41 @@ ifeq ($(CONFIG_PL2303),y) # CONFIGURED_APPS += examples/usbterm endif endif + +############################################################################ +# Networking configurations +############################################################################ + +# Networking libraries. +# Uncomment netutils/ftpc to include an FTP client library +# Uncomment netutils/ftpd to include an FTP server library + +ifeq ($(CONFIG_NET),y) +CONFIGURED_APPS += netutils/uiplib +CONFIGURED_APPS += netutils/resolv +CONFIGURED_APPS += netutils/webclient +CONFIGURED_APPS += netutils/tftpc +#CONFIGURED_APPS += netutils/ftpc +#CONFIGURED_APPS += netutils/ftpd +ifeq ($(CONFIG_NSH_TELNET),y) +CONFIGURED_APPS += netutils/telnetd +endif +endif + +# Uncomment examples/ftpc to include the FTP client example +# Uncomment examples/ftpd to include the FTP daemon example + +ifeq ($(CONFIG_NET),y) +#CONFIGURED_APPS += examples/ftpc +#CONFIGURED_APPS += examples/ftpd +endif + +############################################################################ +# Other pplications that can be configured as an NX built-in commands +############################################################################ + +ifeq ($(CONFIG_I2C),y) +CONFIGURED_APPS += system/i2c +endif + + diff --git a/nuttx/configs/pic32-starterkit/nsh/defconfig b/nuttx/configs/pic32-starterkit/nsh/defconfig index 4f751a7cd..615140a83 100644 --- a/nuttx/configs/pic32-starterkit/nsh/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh/defconfig @@ -194,9 +194,15 @@ CONFIG_PIC32MX_IOPORTG=y # (VBUSON pin is controlled by the USB module, but 0 (GPIO) otherwise. # CONFIG_PIC32MX_WDENABLE - Enabled watchdog on power up. Default 0 (watchdog # can be enabled later by software). +# CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit. 1 (or undefined)= +# Default Ethernet I/O Pins; 0=Alternate Ethernet I/O Pins +# CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit. 1 (or undefined) = MII +# enabled; 0=RMII enabled # CONFIG_PIC32MX_DEBUGGER=2 CONFIG_PIC32MX_ICESEL=1 +CONFIG_PIC32MX_FETHIO=0 +CONFIG_PIC32MX_FMIIEN=0 # # PIC32MX specific serial device driver settings @@ -284,12 +290,10 @@ CONFIG_UART6_2STOP=0 # Automatically set if CONFIG_NET_IGMP is selected. # # Related DEVCFG3 Configuration Settings: -# CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit: -# 1 = Default Ethernet I/O Pins -# 0 = Alternate Ethernet I/O Pins -# CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit -# 1 = MII enabled -# 0 = RMII enabled +# CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit. 1 (or undefined)= +# Default Ethernet I/O Pins; 0=Alternate Ethernet I/O Pins +# CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit. 1 (or undefined) = MII +# enabled; 0=RMII enabled # CONFIG_PHY_KS8721=n CONFIG_PHY_DP83848C=y @@ -338,6 +342,10 @@ CONFIG_HAVE_LIBM=n # CONFIG_DEBUG_VERBOSE - enables verbose debug output # CONFIG_DEBUG_SYMBOLS - build without optimization and with # debug symbols (needed for use with a debugger). +# CONFIG_HAVE_CXX - Enable support for C++ +# CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support +# for initialization of static C++ instances for this architecture +# and for the selected toolchain (via up_cxxinitialize()). # CONFIG_MM_REGIONS - If the architecture includes multiple # regions of memory to allocate from, this specifies the # number of memory regions that the memory manager must @@ -427,6 +435,7 @@ CONFIG_DEBUG_VERBOSE=n CONFIG_DEBUG_SYMBOLS=n CONFIG_DEBUG_SCHED=n CONFIG_DEBUG_USB=n +CONFIG_DEBUG_NET=n CONFIG_HAVE_CXX=n CONFIG_HAVE_CXXINITIALIZE=n @@ -458,7 +467,40 @@ CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n # -# Settings for nxflat +# System Logging +# +# CONFIG_SYSLOG - Enables the System Logging feature. +# CONFIG_RAMLOG - Enables the RAM logging feature +# CONFIG_RAMLOG_CONSOLE - Use the RAM logging device as a system console. +# If this feature is enabled (along with CONFIG_DEV_CONSOLE), then all +# console output will be re-directed to a circular buffer in RAM. This +# is useful, for example, if the only console is a Telnet console. Then +# in that case, console output from non-Telnet threads will go to the +# circular buffer and can be viewed using the NSH 'dmesg' command. +# CONFIG_RAMLOG_SYSLOG - Use the RAM logging device for the syslogging +# interface. If this feature is enabled (along with CONFIG_SYSLOG), +# then all debug output (only) will be re-directed to the circular +# buffer in RAM. This RAM log can be view from NSH using the 'dmesg' +# command. +# CONFIG_RAMLOG_NPOLLWAITERS - The number of threads than can be waiting +# for this driver on poll(). Default: 4 +# +# If CONFIG_RAMLOG_CONSOLE or CONFIG_RAMLOG_SYSLOG is selected, then the +# following may also be provided: +# +# CONFIG_RAMLOG_CONSOLE_BUFSIZE - Size of the console RAM log. Default: 1024 +# + +CONFIG_SYSLOG=n +CONFIG_RAMLOG=n +CONFIG_RAMLOG_CONSOLE=n +CONFIG_RAMLOG_SYSLOG=n +#CONFIG_RAMLOG_NPOLLWAITERS +#CONFIG_RAMLOG_CONSOLE_BUFSIZE + +# +# Settings for NXFLAT +# # CONFIG_NXFLAT. Enable support for the NXFLAT binary format. # This format will support execution of NuttX binaries located # in a ROMFS filesystem (see examples/nxflat). @@ -577,10 +619,19 @@ CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_TIMERS=4 # +# Framebuffer driver options +# +CONFIG_FB_CMAP=n +CONFIG_FB_HWCURSOR=n +CONFIG_FB_HWCURSORIMAGE=n +#CONFIG_FB_HWCURSORSIZE +#CONFIG_FB_TRANSPARENCY + +# # Filesystem configuration # # CONFIG_FS_FAT - Enable FAT filesystem support @@ -711,22 +762,27 @@ CONFIG_NET=n CONFIG_NET_NOINTS=n CONFIG_NET_MULTIBUFFER=y CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 +CONFIG_NSOCKET_DESCRIPTORS=10 CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=n +CONFIG_NET_BUFSIZE=562 +CONFIG_NET_TCP=y CONFIG_NET_TCP_CONNS=40 +#CONFIG_NET_TCP_READAHEAD_BUFSIZE +CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 +CONFIG_NET_TCPBACKLOG=y CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=n +CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y #CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_PING=y #CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y +CONFIG_NET_STATISTICS=n #CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 CONFIG_NET_BROADCAST=n +#CONFIG_NET_ARPTAB_SIZE=8 +CONFIG_NET_ARP_IPIN=n +CONFIG_NET_MULTICAST=n #CONFIG_NET_FWCACHE_SIZE=2 # @@ -738,6 +794,29 @@ CONFIG_NET_DHCP_LIGHT=n CONFIG_NET_RESOLV_ENTRIES=4 # +# FTP Server +# +# CONFIG_FTPD_VENDORID - The vendor name to use in FTP communications. +# Default: "NuttX" +# CONFIG_FTPD_SERVERID - The server name to use in FTP communications. +# Default: "NuttX FTP Server" +# CONFIG_FTPD_CMDBUFFERSIZE - The maximum size of one command. Default: +# 128 bytes. +# CONFIG_FTPD_DATABUFFERSIZE - The size of the I/O buffer for data +# transfers. Default: 512 bytes. +# CONFIG_FTPD_WORKERSTACKSIZE - The stacksize to allocate for each +# FTP daemon worker thread. Default: 2048 bytes. +# +# Other required configuration settings: Of course TCP networking support +# is required. But here are a couple that are less obvious: +# +# CONFIG_DISABLE_PTHREAD - pthread support is required +# CONFIG_DISABLE_POLL - poll() support is required +# +CONFIG_FTPD_CMDBUFFERSIZE=512 +CONFIG_FTPD_DATABUFFERSIZE=2048 + +# # USB Device Configuration # # CONFIG_USBDEV @@ -912,6 +991,156 @@ CONFIG_USBMSC_VERSIONNO=0x0399 CONFIG_USBMSC_REMOVABLE=y # +# Graphics related configuration settings +# +# CONFIG_NX +# Enables overall support for graphics library and NX +# CONFIG_NX_MULTIUSER +# Configures NX in multi-user mode +# CONFIG_NX_NPLANES +# Some YUV color formats requires support for multiple planes, +# one for each color component. Unless you have such special +# hardware, this value should be undefined or set to 1 +# CONFIG_NX_DISABLE_1BPP, CONFIG_NX_DISABLE_2BPP, +# CONFIG_NX_DISABLE_4BPP, CONFIG_NX_DISABLE_8BPP, +# CONFIG_NX_DISABLE_16BPP, CONFIG_NX_DISABLE_24BPP, and +# CONFIG_NX_DISABLE_32BPP +# NX supports a variety of pixel depths. You can save some +# memory by disabling support for unused color depths. +# CONFIG_NX_PACKEDMSFIRST +# If a pixel depth of less than 8-bits is used, then NX needs +# to know if the pixels pack from the MS to LS or from LS to MS +# CONFIG_NX_LCDDRIVER +# By default, NX builds to use a framebuffer driver (see +# include/nuttx/fb.h). If this option is defined, NX will +# build to use an LCD driver (see include/nuttx/lcd/lcd.h). +# CONFIG_LCD_MAXPOWER - The full-on power setting for an LCD device. +# CONFIG_LCD_MAXCONTRAST - The maximum contrast value for an LCD device. +# CONFIG_NX_MOUSE +# Build in support for mouse input +# CONFIG_NX_KBD +# Build in support of keypad/keyboard input +# CONFIG_NXTK_BORDERWIDTH +# Specifies with with of the border (in pixels) used with +# framed windows. The default is 4. +# CONFIG_NXTK_BORDERCOLOR1 and CONFIG_NXTK_BORDERCOLOR2 +# Specify the colors of the border used with framed windows. +# CONFIG_NXTK_BORDERCOLOR2 is the shadow side color and so +# is normally darker. The default is medium and dark grey, +# respectively +# CONFIG_NXTK_AUTORAISE +# If set, a window will be raised to the top if the mouse position +# is over a visible portion of the window. Default: A mouse +# button must be clicked over a visible portion of the window. +# CONFIG_NXFONTS_CHARBITS +# The number of bits in the character set. Current options are +# only 7 and 8. The default is 7. +# CONFIG_NXFONT_SANS17X22 +# This option enables support for a tiny, 17x22 san serif font +# (font ID FONTID_SANS17X22 == 14). +# CONFIG_NXFONT_SANS20X26 +# This option enables support for a tiny, 20x26 san serif font +# (font ID FONTID_SANS20X26 == 15). +# CONFIG_NXFONT_SANS23X27 +# This option enables support for a tiny, 23x27 san serif font +# (font ID FONTID_SANS23X27 == 1). +# CONFIG_NXFONT_SANS22X29 +# This option enables support for a small, 22x29 san serif font +# (font ID FONTID_SANS22X29 == 2). +# CONFIG_NXFONT_SANS28X37 +# This option enables support for a medium, 28x37 san serif font +# (font ID FONTID_SANS28X37 == 3). +# CONFIG_NXFONT_SANS39X48 +# This option enables support for a large, 39x48 san serif font +# (font ID FONTID_SANS39X48 == 4). +# CONFIG_NXFONT_SANS17X23B +# This option enables support for a tiny, 17x23 san serif bold font +# (font ID FONTID_SANS17X23B == 16). +# CONFIG_NXFONT_SANS20X27B +# This option enables support for a tiny, 20x27 san serif bold font +# (font ID FONTID_SANS20X27B == 17). +# CONFIG_NXFONT_SANS22X29B +# This option enables support for a small, 22x29 san serif bold font +# (font ID FONTID_SANS22X29B == 5). +# CONFIG_NXFONT_SANS28X37B +# This option enables support for a medium, 28x37 san serif bold font +# (font ID FONTID_SANS28X37B == 6). +# CONFIG_NXFONT_SANS40X49B +# This option enables support for a large, 40x49 san serif bold font +# (font ID FONTID_SANS40X49B == 7). +# CONFIG_NXFONT_SERIF22X29 +# This option enables support for a small, 22x29 font (with serifs) +# (font ID FONTID_SERIF22X29 == 8). +# CONFIG_NXFONT_SERIF29X37 +# This option enables support for a medium, 29x37 font (with serifs) +# (font ID FONTID_SERIF29X37 == 9). +# CONFIG_NXFONT_SERIF38X48 +# This option enables support for a large, 38x48 font (with serifs) +# (font ID FONTID_SERIF38X48 == 10). +# CONFIG_NXFONT_SERIF22X28B +# This option enables support for a small, 27x38 bold font (with serifs) +# (font ID FONTID_SERIF22X28B == 11). +# CONFIG_NXFONT_SERIF27X38B +# This option enables support for a medium, 27x38 bold font (with serifs) +# (font ID FONTID_SERIF27X38B == 12). +# CONFIG_NXFONT_SERIF38X49B +# This option enables support for a large, 38x49 bold font (with serifs) +# (font ID FONTID_SERIF38X49B == 13). +# +# NX Multi-user only options: +# +# CONFIG_NX_BLOCKING +# Open the client message queues in blocking mode. In this case, +# nx_eventhandler() will not return until a message is received and processed. +# CONFIG_NX_MXSERVERMSGS and CONFIG_NX_MXCLIENTMSGS +# Specifies the maximum number of messages that can fit in +# the message queues. No additional resources are allocated, but +# this can be set to prevent flooding of the client or server with +# too many messages (CONFIG_PREALLOC_MQ_MSGS controls how many +# messages are pre-allocated). +# +CONFIG_NX=n +CONFIG_NX_MULTIUSER=n +CONFIG_NX_NPLANES=1 +CONFIG_NX_DISABLE_1BPP=y +CONFIG_NX_DISABLE_2BPP=y +CONFIG_NX_DISABLE_4BPP=y +CONFIG_NX_DISABLE_8BPP=y +CONFIG_NX_DISABLE_16BPP=n +CONFIG_NX_DISABLE_24BPP=y +CONFIG_NX_DISABLE_32BPP=y +CONFIG_NX_PACKEDMSFIRST=n +CONFIG_NX_LCDDRIVER=y +CONFIG_LCD_MAXPOWER=1 +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_NX_MOUSE=y +CONFIG_NX_KBD=y +#CONFIG_NXTK_BORDERWIDTH=4 +CONFIG_NXTK_BORDERCOLOR1=0xd69a +CONFIG_NXTK_BORDERCOLOR2=0xad55 +CONFIG_NXTK_AUTORAISE=n +CONFIG_NXFONT_SANS17X22=y +CONFIG_NXFONT_SANS20X26=n +CONFIG_NXFONT_SANS22X29=n +CONFIG_NXFONT_SANS23X27=n +CONFIG_NXFONT_SANS28X37=n +CONFIG_NXFONT_SANS17X23B=n +CONFIG_NXFONT_SANS20X27B=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS28X37B=n +CONFIG_NXFONT_SANS40X49B=n +CONFIG_NXFONT_SERIF22X29=n +CONFIG_NXFONT_SERIF29X37=n +CONFIG_NXFONT_SERIF38X48=n +CONFIG_NXFONT_SERIF22X28B=n +CONFIG_NXFONT_SERIF27X38B=n +CONFIG_NXFONT_SERIF38X49B=n +CONFIG_NXFONTS_CHARBITS=7 +CONFIG_NX_BLOCKING=y +CONFIG_NX_MXSERVERMSGS=32 +CONFIG_NX_MXCLIENTMSGS=16 + +# # Settings for examples/uip # CONFIG_EXAMPLE_UIP_IPADDR=(10<<24|0<<16|0<<8|2) @@ -1020,6 +1249,55 @@ CONFIG_NSH_MMCSDSLOTNO=0 CONFIG_NSH_MMCSDMINOR=0 # +# I2C tool settings +# +# CONFIG_I2CTOOL_BUILTIN - Build the tools as an NSH built-in command +# CONFIG_I2CTOOL_MINBUS - Smallest bus index supported by the hardware (default 0). +# CONFIG_I2CTOOL_MAXBUS - Largest bus index supported by the hardware (default 3) +# CONFIG_I2CTOOL_MINADDR - Minium device address (default: 0x03) +# CONFIG_I2CTOOL_MAXADDR - Largest device address (default: 0x77) +# CONFIG_I2CTOOL_MAXREGADDR - Largest register address (default: 0xff) +# CONFIG_I2CTOOL_DEFFREQ - Default frequency (default: 1000000) +# +CONFIG_I2CTOOL_BUILTIN=y +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2CTOOL_MAXBUS=4 +#CONFIG_I2CTOOL_MINADDR +#CONFIG_I2CTOOL_MAXADDR +#CONFIG_I2CTOOL_MAXREGADDR +CONFIG_I2CTOOL_DEFFREQ=100000 + +# +# Settings for examples/ftpd +# +# CONFIG_EXAMPLES_FTPD_PRIO - Priority of the FTP daemon. +# Default: SCHED_PRIORITY_DEFAULT +# CONFIG_EXAMPLES_FTPD_STACKSIZE - Stack size allocated for the +# FTP daemon. Default: 2048 +# CONFIG_EXAMPLES_FTPD_NONETINIT - Define to suppress configuration of the +# network by apps/examples/ftpd. You would need to suppress network +# configuration if the network is configuration prior to running the +# example. +# +# NSH always initializes the network so if CONFIG_NSH_BUILTIN_APPS is +# defined, so is CONFIG_EXAMPLES_FTPD_NONETINIT (se it does not explicitly +# need to be defined in that case): +# +# CONFIG_NSH_BUILTIN_APPS - Build the FTPD daemon example test as an +# NSH built-in function. By default the FTPD daemon will be built +# as a standalone application. +# +# If CONFIG_EXAMPLES_FTPD_NONETINIT is not defined, then the following may +# be specified to customized the network configuration: +# +# CONFIG_EXAMPLE_FTPD_NOMAC - If the hardware has no MAC address of its +# own, define this =y to provide a bogus address for testing. +# CONFIG_EXAMPLE_FTPD_IPADDR - The target IP address. Default 10.0.0.2 +# CONFIG_EXAMPLE_FTPD_DRIPADDR - The default router address. Default +# 10.0.0.1 +# CONFIG_EXAMPLE_FTPD_NETMASK - The network mask. Default: 255.255.255.0 + +# # Settings for examples/usbserial # # CONFIG_EXAMPLES_USBSERIAL_INONLY diff --git a/nuttx/configs/pic32-starterkit/ostest/defconfig b/nuttx/configs/pic32-starterkit/ostest/defconfig index b48bf042a..cd968afc7 100644 --- a/nuttx/configs/pic32-starterkit/ostest/defconfig +++ b/nuttx/configs/pic32-starterkit/ostest/defconfig @@ -194,9 +194,15 @@ CONFIG_PIC32MX_IOPORTG=y # (VBUSON pin is controlled by the USB module, but 0 (GPIO) otherwise. # CONFIG_PIC32MX_WDENABLE - Enabled watchdog on power up. Default 0 (watchdog # can be enabled later by software). +# CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit. 1 (or undefined)= +# Default Ethernet I/O Pins; 0=Alternate Ethernet I/O Pins +# CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit. 1 (or undefined) = MII +# enabled; 0=RMII enabled # CONFIG_PIC32MX_DEBUGGER=2 CONFIG_PIC32MX_ICESEL=1 +CONFIG_PIC32MX_FETHIO=0 +CONFIG_PIC32MX_FMIIEN=0 # # PIC32MX specific serial device driver settings @@ -284,12 +290,10 @@ CONFIG_UART6_2STOP=0 # Automatically set if CONFIG_NET_IGMP is selected. # # Related DEVCFG3 Configuration Settings: -# CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit: -# 1 = Default Ethernet I/O Pins -# 0 = Alternate Ethernet I/O Pins -# CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit -# 1 = MII enabled -# 0 = RMII enabled +# CONFIG_PIC32MX_FETHIO: Ethernet I/O Pin Selection bit. 1 (or undefined)= +# Default Ethernet I/O Pins; 0=Alternate Ethernet I/O Pins +# CONFIG_PIC32MX_FMIIEN: Ethernet MII Enable bit. 1 (or undefined) = MII +# enabled; 0=RMII enabled # CONFIG_PHY_KS8721=n CONFIG_PHY_DP83848C=y @@ -338,6 +342,10 @@ CONFIG_HAVE_LIBM=n # CONFIG_DEBUG_VERBOSE - enables verbose debug output # CONFIG_DEBUG_SYMBOLS - build without optimization and with # debug symbols (needed for use with a debugger). +# CONFIG_HAVE_CXX - Enable support for C++ +# CONFIG_HAVE_CXXINITIALIZE - The platform-specific logic includes support +# for initialization of static C++ instances for this architecture +# and for the selected toolchain (via up_cxxinitialize()). # CONFIG_MM_REGIONS - If the architecture includes multiple # regions of memory to allocate from, this specifies the # number of memory regions that the memory manager must @@ -457,7 +465,40 @@ CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n # -# Settings for nxflat +# System Logging +# +# CONFIG_SYSLOG - Enables the System Logging feature. +# CONFIG_RAMLOG - Enables the RAM logging feature +# CONFIG_RAMLOG_CONSOLE - Use the RAM logging device as a system console. +# If this feature is enabled (along with CONFIG_DEV_CONSOLE), then all +# console output will be re-directed to a circular buffer in RAM. This +# is useful, for example, if the only console is a Telnet console. Then +# in that case, console output from non-Telnet threads will go to the +# circular buffer and can be viewed using the NSH 'dmesg' command. +# CONFIG_RAMLOG_SYSLOG - Use the RAM logging device for the syslogging +# interface. If this feature is enabled (along with CONFIG_SYSLOG), +# then all debug output (only) will be re-directed to the circular +# buffer in RAM. This RAM log can be view from NSH using the 'dmesg' +# command. +# CONFIG_RAMLOG_NPOLLWAITERS - The number of threads than can be waiting +# for this driver on poll(). Default: 4 +# +# If CONFIG_RAMLOG_CONSOLE or CONFIG_RAMLOG_SYSLOG is selected, then the +# following may also be provided: +# +# CONFIG_RAMLOG_CONSOLE_BUFSIZE - Size of the console RAM log. Default: 1024 +# + +CONFIG_SYSLOG=n +CONFIG_RAMLOG=n +CONFIG_RAMLOG_CONSOLE=n +CONFIG_RAMLOG_SYSLOG=n +#CONFIG_RAMLOG_NPOLLWAITERS +#CONFIG_RAMLOG_CONSOLE_BUFSIZE + +# +# Settings for NXFLAT +# # CONFIG_NXFLAT. Enable support for the NXFLAT binary format. # This format will support execution of NuttX binaries located # in a ROMFS filesystem (see examples/nxflat). @@ -580,6 +621,15 @@ CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_TIMERS=4 # +# Framebuffer driver options +# +CONFIG_FB_CMAP=n +CONFIG_FB_HWCURSOR=n +CONFIG_FB_HWCURSORIMAGE=n +#CONFIG_FB_HWCURSORSIZE +#CONFIG_FB_TRANSPARENCY + +# # Filesystem configuration # # CONFIG_FS_FAT - Enable FAT filesystem support @@ -702,19 +752,26 @@ CONFIG_MMCSD_HAVECARDDETECT=n # CONFIG_NET_PINGADDRCONF - Use "ping" packet for setting IP address # CONFIG_NET_STATISTICS - uIP statistics on or off # CONFIG_NET_RECEIVE_WINDOW - The size of the advertised receiver's window -# CONFIG_NET_ARPTAB_SIZE - The size of the ARP table # CONFIG_NET_BROADCAST - Broadcast support -# CONFIG_NET_FWCACHE_SIZE - number of packets to remember when looking for duplicates +# CONFIG_NET_ARPTAB_SIZE - The size of the ARP table +# CONFIG_NET_ARP_IPIN - Harvest IP/MAC address mappings from the ARP table +# from incoming IP packets. +# CONFIG_NET_MULTICAST - Outgoing multi-cast address support +# CONFIG_NET_FWCACHE_SIZE - number of packets to remember when +# looking for duplicates # CONFIG_NET=n CONFIG_NET_NOINTS=n CONFIG_NET_MULTIBUFFER=y CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 +CONFIG_NSOCKET_DESCRIPTORS=10 CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 +CONFIG_NET_BUFSIZE=562 CONFIG_NET_TCP=n CONFIG_NET_TCP_CONNS=40 +#CONFIG_NET_TCP_READAHEAD_BUFSIZE +CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 +CONFIG_NET_TCPBACKLOG=y CONFIG_NET_MAX_LISTENPORTS=40 CONFIG_NET_UDP=n CONFIG_NET_UDP_CHECKSUMS=y @@ -722,10 +779,12 @@ CONFIG_NET_UDP_CHECKSUMS=y CONFIG_NET_ICMP=n CONFIG_NET_ICMP_PING=n #CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y +CONFIG_NET_STATISTICS=n #CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 CONFIG_NET_BROADCAST=n +#CONFIG_NET_ARPTAB_SIZE=8 +CONFIG_NET_ARP_IPIN=n +CONFIG_NET_MULTICAST=n #CONFIG_NET_FWCACHE_SIZE=2 # @@ -737,6 +796,29 @@ CONFIG_NET_DHCP_LIGHT=n CONFIG_NET_RESOLV_ENTRIES=4 # +# FTP Server +# +# CONFIG_FTPD_VENDORID - The vendor name to use in FTP communications. +# Default: "NuttX" +# CONFIG_FTPD_SERVERID - The server name to use in FTP communications. +# Default: "NuttX FTP Server" +# CONFIG_FTPD_CMDBUFFERSIZE - The maximum size of one command. Default: +# 128 bytes. +# CONFIG_FTPD_DATABUFFERSIZE - The size of the I/O buffer for data +# transfers. Default: 512 bytes. +# CONFIG_FTPD_WORKERSTACKSIZE - The stacksize to allocate for each +# FTP daemon worker thread. Default: 2048 bytes. +# +# Other required configuration settings: Of course TCP networking support +# is required. But here are a couple that are less obvious: +# +# CONFIG_DISABLE_PTHREAD - pthread support is required +# CONFIG_DISABLE_POLL - poll() support is required +# +CONFIG_FTPD_CMDBUFFERSIZE=512 +CONFIG_FTPD_DATABUFFERSIZE=2048 + +# # USB Device Configuration # # CONFIG_USBDEV @@ -911,6 +993,156 @@ CONFIG_USBMSC_VERSIONNO=0x0399 CONFIG_USBMSC_REMOVABLE=y # +# Graphics related configuration settings +# +# CONFIG_NX +# Enables overall support for graphics library and NX +# CONFIG_NX_MULTIUSER +# Configures NX in multi-user mode +# CONFIG_NX_NPLANES +# Some YUV color formats requires support for multiple planes, +# one for each color component. Unless you have such special +# hardware, this value should be undefined or set to 1 +# CONFIG_NX_DISABLE_1BPP, CONFIG_NX_DISABLE_2BPP, +# CONFIG_NX_DISABLE_4BPP, CONFIG_NX_DISABLE_8BPP, +# CONFIG_NX_DISABLE_16BPP, CONFIG_NX_DISABLE_24BPP, and +# CONFIG_NX_DISABLE_32BPP +# NX supports a variety of pixel depths. You can save some +# memory by disabling support for unused color depths. +# CONFIG_NX_PACKEDMSFIRST +# If a pixel depth of less than 8-bits is used, then NX needs +# to know if the pixels pack from the MS to LS or from LS to MS +# CONFIG_NX_LCDDRIVER +# By default, NX builds to use a framebuffer driver (see +# include/nuttx/fb.h). If this option is defined, NX will +# build to use an LCD driver (see include/nuttx/lcd/lcd.h). +# CONFIG_LCD_MAXPOWER - The full-on power setting for an LCD device. +# CONFIG_LCD_MAXCONTRAST - The maximum contrast value for an LCD device. +# CONFIG_NX_MOUSE +# Build in support for mouse input +# CONFIG_NX_KBD +# Build in support of keypad/keyboard input +# CONFIG_NXTK_BORDERWIDTH +# Specifies with with of the border (in pixels) used with +# framed windows. The default is 4. +# CONFIG_NXTK_BORDERCOLOR1 and CONFIG_NXTK_BORDERCOLOR2 +# Specify the colors of the border used with framed windows. +# CONFIG_NXTK_BORDERCOLOR2 is the shadow side color and so +# is normally darker. The default is medium and dark grey, +# respectively +# CONFIG_NXTK_AUTORAISE +# If set, a window will be raised to the top if the mouse position +# is over a visible portion of the window. Default: A mouse +# button must be clicked over a visible portion of the window. +# CONFIG_NXFONTS_CHARBITS +# The number of bits in the character set. Current options are +# only 7 and 8. The default is 7. +# CONFIG_NXFONT_SANS17X22 +# This option enables support for a tiny, 17x22 san serif font +# (font ID FONTID_SANS17X22 == 14). +# CONFIG_NXFONT_SANS20X26 +# This option enables support for a tiny, 20x26 san serif font +# (font ID FONTID_SANS20X26 == 15). +# CONFIG_NXFONT_SANS23X27 +# This option enables support for a tiny, 23x27 san serif font +# (font ID FONTID_SANS23X27 == 1). +# CONFIG_NXFONT_SANS22X29 +# This option enables support for a small, 22x29 san serif font +# (font ID FONTID_SANS22X29 == 2). +# CONFIG_NXFONT_SANS28X37 +# This option enables support for a medium, 28x37 san serif font +# (font ID FONTID_SANS28X37 == 3). +# CONFIG_NXFONT_SANS39X48 +# This option enables support for a large, 39x48 san serif font +# (font ID FONTID_SANS39X48 == 4). +# CONFIG_NXFONT_SANS17X23B +# This option enables support for a tiny, 17x23 san serif bold font +# (font ID FONTID_SANS17X23B == 16). +# CONFIG_NXFONT_SANS20X27B +# This option enables support for a tiny, 20x27 san serif bold font +# (font ID FONTID_SANS20X27B == 17). +# CONFIG_NXFONT_SANS22X29B +# This option enables support for a small, 22x29 san serif bold font +# (font ID FONTID_SANS22X29B == 5). +# CONFIG_NXFONT_SANS28X37B +# This option enables support for a medium, 28x37 san serif bold font +# (font ID FONTID_SANS28X37B == 6). +# CONFIG_NXFONT_SANS40X49B +# This option enables support for a large, 40x49 san serif bold font +# (font ID FONTID_SANS40X49B == 7). +# CONFIG_NXFONT_SERIF22X29 +# This option enables support for a small, 22x29 font (with serifs) +# (font ID FONTID_SERIF22X29 == 8). +# CONFIG_NXFONT_SERIF29X37 +# This option enables support for a medium, 29x37 font (with serifs) +# (font ID FONTID_SERIF29X37 == 9). +# CONFIG_NXFONT_SERIF38X48 +# This option enables support for a large, 38x48 font (with serifs) +# (font ID FONTID_SERIF38X48 == 10). +# CONFIG_NXFONT_SERIF22X28B +# This option enables support for a small, 27x38 bold font (with serifs) +# (font ID FONTID_SERIF22X28B == 11). +# CONFIG_NXFONT_SERIF27X38B +# This option enables support for a medium, 27x38 bold font (with serifs) +# (font ID FONTID_SERIF27X38B == 12). +# CONFIG_NXFONT_SERIF38X49B +# This option enables support for a large, 38x49 bold font (with serifs) +# (font ID FONTID_SERIF38X49B == 13). +# +# NX Multi-user only options: +# +# CONFIG_NX_BLOCKING +# Open the client message queues in blocking mode. In this case, +# nx_eventhandler() will not return until a message is received and processed. +# CONFIG_NX_MXSERVERMSGS and CONFIG_NX_MXCLIENTMSGS +# Specifies the maximum number of messages that can fit in +# the message queues. No additional resources are allocated, but +# this can be set to prevent flooding of the client or server with +# too many messages (CONFIG_PREALLOC_MQ_MSGS controls how many +# messages are pre-allocated). +# +CONFIG_NX=n +CONFIG_NX_MULTIUSER=n +CONFIG_NX_NPLANES=1 +CONFIG_NX_DISABLE_1BPP=y +CONFIG_NX_DISABLE_2BPP=y +CONFIG_NX_DISABLE_4BPP=y +CONFIG_NX_DISABLE_8BPP=y +CONFIG_NX_DISABLE_16BPP=n +CONFIG_NX_DISABLE_24BPP=y +CONFIG_NX_DISABLE_32BPP=y +CONFIG_NX_PACKEDMSFIRST=n +CONFIG_NX_LCDDRIVER=y +CONFIG_LCD_MAXPOWER=1 +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_NX_MOUSE=y +CONFIG_NX_KBD=y +#CONFIG_NXTK_BORDERWIDTH=4 +CONFIG_NXTK_BORDERCOLOR1=0xd69a +CONFIG_NXTK_BORDERCOLOR2=0xad55 +CONFIG_NXTK_AUTORAISE=n +CONFIG_NXFONT_SANS17X22=y +CONFIG_NXFONT_SANS20X26=n +CONFIG_NXFONT_SANS22X29=n +CONFIG_NXFONT_SANS23X27=n +CONFIG_NXFONT_SANS28X37=n +CONFIG_NXFONT_SANS17X23B=n +CONFIG_NXFONT_SANS20X27B=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS28X37B=n +CONFIG_NXFONT_SANS40X49B=n +CONFIG_NXFONT_SERIF22X29=n +CONFIG_NXFONT_SERIF29X37=n +CONFIG_NXFONT_SERIF38X48=n +CONFIG_NXFONT_SERIF22X28B=n +CONFIG_NXFONT_SERIF27X38B=n +CONFIG_NXFONT_SERIF38X49B=n +CONFIG_NXFONTS_CHARBITS=7 +CONFIG_NX_BLOCKING=y +CONFIG_NX_MXSERVERMSGS=32 +CONFIG_NX_MXCLIENTMSGS=16 + +# # Settings for examples/uip # CONFIG_EXAMPLE_UIP_IPADDR=(10<<24|0<<16|0<<8|2) @@ -1019,6 +1251,55 @@ CONFIG_NSH_MMCSDSLOTNO=0 CONFIG_NSH_MMCSDMINOR=0 # +# I2C tool settings +# +# CONFIG_I2CTOOL_BUILTIN - Build the tools as an NSH built-in command +# CONFIG_I2CTOOL_MINBUS - Smallest bus index supported by the hardware (default 0). +# CONFIG_I2CTOOL_MAXBUS - Largest bus index supported by the hardware (default 3) +# CONFIG_I2CTOOL_MINADDR - Minium device address (default: 0x03) +# CONFIG_I2CTOOL_MAXADDR - Largest device address (default: 0x77) +# CONFIG_I2CTOOL_MAXREGADDR - Largest register address (default: 0xff) +# CONFIG_I2CTOOL_DEFFREQ - Default frequency (default: 1000000) +# +CONFIG_I2CTOOL_BUILTIN=y +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2CTOOL_MAXBUS=4 +#CONFIG_I2CTOOL_MINADDR +#CONFIG_I2CTOOL_MAXADDR +#CONFIG_I2CTOOL_MAXREGADDR +CONFIG_I2CTOOL_DEFFREQ=100000 + +# +# Settings for examples/ftpd +# +# CONFIG_EXAMPLES_FTPD_PRIO - Priority of the FTP daemon. +# Default: SCHED_PRIORITY_DEFAULT +# CONFIG_EXAMPLES_FTPD_STACKSIZE - Stack size allocated for the +# FTP daemon. Default: 2048 +# CONFIG_EXAMPLES_FTPD_NONETINIT - Define to suppress configuration of the +# network by apps/examples/ftpd. You would need to suppress network +# configuration if the network is configuration prior to running the +# example. +# +# NSH always initializes the network so if CONFIG_NSH_BUILTIN_APPS is +# defined, so is CONFIG_EXAMPLES_FTPD_NONETINIT (se it does not explicitly +# need to be defined in that case): +# +# CONFIG_NSH_BUILTIN_APPS - Build the FTPD daemon example test as an +# NSH built-in function. By default the FTPD daemon will be built +# as a standalone application. +# +# If CONFIG_EXAMPLES_FTPD_NONETINIT is not defined, then the following may +# be specified to customized the network configuration: +# +# CONFIG_EXAMPLE_FTPD_NOMAC - If the hardware has no MAC address of its +# own, define this =y to provide a bogus address for testing. +# CONFIG_EXAMPLE_FTPD_IPADDR - The target IP address. Default 10.0.0.2 +# CONFIG_EXAMPLE_FTPD_DRIPADDR - The default router address. Default +# 10.0.0.1 +# CONFIG_EXAMPLE_FTPD_NETMASK - The network mask. Default: 255.255.255.0 + +# # Settings for examples/usbserial # # CONFIG_EXAMPLES_USBSERIAL_INONLY diff --git a/nuttx/include/nuttx/net/mii.h b/nuttx/include/nuttx/net/mii.h index 50c57245a..6a5fc6e89 100644 --- a/nuttx/include/nuttx/net/mii.h +++ b/nuttx/include/nuttx/net/mii.h @@ -70,9 +70,9 @@ #define MII_MMDCONTROL 0x0d /* MMD access control register */ #define MII_ESTATUS 0x0f /* Extended status register */ -/* Registers 16-31 may be used for vendor specific abilities */ +/* Extended Registers: Registers 16-31 may be used for vendor specific abilities */ -/* DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f reserved */ +/* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f reserved */ #define MII_DP83840_COUNTER 0x12 /* Disconnect counter */ #define MII_DP83840_FCSCOUNTER 0x13 /* False carrier sense counter */ @@ -84,6 +84,21 @@ #define MII_DP83840_10BTSR 0x1b /* 10BASE-T status register */ #define MII_DP83840_10BTCR 0x1c /* 10BASE-T configuration register */ +/* National Semiconductor DP83848C: 0x8-0x15, 0x13, 0x1c reserved */ + +#define MII_DP83848C_PHYSTS 0x10 /* RO PHY Status Register */ +#define MII_DP83848C_MICR 0x11 /* RW MII Interrupt Control Register */ +#define MII_DP83848C_MISR 0x12 /* RO MII Interrupt Status Register */ +#define MII_DP83848C_FCSCR 0x14 /* RO False Carrier Sense Counter Register */ +#define MII_DP83848C_RECR 0x15 /* RO Receive Error Counter Register */ +#define MII_DP83848C_PCSR 0x16 /* RW PCS Sub-Layer Configuration and Status Register */ +#define MII_DP83848C_RBR 0x17 /* RW RMII and Bypass Register */ +#define MII_DP83848C_LEDCR 0x18 /* RW LED Direct Control Register */ +#define MII_DP83848C_PHYCR 0x19 /* RW PHY Control Register */ +#define MII_DP83848C_10BTSCR 0x1a /* RW 10Base-T Status/Control Register */ +#define MII_DP83848C_CDCTRL1 0x1b /* RW CD Test Control Register and BIST Extensions Register */ +#define MII_DP83848C_EDCR 0x1e /* RW Energy Detect */ + /* Am79c874: 0x08-0x0f, 0x14, 0x16, 0x19-0x1f reserved */ #define MII_AM79C874_NPADVERTISE 0x07 /* Auto-negotiation next page advertisement */ @@ -274,6 +289,18 @@ #define MII_PHYID1_DP83848C 0x2000 /* ID1 value for DP83848C */ #define MII_PHYID2_DP83848C 0x5c90 /* ID2 value for DP83848C */ +/* RMII and Bypass Register (0x17) */ + +#define MII_RBR_ELAST_MASK 0x0003 /* Bits 0-1: Receive elasticity buffer */ +# define MII_RBR_ELAST_14 0x0000 /* 14 bit tolerance */ +# define MII_RBR_ELAST_2 0x0001 /* 2 bit tolerance */ +# define MII_RBR_ELAST_6 0x0002 /* 6 bit tolerance */ +# define MII_RBR_ELAST_10 0x0003 /* 10 bit tolerance */ +#define MII_RBR_RXUNFSTS (1 << 2) /* Bit 2: RX FIFO underflow */ +#define MII_RBR_RXOVFSTS (1 << 3) /* Bit 3: RX FIFO overflow */ +#define MII_RBR_RMIIREV10 (1 << 4) /* Bit 4: 0=RMIIv1.2 1-RMIIv1.0 */ +#define MII_RBR_RMIIMODE (1 << 5) /* Bit 5: 0=MII mode 1=RMII mode */ + /* SMSC LAN8720 *************************************************************/ /* SMSC LAN8720 MII ID1/2 register bits */ diff --git a/nuttx/net/getsockname.c b/nuttx/net/getsockname.c index 6706e5e1e..35551ccf3 100644 --- a/nuttx/net/getsockname.c +++ b/nuttx/net/getsockname.c @@ -192,6 +192,7 @@ int getsockname(int sockfd, FAR struct sockaddr *addr, FAR socklen_t *addrlen) /* Set the address family and the IP address */ +#if defined(CONFIG_NET_TCP) || defined(CONFIG_NET_UDP) #ifdef CONFIG_NET_IPv6 #error "Not big enough for IPv6 address" outaddr->sin_family = AF_INET6; @@ -202,6 +203,7 @@ int getsockname(int sockfd, FAR struct sockaddr *addr, FAR socklen_t *addrlen) outaddr->sin_addr.s_addr = dev->d_ipaddr; *addrlen = sizeof(struct sockaddr_in); #endif +#endif netdev_semgive(); /* Return success */ |