LPC1788 header file updates from Rommel Marcelo

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5647 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 270 insertions, 116 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h
index 4179ac965..af0d69243 100644
--- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/********************************************************************************************
  * arch/arm/src/lpc17xx/chip/lpc17_qei.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
@@ -31,89 +31,99 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************************************/
+ ********************************************************************************************/
 
 #ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H
 #define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H
 
-/************************************************************************************
+/********************************************************************************************
  * Included Files
- ************************************************************************************/
+ ********************************************************************************************/
 
 #include <nuttx/config.h>
 
 #include "chip.h"
 #include "chip/lpc17_memorymap.h"
 
-/************************************************************************************
+/********************************************************************************************
  * Pre-processor Definitions
- ************************************************************************************/
+ ********************************************************************************************/
 
-/* Register offsets *****************************************************************/
+/* Register offsets *************************************************************************/
 /* Control registers */
 
-#define LPC17_QEI_CON_OFFSET     0x0000 /* Control register */
-#define LPC17_QEI_STAT_OFFSET    0x0004 /* Encoder status register */
-#define LPC17_QEI_CONF_OFFSET    0x0008 /* Configuration register */
+#define LPC17_QEI_CON_OFFSET          0x0000 /* Control register */
+#define LPC17_QEI_STAT_OFFSET         0x0004 /* Encoder status register */
+#define LPC17_QEI_CONF_OFFSET         0x0008 /* Configuration register */
 
 /* Position, index, and timer registers */
 
-#define LPC17_QEI_POS_OFFSET     0x000c /* Position register */
-#define LPC17_QEI_MAXPOS_OFFSET  0x0010 /* Maximum position register */
-#define LPC17_QEI_CMPOS0_OFFSET  0x0014 /* Position compare register */
-#define LPC17_QEI_CMPOS1_OFFSET  0x0018 /* Position compare register */
-#define LPC17_QEI_CMPOS2_OFFSET  0x001c /* Position compare register */
-#define LPC17_QEI_INXCNT_OFFSET  0x0020 /* Index count register */
-#define LPC17_QEI_INXCMP_OFFSET  0x0024 /* Index compare register */
-#define LPC17_QEI_LOAD_OFFSET    0x0028 /* Velocity timer reload register */
-#define LPC17_QEI_TIME_OFFSET    0x002c /* Velocity timer register */
-#define LPC17_QEI_VEL_OFFSET     0x0030 /* Velocity counter register */
-#define LPC17_QEI_CAP_OFFSET     0x0034 /* Velocity capture register */
-#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
-#define LPC17_QEI_FILTER_OFFSET  0x003c /* Digital filter register */
+#define LPC17_QEI_POS_OFFSET          0x000c /* Position register */
+#define LPC17_QEI_MAXPOS_OFFSET       0x0010 /* Maximum position register */
+#define LPC17_QEI_CMPOS0_OFFSET       0x0014 /* Position compare register */
+#define LPC17_QEI_CMPOS1_OFFSET       0x0018 /* Position compare register */
+#define LPC17_QEI_CMPOS2_OFFSET       0x001c /* Position compare register */
+#define LPC17_QEI_INXCNT_OFFSET       0x0020 /* Index count register */
+#define LPC17_QEI_INXCMP_OFFSET       0x0024 /* Index compare register */
+#define LPC17_QEI_LOAD_OFFSET         0x0028 /* Velocity timer reload register */
+#define LPC17_QEI_TIME_OFFSET         0x002c /* Velocity timer register */
+#define LPC17_QEI_VEL_OFFSET          0x0030 /* Velocity counter register */
+#define LPC17_QEI_CAP_OFFSET          0x0034 /* Velocity capture register */
+#define LPC17_QEI_VELCOMP_OFFSET      0x0038 /* Velocity compare register */
+#define LPC17_QEI_FILTER_OFFSET       0x003c /* Digital filter register */
+
+#ifdef LPC178
+#  define LPC17_QEI_INXCMP0_OFFSET    0x0024 /* Index compare0 register */
+#  define LPC17_QEI_INXCMP1_OFFSET    0x004c /* Index compare1 register */
+#  define LPC17_QEI_INXCMP2_OFFSET    0x0050 /* Index compare2 register */
+#  define LPC17_QEI_FILTER_PHA_OFFSET 0x003c /* Digital filter register */
+#  define LPC17_QEI_FILTER_PHB_OFFSET 0x0040 /* Digital filter register */
+#  define LPC17_QEI_FILTER_INX_OFFSET 0x0044 /* Digital filter register */
+#  define LPC17_QEI_WINDOW_OFFSET     0x0048 /* Index acceptance register */
+#endif
 
 /* Interrupt registers */
 
-#define LPC17_QEI_IEC_OFFSET     0x0fd8 /* Interrupt enable clear register */
-#define LPC17_QEI_IES_OFFSET     0x0fdc /* Interrupt enable set register */
-#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
-#define LPC17_QEI_IE_OFFSET      0x0fe4 /* Interrupt enable register */
-#define LPC17_QEI_CLR_OFFSET     0x0fe8 /* Interrupt status clear register */
-#define LPC17_QEI_SET_OFFSET     0x0fec /* Interrupt status set register */
+#define LPC17_QEI_IEC_OFFSET          0x0fd8 /* Interrupt enable clear register */
+#define LPC17_QEI_IES_OFFSET          0x0fdc /* Interrupt enable set register */
+#define LPC17_QEI_INTSTAT_OFFSET      0x0fe0 /* Interrupt status register */
+#define LPC17_QEI_IE_OFFSET           0x0fe4 /* Interrupt enable register */
+#define LPC17_QEI_CLR_OFFSET          0x0fe8 /* Interrupt status clear register */
+#define LPC17_QEI_SET_OFFSET          0x0fec /* Interrupt status set register */
 
-/* Register addresses ***************************************************************/
+/* Register addresses ***********************************************************************/
 /* Control registers */
 
-#define LPC17_QEI_CON            (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET)
-#define LPC17_QEI_STAT           (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET)
-#define LPC17_QEI_CONF           (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET)
+#define LPC17_QEI_CON                 (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET)
+#define LPC17_QEI_STAT                (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET)
+#define LPC17_QEI_CONF                (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET)
 
 /* Position, index, and timer registers */
 
-#define LPC17_QEI_POS            (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET)
-#define LPC17_QEI_MAXPOS         (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET)
-#define LPC17_QEI_CMPOS0         (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET)
-#define LPC17_QEI_CMPOS1         (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET)
-#define LPC17_QEI_CMPOS2         (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET)
-#define LPC17_QEI_INXCNT         (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET)
-#define LPC17_QEI_INXCMP         (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET)
-#define LPC17_QEI_LOAD           (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET)
-#define LPC17_QEI_TIME           (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET)
-#define LPC17_QEI_VEL            (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET)
-#define LPC17_QEI_CAP            (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET)
-#define LPC17_QEI_VELCOMP        (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET)
-#define LPC17_QEI_FILTER         (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET)
+#define LPC17_QEI_POS                 (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET)
+#define LPC17_QEI_MAXPOS              (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET)
+#define LPC17_QEI_CMPOS0              (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET)
+#define LPC17_QEI_CMPOS1              (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET)
+#define LPC17_QEI_CMPOS2              (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET)
+#define LPC17_QEI_INXCNT              (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET)
+#define LPC17_QEI_INXCMP              (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET)
+#define LPC17_QEI_LOAD                (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET)
+#define LPC17_QEI_TIME                (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET)
+#define LPC17_QEI_VEL                 (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET)
+#define LPC17_QEI_CAP                 (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET)
+#define LPC17_QEI_VELCOMP             (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET)
+#define LPC17_QEI_FILTER              (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET)
 
 /* Interrupt registers */
 
-#define LPC17_QEI_IEC            (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET)
-#define LPC17_QEI_IES            (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET)
-#define LPC17_QEI_INTSTAT        (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET)
-#define LPC17_QEI_IE             (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET)
-#define LPC17_QEI_CLR            (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET)
-#define LPC17_QEI_SET            (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)
+#define LPC17_QEI_IEC                 (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET)
+#define LPC17_QEI_IES                 (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET)
+#define LPC17_QEI_INTSTAT             (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET)
+#define LPC17_QEI_IE                  (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET)
+#define LPC17_QEI_CLR                 (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET)
+#define LPC17_QEI_SET                 (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)
 
-/* Register bit definitions *********************************************************/
+/* Register bit definitions *****************************************************************/
 /* The following registers hold 32-bit integer values and have no bit fields defined
  * in this section:
  *
@@ -135,22 +145,30 @@
 /* Control registers */
 /* Control register */
 
-#define QEI_CON_RESP             (1 << 0)  /* Bit 0:  Reset position counter */
-#define QEI_CON_RESPI            (1 << 1)  /* Bit 1:  Reset position counter on index */
-#define QEI_CON_RESV             (1 << 2)  /* Bit 2:  Reset velocity */
-#define QEI_CON_RESI             (1 << 3)  /* Bit 3:  Reset index counter */
-                                           /* Bits 4-31: reserved */
+#define QEI_CON_RESP                  (1 << 0)  /* Bit 0:  Reset position counter */
+#define QEI_CON_RESPI                 (1 << 1)  /* Bit 1:  Reset position counter on index */
+#define QEI_CON_RESV                  (1 << 2)  /* Bit 2:  Reset velocity */
+#define QEI_CON_RESI                  (1 << 3)  /* Bit 3:  Reset index counter */
+                                                /* Bits 4-31: reserved */
 /* Encoder status register */
 
-#define QEI_STAT_DIR             (1 << 0)  /* Bit 0:  Direction bit */
-                                           /* Bits 1-31: reserved */
+#define QEI_STAT_DIR                  (1 << 0)  /* Bit 0:  Direction bit */
+                                                /* Bits 1-31: reserved */
 /* Configuration register */
 
-#define QEI_CONF_DIRINV          (1 << 0)  /* Bit 0:  Direction invert */
-#define QEI_CONF_SIGMODE         (1 << 1)  /* Bit 1:  Signal Mode */
-#define QEI_CONF_CAPMODE         (1 << 2)  /* Bit 2:  Capture Mode */
-#define QEI_CONF_INVINX          (1 << 3)  /* Bit 3:  Invert Index */
-                                           /* Bits 4-31: reserved */
+#define QEI_CONF_DIRINV               (1 << 0)  /* Bit 0:  Direction invert */
+#define QEI_CONF_SIGMODE              (1 << 1)  /* Bit 1:  Signal Mode */
+#define QEI_CONF_CAPMODE              (1 << 2)  /* Bit 2:  Capture Mode */
+#define QEI_CONF_INVINX               (1 << 3)  /* Bit 3:  Invert Index */
+
+#ifdef LPC178x
+#  define QEI_CONF_CRESPI             (1 << 4)  /* Bit 4:  Continuous Index reset */
+                                                /* Bits 5-15: reserved */
+#  define QEI_CONF_INXGATE_SHIFT      (16)      /* Bit 16:19  Index Gating */
+#  define QEI_CONF_INXGATE_MASK       (15 << QEI_CONF_INXGATE_SHIFT)
+#endif
+                                                /* Bits 20-31: reserved */
+
 /* Position, index, and timer registers (all 32-bit integer values with not bit fields */
 
 /* Interrupt registers */
@@ -160,31 +178,37 @@
  * bit definitions.
  */
 
-#define QEI_INT_INX              (1 << 0)  /* Bit 0:  Index pulse detected */
-#define QEI_INT_TIM              (1 << 1)  /* Bit 1:  Velocity timer overflow occurred */
-#define QEI_INT_VELC             (1 << 2)  /* Bit 2:  Captured velocity less than compare velocity */
-#define QEI_INT_DIR              (1 << 3)  /* Bit 3:  Change of direction detected */
-#define QEI_INT_ERR              (1 << 4)  /* Bit 4:  Encoder phase error detected */
-#define QEI_INT_ENCLK            (1 << 5)  /* Bit 5:  Eencoder clock pulse detected */
-#define QEI_INT_POS0             (1 << 6)  /* Bit 6:  Position 0 compare equal to current position */
-#define QEI_INT_POS1             (1 << 7)  /* Bit 7:  Position 1 compare equal to current position */
-#define QEI_INT_POS2             (1 << 8)  /* Bit 8:  Position 2 compare equal to current position */
-#define QEI_INT_REV              (1 << 9)  /* Bit 9:  Index compare value equal to current index count */
-#define QEI_INT_POS0REV          (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */
-#define QEI_INT_POS1REV          (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
-#define QEI_INT_POS2REV          (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
-                                           /* Bits 13-31: reserved */
-
-/************************************************************************************
+#define QEI_INT_INX                   (1 << 0)  /* Bit 0:  Index pulse detected */
+#define QEI_INT_TIM                   (1 << 1)  /* Bit 1:  Velocity timer overflow occurred */
+#define QEI_INT_VELC                  (1 << 2)  /* Bit 2:  Captured velocity less than compare velocity */
+#define QEI_INT_DIR                   (1 << 3)  /* Bit 3:  Change of direction detected */
+#define QEI_INT_ERR                   (1 << 4)  /* Bit 4:  Encoder phase error detected */
+#define QEI_INT_ENCLK                 (1 << 5)  /* Bit 5:  Eencoder clock pulse detected */
+#define QEI_INT_POS0                  (1 << 6)  /* Bit 6:  Position 0 compare equal to current position */
+#define QEI_INT_POS1                  (1 << 7)  /* Bit 7:  Position 1 compare equal to current position */
+#define QEI_INT_POS2                  (1 << 8)  /* Bit 8:  Position 2 compare equal to current position */
+#define QEI_INT_REV                   (1 << 9)  /* Bit 9:  Index compare value equal to current index count */
+#define QEI_INT_POS0REV               (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */
+#define QEI_INT_POS1REV               (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
+#define QEI_INT_POS2REV               (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
+
+#ifdef LPC178x
+#  define QEI_INT_REV1                (1 << 13) /* Bit 13: Index compare1 value to current index interrupt */
+#  define QEI_INT_REV2                (1 << 14) /* Bit 14: Index compare2 value to current index interrupt */
+#  define QEI_INT_MAXPOS              (1 << 15) /* Bit 15: Current position count interrupt */
+#endif
+                                                /* Bits 16-31: reserved */
+
+/********************************************************************************************
  * Public Types
- ************************************************************************************/
+ ********************************************************************************************/
 
-/************************************************************************************
+/********************************************************************************************
  * Public Data
- ************************************************************************************/
+ ********************************************************************************************/
 
-/************************************************************************************
+/********************************************************************************************
  * Public Functions
- ************************************************************************************/
+ ********************************************************************************************/
 
 #endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H */
diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h
index ddc44d59f..56144c6cf 100644
--- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h
@@ -188,15 +188,22 @@
 #define RTC_AMR_MON             (1 << 6)  /* Bit 6:  Month not compared for alarm */
 #define RTC_AMR_YEAR            (1 << 7)  /* Bit 7:  Year not compared for alarm */
                                           /* Bits 8-31: Reserved */
-/* RTC Auxiliary Enable register */
+
+/* RTC Auxiliary Control Register */
                                           /* Bits 0-3: Reserved */
 #define RTC_AUXEN_RTCOSCF       (1 << 4)  /* Bit 4:  RTC Oscillator Fail detect flag */
-                                          /* Bits 5-31: Reserved */
-/* RTC Auxiliary control register */
+#ifdef LPC178x
+                                          /* Bit 5:  Reserved */
+#  define RTC_AUXEN_RTCPDOUT    (1 << 6)  /* Bit 6:  RTC power down mode flag */
+                                          /* Bits 7-31: Reserved */
+#endif
+
+/* RTC Auxiliary Enable Register */
                                           /* Bits 0-3: Reserved */
 #define RTC_AUX_OSCFEN          (1 << 4)  /* Bit 4:  Oscillator Fail Detect interrupt enable */
                                           /* Bits 5-31: Reserved */
-/* Consolidated time registers */
+
+/* Consolidated Time Registers */
 /* Consolidated Time Register 0 */
 
 #define RTC_CTIME0_SEC_SHIFT    (0)       /* Bits 0-5: Seconds */
diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h
index 1def0d009..d7706561c 100644
--- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h
@@ -72,6 +72,12 @@
 #define LPC17_UART_RS485DLY_OFFSET   0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */
 #define LPC17_UART_FIFOLVL_OFFSET    0x0058 /* FIFO Level register (all) */
 
+#ifdef LPC178x
+#  define LPC17_UART_OSR_OFFSET      0x002c /* Oversampling Register (UART4 only) */
+#  define LPC17_UART_SCICTRL_OFFSET  0x0048 /* Smart Card Interface Register (UART4 only) */
+#  define LPC17_UART_SYNCCTRL_OFFSET 0x0058 /* Synchronous Mode  Register (UART4 only) */
+#endif
+
 /* Register addresses ***************************************************************/
 
 #define LPC17_UART0_RBR              (LPC17_UART0_BASE+LPC17_UART_RBR_OFFSET)
@@ -88,6 +94,13 @@
 #define LPC17_UART0_ICR              (LPC17_UART0_BASE+LPC17_UART_ICR_OFFSET)
 #define LPC17_UART0_FDR              (LPC17_UART0_BASE+LPC17_UART_FDR_OFFSET)
 #define LPC17_UART0_TER              (LPC17_UART0_BASE+LPC17_UART_TER_OFFSET)
+
+#ifdef LPC178x
+#  define LPC17_UART0_RS485CTRL      (LPC17_UART0_BASE+LPC17_UART_RS485CTRL_OFFSET)
+#  define LPC17_UART0_ADRMATCH       (LPC17_UART0_BASE+LPC17_UART_ADRMATCH_OFFSET)
+#  define LPC17_UART0_RS485DLY       (LPC17_UART0_BASE+LPC17_UART_RS485DLY_OFFSET)
+#endif
+
 #define LPC17_UART0_FIFOLVL          (LPC17_UART0_BASE+LPC17_UART_FIFOLVL_OFFSET)
 
 #define LPC17_UART1_RBR              (LPC17_UART1_BASE+LPC17_UART_RBR_OFFSET)
@@ -124,6 +137,13 @@
 #define LPC17_UART2_ICR              (LPC17_UART2_BASE+LPC17_UART_ICR_OFFSET)
 #define LPC17_UART2_FDR              (LPC17_UART2_BASE+LPC17_UART_FDR_OFFSET)
 #define LPC17_UART2_TER              (LPC17_UART2_BASE+LPC17_UART_TER_OFFSET)
+
+#ifdef LPC178x
+#  define LPC17_UART2_RS485CTRL      (LPC17_UART2_BASE+LPC17_UART_RS485CTRL_OFFSET)
+#  define LPC17_UART2_ADRMATCH       (LPC17_UART2_BASE+LPC17_UART_ADRMATCH_OFFSET)
+#  define LPC17_UART2_RS485DLY       (LPC17_UART2_BASE+LPC17_UART_RS485DLY_OFFSET)
+#endif
+
 #define LPC17_UART2_FIFOLVL          (LPC17_UART2_BASE+LPC17_UART_FIFOLVL_OFFSET)
 
 #define LPC17_UART3_RBR              (LPC17_UART3_BASE+LPC17_UART_RBR_OFFSET)
@@ -140,8 +160,39 @@
 #define LPC17_UART3_ICR              (LPC17_UART3_BASE+LPC17_UART_ICR_OFFSET)
 #define LPC17_UART3_FDR              (LPC17_UART3_BASE+LPC17_UART_FDR_OFFSET)
 #define LPC17_UART3_TER              (LPC17_UART3_BASE+LPC17_UART_TER_OFFSET)
+
+#ifdef LPC178x
+#  define LPC17_UART3_RS485CTRL      (LPC17_UART3_BASE+LPC17_UART_RS485CTRL_OFFSET)
+#  define LPC17_UART3_ADRMATCH       (LPC17_UART3_BASE+LPC17_UART_ADRMATCH_OFFSET)
+#  define LPC17_UART3_RS485DLY       (LPC17_UART3_BASE+LPC17_UART_RS485DLY_OFFSET)
+#endif
+
 #define LPC17_UART3_FIFOLVL          (LPC17_UART3_BASE+LPC17_UART_FIFOLVL_OFFSET)
 
+#ifdef LPC178x
+#  define LPC17_UART4_RBR            (LPC17_UART4_BASE+LPC17_UART_RBR_OFFSET)
+#  define LPC17_UART4_THR            (LPC17_UART4_BASE+LPC17_UART_THR_OFFSET)
+#  define LPC17_UART4_DLL            (LPC17_UART4_BASE+LPC17_UART_DLL_OFFSET)
+#  define LPC17_UART4_DLM            (LPC17_UART4_BASE+LPC17_UART_DLM_OFFSET)
+#  define LPC17_UART4_IER            (LPC17_UART4_BASE+LPC17_UART_IER_OFFSET)
+#  define LPC17_UART4_IIR            (LPC17_UART4_BASE+LPC17_UART_IIR_OFFSET)
+#  define LPC17_UART4_FCR            (LPC17_UART4_BASE+LPC17_UART_FCR_OFFSET)
+#  define LPC17_UART4_LCR            (LPC17_UART4_BASE+LPC17_UART_LCR_OFFSET)
+#  define LPC17_UART4_LSR            (LPC17_UART4_BASE+LPC17_UART_LSR_OFFSET)
+#  define LPC17_UART4_SCR            (LPC17_UART4_BASE+LPC17_UART_SCR_OFFSET)
+#  define LPC17_UART4_ACR            (LPC17_UART4_BASE+LPC17_UART_ACR_OFFSET)
+#  define LPC17_UART4_ICR            (LPC17_UART4_BASE+LPC17_UART_ICR_OFFSET)
+#  define LPC17_UART4_FDR            (LPC17_UART4_BASE+LPC17_UART_FDR_OFFSET)
+#  define LPC17_UART4_TER            (LPC17_UART4_BASE+LPC17_UART_TER_OFFSET)
+#  define LPC17_UART4_RS485CTRL      (LPC17_UART4_BASE+LPC17_UART_RS485CTRL_OFFSET)
+#  define LPC17_UART4_ADRMATCH       (LPC17_UART4_BASE+LPC17_UART_ADRMATCH_OFFSET)
+#  define LPC17_UART4_RS485DLY       (LPC17_UART4_BASE+LPC17_UART_RS485DLY_OFFSET)
+#  define LPC17_UART4_FIFOLVL        (LPC17_UART4_BASE+LPC17_UART_FIFOLVL_OFFSET)
+#  define LPC17_UART4_OSR            (LPC17_UART4_BASE+LPC17_UART4_OSR_OFFSET)
+#  define LPC17_UART4_SCICTRL        (LPC17_UART4_BASE+LPC17_UART4_SCICTRL_OFFSET)
+#  define LPC17_UART4_SYNCCTRL       (LPC17_UART4_BASE+LPC17_UART4_SYNCCTRL_OFFSET)
+#endif
+
 /* Register bit definitions *********************************************************/
 
 /* RBR (DLAB =0) Receiver Buffer Register (all) */
@@ -324,6 +375,30 @@
 #define UART_FIFOLVL_TX_MASK         (15 << UART_FIFOLVL_TX_SHIFT)
                                                /* Bits 12-31: Reserved */
 
+/* SCICTL Smart Card Interface (UART4 only) */
+
+#ifdef LPC178x
+#  define UART_SCIEN                 (1 << 0)  /* Bit 0: Smart Card Interface enable */
+#  define UART_NACKDIS               (1 << 1)  /* Bit 1: NACK response disable.Applicable if PROTSEL=0 */
+#  define UART_PROTSEL               (1 << 2)  /* Bit 2: Protocol Selection ISO7816-3 */
+#  define UART_TXRETRY               (7 << 5)  /* Bits 5-7: Maximum number of Re-Transmission */
+#  define UART_GUARDTIME_SHIFT       (8)       /* Bits 8-15: Extra guard time */
+#  define UART_GUARDTIME_MASK        (0xff << UART_GUARDTIME_SHIFT)
+                                               /* Bits 16-31: Reserved */
+#endif
+
+/* OSR Oversampling Register (UART4 only) */
+
+#ifdef LPC178x
+                                               /* Bit 0: Reserved */
+#  define UART_OSFRAC                (7 << 1)  /* Bits 1-3: Fractional part of Oversampling Ratio */
+#  define UART_OSINT_SHIFT           (4)       /* Bits 4-7:  Integer part of (Oversampling Ratio -1) */
+#  define UART_OSINT_MASK            (0x0f << UART_OSINT_SHIFT)
+#  define UART_FDINT_SHIFT           (8)       /* Bits 8-14: OSINT extension in Smart Card mode */
+#  define UART_FDINT_MASK            (0x7f << UART_FDINT_SHIFT)
+                                               /* Bits 15-31: Reserved */
+#endif
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h
index 9c83ac4de..d76ff1762 100644
--- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h
@@ -51,47 +51,95 @@
 
 /* Register offsets *****************************************************************/
 
-#define LPC17_WDT_WDMOD_OFFSET     0x0000  /* Watchdog mode register */
-#define LPC17_WDT_WDTC_OFFSET      0x0004  /* Watchdog timer constant register */
-#define LPC17_WDT_WDFEED_OFFSET    0x0008  /* Watchdog feed sequence register */
-#define LPC17_WDT_WDTV_OFFSET      0x000c  /* Watchdog timer value register */
-#define LPC17_WDT_WDCLKSEL_OFFSET  0x0010  /* Watchdog clock source selection register */
+#define LPC17_WDT_MOD_OFFSET       0x0000  /* Watchdog mode register */
+#define LPC17_WDT_TC_OFFSET        0x0004  /* Watchdog timer constant register */
+#define LPC17_WDT_FEED_OFFSET      0x0008  /* Watchdog feed sequence register */
+#define LPC17_WDT_TV_OFFSET        0x000c  /* Watchdog timer value register */
+
+#ifdef LPC176x
+#  define LPC17_WDT_CLKSEL_OFFSET  0x0010  /* Watchdog clock source selection register */
+#endif
+
+#ifdef LPC178x
+#  define LPC17_WDT_WARNINT_OFFSET 0x0014  /* Watchdog warning interrupt */
+#  define LPC17_WDT_WINDOW_OFFSET  0x0018  /* Watchdog window compare value */
+#endif
 
 /* Register addresses ***************************************************************/
 
-#define LPC17_WDT_WDMOD            (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET)
-#define LPC17_WDT_WDTC             (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET)
-#define LPC17_WDT_WDFEED           (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET)
-#define LPC17_WDT_WDTV             (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET)
-#define LPC17_WDT_WDCLKSEL         (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET)
+#define LPC17_WDT_MOD              (LPC17_WDT_BASE+LPC17_WDT_MOD_OFFSET)
+#define LPC17_WDT_TC               (LPC17_WDT_BASE+LPC17_WDT_TC_OFFSET)
+#define LPC17_WDT_FEED             (LPC17_WDT_BASE+LPC17_WDT_FEED_OFFSET)
+#define LPC17_WDT_TV               (LPC17_WDT_BASE+LPC17_WDT_TV_OFFSET)
+#define LPC17_WDT_CLKSEL           (LPC17_WDT_BASE+LPC17_WDT_CLKSEL_OFFSET)
+
+#ifdef LPC178x
+#  define LPC17_WDT_WARNINT        (LPC17_WDT_BASE+LPC17_WDT_WARNINT_OFFSET)
+#  define LPC17_WDT_WINDOW         (LPC17_WDT_BASE+LPC17_WDT_WINDOW_OFFSET)
+#endif
 
 /* Register bit definitions *********************************************************/
 
 /* Watchdog mode register */
 
-#define WDT_WDMOD_WDEN             (1 << 0)  /* Bit 0: Watchdog enable */
-#define WDT_WDMOD_WDRESET          (1 << 1)  /* Bit 1: Watchdog reset enable */
-#define WDT_WDMOD_WDTOF            (1 << 2)  /* Bit 2: Watchdog time-out */
-#define WDT_WDMOD_WDINT            (1 << 3)  /* Bit 3: Watchdog interrupt */
-                                             /* Bits 14-31: Reserved */
-
-/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */
+#define WDT_MOD_WDEN               (1 << 0)  /* Bit 0: Watchdog enable */
+#define WDT_MOD_WDRESET            (1 << 1)  /* Bit 1: Watchdog reset enable */
+#define WDT_MOD_WDTOF              (1 << 2)  /* Bit 2: Watchdog time-out */
+#define WDT_MOD_WDINT              (1 << 3)  /* Bit 3: Watchdog interrupt */
+#ifdef LPC178x
+#  define WDT_MOD_WDPROTECT        (1 << 4)  /* Bit 4: Watchdog interrupt */
+#endif
+                                             /* Bits 5-31: Reserved */
+/* Watchdog timer constant register */
+
+#ifdef LPC176x
+#  define WDT_TC                   (0xffffffff) /* Bits 0-31: Watchdog time-out interval */
+#endif
+#ifdef LPC178x
+#  define WDT_TC                   (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */
+                                             /* Bits 24-31: Reserved */
+#endif
 
 /* Watchdog feed sequence register  */
 
-#define WDT_WDFEED_MASK            (0xff)    /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */
+#define WDT_FEED_MASK              (0xff)    /* Bits 0-7: Feed value should be 0xaa
+                                              *           followed by 0x55 */
                                              /* Bits 14-31: Reserved */
-/* Watchdog timer value register (Bits 0-31: Counter timer value) */
+/* Watchdog timer value register */
+
+#ifdef LPC176x
+#  define WDT_TVT                  (0xffffffff) /* Bits 0-31: Watchdog timer value */
+#endif
+#ifdef LPC178x
+#  define WDT_TVT                  (0xffffff) /* Bits 0-23: Watchdog timer value */
+                                              /* Bits 24-31: Reserved */
+#endif
 
 /* Watchdog clock source selection register */
 
-#define WDT_WDCLKSEL_WDSEL_SHIFT   (0)       /* Bits 0-1: Clock source for the Watchdog timer */
-#define WDT_WDCLKSEL_WDSEL_MASK    (3 << WDT_WDCLKSEL_WDSEL_SHIFT)
-#  define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */
-#  define WDT_WDCLKSEL_WDSEL_APB   (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */
-#  define WDT_WDCLKSEL_WDSEL_RTC   (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */
+#ifdef LPC176x
+#  define WDT_CLKSEL_WDSEL_SHIFT   (0)       /* Bits 0-1: Clock source for the Watchdog timer */
+#  define WDT_CLKSEL_WDSEL_MASK    (3 << WDT_CLKSEL_WDSEL_SHIFT)
+#    define WDT_CLKSEL_WDSEL_INTRC (0 << WDT_CLKSEL_WDSEL_SHIFT) /* Internal RC osc */
+#    define WDT_CLKSEL_WDSEL_APB   (1 << WDT_CLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */
+#    define WDT_CLKSEL_WDSEL_RTC   (2 << WDT_CLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */
                                              /* Bits 2-30: Reserved */
-#define WDT_WDCLKSEL_WDLOCK        (1 << 31) /* Bit 31: Lock WDT register bits if set */
+#  define WDT_CLKSEL_WDLOCK        (1 << 31) /* Bit 31: Lock WDT register bits if set */
+#endif
+
+/* Watchdog timer warning interrupt register */
+
+#ifdef LPC178x
+# define WDT_WARNINT               (0x3ff)   /* Bits 0-9: Warning Interrupt compare value */
+                                             /* Bits 10-31: Reserved */
+#endif
+
+/* Watchdog timer value register */
+
+#ifdef LPC178x
+# define WDT_WINDOW                (0xffffff) /* Bits 0-23: Watchdog window value */
+                                              /* Bits 24-31: Reserved */
+#endif
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
index 96b203f59..8ae8fe6e7 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
@@ -671,7 +671,7 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port,
 
   /* Set the alternate pin */
 
-  regval |= alt;
+  regval |= (alt & ~IOCON_FUNC_MASK);
 
   /* Set IOCON register */