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author | Gregory Nutt <gnutt@nuttx.org> | 2015-02-26 15:05:11 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2015-02-26 15:05:11 -0600 |
commit | 8fb4981a49e58322a608b4c561f72c2f3d84db74 (patch) | |
tree | e13ba79d359d7e1cbdd8215253f162546d1facc6 | |
parent | aaf210950fb278bd5a29727541afd2f9981b0df8 (diff) | |
download | px4-nuttx-8fb4981a49e58322a608b4c561f72c2f3d84db74.tar.gz px4-nuttx-8fb4981a49e58322a608b4c561f72c2f3d84db74.tar.bz2 px4-nuttx-8fb4981a49e58322a608b4c561f72c2f3d84db74.zip |
PIC32MZ: Add logic to configure peripheral pins for the selecte UARTs
-rw-r--r-- | nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h | 4 | ||||
-rw-r--r-- | nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h | 28 | ||||
-rw-r--r-- | nuttx/arch/mips/src/pic32mz/pic32mz-lowconsole.c | 145 | ||||
-rw-r--r-- | nuttx/configs/pic32mz-starterkit/README.txt | 47 | ||||
-rw-r--r-- | nuttx/configs/pic32mz-starterkit/include/board.h | 11 |
5 files changed, 215 insertions, 20 deletions
diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h index 07370cb9d..f8419b1f0 100644 --- a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h +++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-pps.h @@ -73,8 +73,8 @@ * extract one or the other. */ -#define PPS_OUTPUT_REGADDR(a,b) (b) -#define PPS_OTUPUT_REVAL(a,b) (a) +#define PPS_OUTPUT_REGADDR(a,b) ((uintptr_t)(b)) +#define PPS_OUTPUT_REGVAL(a,b) ((uint32_t(a)) /******************************************************************************************** * Public Types diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h index 795f6b5f6..eac6e2868 100644 --- a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h +++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-pps.h @@ -79,13 +79,13 @@ # define PIC32MZ_U4RXR_OFFSET 0x1480 # define PIC32MZ_U5RXR_OFFSET 0x1488 # define PIC32MZ_U6RXR_OFFSET 0x1490 -#define PIC32MZ_UnTSR_OFFSET(n) (0x1464 + ((n << 3)) /* n=1..6 */ -# define PIC32MZ_U1TSR_OFFSET 0x146c -# define PIC32MZ_U2TSR_OFFSET 0x1474 -# define PIC32MZ_U3TSR_OFFSET 0x147c -# define PIC32MZ_U4TSR_OFFSET 0x1484 -# define PIC32MZ_U5TSR_OFFSET 0x148c -# define PIC32MZ_U6TSR_OFFSET 0x1494 +#define PIC32MZ_UnCTSR_OFFSET(n) (0x1464 + ((n << 3)) /* n=1..6 */ +# define PIC32MZ_U1CTSR_OFFSET 0x146c +# define PIC32MZ_U2CTSR_OFFSET 0x1474 +# define PIC32MZ_U3CTSR_OFFSET 0x147c +# define PIC32MZ_U4CTSR_OFFSET 0x1484 +# define PIC32MZ_U5CTSR_OFFSET 0x148c +# define PIC32MZ_U6CTSR_OFFSET 0x1494 #define PIC32MZ_SDInR_OFFSET(n) (0x1490 + 12*(n)) /* n=1..6 */ # define PIC32MZ_SDI1R_OFFSET 0x149c # define PIC32MZ_SDI2R_OFFSET 0x14a8 @@ -208,13 +208,13 @@ # define PIC32MZ_U4RXR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U4RXR_OFFSET) # define PIC32MZ_U5RXR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U5RXR_OFFSET) # define PIC32MZ_U6RXR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U6RXR_OFFSET) -#define PIC32MZ_UnTSR(n) (PIC32MZ_IOPORT_K1BASE+PIC32MZ_UnTSR_OFFSET(n) -# define PIC32MZ_U1TSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U1TSR_OFFSET) -# define PIC32MZ_U2TSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U2TSR_OFFSET) -# define PIC32MZ_U3TSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U3TSR_OFFSET) -# define PIC32MZ_U4TSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U4TSR_OFFSET) -# define PIC32MZ_U5TSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U5TSR_OFFSET) -# define PIC32MZ_U6TSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U6TSR_OFFSET) +#define PIC32MZ_UnCTSR(n) (PIC32MZ_IOPORT_K1BASE+PIC32MZ_UnCTSR_OFFSET(n) +# define PIC32MZ_U1CTSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U1CTSR_OFFSET) +# define PIC32MZ_U2CTSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U2CTSR_OFFSET) +# define PIC32MZ_U3CTSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U3CTSR_OFFSET) +# define PIC32MZ_U4CTSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U4CTSR_OFFSET) +# define PIC32MZ_U5CTSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U5CTSR_OFFSET) +# define PIC32MZ_U6CTSR (PIC32MZ_IOPORT_K1BASE+PIC32MZ_U6CTSR_OFFSET) #define PIC32MZ_SDInR(n) (PIC32MZ_IOPORT_K1BASE+PIC32MZ_SDInR_OFFSET(n)) # define PIC32MZ_SDI1R (PIC32MZ_IOPORT_K1BASE+PIC32MZ_SDI1R_OFFSET) # define PIC32MZ_SDI2R (PIC32MZ_IOPORT_K1BASE+PIC32MZ_SDI2R_OFFSET) diff --git a/nuttx/arch/mips/src/pic32mz/pic32mz-lowconsole.c b/nuttx/arch/mips/src/pic32mz/pic32mz-lowconsole.c index 2cd91de6b..3cfddafe6 100644 --- a/nuttx/arch/mips/src/pic32mz/pic32mz-lowconsole.c +++ b/nuttx/arch/mips/src/pic32mz/pic32mz-lowconsole.c @@ -43,13 +43,15 @@ #include <debug.h> #include <arch/irq.h> -#include <arch/board/board.h> #include "up_arch.h" #include "up_internal.h" #include "pic32mz-config.h" #include "chip/pic32mz-uart.h" +#include "chip/pic32mz-pps.h" + +#include <arch/board/board.h> /****************************************************************************** * Pre-processor Definitions @@ -321,14 +323,151 @@ void pic32mz_uartconfigure(uintptr_t uart_base, uint32_t baudrate, * ******************************************************************************/ -#ifdef HAVE_SERIAL_CONSOLE void pic32mz_consoleinit(void) { +#ifdef HAVE_UART_DEVICE + + /* Setup up pin selection registers for all configured UARTs. The board.h + * header file must provide these definitions to select the correct pin + * configuration for each enabled UARt. + */ + +#ifdef CONFIG_PIC32MZ_UART1 + /* Configure UART1 RX (input) and TX (output) pins */ + + putreg32(BOARD_U1RX_PPS, PIC32MZ_U1RXR); + putreg32(PPS_OUTPUT_REGVAL(BOARD_U1TX_PPS), + PPS_OUTPUT_REGADDR(BOARD_U1TX_PPS)); + +#ifdef CONFIG_UART1_OFLOWCONTROL + /* Configure the UART1 CTS input pin */ + + putreg32(BOARD_U1CTS_PPS, PIC32MZ_U1CTSR); +#endif +#ifdef CONFIG_UART1_IFLOWCONTROL + /* Configure the UART1 RTS output pin */ + + putreg32(PPS_OUTPUT_REGVAL(BOARD_U1RTS_PPS), + PPS_OUTPUT_REGADDR(BOARD_U1RTS_PPS)); + +#endif /* CONFIG_UART1_IFLOWCONTROL */ +#endif /* CONFIG_PIC32MZ_UART1 */ + +#ifdef CONFIG_PIC32MZ_UART2 + /* Configure UART2 RX (input) and TX (output) pins */ + + putreg32(BOARD_U2RX_PPS, PIC32MZ_U2RXR); + putreg32(PPS_OUTPUT_REGVAL(BOARD_U2TX_PPS), + PPS_OUTPUT_REGADDR(BOARD_U2TX_PPS)); + +#ifdef CONFIG_UART2_OFLOWCONTROL + /* Configure the UART2 CTS input pin */ + + putreg32(BOARD_U2CTS_PPS, PIC32MZ_U2CTSR); +#endif +#ifdef CONFIG_UART2_IFLOWCONTROL + /* Configure the UART2 RTS output pin */ + + putreg32(PPS_OUTPUT_REGVAL(BOARD_U2RTS_PPS), + PPS_OUTPUT_REGADDR(BOARD_U2RTS_PPS)); + +#endif /* CONFIG_UART2_IFLOWCONTROL */ +#endif /* CONFIG_PIC32MZ_UART2 */ + +#ifdef CONFIG_PIC32MZ_UART3 + /* Configure UART3 RX (input) and TX (output) pins */ + + putreg32(BOARD_U3RX_PPS, PIC32MZ_U3RXR); + putreg32(PPS_OUTPUT_REGVAL(BOARD_U3TX_PPS), + PPS_OUTPUT_REGADDR(BOARD_U3TX_PPS)); + +#ifdef CONFIG_UART3_OFLOWCONTROL + /* Configure the UART3 CTS input pin */ + + putreg32(BOARD_U3CTS_PPS, PIC32MZ_U3CTSR); +#endif +#ifdef CONFIG_UART3_IFLOWCONTROL + /* Configure the UART3 RTS output pin */ + + putreg32(PPS_OUTPUT_REGVAL(BOARD_U3RTS_PPS), + PPS_OUTPUT_REGADDR(BOARD_U3RTS_PPS)); + +#endif /* CONFIG_UART3_IFLOWCONTROL */ +#endif /* CONFIG_PIC32MZ_UART3 */ + +#ifdef CONFIG_PIC32MZ_UART4 + /* Configure UART4 RX (input) and TX (output) pins */ + + putreg32(BOARD_U4RX_PPS, PIC32MZ_U4RXR); + putreg32(PPS_OUTPUT_REGVAL(BOARD_U4TX_PPS), + PPS_OUTPUT_REGADDR(BOARD_U4TX_PPS)); + +#ifdef CONFIG_UART4_OFLOWCONTROL + /* Configure the UART4 CTS input pin */ + + putreg32(BOARD_U4CTS_PPS, PIC32MZ_U4CTSR); +#endif +#ifdef CONFIG_UART4_IFLOWCONTROL + /* Configure the UART4 RTS output pin */ + + putreg32(PPS_OUTPUT_REGVAL(BOARD_U4RTS_PPS), + PPS_OUTPUT_REGADDR(BOARD_U4RTS_PPS)); + +#endif /* CONFIG_UART4_IFLOWCONTROL */ +#endif /* CONFIG_PIC32MZ_UART4 */ + +#ifdef CONFIG_PIC32MZ_UART5 + /* Configure UART5 RX (input) and TX (output) pins */ + + putreg32(BOARD_U5RX_PPS, PIC32MZ_U5RXR); + putreg32(PPS_OUTPUT_REGVAL(BOARD_U5TX_PPS), + PPS_OUTPUT_REGADDR(BOARD_U5TX_PPS)); + +#ifdef CONFIG_UART5_OFLOWCONTROL + /* Configure the UART5 CTS input pin */ + + putreg32(BOARD_U5CTS_PPS, PIC32MZ_U5CTSR); +#endif +#ifdef CONFIG_UART5_IFLOWCONTROL + /* Configure the UART5 RTS output pin */ + + putreg32(PPS_OUTPUT_REGVAL(BOARD_U5RTS_PPS), + PPS_OUTPUT_REGADDR(BOARD_U5RTS_PPS)); + +#endif /* CONFIG_UART5_IFLOWCONTROL */ +#endif /* CONFIG_PIC32MZ_UART5 */ + +#ifdef CONFIG_PIC32MZ_UART6 + /* Configure UART6 RX (input) and TX (output) pins */ + + putreg32(BOARD_U6RX_PPS, PIC32MZ_U6RXR); + putreg32(PPS_OUTPUT_REGVAL(BOARD_U6TX_PPS), + PPS_OUTPUT_REGADDR(BOARD_U6TX_PPS)); + +#ifdef CONFIG_UART6_OFLOWCONTROL + /* Configure the UART6 CTS input pin */ + + putreg32(BOARD_U6CTS_PPS, PIC32MZ_U6CTSR); +#endif +#ifdef CONFIG_UART6_IFLOWCONTROL + /* Configure the UART6 RTS output pin */ + + putreg32(PPS_OUTPUT_REGVAL(BOARD_U6RTS_PPS), + PPS_OUTPUT_REGADDR(BOARD_U6RTS_PPS)); + +#endif /* CONFIG_UART6_IFLOWCONTROL */ +#endif /* CONFIG_PIC32MZ_UART6 */ + +#ifdef HAVE_SERIAL_CONSOLE + /* Configure the console uart */ + pic32mz_uartconfigure(PIC32MZ_CONSOLE_BASE, PIC32MZ_CONSOLE_BAUD, PIC32MZ_CONSOLE_PARITY, PIC32MZ_CONSOLE_BITS, PIC32MZ_CONSOLE_2STOP); + +#endif /* HAVE_SERIAL_CONSOLE */ +#endif /* HAVE_UART_DEVICE */ } -#endif /****************************************************************************** * Name: up_lowputc diff --git a/nuttx/configs/pic32mz-starterkit/README.txt b/nuttx/configs/pic32mz-starterkit/README.txt index 6682dea64..9f6cf1726 100644 --- a/nuttx/configs/pic32mz-starterkit/README.txt +++ b/nuttx/configs/pic32mz-starterkit/README.txt @@ -33,6 +33,14 @@ Key features of the PIC32MZ Starter Kit include; The PIC32MZ starter kit comes complete with a LAN8740 PHY daughter board. +Testing was performed with the following additional hardware: + +- Microchip PIC32MZ Embedded Connectivity (EC) Adapter Board (AC320006) + that allows connection of the PIC32MZEC Starter Kit to the Microchip + Multimedia Expansion Board (MEB, DM320005) or PIC32 I/O Expansion Board + (DM320002). These were previously used with the PIC32MX bringup. +- Microchip Multimedia Expansion Board II (MEB II, DM320005-2). + Contents ======== @@ -102,7 +110,44 @@ Creating Compatible NuttX HEX files Serial Console ============== -To be provided + The Microchip PIC32MZ Embedded Connectivity (EC) Adapter Board (AC320006) + brings out UART signals as follows: + + JP7 redirects J1 U3_TX to either J2 SOSCO/RC14 or U1_TX: + + Adapter + ----------------------------------------------------------------------- + JP7, Pin 1: J2 Pin 32, SOSCO/RC14 + Pin 2: J1 Pin 17, U3_TX + Pin 3: J2 Pin 90, U1_TX + + PIC32MZ Starter Kit + ----------------------------------------------------------------------- + J1 Pin 17, SOSCO/RC14 PIC32MZ SOSCO/RPC14/T1CK/RC14 + + RPC14 supports U1RX, U4RX, and U3TX + + JP8 redirects J1 RB3/AN3/SDO4/WIFI_SDI to either J2 AN3/SDO4/WIFI_SDI or U3_RX: + + Adapter PIC32MZ Starter Kit + ---------------------------------------------- ------------------------- + JP8, Pin 1: J2, Pin 66, AN3/SDO4/WIFI_SDI + Pin 2: J1, Pin 105, RB3/AN3/SDO4/WIFI_SDI + Pin 3: J2, Pin 88, U3_RX + + PIC32MZ Starter Kit + ----------------------------------------------------------------------- + J1, Pin 105, AN3/C2INA/RPB3/RB3 + + RPB3 supports U3RX, U1TX, and U5TX + + Thus UART1 or UART3 could be used as a serial console if only the + PIC32MZEC Adapter Board is connected. + + The default serial configuration here in these configurations is UART1 + using RPC14 and RPB3. That UART selection can be change by running 'make + menuconfig'. The UART pin selections would need to be changed by editing + configs/pc32mz-starterkit/include/board.h. LEDs and Buttons ================ diff --git a/nuttx/configs/pic32mz-starterkit/include/board.h b/nuttx/configs/pic32mz-starterkit/include/board.h index 4da362fa8..eced37090 100644 --- a/nuttx/configs/pic32mz-starterkit/include/board.h +++ b/nuttx/configs/pic32mz-starterkit/include/board.h @@ -214,6 +214,17 @@ * are grounded when pressed. */ +/* UARTS ********************************************************************/ +/* If the PIC32MZEC Adaptor Board is connected, then UART1 signals are + * available at these locations on the adaptor board: + * + * JP7 Pin 2: RPC14 + * JP8 Pin 2: RPB3 + */ + +#define BOARD_U1RX_PPS U1RXR_RPC14 +#define BOARD_U1TX_PPS U1TX_RPB3R + /**************************************************************************** * Public Types ****************************************************************************/ |