diff options
| author | Gregory Nutt <gnutt@nuttx.org> | 2015-03-02 10:33:42 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2015-03-02 10:33:42 -0600 |
| commit | 94ae791b65fa53b4311ffd29963677d136604e6a (patch) | |
| tree | 88997d9fb80b7a182d827290ff89dbb462bc7ce5 | |
| parent | 9b74af4ef27b42be17b733e5764d244b8849ad9f (diff) | |
| download | px4-nuttx-94ae791b65fa53b4311ffd29963677d136604e6a.tar.gz px4-nuttx-94ae791b65fa53b4311ffd29963677d136604e6a.tar.bz2 px4-nuttx-94ae791b65fa53b4311ffd29963677d136604e6a.zip | |
Adds architecture support for the STM32F372 and F373 (no board support yet). Only tested on STM32F373CC, but should work on the rest. Contributed by Marten Svanfeldt.
27 files changed, 2505 insertions, 36 deletions
diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h index ec22d3987..2a008f4bc 100644 --- a/nuttx/arch/arm/include/stm32/chip.h +++ b/nuttx/arch/arm/include/stm32/chip.h @@ -86,6 +86,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 0 /* No advanced timers */ @@ -125,6 +126,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 0 /* No advanced timers */ @@ -164,6 +166,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 0 /* No advanced timers */ @@ -203,6 +206,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 0 /* No advanced timers */ @@ -242,6 +246,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 0 /* No advanced timers */ @@ -281,6 +286,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 0 /* No advanced timers */ @@ -398,6 +404,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -434,6 +441,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -473,6 +481,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -510,6 +519,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -585,6 +595,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -621,6 +632,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -657,6 +669,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -693,6 +706,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -734,6 +748,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ @@ -773,6 +788,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ @@ -812,6 +828,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -849,6 +866,7 @@ # define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ @@ -884,6 +902,7 @@ # define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ @@ -921,6 +940,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -958,6 +978,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -987,9 +1008,9 @@ /* Part Numbering: STM32Fssscfxxx * * Where - * sss = 302 or 303 + * sss = 302/303 or 372/373 * c = C (48pins) R (68 pins) V (100 pins) - * f = B (128KB FLASH), C (256KB FLASH) + * f = 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) * xxx = Package, temperature range, options (ignored here) */ @@ -1005,6 +1026,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ @@ -1044,6 +1066,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ @@ -1083,6 +1106,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ @@ -1122,6 +1146,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1161,6 +1186,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1200,6 +1226,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ @@ -1227,6 +1254,47 @@ # define STM32_NRNG 0 /* (0) No random number generator (RNG) */ # define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ +#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */ +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# define CONFIG_STM32_STM32F37XX 1 /* STM32F37xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ + +# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ +# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 + * (2) 32-bit general timers with DMA: TIM2 and TIM5 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ +# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 1 /* (3) 12-bit ADC1 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + + + /* STM23 F4 Family ******************************************************************/ #elif defined(CONFIG_ARCH_CHIP_STM32F401RE) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ @@ -1241,6 +1309,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ @@ -1278,6 +1347,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ @@ -1315,6 +1385,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1352,6 +1423,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1389,6 +1461,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1426,6 +1499,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1463,6 +1537,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1500,6 +1575,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1537,6 +1613,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1574,6 +1651,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1611,6 +1689,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1648,6 +1727,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1685,6 +1765,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1722,6 +1803,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1759,6 +1841,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1796,6 +1879,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437/429/439 */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -1833,6 +1917,7 @@ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ # undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ diff --git a/nuttx/arch/arm/include/stm32/irq.h b/nuttx/arch/arm/include/stm32/irq.h index 12318a370..1cc8bcd76 100644 --- a/nuttx/arch/arm/include/stm32/irq.h +++ b/nuttx/arch/arm/include/stm32/irq.h @@ -85,6 +85,8 @@ # include <arch/stm32/stm32f20xxx_irq.h> #elif defined(CONFIG_STM32_STM32F30XX) # include <arch/stm32/stm32f30xxx_irq.h> +#elif defined(CONFIG_STM32_STM32F37XX) +# include <arch/stm32/stm32f37xxx_irq.h> #elif defined(CONFIG_STM32_STM32F40XX) # include <arch/stm32/stm32f40xxx_irq.h> #else diff --git a/nuttx/arch/arm/include/stm32/stm32f37xxx_irq.h b/nuttx/arch/arm/include/stm32/stm32f37xxx_irq.h new file mode 100644 index 000000000..ea6dad9f5 --- /dev/null +++ b/nuttx/arch/arm/include/stm32/stm32f37xxx_irq.h @@ -0,0 +1,180 @@ +/**************************************************************************************************** + * arch/arm/include/stm32s/stm32f37xxx_irq.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F37XXX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F37XXX_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/irq.h> + +/**************************************************************************************************** + * Definitions + ****************************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in nuttx/arch/arm/include/stm32/irq.h + * + * External interrupts (vectors >= 16) + */ + +#define STM32_IRQ_WWDG (STM32_IRQ_INTERRUPTS+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_INTERRUPTS+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_INTERRUPTS+2) /* 2: Tamper interrupt, or */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_INTERRUPTS+2) /* 2: Time stamp interrupt */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_INTERRUPTS+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_INTERRUPTS+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_INTERRUPTS+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_INTERRUPTS+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_INTERRUPTS+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_INTERRUPTS+8) /* 8: EXTI Line 2 interrupt, or */ +#define STM32_IRQ_TSC (STM32_IRQ_INTERRUPTS+8) /* 8: TSC interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_INTERRUPTS+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_INTERRUPTS+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_INTERRUPTS+11) /* 11: DMA1 channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_INTERRUPTS+12) /* 12: DMA1 channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_INTERRUPTS+13) /* 13: DMA1 channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_INTERRUPTS+14) /* 14: DMA1 channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_INTERRUPTS+15) /* 15: DMA1 channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_INTERRUPTS+16) /* 16: DMA1 channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_INTERRUPTS+17) /* 17: DMA1 channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_INTERRUPTS+18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_INTERRUPTS+19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_INTERRUPTS+20) /* 20: CAN1 RX0 interrupts*/ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_INTERRUPTS+21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_INTERRUPTS+22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_INTERRUPTS+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM15 (STM32_IRQ_INTERRUPTS+24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_INTERRUPTS+25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_INTERRUPTS+26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM18 (STM32_IRQ_INTERRUPTS+27) /* 27: TIM18 global interrupt, or */ +#define STM32_IRQ_DAC2 (STM32_IRQ_INTERRUPTS+27) /* 27: DAC2 global interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_INTERRUPTS+28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_INTERRUPTS+29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_INTERRUPTS+30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_INTERRUPTS+31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_INTERRUPTS+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_INTERRUPTS+33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_INTERRUPTS+34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_INTERRUPTS+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_INTERRUPTS+36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_INTERRUPTS+37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_INTERRUPTS+38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_INTERRUPTS+39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_INTERRUPTS+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_INTERRUPTS+41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_CEC (STM32_IRQ_INTERRUPTS+42) /* 42: CEC Interrupt */ +#define STM32_IRQ_TIM12 (STM32_IRQ_INTERRUPTS+43) /* 43: TIM12 global interrupt */ +#define STM32_IRQ_TIM13 (STM32_IRQ_INTERRUPTS+44) /* 44: TIM13 global interrupt */ +#define STM32_IRQ_TIM14 (STM32_IRQ_INTERRUPTS+45) /* 45: TIM14 global interrupt */ +#define STM32_IRQ_RESERVED46 (STM32_IRQ_INTERRUPTS+46) /* 46: Reserved */ +#define STM32_IRQ_RESERVED47 (STM32_IRQ_INTERRUPTS+47) /* 47: Reserved */ +#define STM32_IRQ_RESERVED48 (STM32_IRQ_INTERRUPTS+48) /* 48: Reserved */ +#define STM32_IRQ_RESERVED49 (STM32_IRQ_INTERRUPTS+49) /* 49: Reserved */ +#define STM32_IRQ_RESERVED50 (STM32_IRQ_INTERRUPTS+50) /* 50: Reserved */ +#define STM32_IRQ_SPI3 (STM32_IRQ_INTERRUPTS+51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_RESERVED52 (STM32_IRQ_INTERRUPTS+52) /* 52: Reserved */ +#define STM32_IRQ_RESERVED53 (STM32_IRQ_INTERRUPTS+53) /* 53: Reserved */ +#define STM32_IRQ_TIM6 (STM32_IRQ_INTERRUPTS+54) /* 54: TIM6 global interrupt, or */ +#define STM32_IRQ_DAC1 (STM32_IRQ_INTERRUPTS+54) /* 54: DAC1 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_INTERRUPTS+55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_INTERRUPTS+56) /* 56: DMA2 channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_INTERRUPTS+57) /* 57: DMA2 channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_INTERRUPTS+58) /* 58: DMA2 channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_INTERRUPTS+59) /* 59: DMA2 channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_INTERRUPTS+60) /* 60: DMA2 channel 5 global interrupt */ +#define STM32_IRQ_SDADC1 (STM32_IRQ_INTERRUPTS+61) /* 61: ADC Sigma Delta 1 global interrupt */ +#define STM32_IRQ_SDADC2 (STM32_IRQ_INTERRUPTS+62) /* 62: ADC Sigma Delta 2 global interrupt */ +#define STM32_IRQ_SDADC3 (STM32_IRQ_INTERRUPTS+63) /* 63: ADC Sigma Delta 3 global interrupt */ +#define STM32_IRQ_COMP12 (STM32_IRQ_INTERRUPTS+64) /* 64: COMP1 & COMP2 interrupts*/ +#define STM32_IRQ_RESERVED65 (STM32_IRQ_INTERRUPTS+65) /* 65: Reserved */ +#define STM32_IRQ_RESERVED66 (STM32_IRQ_INTERRUPTS+66) /* 66: Reserved */ +#define STM32_IRQ_RESERVED67 (STM32_IRQ_INTERRUPTS+67) /* 67: Reserved */ +#define STM32_IRQ_RESERVED68 (STM32_IRQ_INTERRUPTS+68) /* 68: Reserved */ +#define STM32_IRQ_RESERVED69 (STM32_IRQ_INTERRUPTS+69) /* 69: Reserved */ +#define STM32_IRQ_RESERVED70 (STM32_IRQ_INTERRUPTS+70) /* 70: Reserved */ +#define STM32_IRQ_RESERVED71 (STM32_IRQ_INTERRUPTS+71) /* 71: Reserved */ +#define STM32_IRQ_RESERVED72 (STM32_IRQ_INTERRUPTS+72) /* 72: Reserved */ +#define STM32_IRQ_RESERVED73 (STM32_IRQ_INTERRUPTS+73) /* 73: Reserved */ +#define STM32_IRQ_USBHP (STM32_IRQ_INTERRUPTS+74) /* 74: USB High priority interrupt */ +#define STM32_IRQ_USBLP (STM32_IRQ_INTERRUPTS+75) /* 75: USB Low priority interrupt */ +#define STM32_IRQ_USBWKUP (STM32_IRQ_INTERRUPTS+76) /* 76: USB wakeup from suspend */ +#define STM32_IRQ_RESERVED77 (STM32_IRQ_INTERRUPTS+77) /* 77: Reserved */ +#define STM32_IRQ_RESERVED78 (STM32_IRQ_INTERRUPTS+78) /* 78: Reserved */ +#define STM32_IRQ_RESERVED79 (STM32_IRQ_INTERRUPTS+79) /* 79: Reserved */ +#define STM32_IRQ_RESERVED80 (STM32_IRQ_INTERRUPTS+80) /* 80: Reserved */ +#define STM32_IRQ_FPU (STM32_IRQ_INTERRUPTS+81) /* 81: FPU global interrupt */ + +#define NR_VECTORS (STM32_IRQ_INTERRUPTS+82) +#define NR_IRQS (STM32_IRQ_INTERRUPTS+82) + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data +****************************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ + diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 8740208e9..8c0b7035f 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -467,6 +467,114 @@ config ARCH_CHIP_STM32F303VC select STM32_STM32F30XX select ARCH_HAVE_FPU +config ARCH_CHIP_STM32F372C8 + bool "STM32F372C8" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372R8 + bool "STM32F372R8" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372V8 + bool "STM32F372V8" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372CB + bool "STM32F372CB" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372RB + bool "STM32F372RB" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372VB + bool "STM32F372VB" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372CC + bool "STM32F372CC" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372RC + bool "STM32F372RC" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F372VC + bool "STM32F372VC" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373C8 + bool "STM32F373C8" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373R8 + bool "STM32F373R8" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373V8 + bool "STM32F373V8" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373CB + bool "STM32F373CB" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373RB + bool "STM32F373RB" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373VB + bool "STM32F373VB" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373CC + bool "STM32F373CC" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373RC + bool "STM32F373RC" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + +config ARCH_CHIP_STM32F373VC + bool "STM32F373VC" + select ARCH_CORTEXM4 + select STM32_STM32F37XX + select ARCH_HAVE_FPU + config ARCH_CHIP_STM32F401RE bool "STM32F401RE" select ARCH_CORTEXM4 @@ -786,6 +894,19 @@ config STM32_STM32F30XX select STM32_HAVE_CAN1 select STM32_HAVE_SPI2 +config STM32_STM32F37XX + bool + default n + select STM32_HAVE_USBDEV + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_CAN1 + select STM32_HAVE_USART3 + config STM32_STM32F40XX bool default n @@ -1328,7 +1449,7 @@ config STM32_SPI6 config STM32_SYSCFG bool "SYSCFG" default y - depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F207 || STM32_STM32F40XX + depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F40XX config STM32_TIM1 bool "TIM1" diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h index 17d9cc9f8..bba330edf 100644 --- a/nuttx/arch/arm/src/stm32/chip.h +++ b/nuttx/arch/arm/src/stm32/chip.h @@ -124,6 +124,8 @@ #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_pinmap.h" /* STM32 F4 Family ******************************************************************/ @@ -146,6 +148,8 @@ # include "chip/stm32f20xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +# elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_vectors.h" # else diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h index 06e33386a..e63c7b9b7 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h @@ -70,6 +70,10 @@ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE (2*1024) +#elif defined(CONFIG_STM32_STM32F37XX) +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE (2*1024) + #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # define STM32_FLASH_NPAGES 8 /* STM32F4 has mixed page size */ @@ -90,7 +94,7 @@ #define STM32_FLASH_SR_OFFSET 0x000c #define STM32_FLASH_CR_OFFSET 0x0010 -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define STM32_FLASH_AR_OFFSET 0x0014 # define STM32_FLASH_OBR_OFFSET 0x001c # define STM32_FLASH_WRPR_OFFSET 0x0020 @@ -110,7 +114,7 @@ #define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) #define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) # define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) # define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) @@ -143,10 +147,10 @@ # define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */ # define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_ACR_HLFCYA (1 << 3) /* Bit 3: FLASH half cycle access */ # define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */ -# ifdef CONFIG_STM32_STM32F30XX +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */ # endif # elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) @@ -160,7 +164,7 @@ /* Flash Status Register (SR) */ -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_SR_BSY (1 << 0) /* Busy */ # define FLASH_SR_PGERR (1 << 2) /* Programming Error */ # define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ @@ -177,7 +181,7 @@ /* Flash Control Register (CR) */ -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */ # define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */ # define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */ @@ -188,7 +192,7 @@ # define FLASH_CR_OPTWRE (1 << 9) /* Bit 8: Option Bytes Write Enable */ # define FLASH_CR_ERRIE (1 << 10) /* Bit 10: Error Interrupt Enable */ # define FLASH_CR_EOPIE (1 << 12) /* Bit 12: End of Program Interrupt Enable */ -# ifdef CONFIG_STM32_STM32F30XX +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */ # endif #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h index 73c264ab7..28f659003 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h @@ -51,6 +51,8 @@ # include "chip/stm32f20xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_memorymap.h" #else diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_usbdev.h b/nuttx/arch/arm/src/stm32/chip/stm32_usbdev.h index 02f347386..010f0ea5d 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_usbdev.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_usbdev.h @@ -43,7 +43,8 @@ #include <nuttx/config.h> #include <chip.h> -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) \ + || defined(CONFIG_STM32_STM32F37XX) /************************************************************************************ * Definitions @@ -231,6 +232,6 @@ #define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F10XX */ +#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */ #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_USBDEV_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h index cb6d89a6f..d9ba76170 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h @@ -520,6 +520,87 @@ # define DMACHAN_UART4_TX STM32_DMA2_CHAN5 # define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 +#elif defined(CONFIG_STM32_STM32F37XX) + +# define DMACHAN_ADC1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1 +# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_CH1 STM32_DMA1_CHAN1 +# define DMACHAN_TIM17_UP STM32_DMA1_CHAN1 + +# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2 +# define DMACHAN_USART3_TX STM32_DMA1_CHAN2 +# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2 +# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2 +# define DMACHAN_TIM19_CH1 STM32_DMA1_CHAN2 + +# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3 +# define DMACHAN_USART3_RX STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3 +# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM6_UP STM32_DMA1_CHAN3 +# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_CH1 STM32_DMA1_CHAN3 +# define DMACHAN_TIM16_UP STM32_DMA1_CHAN3 +# define DMACHAN_TIM19_CH2 STM32_DMA1_CHAN3 + +# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4 +# define DMACHAN_USART1_TX STM32_DMA1_CHAN4 +# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4 +# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_TIM7_UP STM32_DMA1_CHAN4 +# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 +# define DMACHAN_TIM19_UP STM32_DMA1_CHAN4 + +# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5 +# define DMACHAN_USART1_RX STM32_DMA1_CHAN5 +# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5 +# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5 +# define DMACHAN_TIM18_UP STM32_DMA1_CHAN5 +# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5 +# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5 + +# define DMACHAN_USART2_RX STM32_DMA1_CHAN6 +# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6 +# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6 + +# define DMACHAN_USART2_TX STM32_DMA1_CHAN7 +# define DMACHAN_I2C1_RX STM32_DMA1_CHAN6 +# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN6 +# define DMACHAN_TIM4_UP STM32_DMA1_CHAN6 +# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN6 +# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN6 + +# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1 +# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1 + +# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2 +# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2 + +# define DMACHAN_SDADC1 STM32_DMA2_CHAN3 +# define DMACHAN_TIM6_UP_2 STM32_DMA2_CHAN3 +# define DMACHAN_DAC1_CH1_2 STM32_DMA2_CHAN3 + +# define DMACHAN_SDADC2 STM32_DMA2_CHAN4 +# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4 +# define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4 +# define DMACHAN_DAC1_CH2_2 STM32_DMA2_CHAN4 + +# define DMACHAN_SDADC3 STM32_DMA2_CHAN5 +# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5 +# define DMACHAN_TIM18_UP_2 STM32_DMA2_CHAN5 +# define DMACHAN_DAC2_CH1_2 STM32_DMA2_CHAN5 + #else # error "Unknown DMA channel assignments" #endif diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h new file mode 100644 index 000000000..a745cb2de --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h @@ -0,0 +1,149 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* STM32F40XXX Address Blocks *******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ + /* 0x60000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */ + /* 0x1fff7a10-0x1fff7fff: Reserved */ +#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ + /* 0x1fffc008-0x1fffffff: Reserved */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ + /* 0x4000a000-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */ + /* 0x40016c00-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x4007ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */ + /* 0x48001800-0x4fffFfff: Reserved */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ +#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff TIM4 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ +#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff TIM12 */ +#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff TIM13 */ +#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */ +#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */ +#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff SPI3, or */ +#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff I2S3 */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ +#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */ +#define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ +#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC1 */ +#define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff CEC */ +#define STM32_DAC2_BASE 0x40009800 /* 0x40009800-0x40009bff DAC2 */ +#define STM32_TIM18_BASE 0x40009c00 /* 0x40009c00-0x40009fff TIM18 */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */ +#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */ +#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ +#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ +#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ +#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ +#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ +#define STM32_TIM19_BASE 0x40015c00 /* 0x40015c00-0x40015fff TIM19 */ +#define STM32_SDADC1_BASE 0x40016000 /* 0x40016000-0x400163ff SDADC1 */ +#define STM32_SDADC2_BASE 0x40016400 /* 0x40016000-0x400167ff SDADC2 */ +#define STM32_SDADC3_BASE 0x40016800 /* 0x40016000-0x40016bff SDADC3 */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ +#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ +#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ +#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ +#define STM32_GPIOD_BASE 0X40000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ +#define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ +#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ + +/* Cortex-M4 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this + * address range + */ + +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_MEMORYMAP_H */ + diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h new file mode 100644 index 000000000..4cc7543f7 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h @@ -0,0 +1,549 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "stm32_gpio.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Alternate Pin Functions. All members of the STM32F37xxx family share the same + * pin multiplexing (although they may differ in the pins physically available). + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN1_RX connects vis PA11 on some board, then the following definitions should + * appear inthe board.h header file for that board: + * + * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 + * + * The driver will then automatically configre PA11 as the CAN1 RX pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* CAN */ + +#define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_CAN_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_CAN_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_CAN_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_CAN_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_CAN_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) + + +/* Comparator Outputs */ +#define GPIO_COMP1_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN0) +#define GPIO_COMP1_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN11) +#define GPIO_COMP1_OUT_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN6) +#define GPIO_COMP1_OUT_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN8) +#define GPIO_COMP2_OUT_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2) +#define GPIO_COMP2_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12) +#define GPIO_COMP2_OUT_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN7) +#define GPIO_COMP2_OUT_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN9) + + +/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin + * (PA4 or PA5) is automatically connected to the analog converter output + * (DACy_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin + * should first be configured to analog (AIN)". + */ + +#define GPIO_DAC1_1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC1_2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_DAC2_1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) + +/* I2C */ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN15) +#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN14) +#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) + +#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1) +#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN6) +#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10) +#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0) +#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN7) +#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2) + +/* I2S */ + +#define GPIO_I2S1_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN5) +#define GPIO_I2S1_CK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN12) +#define GPIO_I2S1_CK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S1_CK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN7) +#define GPIO_I2S1_MCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN6) +#define GPIO_I2S1_MCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN13) +#define GPIO_I2S1_MCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN4) +#define GPIO_I2S1_MCK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN8) +#define GPIO_I2S1_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN7) +#define GPIO_I2S1_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN0) +#define GPIO_I2S1_SD_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S1_SD_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN9) +#define GPIO_I2S1_SD_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTF|GPIO_PIN6) +#define GPIO_I2S1_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN4) +#define GPIO_I2S1_WS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN11) +#define GPIO_I2S1_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN15) +#define GPIO_I2S1_WS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6) + +#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN8) +#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN10) +#define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN7) +#define GPIO_I2S2_CK_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN8) +#define GPIO_I2S2_MCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2S2_MCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN14) +#define GPIO_I2S2_MCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN2) +#define GPIO_I2S2_MCK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3) +#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN10) +#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN15) +#define GPIO_I2S2_SD_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3) +#define GPIO_I2S2_SD_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN4) +#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN11) +#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN6) + +#define GPIO_I2S3_CK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN1) +#define GPIO_I2S3_CK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S3_CK_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10) +#define GPIO_I2S3_MCK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN2) +#define GPIO_I2S3_MCK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN4) +#define GPIO_I2S3_MCK_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11) +#define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN3) +#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12) +#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4) +#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15) + +/* IR */ + +#define GPIO_IR_OUT_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN13) +#define GPIO_IR_OUT_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN9) + +/* JTAG/SWD */ + +#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) +#define GPIO_JTDO_TRACES_WO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_NJTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SWCLK_JTCK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_SWDIO_JTMS (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) + +/* MCO */ + +#define GPIO_MCO (GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) + +/* SPI */ + +#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN13) +#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI1_MISO_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) +#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI1_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI1_NSS_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI1_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) + +#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_SPI2_MISO_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3) +#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN4) +#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8) + +#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI3_MISO_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) + + +/* Timers */ + +#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH3OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH4OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_5 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH2OUT_5 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH3OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN2) + +#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH2OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN13) +#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN13) +#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH3OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH4IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM4_CH4OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM4_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM4_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM4_ETR_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) + +#define GPIO_TIM15_BKIN (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN10) +#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN10) +#define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) + +#define GPIO_TIM16_BKIN (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM16_CH1IN_4 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1OUT_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1IN_5 (GPIO_ALT|GPIO_FLOAT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) +#define GPIO_TIM16_CHOUT1_5 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) +#define GPIO_TIM16_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN13) +#define GPIO_TIM16_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6) + +#define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GGPIO_FLOAT|PIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1IN_4 (GPIO_ALT|GPIO_FLOAT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN1) +#define GPIO_TIM17_CH1OUT_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN1) +#define GPIO_TIM17_CH1N (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) + +/* TSC */ + +#define GPIO_TSC_G1_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TSC_G1_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TSC_G1_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TSC_G1_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TSC_G2_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN4) +#define GPIO_TSC_G2_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TSC_G2_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TSC_G2_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TSC_G3_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN5) +#define GPIO_TSC_G3_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TSC_G3_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TSC_G3_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN2) +#define GPIO_TSC_G4_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TSC_G4_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TSC_G4_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN13) +#define GPIO_TSC_G4_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN14) +#define GPIO_TSC_G5_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TSC_G5_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TSC_G5_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TSC_G5_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TSC_G6_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TSC_G6_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TSC_G6_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TSC_G6_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TSC_G7_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN2) +#define GPIO_TSC_G7_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TSC_G7_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TSC_G7_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TSC_G8_IO1 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TSC_G8_IO2 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TSC_G8_IO3 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TSC_G8_IO4 (GPIO_ALT|GPIO_AF3|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TSC_SYNC_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TSC_SYNC_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN8) + +/* Trace */ + +#define GPIO_TRACECK (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2) +#define GPIO_TRACED0 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TRACED1 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TRACED2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TRACED3 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6) + +/* USARTs/UARTs */ + +#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8) +#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12) +#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN5) +#define GPIO_USART1_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN1) +#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN4) +#define GPIO_USART1_TX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) + +#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4) +#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5) +#define GPIO_USART2_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7) +#define GPIO_USART2_CK_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTF|GPIO_PIN7) +#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0) +#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3) +#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1) +#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4) +#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_USART2_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6) +#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_USART2_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN5) + +#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12) +#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10) +#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN7) +#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11) +#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14) +#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12) +#define GPIO_USART3_RTS_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTF|GPIO_PIN6) +#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11) +#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN9) +#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN15) +#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10) +#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN8) + +/* USB */ + +#define GPIO_USB_DM (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USB_DP (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) + +/* Event Outputs */ + +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA1_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN1) +#define GPIO_PA2_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN2) +#define GPIO_PA3_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN3) +#define GPIO_PA4_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN4) +#define GPIO_PA5_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN5) +#define GPIO_PA6_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN6) +#define GPIO_PA7_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN7) +#define GPIO_PA8_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN8) +#define GPIO_PA9_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN9) +#define GPIO_PA10_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN10) +#define GPIO_PA11_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN11) +#define GPIO_PA12_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN12) +#define GPIO_PA13_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN13) +#define GPIO_PA14_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN14) +#define GPIO_PA15_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_PB0_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN0) +#define GPIO_PB1_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN1) +#define GPIO_PB2_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN2) +#define GPIO_PB3_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN3) +#define GPIO_PB4_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN4) +#define GPIO_PB5_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN5) +#define GPIO_PB6_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN6) +#define GPIO_PB7_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN7) +#define GPIO_PB8_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN8) +#define GPIO_PB9_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN9) +#define GPIO_PB10_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN10) +#define GPIO_PB11_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN11) +#define GPIO_PB12_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN12) +#define GPIO_PB13_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN13) +#define GPIO_PB14_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN14) +#define GPIO_PB15_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN15) + +#define GPIO_PC0_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN0) +#define GPIO_PC1_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN1) +#define GPIO_PC2_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN2) +#define GPIO_PC3_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN3) +#define GPIO_PC4_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN4) +#define GPIO_PC5_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN5) +#define GPIO_PC6_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN6) +#define GPIO_PC7_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN7) +#define GPIO_PC8_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN8) +#define GPIO_PC9_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN9) +#define GPIO_PC10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN10) +#define GPIO_PC11_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN11) +#define GPIO_PC12_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN12) + +#define GPIO_PD0_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN0) +#define GPIO_PD1_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN1) +#define GPIO_PD2_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN2) +#define GPIO_PD3_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN3) +#define GPIO_PD4_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN4) +#define GPIO_PD5_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN5) +#define GPIO_PD6_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN6) +#define GPIO_PD7_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN7) +#define GPIO_PD8_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN8) +#define GPIO_PD9_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN9) +#define GPIO_PD10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN10) +#define GPIO_PD11_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN11) +#define GPIO_PD12_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN12) +#define GPIO_PD13_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN13) +#define GPIO_PD14_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN14) +#define GPIO_PD15_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN15) + +#define GPIO_PE0_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN0) +#define GPIO_PE1_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN1) +#define GPIO_PE2_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN2) +#define GPIO_PE3_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN3) +#define GPIO_PE4_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN4) +#define GPIO_PE5_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN5) +#define GPIO_PE6_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN6) +#define GPIO_PE7_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN7) +#define GPIO_PE8_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_PE9_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN9) +#define GPIO_PE10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10) +#define GPIO_PE11_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN11) +#define GPIO_PE12_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12) +#define GPIO_PE13_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN13) +#define GPIO_PE14_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN14) +#define GPIO_PE15_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15) + +#define GPIO_PF2_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN2) +#define GPIO_PF4_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN4) +#define GPIO_PF6_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN6) +#define GPIO_PF9_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9) +#define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10) + + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H */ + diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h new file mode 100644 index 000000000..9c48bbd5d --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h @@ -0,0 +1,384 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f37xx_rcc.h + * For STM32F37xx advanced ARM-based 32-bit MCUs + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_RCC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_RCC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */ +#define STM32_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */ +#define STM32_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */ +#define STM32_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */ +#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */ +#define STM32_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */ +#define STM32_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */ +#define STM32_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */ + +/* Register Addresses ***************************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_AHBRSTR (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET) +#define STM32_RCC_CFGR2 (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET) +#define STM32_RCC_CFGR3 (STM32_RCC_BASE+STM32_RCC_CFGR3_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */ +#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT) +#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */ +#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT) +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */ +#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */ +#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */ + +/* Clock configuration register */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 1-0: System clock Switch */ +#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ +# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ +#define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ +# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ +#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */ +#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ +#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) +# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 13-11: APB High speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) +# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */ +#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */ +#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */ +#define RCC_CFGR_PLLMUL_MASK (0x0f << RCC_CFGR_PLLMUL_SHIFT) +# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */ +# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */ +# define RCC_CFGR_PLLMUL_CLKx4 (2 << RCC_CFGR_PLLMUL_SHIFT) /* 0010: PLL input clock x 4 */ +# define RCC_CFGR_PLLMUL_CLKx5 (3 << RCC_CFGR_PLLMUL_SHIFT) /* 0011: PLL input clock x 5 */ +# define RCC_CFGR_PLLMUL_CLKx6 (4 << RCC_CFGR_PLLMUL_SHIFT) /* 0100: PLL input clock x 6 */ +# define RCC_CFGR_PLLMUL_CLKx7 (5 << RCC_CFGR_PLLMUL_SHIFT) /* 0101: PLL input clock x 7 */ +# define RCC_CFGR_PLLMUL_CLKx8 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL input clock x 8 */ +# define RCC_CFGR_PLLMUL_CLKx9 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL input clock x 9 */ +# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */ +# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */ +# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */ +# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */ +# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */ +# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */ +# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */ +#define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB prescaler */ +#define RCC_CFGR_MCO_SHIFT (24) /* Bits 26-24: Microcontroller Clock Output */ +#define RCC_CFGR_MCO_MASK (3 << RCC_CFGR_MCO_SHIFT) +# define RCC_CFGR_MCO_DISABLED (0 << RCC_CFGR_MCO_SHIFT) /* 000: MCO output disabled, no clock on MCO */ +# define RCC_CFGR_MCO_LSICLK (2 << RCC_CFGR_MCO_SHIFT) /* 010: LSI clock selected */ +# define RCC_CFGR_MCO_LSECLK (3 << RCC_CFGR_MCO_SHIFT) /* 011: LSE clock selected */ +# define RCC_CFGR_MCO_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 100: System clock (SYSCLK) selected */ +# define RCC_CFGR_MCO_HSICLK (5 << RCC_CFGR_MCO_SHIFT) /* 101: HSI clock selected */ +# define RCC_CFGR_MCO_HSECLK (6 << RCC_CFGR_MCO_SHIFT) /* 101: HSE clock selected */ +# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */ +#define RCC_CFGR_SDADCPRE_SHIFT (24) /* Bits 27-31: SDADC Prescaler */ +#define RCC_CFGR_SDADCPRE_MASK (31 << RCC_CFGR_SDADCPRE_SHIFT) +# define RCC_CFGR_SDADCPRE_DIV2 (0 << RCC_CFGR_SDADCPRE_SHIFT) /* 0xxxx: System clock divided by 2 */ +# define RCC_CFGR_SDADCPRE_DIV4 (17 << RCC_CFGR_SDADCPRE_SHIFT) /* 10001: System clock divided by 4 */ +# define RCC_CFGR_SDADCPRE_DIV6 (18 << RCC_CFGR_SDADCPRE_SHIFT) /* 10010: System clock divided by 6 */ +# define RCC_CFGR_SDADCPRE_DIV8 (19 << RCC_CFGR_SDADCPRE_SHIFT) /* 10011: System clock divided by 8 */ +# define RCC_CFGR_SDADCPRE_DIV10 (20 << RCC_CFGR_SDADCPRE_SHIFT) /* 10100: System clock divided by 10 */ +# define RCC_CFGR_SDADCPRE_DIV12 (21 << RCC_CFGR_SDADCPRE_SHIFT) /* 10101: System clock divided by 12 */ +# define RCC_CFGR_SDADCPRE_DIV14 (22 << RCC_CFGR_SDADCPRE_SHIFT) /* 10110: System clock divided by 14 */ +# define RCC_CFGR_SDADCPRE_DIV16 (23 << RCC_CFGR_SDADCPRE_SHIFT) /* 10111: System clock divided by 16 */ +# define RCC_CFGR_SDADCPRE_DIV20 (24 << RCC_CFGR_SDADCPRE_SHIFT) /* 11000: System clock divided by 20 */ +# define RCC_CFGR_SDADCPRE_DIV24 (25 << RCC_CFGR_SDADCPRE_SHIFT) /* 11001: System clock divided by 24 */ +# define RCC_CFGR_SDADCPRE_DIV28 (26 << RCC_CFGR_SDADCPRE_SHIFT) /* 11010: System clock divided by 28 */ +# define RCC_CFGR_SDADCPRE_DIV32 (27 << RCC_CFGR_SDADCPRE_SHIFT) /* 11011: System clock divided by 32 */ +# define RCC_CFGR_SDADCPRE_DIV36 (28 << RCC_CFGR_SDADCPRE_SHIFT) /* 11100: System clock divided by 36 */ +# define RCC_CFGR_SDADCPRE_DIV40 (29 << RCC_CFGR_SDADCPRE_SHIFT) /* 11101: System clock divided by 40 */ +# define RCC_CFGR_SDADCPRE_DIV44 (30 << RCC_CFGR_SDADCPRE_SHIFT) /* 11110: System clock divided by 44 */ +# define RCC_CFGR_SDADCPRE_DIV48 (31 << RCC_CFGR_SDADCPRE_SHIFT) /* 11111: System clock divided by 48 */ + +/* Clock interrupt register */ + +#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers reset */ +#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ +#define RCC_APB2RSTR_TIM19RST (1 << 19) /* Bit 19: TIM19 reset */ +#define RCC_APB2RSTR_SDADC1RST (1 << 24) /* Bit 24: SDADC1 reset */ +#define RCC_APB2RSTR_SDADC2RST (1 << 25) /* Bit 25: SDADC2 reset */ +#define RCC_APB2RSTR_SDADC3RST (1 << 26) /* Bit 26: SDADC3 reset */ + +/* APB1 Peripheral reset register */ + +#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */ +#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: Timer 4 reset */ +#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 2: Timer 5 reset */ +#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */ +#define RCC_APB1RSTR_TIM12RST (1 << 6) /* Bit 6: Timer 12 reset */ +#define RCC_APB1RSTR_TIM13RST (1 << 7) /* Bit 7: Timer 13 reset */ +#define RCC_APB1RSTR_TIM14RST (1 << 8) /* Bit 8: Timer 14 reset */ +#define RCC_APB1RSTR_TIM18RST (1 << 9) /* Bit 9: Timer 18 reset */ +#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window Watchdog reset */ +#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */ +#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */ +#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ +#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ +#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */ +#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* Bit 25: CAN reset */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN reset */ +#define RCC_APB1RSTR_DAC2RST (1 << 26) /* Bit 26: DAC1 interface reset */ +#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ +#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */ +#define RCC_APB1RSTR_CECRST (1 << 30) /* Bit 30: CEC reset */ + +/* AHB Peripheral Clock enable register */ + +#define RCC_AHBENR_DMA1EN (1 << 0) /* Bit 0: DMA1 clock enable */ +#define RCC_AHBENR_DMA2EN (1 << 1) /* Bit 1: DMA2 clock enable */ +#define RCC_AHBENR_SRAMEN (1 << 2) /* Bit 2: SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN (1 << 4) /* Bit 4: FLITF clock enable */ +#define RCC_AHBENR_CRCEN (1 << 6) /* Bit 6: CRC clock enable */ +#define RCC_AHBENR_IOPAEN (1 << 17) /* Bit 17: I/O port A clock enable */ +#define RCC_AHBENR_IOPBEN (1 << 18) /* Bit 17: I/O port B clock enable */ +#define RCC_AHBENR_IOPCEN (1 << 19) /* Bit 17: I/O port C clock enable */ +#define RCC_AHBENR_IOPDEN (1 << 20) /* Bit 17: I/O port D clock enable */ +#define RCC_AHBENR_IOPEEN (1 << 21) /* Bit 17: I/O port E clock enable */ +#define RCC_AHBENR_IOPFEN (1 << 22) /* Bit 17: I/O port F clock enable */ +#define RCC_AHBENR_TSCEN (1 << 24) /* Bit 24: TSCEN: Touch sensing controller clock enable */ + +/* APB2 Peripheral Clock enable register */ + +#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers clock enable */ +#define RCC_APB2ENR_ADC1EN (1 << 9) /* Bit 9: ADC1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 clock enable */ +#define RCC_APB2ENR_TIM19EN (1 << 19) /* Bit 19: TIM19 clock enable */ +#define RCC_APB2ENR_SDADC1EN (1 << 24) /* Bit 24: SDADC1 clock enable */ +#define RCC_APB2ENR_SDADC2EN (1 << 25) /* Bit 25: SDADC2 clock enable */ +#define RCC_APB2ENR_SDADC3EN (1 << 26) /* Bit 26: SDADC3 clock enable */ + +/* APB1 Peripheral Clock enable register */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */ +#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */ +#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: Timer 4 clock enable */ +#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 2: Timer 5 clock enable */ +#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 clock enable */ +#define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: Timer 12 clock enable */ +#define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: Timer 13 clock enable */ +#define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: Timer 14 clock enable */ +#define RCC_APB1ENR_TIM18EN (1 << 9) /* Bit 9: Timer 18 clock enable */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */ +#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI 3 clock enable */ +#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ +#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */ +#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */ +#define RCC_APB1ENR_CANEN (1 << 25) /* Bit 25: CAN clock enable */ +#define RCC_APB1ENR_DAC2EN (1 << 26) /* Bit 26: DAC1 interface clock enable */ +#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */ +#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */ +#define RCC_APB1ENR_CECEN (1 << 30) /* Bit 30: CEC clock enable */ + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator drive capability */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' lower driving capability */ +# define RCC_BDCR_LSEDRV_MEDLOW (1 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' medium low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHIGH (2 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' medium high driving capability */ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' higher driving capability */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + +/* Control/status register */ + +#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */ +#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option byte loader reset flag */ +#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* AHB peripheral clock reset register (RCC_AHBRSTR) */ + +#define RCC_AHBRSTR_IOPARST (1 << 17) /* Bit 17: I/O port A reset */ +#define RCC_AHBRSTR_IOPBRST (1 << 18) /* Bit 18: I/O port B reset */ +#define RCC_AHBRSTR_IOPCRST (1 << 29) /* Bit 19: I/O port C reset */ +#define RCC_AHBRSTR_IOPDRST (1 << 20) /* Bit 20: I/O port D reset */ +#define RCC_AHBRSTR_IOPERST (1 << 21) /* Bit 21: I/O port E reset */ +#define RCC_AHBRSTR_IOPFRST (1 << 22) /* Bit 22: I/O port F reset */ +#define RCC_AHBRSTR_TSCRST (1 << 24) /* Bit 24: Touch sensing controller reset */ + +/* Clock configuration register 2 */ + +#define RCC_CFGR2_PREDIV_SHIFT (0) /* Bits 0-3: PREDIV division factor */ +#define RCC_CFGR2_PREDIV_MASK (15 << RCC_CFGR2_PREDIV_SHIFT) +# define RCC_CFGR2_PREDIVd1 (0 << RCC_CFGR2_PREDIV_SHIFT) /* 0000: HSE input to PLL not divided */ +# define RCC_CFGR2_PREDIVd2 (1 << RCC_CFGR2_PREDIV_SHIFT) /* 0001: HSE input to PLL divided by 2 */ +# define RCC_CFGR2_PREDIVd3 (2 << RCC_CFGR2_PREDIV_SHIFT) /* 0010: HSE input to PLL divided by 3 */ +# define RCC_CFGR2_PREDIVd4 (3 << RCC_CFGR2_PREDIV_SHIFT) /* 0011: HSE input to PLL divided by 4 */ +# define RCC_CFGR2_PREDIVd5 (4 << RCC_CFGR2_PREDIV_SHIFT) /* 0100: HSE input to PLL divided by 5 */ +# define RCC_CFGR2_PREDIVd6 (5 << RCC_CFGR2_PREDIV_SHIFT) /* 0101: HSE input to PLL divided by 6 */ +# define RCC_CFGR2_PREDIVd7 (6 << RCC_CFGR2_PREDIV_SHIFT) /* 0110: HSE input to PLL divided by 7 */ +# define RCC_CFGR2_PREDIVd8 (7 << RCC_CFGR2_PREDIV_SHIFT) /* 0111: HSE input to PLL divided by 8 */ +# define RCC_CFGR2_PREDIVd9 (8 << RCC_CFGR2_PREDIV_SHIFT) /* 1000: HSE input to PLL divided by 9 */ +# define RCC_CFGR2_PREDIVd10 (9 << RCC_CFGR2_PREDIV_SHIFT) /* 1001: HSE input to PLL divided by 10 */ +# define RCC_CFGR2_PREDIVd11 (10 << RCC_CFGR2_PREDIV_SHIFT) /* 1010: HSE input to PLL divided by 11 */ +# define RCC_CFGR2_PREDIVd12 (11 << RCC_CFGR2_PREDIV_SHIFT) /* 1011: HSE input to PLL divided by 12 */ +# define RCC_CFGR2_PREDIVd13 (12 << RCC_CFGR2_PREDIV_SHIFT) /* 1100: HSE input to PLL divided by 13 */ +# define RCC_CFGR2_PREDIVd14 (13 << RCC_CFGR2_PREDIV_SHIFT) /* 1101: HSE input to PLL divided by 14 */ +# define RCC_CFGR2_PREDIVd15 (14 << RCC_CFGR2_PREDIV_SHIFT) /* 1110: HSE input to PLL divided by 15 */ +# define RCC_CFGR2_PREDIVd16 (15 << RCC_CFGR2_PREDIV_SHIFT) /* 1111: HSE input to PLL divided by 16 */ + +/* Clock configuration register 3 */ + +#define RCC_CFGR3_USART1SW_SHIFT (0) /* Bits 0-1: USART1 clock source selection */ +#define RCC_CFGR3_USART1SW_MASK (3 << RCC_CFGR3_USART1SW_SHIFT) +# define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) /* PCLK */ +# define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* System clock (SYSCLK) */ +# define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE clock */ +# define RCC_CFGR3_USART1SW_HSI (0 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */ +#define RCC_CFGR3_I2C1SW (1 << 4) /* Bit 4: I2C1 clock source selection */ +#define RCC_CFGR3_I2C2SW (1 << 5) /* Bit 5: I2C2 clock source selection */ +#define RCC_CFGR3_CECSW (1 << 6) /* Bit 6: CEC clock source selection */ +#define RCC_CFGR3_USART2SW_SHIFT (16) /* Bits 16-17: USART2 clock source selection */ +#define RCC_CFGR3_USART2SW_MASK (3 << RCC_CFGR3_USART2SW_SHIFT) +# define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK */ +# define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* System clock (SYSCLK) */ +# define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE clock */ +# define RCC_CFGR3_USART2SW_HSI (0 << RCC_CFGR3_USART2SW_SHIFT) /* HSI clock */ +#define RCC_CFGR3_USART3SW_SHIFT (18) /* Bits 18-19: USART3 clock source selection */ +#define RCC_CFGR3_USART3SW_MASK (3 << RCC_CFGR3_USART3SW_SHIFT) +# define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK */ +# define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART3SW_SHIFT) /* System clock (SYSCLK) */ +# define RCC_CFGR3_USART3SW_LSE (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE clock */ +# define RCC_CFGR3_USART3SW_HSI (0 << RCC_CFGR3_USART3SW_SHIFT) /* HSI clock */ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_RCC_H */ + diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h new file mode 100644 index 000000000..2219009ef --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h @@ -0,0 +1,166 @@ +/**************************************************************************************************** + * arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SYSCFG_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SYSCFG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +#ifdef CONFIG_STM32_STM32F37XX + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ + +#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) + +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) + +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* SYSCFG memory remap register */ + +#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */ +#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) +# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */ +#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */ +#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */ +#define SYSCFG_CFGR1_TIM6_DMARMP (1 << 13) /* Bit 13: TIM6 DMA remap, or */ +#define SYSCFG_CFGR1_DAC1_CH1_DMARMP (1 << 13) /* Bit 13: DAC 1 channel 2 DMA remap */ +#define SYSCFG_CFGR1_TIM7_DMARMP (1 << 14) /* Bit 14: TIM7 DMA remap */ +#define SYSCFG_CFGR1_DAC1_CH2_DMARMP (1 << 14) /* Bit 14: DAC 1 channel 2 DMA remap */ +#define SYSCFG_CFGR1_TIM18_DMARMP (1 << 15) /* Bit 15: TIM18 DMA remap */ +#define SYSCFG_CFGR1_DAC2_CH1_DMARMP (1 << 15) /* Bit 15: DAC 2 channel 1 DMA remap */ +#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */ +#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT) +#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */ +#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */ +#define SYSCFG_CFGR1_VBAT (1 << 24) /* Bit 24: VBat monitor enable */ +#define SYSCFG_CFGR1_FPUIE_SHIFT (26) /* Bits 26-31: Floating Point Unit interrupts enable bits */ +#define SYSCFG_CFGR1_FPUIE_MASK (63 << SYSCFG_CFGR1_FPUIE_SHIFT) +# define SYSCFG_CFGR1_FPUIE_INVALIDOP (1 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Invalid operation interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_DIVZERO (2 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Divide-by-zero interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_UNDERFLOW (4 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Underflow interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_OVERFLOW (8 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Overflow interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_DENORMAL (16 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Input denormal interrupt enable */ +# define SYSCFG_CFGR1_FPUIE_INEXACT (32 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Inexact interrupt enable */ + + +/* SYSCFG external interrupt configuration register 1-4 */ + +#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */ +#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */ +#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */ +#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */ +#define SYSCFG_EXTICR_PORTE (4) /* 0100: Reserved */ +#define SYSCFG_EXTICR_PORTE (5) /* 0101: PF[x] pin */ + +#define SYSCFG_EXTICR_PORT_MASK (15) +#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2) +#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g))) + +#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT) +#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT) +#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT) +#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT) + +#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT) +#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT) +#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT) +#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT) + +#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT) +#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT) +#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT) +#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT) + +#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT) +#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT) +#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT) +#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) + +/* SYSCFG configuration register 2 */ + +#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M4 Hardfault output bit enable */ +#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */ +#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */ +#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */ + +#endif /* CONFIG_STM32_STM32F37XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SYSCFG_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_vectors.h new file mode 100644 index 000000000..c85269daf --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_vectors.h @@ -0,0 +1,150 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f37xxx_vectors.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by stm32_vectors.S. It provides the macro VECTOR that + * supplies each STM32F37xxx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f37xxx_irq.h. + * stm32_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 82 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 82 + +#else + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */ +VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */ + +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */ +VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */ +VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */ +VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */ +VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */ +VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */ +VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */ +VECTOR(stm32_adc1, STM32_IRQ_ADC1) /* 18: ADC1 global interrupt */ +VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: CAN1 TX interrupts */ + +VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: CAN1 RX0 interrupts*/ +VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */ +VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim15, STM32_IRQ_TIM15) /* 24: TIM15 global interrupt */ +VECTOR(stm32_tim16, STM32_IRQ_TIM16) /* 25: TIM16 global interrupt */ +VECTOR(stm32_tim17, STM32_IRQ_TIM17) /* 26: TIM17 global interrupt */ +VECTOR(stm32_tim18, STM32_IRQ_TIM18) /* 27: TIM18 global interrupt or DAC2 interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */ + +VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */ +VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event or EXTI Line24 interrupt */ +VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */ +VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */ + +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */ +VECTOR(stm32_cec, STM32_IRQ_CEC) /* 42: CEC global interrupt */ +VECTOR(stm32_tim12, STM32_IRQ_TIM12) /* 43: TIM12 global interrupt */ +VECTOR(stm32_tim13, STM32_IRQ_TIM13) /* 44: TIM13 global interrupt */ +VECTOR(stm32_tim14, STM32_IRQ_TIM14) /* 45: TIM14 global interrupt */ +UNUSED(STM32_IRQ_RESERVED46) /* 46: Reserved */ +UNUSED(STM32_IRQ_RESERVED47) /* 47: Reserved */ +UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */ +UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */ + +UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */ +VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 51: SPI3 global interrupt */ +UNUSED(STM32_IRQ_RESERVED52) /* 52: Reserved */ +UNUSED(STM32_IRQ_RESERVED53) /* 53: Reserved */ +VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 54: TIM6 global or DAC1 underrun interrupts */ +VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 55: TIM7 global interrupt */ +VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 56: DMA2 channel 1 global interrupt */ +VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 57: DMA2 channel 2 global interrupt */ +VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 58: DMA2 channel 3 global interrupt */ +VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 59: DMA2 channel 4 global interrupt */ + +VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 60: DMA2 channel 5 global interrupt */ +VECTOR(stm32_sdadc1, STM32_IRQ_SDADC1) /* 61: SDADC1 global interrupt */ +VECTOR(stm32_sdadc2, STM32_IRQ_SDADC2) /* 62: SDADC2 global interrupt */ +VECTOR(stm32_sdadc3, STM32_IRQ_SDADC3) /* 63: SDADC3 global interrupt */ +VECTOR(stm32_comp12, STM32_IRQ_COMP12) /* 64: COMP1-2 */ +UNUSED(STM32_IRQ_RESERVED65) /* 65: Reserved */ +UNUSED(STM32_IRQ_RESERVED66) /* 66: Reserved */ +UNUSED(STM32_IRQ_RESERVED67) /* 67: Reserved */ +UNUSED(STM32_IRQ_RESERVED68) /* 68: Reserved */ +UNUSED(STM32_IRQ_RESERVED69) /* 69: Reserved */ + +UNUSED(STM32_IRQ_RESERVED70) /* 70: Reserved */ +UNUSED(STM32_IRQ_RESERVED71) /* 71: Reserved */ +UNUSED(STM32_IRQ_RESERVED72) /* 72: Reserved */ +UNUSED(STM32_IRQ_RESERVED73) /* 73: Reserved */ +VECTOR(stm32_usbhp, STM32_IRQ_USBHP) /* 74: USB High priority interrupt */ +VECTOR(stm32_usblp, STM32_IRQ_USBLP) /* 75: USB Low priority interrupt */ +VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP) /* 76: USB wakeup from suspend through EXTI line interrupt*/ +UNUSED(STM32_IRQ_RESERVED77) /* 77: Reserved */ +UNUSED(STM32_IRQ_RESERVED78) /* 78: Reserved */ +UNUSED(STM32_IRQ_RESERVED79) /* 79: Reserved */ + +UNUSED(STM32_IRQ_RESERVED80) /* 80: Reserved */ +VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 81: FPU global interrupt */ + +#endif /* CONFIG_ARMV7M_CMNVECTOR */ diff --git a/nuttx/arch/arm/src/stm32/stm32_allocateheap.c b/nuttx/arch/arm/src/stm32/stm32_allocateheap.c index fcc95cd7f..d8ee41189 100644 --- a/nuttx/arch/arm/src/stm32/stm32_allocateheap.c +++ b/nuttx/arch/arm/src/stm32/stm32_allocateheap.c @@ -219,6 +219,31 @@ # endif # endif +/* All members of the STM32F37xxx families have 16-32 Kib ram in a single + * bank. No external RAM is supported (the F3 family has no FSMC). + */ +#elif defined(CONFIG_STM32_STM32F37XX) + + /* Set the end of system SRAM */ + +# define SRAM1_END CONFIG_RAM_END + + /* There is no FSMC */ + +# undef CONFIG_STM32_FSMC_SRAM + + /* The STM32 F37xx has no CCM SRAM */ + +# undef CONFIG_STM32_CCMEXCLUDE +# define CONFIG_STM32_CCMEXCLUDE 1 + + /* Only one memory region can be support (internal SRAM) */ + +# if CONFIG_MM_REGIONS > 1 +# error "CONFIG_MM_REGIONS > 1. The STM32L15X has only one memory region." +# endif + + /* Most members of both the STM32F20xxx and STM32F40xxx families have 128Kib * in two banks: * diff --git a/nuttx/arch/arm/src/stm32/stm32_dma.h b/nuttx/arch/arm/src/stm32/stm32_dma.h index a552345e3..b2f968fe1 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dma.h +++ b/nuttx/arch/arm/src/stm32/stm32_dma.h @@ -48,7 +48,7 @@ /* Include the correct DMA register definitions for this STM32 family */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f10xxx_dma.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_dma.h" @@ -63,7 +63,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define DMA_STATUS_FEIF 0 /* (Not available in F1) */ # define DMA_STATUS_DMEIF 0 /* (Not available in F1) */ # define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ @@ -106,7 +106,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) struct stm32_dmaregs_s { uint32_t isr; diff --git a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c index 06976956d..89749eab4 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c @@ -174,7 +174,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) g_portchar[port], getreg32(STM32_RCC_AHBENR)); } -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) DEBUGASSERT(port < STM32_NGPIO_PORTS); diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c index f6e01f65c..e2adaea1f 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.c +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c @@ -55,7 +55,8 @@ #include "stm32_gpio.h" #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32_syscfg.h" #endif @@ -420,7 +421,8 @@ int stm32_configgpio(uint32_t cfgset) ****************************************************************************/ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) int stm32_configgpio(uint32_t cfgset) { uintptr_t base; @@ -576,7 +578,7 @@ int stm32_configgpio(uint32_t cfgset) setting = GPIO_OSPEED_50MHz; break; -#ifndef CONFIG_STM32_STM32F30XX +#if !defined(CONFIG_STM32_STM32F30XX) && !defined(CONFIG_STM32_STM32F37XX) case GPIO_SPEED_100MHz: /* 100 MHz High speed output */ setting = GPIO_OSPEED_100MHz; break; @@ -680,7 +682,8 @@ int stm32_unconfiggpio(uint32_t cfgset) #if defined(CONFIG_STM32_STM32F10XX) cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) cfgset |= GPIO_INPUT | GPIO_FLOAT; #else # error "Unsupported STM32 chip" @@ -705,7 +708,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value) #if defined(CONFIG_STM32_STM32F10XX) uint32_t offset; #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) uint32_t bit; #endif unsigned int port; @@ -738,7 +742,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value) putreg32((1 << pin), base + offset); #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) if (value) { diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h index b0b000a89..50ffc84b9 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.h +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h @@ -59,7 +59,7 @@ # include "chip/stm32f10xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_gpio.h" -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f30xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_gpio.h" @@ -201,7 +201,8 @@ #define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) /* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured * by software in several modes: diff --git a/nuttx/arch/arm/src/stm32/stm32_lowputc.c b/nuttx/arch/arm/src/stm32/stm32_lowputc.c index dd7c04653..bbf6e4868 100644 --- a/nuttx/arch/arm/src/stm32/stm32_lowputc.c +++ b/nuttx/arch/arm/src/stm32/stm32_lowputc.c @@ -230,7 +230,7 @@ # define USART_CR1_PARITY_VALUE 0 # endif -# ifdef CONFIG_STM32_STM32F30XX +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define USART_CR1_CLRBITS\ (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS |\ USART_CR1_PCE |USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME |\ @@ -252,7 +252,7 @@ # define USART_CR2_STOP2_VALUE 0 # endif -# ifdef CONFIG_STM32_STM32F30XX +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define USART_CR2_CLRBITS \ (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL |\ USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK |\ @@ -268,7 +268,7 @@ /* CR3 settings */ -# ifdef CONFIG_STM32_STM32F30XX +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define USART_CR3_CLRBITS \ (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL |\ @@ -288,7 +288,7 @@ /* Calculate USART BAUD rate divider */ -# ifdef CONFIG_STM32_STM32F30XX +# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) /* Baud rate for standard USART (SPI mode included): * @@ -563,7 +563,8 @@ void stm32_lowsetup(void) } #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) void stm32_lowsetup(void) { diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c index 67dfea713..0d7a3cbe1 100644 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c @@ -84,6 +84,8 @@ # include "stm32f20xxx_rcc.c" #elif defined(CONFIG_STM32_STM32F30XX) # include "stm32f30xxx_rcc.c" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "stm32f37xxx_rcc.c" #elif defined(CONFIG_STM32_STM32F40XX) # include "stm32f40xxx_rcc.c" #else @@ -183,3 +185,4 @@ void stm32_clockenable(void) #endif } #endif + diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h index 3c20e031e..d114e9f8e 100644 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.h +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h @@ -53,6 +53,8 @@ # include "chip/stm32f20xxx_rcc.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_rcc.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_rcc.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_rcc.h" #endif diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index 19a1cf01b..da254c2bb 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -150,7 +150,7 @@ # endif # elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F30XX) # if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ defined(CONFIG_USART3_RXDMA) @@ -186,7 +186,7 @@ # ifndef CONFIG_USART_DMAPRIO # if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED # elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # define CONFIG_USART_DMAPRIO DMA_SCR_PRIMED @@ -195,7 +195,7 @@ # endif # endif # if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F30XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_USART_DMAPRIO" # endif @@ -1154,7 +1154,7 @@ static void up_set_format(struct uart_dev_s *dev) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t regval; -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. */ @@ -1803,7 +1803,7 @@ static int up_interrupt_common(struct up_dev_s *priv) else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) { -#ifdef CONFIG_STM32_STM32F30XX +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) /* These errors are cleared by writing the corresponding bit to the * interrupt clear register (ICR). */ diff --git a/nuttx/arch/arm/src/stm32/stm32_syscfg.h b/nuttx/arch/arm/src/stm32/stm32_syscfg.h index 657734df3..8098779f2 100644 --- a/nuttx/arch/arm/src/stm32/stm32_syscfg.h +++ b/nuttx/arch/arm/src/stm32/stm32_syscfg.h @@ -49,6 +49,8 @@ # include "chip/stm32f20xxx_syscfg.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_syscfg.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_syscfg.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_syscfg.h" #endif diff --git a/nuttx/arch/arm/src/stm32/stm32_uart.h b/nuttx/arch/arm/src/stm32/stm32_uart.h index 2229e0036..c0ffd1fc3 100644 --- a/nuttx/arch/arm/src/stm32/stm32_uart.h +++ b/nuttx/arch/arm/src/stm32/stm32_uart.h @@ -50,7 +50,7 @@ # include "chip/stm32f10xxx_uart.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F30XX) +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f30xxx_uart.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_uart.h" diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S index 8f015b7e2..f4fb29185 100644 --- a/nuttx/arch/arm/src/stm32/stm32_vectors.S +++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S @@ -177,6 +177,8 @@ _vectors: # include "chip/stm32f20xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_vectors.h" #else @@ -217,6 +219,8 @@ handlers: # include "chip/stm32f20xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_vectors.h" #else @@ -359,7 +363,7 @@ exception_common: * * Here: * r0 = Address of the register save area - + * * NOTE: It is a requirement that up_restorefpu() preserve the value of * r0! */ diff --git a/nuttx/arch/arm/src/stm32/stm32f37xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f37xxx_rcc.c new file mode 100644 index 000000000..ddf3c5d9b --- /dev/null +++ b/nuttx/arch/arm/src/stm32/stm32f37xxx_rcc.c @@ -0,0 +1,548 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32f37xxx_rcc.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Put all RCC registers in reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */ + putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */ + putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */ + putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */ + putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */ + + regval = getreg32(STM32_RCC_CR); /* Set the HSION bit */ + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, USBPRE, and MCO bits */ + regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK | + RCC_CFGR_PPRE2_MASK | RCC_CFGR_USBPRE | RCC_CFGR_MCO_MASK); + putreg32(regval, STM32_RCC_CFGR); + + regval = getreg32(STM32_RCC_CFGR2); /* Reset PREDIV bits */ + regval &= ~(RCC_CFGR2_PREDIV_MASK); + putreg32(regval, STM32_RCC_CFGR2); + + putreg32(0, STM32_RCC_CFGR2); /* Reset fCK source for all U[S]ARTs to PCLK */ + + regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */ + regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON); + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */ + regval &= ~RCC_CR_HSEBYP; + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK | + RCC_CFGR_USBPRE); + putreg32(regval, STM32_RCC_CFGR); + + putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ +} + +/**************************************************************************** + * Name: rcc_enableahb + * + * Description: + * Enable selected AHB peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb(void) +{ + uint32_t regval; + + /* Always enable FLITF clock and SRAM clock */ + + regval = RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN; + + /* Enable GPIO PORTA, PORTB, ... PORTF */ + + regval |= (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN | + RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN); + +#ifdef CONFIG_STM32_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHBENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHBENR_DMA2EN; +#endif + +#ifdef CONFIG_STM32_CRC + /* CRC clock enable */ + + regval |= RCC_AHBENR_CRCEN; +#endif + +#ifdef CONFIG_STM32_TSC + /* TSC clock enable */ + + regval |= RCC_AHBENR_TSCEN; +#endif + + putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + +#ifdef CONFIG_STM32_USB + /* USB clock divider. This bit must be valid before enabling the USB + * clock in the RCC_APB1ENR register. This bit can’t be reset if the USB + * clock is enabled. + */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_USBPRE; + regval |= STM32_CFGR_USBPRE; + putreg32(regval, STM32_RCC_CFGR); +#endif + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + +#ifdef CONFIG_STM32_TIM2 + /* Timer 2 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM2EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM3 + /* Timer 3 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM3EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM4 + /* Timer 4 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM4EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM5 + /* Timer 5 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM4EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM6 + /* Timer 6 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM6EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM7 + /* Timer 7 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM7EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM12 + /* Timer 12 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM12EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM13 + /* Timer 13 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM13EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM14 + /* Timer 14 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM14EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM18 + /* Timer 7 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM18EN; +#endif +#endif + +#ifdef CONFIG_STM32_WWDG + /* Window Watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#ifdef CONFIG_STM32_SPI2 + /* SPI 2 clock enable */ + + regval |= RCC_APB1ENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32_SPI3 + /* SPI 3 clock enable */ + + regval |= RCC_APB1ENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32_USART2 + /* USART 2 clock enable */ + + regval |= RCC_APB1ENR_USART2EN; +#endif + +#ifdef CONFIG_STM32_USART3 + /* USART 3 clock enable */ + + regval |= RCC_APB1ENR_USART3EN; +#endif + +#ifdef CONFIG_STM32_I2C1 + /* I2C 1 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_I2C1EN; +#endif +#endif + +#ifdef CONFIG_STM32_I2C2 + /* I2C 2 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_I2C2EN; +#endif +#endif + +#ifdef CONFIG_STM32_USB + /* USB clock enable */ + + regval |= RCC_APB1ENR_USBEN; +#endif + +#ifdef CONFIG_STM32_CAN1 + /* CAN1 clock enable */ + + regval |= RCC_APB1ENR_CANEN; +#endif + +#ifdef CONFIG_STM32_DAC2 + /* DAC 2 interface clock enable */ + + regval |= RCC_APB1ENR_DAC2EN; +#endif + +#ifdef CONFIG_STM32_PWR + /* Power interface clock enable */ + + regval |= RCC_APB1ENR_PWREN; +#endif + +#ifdef CONFIG_STM32_DAC1 + /* DAC 1 interface clock enable */ + + regval |= RCC_APB1ENR_DAC1EN; +#endif + + + putreg32(regval, STM32_RCC_APB1ENR); +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32_SYSCFG + /* SYSCFG clock */ + + regval |= RCC_APB2ENR_SYSCFGEN; +#endif + + +#ifdef CONFIG_STM32_SPI1 + /* SPI 1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32_TIM15 + /* TIM15 Timer clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM15EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM16 + /* TIM16 Timer clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM16EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM17 + /* TIM17 Timer clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM17EN; +#endif +#endif + +#ifdef CONFIG_STM32_TIM19 + /* TIM17 Timer clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM17EN; +#endif +#endif + + putreg32(regval, STM32_RCC_APB2ENR); +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h. + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + + /* If the PLL is using the HSE, or the HSE is the system clock */ + +#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) + + { + volatile int32_t timeout; + + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + + if (timeout == 0) + { + /* In the case of a timeout starting the HSE, we really don't have a + * strategy. This is almost always a hardware failure or misconfiguration. + */ + + return; + } + } + + /* If this is a value-line part and we are using the HSE as the PLL */ +# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1) +# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1 +# endif + + /* Set the HSE prescaler */ + + regval = STM32_CFGR2_PREDIV1; + putreg32(regval, STM32_RCC_CFGR2); + +# endif + + + /* Enable FLASH prefetch buffer and 2 wait states */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); + + + /* Set the HCLK source/divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE2_MASK; + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + + /* If we are using the PLL, configure and start it */ + +#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL + + /* Set the PLL divider and multipler */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK); + regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL); + putreg32(regval, STM32_RCC_CFGR); + + /* Enable the PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLL is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); + +#endif + + /* Select the system clock source (probably the PLL) */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= STM32_SYSCLK_SW; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the selected source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb(); + rcc_enableapb2(); + rcc_enableapb1(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ |