Add LPC43xx GIMA and GPIO header files

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4887 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 1157 insertions, 118 deletions

diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h
new file mode 100644
index 000000000..641fcf8c6
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h
@@ -0,0 +1,336 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_gima.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+/* Timer capture input multiplexor registers */
+
+#define LPC32_GIMA_CAP_OFFSET(t,i)    (((t) << 4) | ((i) << 2))
+#define LPC43_GIMA_CAP00_OFFSET       0x0000  /* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+#define LPC43_GIMA_CAP01_OFFSET       0x0004  /* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+#define LPC43_GIMA_CAP02_OFFSET       0x0008  /* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+#define LPC43_GIMA_CAP03_OFFSET       0x000c  /* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+#define LPC43_GIMA_CAP10_OFFSET       0x0010  /* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+#define LPC43_GIMA_CAP11_OFFSET       0x0014  /* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+#define LPC43_GIMA_CAP12_OFFSET       0x0018  /* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+#define LPC43_GIMA_CAP13_OFFSET       0x001c  /* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+#define LPC43_GIMA_CAP20_OFFSET       0x0020  /* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+#define LPC43_GIMA_CAP21_OFFSET       0x0024  /* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+#define LPC43_GIMA_CAP22_OFFSET       0x0028  /* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+#define LPC43_GIMA_CAP23_OFFSET       0x002c  /* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+#define LPC43_GIMA_CAP30_OFFSET       0x0030  /* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+#define LPC43_GIMA_CAP31_OFFSET       0x0034  /* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+#define LPC43_GIMA_CAP32_OFFSET       0x0038  /* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+#define LPC43_GIMA_CAP33_OFFSET       0x003c  /* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+
+#define LPC32_GIMA_CTIN_OFFSET(i)     (0x0040 + ((i) << 2))
+#define LPC43_GIMA_CTIN0_OFFSET       0x0040  /* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+#define LPC43_GIMA_CTIN1_OFFSET       0x0044  /* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+#define LPC43_GIMA_CTIN2_OFFSET       0x0048  /* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+#define LPC43_GIMA_CTIN3_OFFSET       0x004c  /* SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+#define LPC43_GIMA_CTIN4_OFFSET       0x0050  /* SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+#define LPC43_GIMA_CTIN5_OFFSET       0x0054  /* SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+#define LPC43_GIMA_CTIN6_OFFSET       0x0058  /* SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+#define LPC43_GIMA_CTIN7_OFFSET       0x005c  /* SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+
+#define LPC43_GIMA_VADCTRIG_OFFSET    0x0060  /* VADC trigger input multiplexer (GIMA output 24) */
+#define LPC43_GIMA_EVNTRTR13_OFFSET   0x0064  /* Event router input 13 multiplexer (GIMA output 25) */
+#define LPC43_GIMA_EVNTRTR14_OFFSET   0x0068  /* Event router input 14 multiplexer (GIMA output 26) */
+#define LPC43_GIMA_EVNTRTR16_OFFSET   0x006c  /* Event router input 16 multiplexer (GIMA output 27) */
+#define LPC43_GIMA_ADCSTART0_OFFSET   0x0070  /* ADC start0 input multiplexer (GIMA output 28) */
+#define LPC43_GIMA_ADCSTART1_OFFSET   0x0074  /* ADC start1 input multiplexer (GIMA output 29) */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC32_GIMA_CAP(t,i)           (LPC43_GIMA_BASE+LPC32_GIMA_CAP_OFFSET(t,i))
+#define LPC43_GIMA_CAP00              (LPC43_GIMA_BASE+LPC43_GIMA_CAP00_OFFSET)
+#define LPC43_GIMA_CAP01              (LPC43_GIMA_BASE+LPC43_GIMA_CAP01_OFFSET)
+#define LPC43_GIMA_CAP02              (LPC43_GIMA_BASE+LPC43_GIMA_CAP02_OFFSET)
+#define LPC43_GIMA_CAP03              (LPC43_GIMA_BASE+LPC43_GIMA_CAP03_OFFSET)
+#define LPC43_GIMA_CAP10              (LPC43_GIMA_BASE+LPC43_GIMA_CAP10_OFFSET)
+#define LPC43_GIMA_CAP11              (LPC43_GIMA_BASE+LPC43_GIMA_CAP11_OFFSET)
+#define LPC43_GIMA_CAP12              (LPC43_GIMA_BASE+LPC43_GIMA_CAP12_OFFSET)
+#define LPC43_GIMA_CAP13              (LPC43_GIMA_BASE+LPC43_GIMA_CAP13_OFFSET)
+#define LPC43_GIMA_CAP20              (LPC43_GIMA_BASE+LPC43_GIMA_CAP20_OFFSET)
+#define LPC43_GIMA_CAP21              (LPC43_GIMA_BASE+LPC43_GIMA_CAP21_OFFSET)
+#define LPC43_GIMA_CAP22              (LPC43_GIMA_BASE+LPC43_GIMA_CAP22_OFFSET)
+#define LPC43_GIMA_CAP23              (LPC43_GIMA_BASE+LPC43_GIMA_CAP23_OFFSET)
+#define LPC43_GIMA_CAP30              (LPC43_GIMA_BASE+LPC43_GIMA_CAP30_OFFSET)
+#define LPC43_GIMA_CAP31              (LPC43_GIMA_BASE+LPC43_GIMA_CAP31_OFFSET)
+#define LPC43_GIMA_CAP32              (LPC43_GIMA_BASE+LPC43_GIMA_CAP32_OFFSET)
+#define LPC43_GIMA_CAP33              (LPC43_GIMA_BASE+LPC43_GIMA_CAP33_OFFSET)
+
+#define LPC32_GIMA_CTIN(i)            (LPC43_GIMA_BASE+LPC32_GIMA_CTIN_OFFSET(i))
+#define LPC43_GIMA_CTIN0              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN0_OFFSET)
+#define LPC43_GIMA_CTIN1              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN1_OFFSET)
+#define LPC43_GIMA_CTIN2              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN2_OFFSET)
+#define LPC43_GIMA_CTIN3              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN3_OFFSET)
+#define LPC43_GIMA_CTIN4              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN4_OFFSET)
+#define LPC43_GIMA_CTIN5              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN5_OFFSET)
+#define LPC43_GIMA_CTIN6              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN6_OFFSET)
+#define LPC43_GIMA_CTIN7              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN7_OFFSET)
+#define LPC43_GIMA_VADCTRIG           (LPC43_GIMA_BASE+LPC43_GIMA_VADCTRIG_OFFSET)
+#define LPC43_GIMA_EVNTRTR13          (LPC43_GIMA_BASE+LPC43_GIMA_EVNTRTR13_OFFSET)
+#define LPC43_GIMA_EVNTRTR14          (LPC43_GIMA_BASE+LPC43_GIMA_EVNTRTR14_OFFSET)
+#define LPC43_GIMA_EVNTRTR16          (LPC43_GIMA_BASE+LPC43_GIMA_EVNTRTR16_OFFSET)
+#define LPC43_GIMA_ADCSTART0          (LPC43_GIMA_BASE+LPC43_GIMA_ADCSTART0_OFFSET)
+#define LPC43_GIMA_ADCSTART1          (LPC43_GIMA_BASE+LPC43_GIMA_ADCSTART1_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Common register field definitions */
+
+#define GIMA_INV                      (1 << 0)  /* Bit 0:  Invert input  */
+#define GIMA_EDGE                     (1 << 1)  /* Bit 1:  Enable rising edge detection */
+#define GIMA_SYNCH                    (1 << 2)  /* Bit 2:  Enable synchronization */
+#define GIMA_PULSE                    (1 << 3)  /* Bit 3:  Enable single pulse generation */
+#define GIMA_SELECT_SHIFT             (4)       /* Bits 4-7: Select input */
+#define GIMA_SELECT_MASK              (15 << GIMA_SELECT_SHIFT)
+                                                /* Bits 8-31:  Reserved */
+/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP00_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP00_SELECT_SGPIO3    (1 << GIMA_SELECT_SHIFT) /* SGPIO3 */
+#  define GIMA_CAP00_SELECT_TOCAP0    (2 << GIMA_SELECT_SHIFT) /* T0_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP01_SELECT_CTIN1     (0 << GIMA_SELECT_SHIFT) /* CTIN_1 */
+#  define GIMA_CAP01_SELECT_U2TX      (1 << GIMA_SELECT_SHIFT) /* USART2 TX active */
+#  define GIMA_CAP01_SELECT_TOCAP1    (2 << GIMA_SELECT_SHIFT) /* T0_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP02_SELECT_CTIN2     (0 << GIMA_SELECT_SHIFT) /* CTIN_2 */
+#  define GIMA_CAP02_SELECT_SGPIO3D   (1 << GIMA_SELECT_SHIFT) /* SGPIO3_DIV */
+#  define GIMA_CAP02_SELECT_T0CAP2    (2 << GIMA_SELECT_SHIFT) /* T0_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP03_SELECT_CTOUT15   (0 << GIMA_SELECT_SHIFT) /* CTOUT_15 or T3_MAT3 */
+#  define GIMA_CAP03_SELECT_T0CAP3    (1 << GIMA_SELECT_SHIFT) /* T0_CAP3 */
+#  define GIMA_CAP03_SELECT_T3MAT3    (2 << GIMA_SELECT_SHIFT) /* T3_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP10_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP10_SELECT_SGPIO12   (1 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_CAP10_SELECT_T1CAP0    (2 << GIMA_SELECT_SHIFT) /* T1_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+                                                 /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP11_SELECT_CTIN3     (0 << GIMA_SELECT_SHIFT) /* CTIN_3 */
+#  define GIMA_CAP11_SELECT_U0TX      (1 << GIMA_SELECT_SHIFT) /* USART0 TX active */
+#  define GIMA_CAP11_SELECT_T1CAP1    (2 << GIMA_SELECT_SHIFT) /* T1_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP12_SELECT_CTIN4     (0 << GIMA_SELECT_SHIFT) /* CTIN_4 */
+#  define GIMA_CAP12_SELECT_U0RX      (1 << GIMA_SELECT_SHIFT) /* USART0 RX active */
+#  define GIMA_CAP12_SELECT_T1CAP2    (2 << GIMA_SELECT_SHIFT) /* T1_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP13_SELECT_CTOUT3    (0 << GIMA_SELECT_SHIFT) /* CTOUT_3 or T0_MAT3 */
+#  define GIMA_CAP13_SELECT_T1CAP3    (1 << GIMA_SELECT_SHIFT) /* T1_CAP3 */
+#  define GIMA_CAP13_SELECT_T0MAT3    (2 << GIMA_SELECT_SHIFT) /* T0_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP20_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP20_SELECT_SGPIO12D  (1 << GIMA_SELECT_SHIFT) /* SGPIO12_DIV */
+#  define GIMA_CAP20_SELECT_T2CAP0    (2 << GIMA_SELECT_SHIFT) /* T2_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP21_SELECT_CTIN1     (0 << GIMA_SELECT_SHIFT) /* CTIN_1 */
+#  define GIMA_CAP21_SELECT_U2TX      (1 << GIMA_SELECT_SHIFT) /* USART2 TX active */
+#  define GIMA_CAP21_SELECT_T2CAP1    (2 << GIMA_SELECT_SHIFT) /* T2_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP22_SELECT_CTIN5     (0 << GIMA_SELECT_SHIFT) /* CTIN_5 */
+#  define GIMA_CAP22_SELECT_U2RX      (1 << GIMA_SELECT_SHIFT) /* USART2 RX active */
+#  define GIMA_CAP22_SELECT_I2S1TX    (2 << GIMA_SELECT_SHIFT) /* I2S1_TX_MWS */
+#  define GIMA_CAP22_SELECT_T2CAP2    (3 << GIMA_SELECT_SHIFT) /* T2_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP23_SELECT_CTOUT7    (0 << GIMA_SELECT_SHIFT) /* CTOUT_7 or T1_MAT3 */
+#  define GIMA_CAP23_SELECT_T2CAP3    (1 << GIMA_SELECT_SHIFT) /* T2_CAP3 */
+#  define GIMA_CAP23_SELECT_T1MAT3    (2 << GIMA_SELECT_SHIFT) /* T1_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP30_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP30_SELECT_I2S0RX    (1 << GIMA_SELECT_SHIFT) /* I2S0_RX_MWS */
+#  define GIMA_CAP30_SELECT_T3CAP0    (2 << GIMA_SELECT_SHIFT) /* T3_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP31_SELECT_CTIN6     (0 << GIMA_SELECT_SHIFT) /* CTIN_6 */
+#  define GIMA_CAP31_SELECT_U3TX      (1 << GIMA_SELECT_SHIFT) /* USART3 TX active */
+#  define GIMA_CAP31_SELECT_I2S0TX    (2 << GIMA_SELECT_SHIFT) /* I2S0_TX_MWS */
+#  define GIMA_CAP31_SELECT_T3CAP1    (3 << GIMA_SELECT_SHIFT) /* T3_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP32_SELECT_CTIN7     (0 << GIMA_SELECT_SHIFT) /* CTIN_7 */
+#  define GIMA_CAP32_SELECT_U3RX      (1 << GIMA_SELECT_SHIFT) /* USART3 RX active */
+#  define GIMA_CAP32_SELECT_SOF0      (2 << GIMA_SELECT_SHIFT) /* SOF0 (Start-Of-Frame USB0) */
+#  define GIMA_CAP32_SELECT_T3CAP2    (3 << GIMA_SELECT_SHIFT) /* T3_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP33_SELECT_CTOUT11   (0 << GIMA_SELECT_SHIFT) /* CTOUT11 or T2_MAT3 */
+#  define GIMA_CAP33_SELECT_SOF1      (1 << GIMA_SELECT_SHIFT) /* SOF1 (Start-Of-Frame USB1) */
+#  define GIMA_CAP33_SELECT_T3CAP3    (2 << GIMA_SELECT_SHIFT) /* T3_CAP3 */
+#  define GIMA_CAP33_SELECT_T2MAT3    (3 << GIMA_SELECT_SHIFT) /* T2_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN0_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CTIN0_SELECT_SGPIO3    (1 << GIMA_SELECT_SHIFT) /* SGPIO3 */
+#  define GIMA_CTIN0_SELECT_SGPIO3D   (2 << GIMA_SELECT_SHIFT) /* SGPIO3_DIV */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN1_SELECT_CTIN1     (0 << GIMA_SELECT_SHIFT) /* CTIN_1 */
+#  define GIMA_CTIN1_SELECT_U2TX      (1 << GIMA_SELECT_SHIFT) /* USART2 TX active */
+#  define GIMA_CTIN1_SELECT_SGPIO12   (2 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN2_SELECT_CTIN2     (0 << GIMA_SELECT_SHIFT) /* CTIN_2 */
+#  define GIMA_CTIN2_SELECT_SGPIO12   (1 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_CTIN2_SELECT_SGPIO12D  (2 << GIMA_SELECT_SHIFT) /* SGPIO12_DIV */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN3_SELECT_CTIN3     (0 << GIMA_SELECT_SHIFT) /* CTIN_3 */
+#  define GIMA_CTIN3_SELECT_U0TX      (1 << GIMA_SELECT_SHIFT) /* USART0 TX active */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN4_SELECT_CTIN4     (0 << GIMA_SELECT_SHIFT) /* CTIN_4*/
+#  define GIMA_CTIN4_SELECT_U0RX      (1 << GIMA_SELECT_SHIFT) /* USART0 RX active */
+#  define GIMA_CTIN4_SELECT_I2S1RX    (2 << GIMA_SELECT_SHIFT) /* I2S1_RX_MWS1 */
+#  define GIMA_CTIN4_SELECT_I2S1TX    (3 << GIMA_SELECT_SHIFT) /* I2S1_TX_MWS1 */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN5_SELECT_CTIN5     (0 << GIMA_SELECT_SHIFT) /* CTIN_5 */
+#  define GIMA_CTIN5_SELECT_U2RX      (1 << GIMA_SELECT_SHIFT) /* USART2 RX active */
+#  define GIMA_CTIN5_SELECT_SGPIO12D  (2 << GIMA_SELECT_SHIFT) /* SGPIO12_DIV */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN6_SELECT_CTIN6     (0 << GIMA_SELECT_SHIFT) /* CTIN_6 */
+#  define GIMA_CTIN6_SELECT_U3TX      (1 << GIMA_SELECT_SHIFT) /* USART3 TX active */
+#  define GIMA_CTIN6_SELECT_I2S0RX    (2 << GIMA_SELECT_SHIFT) /* I2S0_RX_MWS */
+#  define GIMA_CTIN6_SELECT_I2S0TX    (3 << GIMA_SELECT_SHIFT) /* I2S0_TX_MWS */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN7_SELECT_CTIN7     (0 << GIMA_SELECT_SHIFT) /* CTIN_7 */
+#  define GIMA_CTIN7_SELECT_U3RX      (1 << GIMA_SELECT_SHIFT) /* USART3 RX active */
+#  define GIMA_CTIN7_SELECT_SOF0      (2 << GIMA_SELECT_SHIFT) /* SOF0 (Start-Of-Frame USB0) */
+#  define GIMA_CTIN7_SELECT_SOF1      (3 << GIMA_SELECT_SHIFT) /* SOF1 (Start-Of-Frame USB1) */
+                                                /* Bits 8-31: Reserved */
+/* VADC trigger input multiplexer (GIMA output 24) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_VADC_SELECT_GPIO6p28   (0 << GIMA_SELECT_SHIFT) /* GPIO6[28] */
+#  define GIMA_VADC_SELECT_GPIO5p3    (1 << GIMA_SELECT_SHIFT) /* GPIO5[3] */
+#  define GIMA_VADC_SELECT_SGPIO10    (2 << GIMA_SELECT_SHIFT) /* SGPIO10 */
+#  define GIMA_VADC_SELECT_SGPIO12    (3 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_VADC_SELECT_MCOB2      (5 << GIMA_SELECT_SHIFT) /* MCOB2 */
+#  define GIMA_VADC_SELECT_CTOUT0     (6 << GIMA_SELECT_SHIFT) /* CTOUT_0 or T0_MAT0 */
+#  define GIMA_VADC_SELECT_CTOUT8     (7 << GIMA_SELECT_SHIFT) /* CTOUT_8 or T2_MAT0 */
+#  define GIMA_VADC_SELECT_T0MAT0     (8 << GIMA_SELECT_SHIFT) /* T0_MAT0 */
+#  define GIMA_VADC_SELECT_T2MAT0     (9 << GIMA_SELECT_SHIFT) /* T2_MAT0 */
+                                                /* Bits 8-31: Reserved */
+/* Event router input 13 multiplexer (GIMA output 25) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_EVNTRTR_SELECT_CTOUT2  (0 << GIMA_SELECT_SHIFT) /* CTOUT_2 or T0_MAT2 */
+#  define GIMA_EVNTRTR_SELECT_SGPIO3  (1 << GIMA_SELECT_SHIFT) /* SGPIO3 */
+#  define GIMA_EVNTRTR_SELECT_T0MAT2  (2 << GIMA_SELECT_SHIFT) /* T0_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* Event router input 14 multiplexer (GIMA output 26) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_EVNTRTR_SELECT_CTOUT6  (0 << GIMA_SELECT_SHIFT) /* CTOUT_6 or T1_MAT2 */
+#  define GIMA_EVNTRTR_SELECT_SGPIO12 (1 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_EVNTRTR_SELECT_T1MAT2  (2 << GIMA_SELECT_SHIFT) /* T1_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* Event router input 16 multiplexer (GIMA output 27) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_EVNTRTR_SELECT_CTOUT14 (0 << GIMA_SELECT_SHIFT) /* CTOUT_14 or T3_MAT2 */
+#  define GIMA_EVNTRTR_SELECT_T3MAT2  (1 << GIMA_SELECT_SHIFT) /* T3_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* ADC start0 input multiplexer (GIMA output 28) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_ADC0_SELECT_CTOUT15    (0 << GIMA_SELECT_SHIFT) /* CTOUT_15 or T3_MAT3 */
+#  define GIMA_ADC0_SELECT_T3MAT2     (1 << GIMA_SELECT_SHIFT) /* T3_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* ADC start1 input multiplexer (GIMA output 29) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_ADC1_SELECT_CTOUT8     (0 << GIMA_SELECT_SHIFT) /* CTOUT_8 or T2_MAT0 */
+#  define GIMA_ADC1_SELECT_T2MAT0     (1 << GIMA_SELECT_SHIFT) /* T2_MAT0 */
+                                                /* Bits 8-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h
new file mode 100644
index 000000000..49c0fea62
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h
@@ -0,0 +1,506 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_gpio.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Indices */
+
+#deine LPC43_GPIO_PORT0             0
+#deine LPC43_GPIO_PORT1             1
+#deine LPC43_GPIO_PORT2             2
+#deine LPC43_GPIO_PORT3             3
+#deine LPC43_GPIO_PORT4             4
+#deine LPC43_GPIO_PORT5             5
+#deine LPC43_GPIO_PORT6             6
+#deine LPC43_GPIO_PORT7             7
+
+#deine LPC43_GPIO_PIN0              0
+#deine LPC43_GPIO_PIN1              1
+#deine LPC43_GPIO_PIN2              2
+#deine LPC43_GPIO_PIN3              3
+#deine LPC43_GPIO_PIN4              4
+#deine LPC43_GPIO_PIN5              5
+#deine LPC43_GPIO_PIN6              6
+#deine LPC43_GPIO_PIN7              7
+#deine LPC43_GPIO_PIN8              8
+#deine LPC43_GPIO_PIN9              9
+#deine LPC43_GPIO_PIN10             10
+#deine LPC43_GPIO_PIN11             11
+#deine LPC43_GPIO_PIN12             12
+#deine LPC43_GPIO_PIN13             13
+#deine LPC43_GPIO_PIN14             14
+#deine LPC43_GPIO_PIN15             15
+#deine LPC43_GPIO_PIN16             16
+#deine LPC43_GPIO_PIN17             17
+#deine LPC43_GPIO_PIN18             18
+#deine LPC43_GPIO_PIN19             19
+#deine LPC43_GPIO_PIN20             20
+#deine LPC43_GPIO_PIN21             21
+#deine LPC43_GPIO_PIN22             22
+#deine LPC43_GPIO_PIN23             23
+#deine LPC43_GPIO_PIN24             24
+#deine LPC43_GPIO_PIN25             25
+#deine LPC43_GPIO_PIN26             26
+#deine LPC43_GPIO_PIN27             27
+#deine LPC43_GPIO_PIN28             28
+#deine LPC43_GPIO_PIN29             29
+#deine LPC43_GPIO_PIN30             30
+#deine LPC43_GPIO_PIN31             31
+
+/* Register Offsets *********************************************************************************/
+
+/* Pin interrupt registers (relative to LPC43_GPIOINT_BASE) */
+
+#define LPC43_GPIOINT_ISEL_OFFSET   0x000 /* Pin Interrupt Mode register */
+#define LPC43_GPIOINT_IENR_OFFSET   0x004 /* Pin interrupt level (rising edge) interrupt enable register */
+#define LPC43_GPIOINT_SIENR_OFFSET  0x008 /* Pin interrupt level (rising edge) interrupt set register */
+#define LPC43_GPIOINT_CIENR_OFFSET  0x00c /* Pin interrupt level (rising edge interrupt) clear register */
+#define LPC43_GPIOINT_IENF_OFFSET   0x010 /* Pin interrupt active level (falling edge) interrupt enable register */
+#define LPC43_GPIOINT_SIENF_OFFSET  0x014 /* Pin interrupt active level (falling edge) interrupt set register */
+#define LPC43_GPIOINT_CIENF_OFFSET  0x018 /* Pin interrupt active level (falling edge) interrupt clear register */
+#define LPC43_GPIOINT_RISE_OFFSET   0x01c /* Pin interrupt rising edge register */
+#define LPC43_GPIOINT_FALL_OFFSET   0x020 /* Pin interrupt falling edge register */
+#define LPC43_GPIOINT_IST_OFFSET    0x024 /* Pin interrupt status register */
+
+/* GPIO GROUP0 interrupt registers (relative to LPC43_GRP0INT_BASE) */
+
+#define LPC43_GRP0INT_CTRL_OFFSET   0x000 /* GPIO grouped interrupt control register */
+
+#define LPC43_GRP0INT_POL_OFFSET(p) (0x020 + ((p) << 2 ))
+#define LPC43_GRP0INT_POL0_OFFSET   0x020 /* GPIO grouped interrupt port 0 polarity register */
+#define LPC43_GRP0INT_POL1_OFFSET   0x024 /* GPIO grouped interrupt port 1 polarity register */
+#define LPC43_GRP0INT_POL2_OFFSET   0x028 /* GPIO grouped interrupt port 2 polarity register */
+#define LPC43_GRP0INT_POL3_OFFSET   0x02c /* GPIO grouped interrupt port 3 polarity register */
+#define LPC43_GRP0INT_POL4_OFFSET   0x030 /* GPIO grouped interrupt port 4 polarity register */
+#define LPC43_GRP0INT_POL5_OFFSET   0x034 /* GPIO grouped interrupt port 5 polarity register */
+#define LPC43_GRP0INT_POL6_OFFSET   0x038 /* GPIO grouped interrupt port 6 polarity register */
+#define LPC43_GRP0INT_POL7_OFFSET   0x03c /* GPIO grouped interrupt port 7 polarity register */
+
+#define LPC43_GRP0INT_ENA_OFFSET(p) (0x040 + ((p) << 2 ))
+#define LPC43_GRP0INT_ENA0_OFFSET   0x040 /* GPIO grouped interrupt port 0 enable register */
+#define LPC43_GRP0INT_ENA1_OFFSET   0x044 /* GPIO grouped interrupt port 1 enable register */
+#define LPC43_GRP0INT_ENA2_OFFSET   0x048 /* GPIO grouped interrupt port 2 enable register */
+#define LPC43_GRP0INT_ENA3_OFFSET   0x04c /* GPIO grouped interrupt port 3 enable register */
+#define LPC43_GRP0INT_ENA4_OFFSET   0x050 /* GPIO grouped interrupt port 4 enable register */
+#define LPC43_GRP0INT_ENA5_OFFSET   0x054 /* GPIO grouped interrupt port 5 enable register */
+#define LPC43_GRP0INT_ENA6_OFFSET   0x058 /* GPIO grouped interrupt port 5 enable register */
+#define LPC43_GRP0INT_ENA7_OFFSET   0x05c /* GPIO grouped interrupt port 5 enable register */
+
+/* GPIO GROUP1 interrupt registers (relative to LPC43_GRP1INT_BASE) */
+
+#define LPC43_GRP1INT_CTRL_OFFSET   0x000 /* GPIO grouped interrupt control register */
+
+#define LPC43_GRP1INT_POL_OFFSET(p) (0x020 + ((p) << 2 ))
+#define LPC43_GRP1INT_POL0_OFFSET   0x020 /* GPIO grouped interrupt port 0 polarity register */
+#define LPC43_GRP1INT_POL1_OFFSET   0x024 /* GPIO grouped interrupt port 1 polarity register */
+#define LPC43_GRP1INT_POL2_OFFSET   0x028 /* GPIO grouped interrupt port 2 polarity register */
+#define LPC43_GRP1INT_POL3_OFFSET   0x02c /* GPIO grouped interrupt port 3 polarity register */
+#define LPC43_GRP1INT_POL4_OFFSET   0x030 /* GPIO grouped interrupt port 4 polarity register */
+#define LPC43_GRP1INT_POL5_OFFSET   0x034 /* GPIO grouped interrupt port 5 polarity register */
+#define LPC43_GRP1INT_POL6_OFFSET   0x038 /* GPIO grouped interrupt port 6 polarity register */
+#define LPC43_GRP1INT_POL7_OFFSET   0x03c /* GPIO grouped interrupt port 7 polarity register */
+
+#define LPC43_GRP1INT_ENA_OFFSET(p) (0x040 + ((p) << 2 ))
+#define LPC43_GRP1INT_ENA0_OFFSET   0x040 /* GPIO grouped interrupt port 0 enable register */
+#define LPC43_GRP1INT_ENA1_OFFSET   0x044 /* GPIO grouped interrupt port 1 enable register */
+#define LPC43_GRP1INT_ENA2_OFFSET   0x048 /* GPIO grouped interrupt port 2 enable register */
+#define LPC43_GRP1INT_ENA3_OFFSET   0x04c /* GPIO grouped interrupt port 3 enable register */
+#define LPC43_GRP1INT_ENA4_OFFSET   0x050 /* GPIO grouped interrupt port 4 enable register */
+#define LPC43_GRP1INT_ENA5_OFFSET   0x054 /* GPIO grouped interrupt port 5 enable register */
+#define LPC43_GRP1INT_ENA6_OFFSET   0x058 /* GPIO grouped interrupt port 5 enable register */
+#define LPC43_GRP1INT_ENA7_OFFSET   0x05c /* GPIO grouped interrupt port 5 enable register */
+
+/* GPIO Port Registers (relative to LPC43_GPIO_BASE) */
+
+#define LPC43_GPIO_B_OFFSET(p,n)    (((p) << 5) + (n))
+#define LPC43_GPIO_B0_OFFSET(n)     (0x0000 + (n)) /* PIO0_0 to PIO0_31 byte pin registers */
+#define LPC43_GPIO_B1_OFFSET(n)     (0x0020 + (n)) /* PIO1_0 to PIO1_31 byte pin registers */
+#define LPC43_GPIO_B2_OFFSET(n)     (0x0040 + (n)) /* PIO2_0 to PIO2_31 byte pin registers */
+#define LPC43_GPIO_B3_OFFSET(n)     (0x0060 + (n)) /* PIO3_0 to PIO3_31 byte pin registers */
+#define LPC43_GPIO_B4_OFFSET(n)     (0x0080 + (n)) /* PIO4_0 to PIO4_31 byte pin registers */
+#define LPC43_GPIO_B5_OFFSET(n)     (0x00a0 + (n)) /* PIO5_0 to PIO5_31 byte pin registers */
+#define LPC43_GPIO_B6_OFFSET(n)     (0x00c0 + (n)) /* PIO6_0 to PIO6_31 byte pin registers */
+#define LPC43_GPIO_B7_OFFSET(n)     (0x00e0 + (n)) /* PIO7_0 to PIO7_31 byte pin registers */
+
+#define LPC43_GPIO_W_OFFSET(p,n)    (0x1000 + ((p) << 7) + ((n) << 2))
+#define LPC43_GPIO_W0_OFFSET(n)     (0x1000 + ((n) << 2)) /* PIO0_0 to PIO0_31 word pin registers */
+#define LPC43_GPIO_W1_OFFSET(n)     (0x1080 + ((n) << 2)) /* PIO1_0 to PIO1_31 word pin registers */
+#define LPC43_GPIO_W2_OFFSET(n)     (0x1100 + ((n) << 2)) /* PIO2_0 to PIO2_31 word pin registers */
+#define LPC43_GPIO_W3_OFFSET(n)     (0x1180 + ((n) << 2)) /* PIO3_0 to PIO3_31 word pin registers */
+#define LPC43_GPIO_W4_OFFSET(n)     (0x1200 + ((n) << 2)) /* PIO4_0 to PIO4_31 word pin registers */
+#define LPC43_GPIO_W5_OFFSET(n)     (0x1280 + ((n) << 2)) /* PIO5_0 to PIO5_31 word pin registers */
+#define LPC43_GPIO_W6_OFFSET(n)     (0x1300 + ((n) << 2)) /* PIO6_0 to PIO6_31 word pin registers */
+#define LPC43_GPIO_W7_OFFSET(n)     (0x1380 + ((n) << 2)) /* PIO7_0 to PIO7_31 word pin registers */
+
+#define LPC43_GPIO_DIR_OFFSET(p)    (0x2000 + ((p) << 2))
+#define LPC43_GPIO_DIR0_OFFSET      0x2000 /* Direction registers port 0 */
+#define LPC43_GPIO_DIR1_OFFSET      0x2004 /* Direction registers port 1 */
+#define LPC43_GPIO_DIR2_OFFSET      0x2008 /* Direction registers port 2 */
+#define LPC43_GPIO_DIR3_OFFSET      0x200c /* Direction registers port 3 */
+#define LPC43_GPIO_DIR4_OFFSET      0x2010 /* Direction registers port 4 */
+#define LPC43_GPIO_DIR5_OFFSET      0x2014 /* Direction registers port 5 */
+#define LPC43_GPIO_DIR6_OFFSET      0x2018 /* Direction registers port 6 */
+#define LPC43_GPIO_DIR7_OFFSET      0x201c /* Direction registers port 7 */
+
+#define LPC43_GPIO_MASK_OFFSET(p)   (0x2080 + ((p) << 2))
+#define LPC43_GPIO_MASK0_OFFSET     0x2080 /* Mask register port 0 */
+#define LPC43_GPIO_MASK1_OFFSET     0x2084 /* Mask register port 1 */
+#define LPC43_GPIO_MASK2_OFFSET     0x2088 /* Mask register port 2 */
+#define LPC43_GPIO_MASK3_OFFSET     0x208c /* Mask register port 3 */
+#define LPC43_GPIO_MASK4_OFFSET     0x2090 /* Mask register port 4 */
+#define LPC43_GPIO_MASK5_OFFSET     0x2094 /* Mask register port 5 */
+#define LPC43_GPIO_MASK6_OFFSET     0x2098 /* Mask register port 6 */
+#define LPC43_GPIO_MASK7_OFFSET     0x209c /* Mask register port 7 */
+
+#define LPC43_GPIO_PIN_OFFSET(p)    (0x2100 + ((p) << 2))
+#define LPC43_GPIO_PIN0_OFFSET      0x2100 /* Port pin register port 0 */
+#define LPC43_GPIO_PIN1_OFFSET      0x2104 /* Port pin register port 1 */
+#define LPC43_GPIO_PIN2_OFFSET      0x2108 /* Port pin register port 2 */
+#define LPC43_GPIO_PIN3_OFFSET      0x210c /* Port pin register port 3 */
+#define LPC43_GPIO_PIN4_OFFSET      0x2110 /* Port pin register port 4 */
+#define LPC43_GPIO_PIN5_OFFSET      0x2114 /* Port pin register port 5 */
+#define LPC43_GPIO_PIN6_OFFSET      0x2118 /* Port pin register port 6 */
+#define LPC43_GPIO_PIN7_OFFSET      0x211c /* Port pin register port 7 */
+
+#define LPC43_GPIO_MPIN_OFFSET(p)   (0x2100 + ((p) << 2))
+#define LPC43_GPIO_MPIN0_OFFSET     0x2180 /* Masked port register port 0 */
+#define LPC43_GPIO_MPIN1_OFFSET     0x2184 /* Masked port register port 1 */
+#define LPC43_GPIO_MPIN2_OFFSET     0x2188 /* Masked port register port 2 */
+#define LPC43_GPIO_MPIN3_OFFSET     0x218c /* Masked port register port 3 */
+#define LPC43_GPIO_MPIN4_OFFSET     0x2190 /* Masked port register port 4 */
+#define LPC43_GPIO_MPIN5_OFFSET     0x2194 /* Masked port register port 5 */
+#define LPC43_GPIO_MPIN6_OFFSET     0x2198 /* Masked port register port 6 */
+#define LPC43_GPIO_MPIN7_OFFSET     0x219c /* Masked port register port 7 */
+
+#define LPC43_GPIO_SET_OFFSET(p)    (0x2200 + ((p) << 2))
+#define LPC43_GPIO_SET0_OFFSET      0x2200 /* Write: Set register for port 0 */
+#define LPC43_GPIO_SET1_OFFSET      0x2204 /* Write: Set register for port 1 */
+#define LPC43_GPIO_SET2_OFFSET      0x2208 /* Write: Set register for port 2 */
+#define LPC43_GPIO_SET3_OFFSET      0x220c /* Write: Set register for port 3 */
+#define LPC43_GPIO_SET4_OFFSET      0x2210 /* Write: Set register for port 4 */
+#define LPC43_GPIO_SET5_OFFSET      0x2214 /* Write: Set register for port 5 */
+#define LPC43_GPIO_SET6_OFFSET      0x2218 /* Write: Set register for port 6 */
+#define LPC43_GPIO_SET7_OFFSET      0x221c /* Write: Set register for port 7 */
+
+#define LPC43_GPIO_CLR_OFFSET(p)    (0x2280 + ((p) << 2))
+#define LPC43_GPIO_CLR0_OFFSET      0x2280 /* Clear port 0 */
+#define LPC43_GPIO_CLR1_OFFSET      0x2284 /* Clear port 1 */
+#define LPC43_GPIO_CLR2_OFFSET      0x2288 /* Clear port 2 */
+#define LPC43_GPIO_CLR3_OFFSET      0x228c /* Clear port 3 */
+#define LPC43_GPIO_CLR4_OFFSET      0x2290 /* Clear port 4 */
+#define LPC43_GPIO_CLR5_OFFSET      0x2294 /* Clear port 5 */
+#define LPC43_GPIO_CLR6_OFFSET      0x2298 /* Clear port 6 */
+#define LPC43_GPIO_CLR7_OFFSET      0x229c /* Clear port 7 */
+
+#define LPC43_GPIO_NOT_OFFSET(p)    (0x2300 + ((p) << 2))
+#define LPC43_GPIO_NOT0_OFFSET      0x2300 /* Toggle port 0 */
+#define LPC43_GPIO_NOT1_OFFSET      0x2304 /* Toggle port 1 */
+#define LPC43_GPIO_NOT2_OFFSET      0x2308 /* Toggle port 2 */
+#define LPC43_GPIO_NOT3_OFFSET      0x230c /* Toggle port 3 */
+#define LPC43_GPIO_NOT4_OFFSET      0x2310 /* Toggle port 4 */
+#define LPC43_GPIO_NOT5_OFFSET      0x2314 /* Toggle port 5 */
+#define LPC43_GPIO_NOT6_OFFSET      0x2318 /* Toggle port 6 */
+#define LPC43_GPIO_NOT7_OFFSET      0x231c /* Toggle port 7 */
+
+/* Register Addresses *******************************************************************************/
+
+/* Pin interrupt registers (relative to LPC43_GPIOINT_BASE) */
+
+#define LPC43_GPIOINT_ISEL          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_ISEL_OFFSET)
+#define LPC43_GPIOINT_IENR          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_IENR_OFFSET)
+#define LPC43_GPIOINT_SIENR         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_SIENR_OFFSET)
+#define LPC43_GPIOINT_CIENR         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_CIENR_OFFSET)
+#define LPC43_GPIOINT_IENF          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_IENF_OFFSET)
+#define LPC43_GPIOINT_SIENF         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_SIENF_OFFSET)
+#define LPC43_GPIOINT_CIENF         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_CIENF_OFFSET)
+#define LPC43_GPIOINT_RISE          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_RISE_OFFSET)
+#define LPC43_GPIOINT_FALL          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_FALL_OFFSET)
+#define LPC43_GPIOINT_IST           (LPC43_GPIOINT_BASE+LPC43_GPIOINT_IST_OFFSET)
+
+/* GPIO GROUP0 interrupt registers (relative to LPC43_GRP0INT_BASE) */
+
+#define LPC43_GRP0INT_CTRL          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_CTRL_OFFSET)
+
+#define LPC43_GRP0INT_POL(p)        (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL_OFFSET(p))
+#define LPC43_GRP0INT_POL0          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL0_OFFSET)
+#define LPC43_GRP0INT_POL1          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL1_OFFSET)
+#define LPC43_GRP0INT_POL2          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL2_OFFSET)
+#define LPC43_GRP0INT_POL3          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL3_OFFSET)
+#define LPC43_GRP0INT_POL4          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL4_OFFSET)
+#define LPC43_GRP0INT_POL5          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL5_OFFSET)
+#define LPC43_GRP0INT_POL6          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL6_OFFSET)
+#define LPC43_GRP0INT_POL7          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL7_OFFSET)
+
+#define LPC43_GRP0INT_ENA(p)        (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA_OFFSET(p))
+#define LPC43_GRP0INT_ENA0          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA0_OFFSET)
+#define LPC43_GRP0INT_ENA1          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA1_OFFSET)
+#define LPC43_GRP0INT_ENA2          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA2_OFFSET)
+#define LPC43_GRP0INT_ENA3          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA3_OFFSET)
+#define LPC43_GRP0INT_ENA4          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA4_OFFSET)
+#define LPC43_GRP0INT_ENA5          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA5_OFFSET)
+#define LPC43_GRP0INT_ENA6          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA6_OFFSET)
+#define LPC43_GRP0INT_ENA7          (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA7_OFFSET)
+
+/* GPIO GROUP1 interrupt registers (relative to LPC43_GRP1INT_BASE) */
+
+#define LPC43_GRP1INT_CTRL          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_CTRL_OFFSET)
+
+#define LPC43_GRP1INT_POL(p)        (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL_OFFSET(p))
+#define LPC43_GRP1INT_POL0          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL0_OFFSET)
+#define LPC43_GRP1INT_POL1          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL1_OFFSET)
+#define LPC43_GRP1INT_POL2          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL2_OFFSET)
+#define LPC43_GRP1INT_POL3          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL3_OFFSET)
+#define LPC43_GRP1INT_POL4          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL4_OFFSET)
+#define LPC43_GRP1INT_POL5          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL5_OFFSET)
+#define LPC43_GRP1INT_POL6          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL6_OFFSET)
+#define LPC43_GRP1INT_POL7          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL7_OFFSET)
+
+#define LPC43_GRP1INT_ENA(p)        (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA_OFFSET(p))
+#define LPC43_GRP1INT_ENA0          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA0_OFFSET)
+#define LPC43_GRP1INT_ENA1          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA1_OFFSET)
+#define LPC43_GRP1INT_ENA2          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA2_OFFSET)
+#define LPC43_GRP1INT_ENA3          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA3_OFFSET)
+#define LPC43_GRP1INT_ENA4          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA4_OFFSET)
+#define LPC43_GRP1INT_ENA5          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA5_OFFSET)
+#define LPC43_GRP1INT_ENA6          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA6_OFFSET)
+#define LPC43_GRP1INT_ENA7          (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA7_OFFSET)
+
+/* GPIO Port Registers (relative to LPC43_GPIO_BASE) */
+
+#define LPC43_GPIO_B(p,n)           (LPC43_GPIO_BASE+LPC43_GPIO_B_OFFSET(p,n))
+#define LPC43_GPIO_B0(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B0_OFFSET(n))
+#define LPC43_GPIO_B1(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B1_OFFSET(n))
+#define LPC43_GPIO_B2(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B2_OFFSET(n))
+#define LPC43_GPIO_B3(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B3_OFFSET(n))
+#define LPC43_GPIO_B4(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B4_OFFSET(n))
+#define LPC43_GPIO_B5(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B5_OFFSET(n))
+#define LPC43_GPIO_B6(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B6_OFFSET(n))
+#define LPC43_GPIO_B7(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B7_OFFSET(n))
+
+#define LPC43_GPIO_W(p,n)           (LPC43_GPIO_BASE+LPC43_GPIO_W_OFFSET(p,n))
+#define LPC43_GPIO_W0(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W0_OFFSET(n))
+#define LPC43_GPIO_W1(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W1_OFFSET(n))
+#define LPC43_GPIO_W2(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W2_OFFSET(n))
+#define LPC43_GPIO_W3(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W3_OFFSET(n))
+#define LPC43_GPIO_W4(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W4_OFFSET(n))
+#define LPC43_GPIO_W5(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W5_OFFSET(n))
+#define LPC43_GPIO_W6(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W6_OFFSET(n))
+#define LPC43_GPIO_W7(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W7_OFFSET(n))
+
+#define LPC43_GPIO_DIR(p)           (LPC43_GPIO_BASE+LPC43_GPIO_DIR_OFFSET(p))
+#define LPC43_GPIO_DIR0             (LPC43_GPIO_BASE+LPC43_GPIO_DIR0_OFFSET)
+#define LPC43_GPIO_DIR1             (LPC43_GPIO_BASE+LPC43_GPIO_DIR1_OFFSET)
+#define LPC43_GPIO_DIR2             (LPC43_GPIO_BASE+LPC43_GPIO_DIR2_OFFSET)
+#define LPC43_GPIO_DIR3             (LPC43_GPIO_BASE+LPC43_GPIO_DIR3_OFFSET)
+#define LPC43_GPIO_DIR4             (LPC43_GPIO_BASE+LPC43_GPIO_DIR4_OFFSET)
+#define LPC43_GPIO_DIR5             (LPC43_GPIO_BASE+LPC43_GPIO_DIR5_OFFSET)
+#define LPC43_GPIO_DIR6             (LPC43_GPIO_BASE+LPC43_GPIO_DIR6_OFFSET)
+#define LPC43_GPIO_DIR7             (LPC43_GPIO_BASE+LPC43_GPIO_DIR7_OFFSET)
+
+#define LPC43_GPIO_MASK(p)          (LPC43_GPIO_BASE+LPC43_GPIO_MASK_OFFSET(p))
+#define LPC43_GPIO_MASK0            (LPC43_GPIO_BASE+LPC43_GPIO_MASK0_OFFSET)
+#define LPC43_GPIO_MASK1            (LPC43_GPIO_BASE+LPC43_GPIO_MASK1_OFFSET)
+#define LPC43_GPIO_MASK2            (LPC43_GPIO_BASE+LPC43_GPIO_MASK2_OFFSET)
+#define LPC43_GPIO_MASK3            (LPC43_GPIO_BASE+LPC43_GPIO_MASK3_OFFSET)
+#define LPC43_GPIO_MASK4            (LPC43_GPIO_BASE+LPC43_GPIO_MASK4_OFFSET)
+#define LPC43_GPIO_MASK5            (LPC43_GPIO_BASE+LPC43_GPIO_MASK5_OFFSET)
+#define LPC43_GPIO_MASK6            (LPC43_GPIO_BASE+LPC43_GPIO_MASK6_OFFSET)
+#define LPC43_GPIO_MASK7            (LPC43_GPIO_BASE+LPC43_GPIO_MASK7_OFFSET)
+
+#define LPC43_GPIO_PIN(p)           (LPC43_GPIO_BASE+LPC43_GPIO_PIN_OFFSET(p))
+#define LPC43_GPIO_PIN0             (LPC43_GPIO_BASE+LPC43_GPIO_PIN0_OFFSET)
+#define LPC43_GPIO_PIN1             (LPC43_GPIO_BASE+LPC43_GPIO_PIN1_OFFSET)
+#define LPC43_GPIO_PIN2             (LPC43_GPIO_BASE+LPC43_GPIO_PIN2_OFFSET)
+#define LPC43_GPIO_PIN3             (LPC43_GPIO_BASE+LPC43_GPIO_PIN3_OFFSET)
+#define LPC43_GPIO_PIN4             (LPC43_GPIO_BASE+LPC43_GPIO_PIN4_OFFSET)
+#define LPC43_GPIO_PIN5             (LPC43_GPIO_BASE+LPC43_GPIO_PIN5_OFFSET)
+#define LPC43_GPIO_PIN6             (LPC43_GPIO_BASE+LPC43_GPIO_PIN6_OFFSET)
+#define LPC43_GPIO_PIN7             (LPC43_GPIO_BASE+LPC43_GPIO_PIN7_OFFSET)
+
+#define LPC43_GPIO_MPIN(p)          (LPC43_GPIO_BASE+LPC43_GPIO_MPIN_OFFSET(p))
+#define LPC43_GPIO_MPIN0            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN0_OFFSET)
+#define LPC43_GPIO_MPIN1            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN1_OFFSET)
+#define LPC43_GPIO_MPIN2            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN2_OFFSET)
+#define LPC43_GPIO_MPIN3            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN3_OFFSET)
+#define LPC43_GPIO_MPIN4            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN4_OFFSET)
+#define LPC43_GPIO_MPIN5            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN5_OFFSET)
+#define LPC43_GPIO_MPIN6            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN6_OFFSET)
+#define LPC43_GPIO_MPIN7            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN7_OFFSET)
+
+#define LPC43_GPIO_SET(p)           (LPC43_GPIO_BASE+LPC43_GPIO_SET_OFFSET(p))
+#define LPC43_GPIO_SET0             (LPC43_GPIO_BASE+LPC43_GPIO_SET0_OFFSET)
+#define LPC43_GPIO_SET1             (LPC43_GPIO_BASE+LPC43_GPIO_SET1_OFFSET)
+#define LPC43_GPIO_SET2             (LPC43_GPIO_BASE+LPC43_GPIO_SET2_OFFSET)
+#define LPC43_GPIO_SET3             (LPC43_GPIO_BASE+LPC43_GPIO_SET3_OFFSET)
+#define LPC43_GPIO_SET4             (LPC43_GPIO_BASE+LPC43_GPIO_SET4_OFFSET)
+#define LPC43_GPIO_SET5             (LPC43_GPIO_BASE+LPC43_GPIO_SET5_OFFSET)
+#define LPC43_GPIO_SET6             (LPC43_GPIO_BASE+LPC43_GPIO_SET6_OFFSET)
+#define LPC43_GPIO_SET7             (LPC43_GPIO_BASE+LPC43_GPIO_SET7_OFFSET)
+
+#define LPC43_GPIO_CLR(p)           (LPC43_GPIO_BASE+LPC43_GPIO_CLR_OFFSET(p))
+#define LPC43_GPIO_CLR0             (LPC43_GPIO_BASE+LPC43_GPIO_CLR0_OFFSET)
+#define LPC43_GPIO_CLR1             (LPC43_GPIO_BASE+LPC43_GPIO_CLR1_OFFSET)
+#define LPC43_GPIO_CLR2             (LPC43_GPIO_BASE+LPC43_GPIO_CLR2_OFFSET)
+#define LPC43_GPIO_CLR3             (LPC43_GPIO_BASE+LPC43_GPIO_CLR3_OFFSET)
+#define LPC43_GPIO_CLR4             (LPC43_GPIO_BASE+LPC43_GPIO_CLR4_OFFSET)
+#define LPC43_GPIO_CLR5             (LPC43_GPIO_BASE+LPC43_GPIO_CLR5_OFFSET)
+#define LPC43_GPIO_CLR6             (LPC43_GPIO_BASE+LPC43_GPIO_CLR6_OFFSET)
+#define LPC43_GPIO_CLR7             (LPC43_GPIO_BASE+LPC43_GPIO_CLR7_OFFSET)
+
+#define LPC43_GPIO_NOT(p)           (LPC43_GPIO_BASE+LPC43_GPIO_NOT_OFFSET(p))
+#define LPC43_GPIO_NOT0             (LPC43_GPIO_BASE+LPC43_GPIO_NOT0_OFFSET)
+#define LPC43_GPIO_NOT1             (LPC43_GPIO_BASE+LPC43_GPIO_NOT1_OFFSET)
+#define LPC43_GPIO_NOT2             (LPC43_GPIO_BASE+LPC43_GPIO_NOT2_OFFSET)
+#define LPC43_GPIO_NOT3             (LPC43_GPIO_BASE+LPC43_GPIO_NOT3_OFFSET)
+#define LPC43_GPIO_NOT4             (LPC43_GPIO_BASE+LPC43_GPIO_NOT4_OFFSET)
+#define LPC43_GPIO_NOT5             (LPC43_GPIO_BASE+LPC43_GPIO_NOT5_OFFSET)
+#define LPC43_GPIO_NOT6             (LPC43_GPIO_BASE+LPC43_GPIO_NOT6_OFFSET)
+#define LPC43_GPIO_NOT7             (LPC43_GPIO_BASE+LPC43_GPIO_NOT7_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Pin Interrupt Mode register */
+
+#define GPIOINT_ISEL(i)             (1 << (i)) /* Bits 0-7: Selects the interrupt mode */
+
+/* Pin interrupt level (rising edge) interrupt enable register */
+
+#define GPIOINT_IENR(i)             (1 << (i)) /* Bits 0-7: Enables the rising edge or level interrupt */
+
+/* Pin interrupt level (rising edge) interrupt set register */
+
+#define GPIOINT_SIENR(i)            (1 << (i)) /* Bits 0-7: Set bits in the IENR, enabling interrupts */
+
+/* Pin interrupt level (rising edge interrupt) clear register */
+
+#define GPIOINT_CIENR(i)            (1 << (i)) /* Bits 0-7: Clears bits in the IENR, disabling interrupts */
+
+/* Pin interrupt active level (falling edge) interrupt enable register */
+
+#define GPIOINT_IENF(i)             (1 << (i)) /* Bits 0-7: Enables the falling edge or configures the active level interrupt */
+
+/* Pin interrupt active level (falling edge) interrupt set register */
+
+#define GPIOINT_SIENF(i)            (1 << (i)) /* Bits 0-7: Set bits in the IENF, enabling interrupts */
+
+/* Pin interrupt active level (falling edge) interrupt clear register */
+
+#define GPIOINT_CIENF(i)            (1 << (i)) /* Bits 0-7: Clears bits in the IENF, disabling interrupts */
+
+/* Pin interrupt rising edge register */
+
+#define GPIOINT_RISE(i)             (1 << (i)) /* Bits 0-7: Rising edge detect */
+
+/* Pin interrupt falling edge register */
+
+#define GPIOINT_FALL(i)             (1 << (i)) /* Bits 0-7: Falling edge detect */
+
+/* Pin interrupt status register */
+
+#define GPIOINT_IST(i)              (1 << (i)) /* Bits 0-7: Pin interrupt status */
+
+/* GPIO grouped interrupt control registers */
+
+#define GRPINT_CTRL_INT             (1 << 0)  /* Bit 0:  Group interrupt status */
+#define GRPINT_CTRL_COMB            (1 << 1)  /* Bit 1:  Combine enabled inputs for group interrupt */
+#define GRPINT_CTRL_TRIG            (1 << 2)  /* Bit 2:  Group interrupt trigger */
+                                              /* Bits 3-31:  Reserved */
+/* GPIO grouped interrupt polarity registers */
+
+#define GRPINT_POL(p)               (1 << (p)) /* Bits 0-31: Configure polarity of port pins */
+
+/* GPIO grouped interrupt enable registers */
+
+#define GRPINT_ENA(p)               (1 << (p)) /* Bits 0-31: Enable pin for group interrupt */
+
+/* Byte pin registers */
+
+#define GPIO_B                      (1 << 0)  /* Bit 0:  State of GPIO pin */
+                                              /* Bits 1-7: Reserved */
+/* Byte word registers.  On Read:  0x00000000 or 0xffffffff.  On write 0x0000000 or any
+ * non-zero value
+ */
+
+/* Direction registers */
+
+#define GPIO_DIR(p)                 (1 << (p)) /* Bits 0-31: Selects pin direction for pin */
+
+/* Mask registers */
+
+#define GPIO_MASK(p)                (1 << (p)) /* Bits 0-31: Controls which bits are active */
+
+/* Port pin registers */
+
+#define GPIO_PIN(p)                 (1 << (p)) /* Bits 0-31: Read/write pin state */
+
+/* Masked port registers */
+
+#define GPIO_MPIN(p)                (1 << (p)) /* Bits 0-31: Read/write masked pin state */
+
+/* Write: Set registers */
+
+#define GPIO_SET(p)                 (1 << (p)) /* Bits 0-31: Read or set output bits */
+
+/* Write: Clear registers */
+
+#define GPIO_CLR(p)                 (1 << (p)) /* Bits 0-31: Clear output bits */
+
+/* Toggle registers */
+
+#define GPIO_NOT(p)                 (1 << (p)) /* Bits 0-31: Toggle output bits */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h
new file mode 100644
index 000000000..b3aa0c583
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h
@@ -0,0 +1,302 @@
+/********************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_gpio.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_GPIO_H
+#define __ARCH_ARM_SRC_LPC43XX_GPIO_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the chip capabilities and GPIO definitions file */
+
+#include "chip.h"
+#include "chip/lpc43_gpio.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+#define NUM_GPIO_PORTS                8
+#define NUM_GPIO_PINS                 32
+
+/* Each configurable pin can be individually configured by software in several modes. The
+ * following definitions provide the bit encoding that is used to define a pin configuration.
+ * Note that these pins do not corresponding GPIO ports and pins.
+ *
+ * 16-bit Encoding:
+ *             1111 1100 0000 0000
+ *             5432 1098 7654 3210
+ *             ---- ---- ---- ----
+ * Normal:    .MM. .... PPPB BBBB
+ * Interrupt: .MMG GPII PPPB BBBB
+ */
+
+/* GPIO mode:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .MM. .... .... ....
+ */
+
+#define GPIO_MODE_SHIFT            (13)       /* Bits 13-14: Mode of the GPIO pin */
+#define GPIO_MODE_MASK             (3 << GPIO_MODE_SHIFT)
+#  define GPIO_MODE_INPUT          (1 << GPIO_MODE_SHIFT)
+#  define GPIO_MODE_OUTPUT         (2 << GPIO_MODE_SHIFT)
+#  define GPIO_MODE_INTERRUPT      (3 << GPIO_MODE_SHIFT)
+
+#define GPIO_IS_OUTPUT(p)          ((p) & GPIO_MODE_MASK) == GPIO_MODE_INPUT)
+#define GPIO_IS_INPUT(p)           ((p) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT)
+#define GPIO_IS_INTERRUPT(p)       ((p) & GPIO_MODE_MASK) == GPIO_MODE_INTERRUPT)
+
+/* Group Interrupt Selection (valid only for interrupt GPIO pins):
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * ...G G... .... ....
+ */
+
+#define GPIO_GRPINT_SHIFT          (11)       /* Bits 11-12: Group interrupt selection */
+#define GPIO_GRPINT_MASK           (3 << GPIO_GRPINT_SHIFT)
+#  define GPIO_GRPINT_NONE         (0 << GPIO_GRPINT_SHIFT) /* 00 Not a member of a group */
+#  define GPIO_GRPINT_GROUP0       (2 << GPIO_GRPINT_SHIFT) /* 10 Member of group 0 */
+#  define GPIO_GRPINT_GROUP1       (3 << GPIO_GRPINT_SHIFT) /* 11 Member of group 1 */
+
+#define _GPIO_GRPINT               (1 << (GPIO_GRPINT_SHIFT+1)) /* Bit 12: 1=Member of a group */
+#define _GPIO_GRPNO                (1 << GPIO_GRPINT_SHIFT)     /* Bit 11: Group number */
+
+#define GPIO_IS_GRPINT(p)          ((p) & _GPIO_GRPINT) != 0)
+#define GPIO_GRPPNO(p)             ((p) & _GPIO_GRPNO) >> GPIO_GRPINT_SHIFT)
+
+/* Group Interrupt Polarity (valid only for interrupt GPIO group interrupts ):
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... .P.. .... ....
+ */
+
+#define GPIO_POLARITY              (1 << 10) /* Bit 10: Group Polarity */
+
+#define GPIO_POLARITY_HI           GPIO_POLARITY
+#define GPIO_POLARITY_LOW          0
+
+#define GPIO_IS_POLARITY_HI(p)     (((p) & GPIO_POLARITY) != 0)
+#define GPIO_IS_POLARITY_LOW(p)    (((p) & GPIO_POLARITY) == 0)
+
+/* Interrupt Configuration (valid only for interrupt GPIO pins):
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... ..II .... ....
+ */
+
+#define GPIO_INT_SHIFT             (8)        /* Bits 8-9: Interrupt mode */
+#define GPIO_INT_MASK              (3 << GPIO_INT_SHIFT)
+#  define GPIO_INT_LEVEL_LOW       (0 << GPIO_INT_SHIFT) /* 00 Edge=NO, Active=LOW */
+#  define GPIO_INT_LEVEL_HI        (1 << GPIO_INT_SHIFT) /* 01 Edge=NO, Active=HIGH */
+#  define GPIO_INT_EDGE_FALLING    (2 << GPIO_INT_SHIFT) /* 10 Edge=YES, Active=LOW */
+#  define GPIO_INT_EDGE_RISING     (3 << GPIO_INT_SHIFT) /* 11 Edge=YES, Active=LOW */
+
+#define _GPIO_ACTIVE_HI            (1 << GPIO_INT_SHIFT)
+#define _GPIO_EDGE                 (1 << (GPIO_INT_SHIFT+1))
+
+#define GPIO_IS_ACTIVE_HI(p)       ((p) & _GPIO_ACTIVE_HI) != 0)
+#define GPIO_IS_ACTIVE_LOW(p)      ((p) & _GPIO_ACTIVE_HI) == 0)
+#define GPIO_IS_EDGE(p)            ((p) & _GPIO_EDGE) != 0)
+#define GPIO_IS_LEVEL(p)           ((p) & _GPIO_EDGE) == 0)
+
+/* GPIO Port Number:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... GPII .... ....
+ */
+
+#define GPIO_PORT_SHIFT               (4)        /* Bits 4-6: Port number */
+#define GPIO_PORT_MASK                (7 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT0                  (0 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT1                  (1 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT2                  (2 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT3                  (3 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT4                  (4 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT5                  (5 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT6                  (6 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT7                  (7 << GPIO_PORT_SHIFT)
+
+/* GPIO Pin Number:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... .... ...B BBBB
+ */
+
+#define GPIO_PIN_SHIFT                (0)        /* Bits 0-5: Pin number */
+#define GPIO_PIN_MASK                 (31 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN0                   (0 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN1                   (1 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN2                   (2 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN3                   (3 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN4                   (4 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN5                   (5 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN6                   (6 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN7                   (7 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN8                   (8 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN9                   (9 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN10                  (10 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN11                  (11 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN12                  (12 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN13                  (13 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN14                  (14 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN15                  (15 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN16                  (16 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN17                  (17 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN18                  (18 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN19                  (19 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN20                  (20 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN21                  (21 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN22                  (22 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN23                  (23 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN24                  (24 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN25                  (25 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN26                  (26 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN27                  (27 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN28                  (28 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN29                  (29 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN30                  (30 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN31                  (31 << GPIO_PIN_SHIFT)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/* Base addresses for each GPIO block */
+
+extern const uint32_t g_gpiobase[NUM_GPIO_PORTS];
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Name: lpc43_gpioconfig
+ *
+ * Description:
+ *   Configure a GPIO based on bit-encoded description of the pin.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ************************************************************************************/
+
+EXTERN int lpc43_gpioconfig(uint16_t gpiocfg);
+
+/************************************************************************************
+ * Name: lpc43_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+EXTERN void lpc43_gpiowrite(uint16_t gpiocfg, bool value);
+
+/************************************************************************************
+ * Name: lpc43_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ * Returned Value:
+ *   The boolean state of the input pin
+ *
+ ************************************************************************************/
+
+EXTERN bool lpc43_gpioread(uint16_t gpiocfg);
+
+/************************************************************************************
+ * Name: lpc43_gpioattach
+ *
+ * Description:
+ *   Attach and enable a GPIO interrupts on the selected GPIO pin, receiving the
+ *   interrupt with the selected interrupt handler.  The GPIO interrupt may be
+ *   disabled by providing a NULL value for the interrupt handler function pointer.
+ *
+ * Parameters:
+ *  - gpiocfg: GPIO pin identification
+ *  - func:   Interrupt handler
+ *
+ * Returns:
+ *  The previous value of the interrupt handler function pointer.  This value may,
+ *  for example, be used to restore the previous handler when multiple handlers are
+ *  used.
+ *
+ ************************************************************************************/
+
+EXTERN xcpt_t lpc43_gpioattach(uint16_t gpiocfg, xcpt_t func);
+
+/************************************************************************************
+ * Function:  lpc43_dumpgpio
+ *
+ * Description:
+ *   Dump all pin configuration registers associated with the provided base address
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG
+EXTERN int lpc43_dumpgpio(uint16_t gpiocfg, const char *msg);
+#else
+#  define lpc43_dumpgpio(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_GPIO_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
index 838d27ddb..39273a5f6 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
@@ -54,14 +54,14 @@
  * following definitions provide the bit encoding that is used to define a pin configuration.
  * Note that these pins do not corresponding GPIO ports and pins.
  *
- * 20-bit Encoding:         1111 1111 1100 0000 0000
- *                          9876 5432 1098 7654 3210
- *                          ---- ---- ---- ---- ----
- * Normal Pins:             AMM. UUDD IGWS SSSP PPPP
- * Alternate Function Pins: AFFF UUDD IGWS SSSP PPPP
+ * 20-bit Encoding:
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * AFFF UUDD IGWS SSSP PPPP
  */
 
-/* Alternate vs Normal encoding:
+/* Analog (input) / digital:
  *
  * 1111 1111 1100 0000 0000
  * 9876 5432 1098 7654 3210
@@ -69,50 +69,23 @@
  * A... .... .... .... ....
  */
 
-#define PINCONF_ALTERNATE             (1 << 19)  /* Bit 19: 1=Alternate function */
-#define PINCONF_NORMAL                (0)        /* Bit 19: 0=Normal function */
+#define PINCONF_ANALOG                 (1 << 19)  /* Bit 19: 1=Analog */
+#define PINCONF_DIGITAL                (0)        /* Bit 19: 0=Digial */
 
-#define PINCONF_IS_ALTERNATE(p)       ((p) & PINCONF_ALTERNATE) != 0)
-#define PINCONF_IS_NORMAL(p)          ((p) & PINCONF_ALTERNATE) == 0)
+#define PINCONF_IS_ANALOG(p)           ((p) & PINCONF_ANALOG) != 0)
+#define PINCONF_IS_DIGITAL(p)          ((p) & PINCONF_ANALOG) == 0)
 
 /* Alternate function number:
  *
  * 1111 1111 1100 0000 0000
  * 9876 5432 1098 7654 3210
  * ---- ---- ---- ---- ----
- * AFFF UUDD IGWS SSSP PPPP
  * .FFF .... .... .... ....
  */
 
 #define PINCONF_FUNC_SHIFT            (16)       /* Bits 16-18: Alternate function number */
 #define PINCONF_FUNC_MASK             (7 << PINCONF_MODE_SHIFT)
 
-/* Mode of a normal pin
- *
- * 1111 1111 1100 0000 0000
- * 9876 5432 1098 7654 3210
- * ---- ---- ---- ---- ----
- * .MM. .... .... .... ....
- */
-
-#define _PINCONF_OUTPUT               (1 << 18)  /* Bit 18: 1=Output */
-#define _PINCONF_INPUT                (0)        /* Bit 18: 0=Input */
-#define _PINCONF_ANALOG               (1 << 17)  /* Bit 17: 1=Analog */
-#define _PINCONF_DIGITAL              (0)        /* Bit 17: 0=Digital */
-
-#define PINCONF_MODE_SHIFT            (17)       /* Bits 17-18 = Mode of a normal pin*/
-#define PINCONF_MODE_MASK             (3 << PINCONF_MODE_SHIFT)
-#  define PINCONF_MODE_INPUT          (_PINCONF_INPUT  | _PINCONF_DIGITAL)
-#  define PINCONF_MODE_OUTPUT         (_PINCONF_OUTPUT | _PINCONF_DIGITAL)
-#  define PINCONF_MODE_ANALOGIN       (_PINCONF_INPUT  | _PINCONF_ANALOG)
-#  define PINCONF_MODE_ANALOGOUT      (_PINCONF_OUTPUT | _PINCONF_ANALOG)
-
-#define PINCONF_IS_OUTPUT(p)          ((p) & _PINCONF_OUTPUT) != 0)
-#define PINCONF_IS_INPUT(p)           ((p) & _PINCONF_OUTPUT) == 0)
-
-#define PINCONF_IS_ANALOG(p)          ((p) & _PINCONF_ANALOG) != 0)
-#define PINCONF_IS_DIGITAL(p)         ((p) & _PINCONF_ANALOG) == 0)
-
 /* Pull-up/down resisters.  These selections are available for all pins but may not
  * make sense for all pins.  NOTE: that both pull up and down is not precluded.
  *
@@ -251,33 +224,6 @@
 #  define PINCONF_PIN_30              (30 << PINCONF_PIN_SHIFT)
 #  define PINCONF_PIN_31              (31 << PINCONF_PIN_SHIFT)
 
-/* GPIO input pins may also be configurated as interrupting inputs. */
-
-#define NUM_GPIO_PORTS                8
-#define NUM_GPIO_PINS                 8
-
-#define GPIO_PORT_SHIFT               (4)        /* Bits 4-6: Pin set */
-#define GPIO_PORT_MASK                (7 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT0                  (0 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT1                  (1 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT2                  (2 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT3                  (3 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT4                  (4 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT5                  (5 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT6                  (6 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT7                  (7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PIN_SHIFT                (0)        /* Bits 0-2: Pin number */
-#define GPIO_PIN_MASK                 (7 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN0                   (0 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN1                   (1 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN2                   (2 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN3                   (3 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN4                   (4 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN5                   (5 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN6                   (6 << GPIO_PIN_SHIFT)
-#  define GPIO_PIN7                   (7 << GPIO_PIN_SHIFT)
-
 /********************************************************************************************
  * Public Types
  ********************************************************************************************/
@@ -286,10 +232,6 @@
  * Public Data
  ********************************************************************************************/
 
-/* Base addresses for each GPIO block */
-
-extern const uint32_t g_gpiobase[NUM_GPIO_PORTS];
-
 /********************************************************************************************
  * Public Functions
  ********************************************************************************************/
@@ -300,6 +242,9 @@ extern const uint32_t g_gpiobase[NUM_GPIO_PORTS];
  * Description:
  *   Configure a pin based on bit-encoded description of the pin.
  *
+ * Input Value:
+ *   20-bit encoded value describing the pin.
+ *
  * Returned Value:
  *   OK on success; A negated errno value on failure.
  *
@@ -308,56 +253,6 @@ extern const uint32_t g_gpiobase[NUM_GPIO_PORTS];
 EXTERN int lpc43_pinconfig(uint32_t pinset);
 
 /************************************************************************************
- * Name: lpc43_gpiowrite
- *
- * Description:
- *   Write one or zero to the selected GPIO pin
- *
- * Returned Value:
- *   None
- *
- ************************************************************************************/
-
-EXTERN void lpc43_gpiowrite(uint8_t gpioset, bool value);
-
-/************************************************************************************
- * Name: lpc43_gpioread
- *
- * Description:
- *   Read one or zero from the selected GPIO pin
- *
- * Returned Value:
- *   The boolean state of the input pin
- *
- ************************************************************************************/
-
-EXTERN bool lpc43_gpioread(uint8_t gpioset);
-
-/************************************************************************************
- * Name: lpc43_gpiointerrupt
- *
- * Description:
- *   Configure to receive GPIO interrupts on the select GPIO pin, reveiving the
- *   interrupt with the sectioned interrupt handler.  The GPIO interrupt may be
- *   disabled by providing a NULL value for the interrupt handler function pointer.
- *
- * Parameters:
- *  - gpioset: GPIO pin identification
- *  - rising:  Enable interrupt generation on the rising edge
- *  - falling: Enable interrupt generation on the falling edge
- *  - func:   Interrupt handler
- *
- * Returns:
- *  The previous value of the interrupt handler function pointer.  This value may,
- *  for example, be used to restore the previous handler when multiple handlers are
- *  used.
- *
- ************************************************************************************/
-
-EXTERN xcpt_t lpc43_gpiointerrupt(uint8_t gpioset, bool risingedge, bool fallingedge,
-                                  xcpt_t func);
-
-/************************************************************************************
  * Function:  lpc43_dumppinconfig
  *
  * Description: