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author | Gregory Nutt <gnutt@nuttx.org> | 2014-01-28 15:54:03 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2014-01-28 15:54:03 -0600 |
commit | af40f98f2e251091131cea2058c33bc63228a73a (patch) | |
tree | fd175965d5c18dad694a58a47380e9d38c51f739 | |
parent | 944d9107dbe472e9d684fddd1d0d001e4d769f06 (diff) | |
download | px4-nuttx-af40f98f2e251091131cea2058c33bc63228a73a.tar.gz px4-nuttx-af40f98f2e251091131cea2058c33bc63228a73a.tar.bz2 px4-nuttx-af40f98f2e251091131cea2058c33bc63228a73a.zip |
SAMA5: Mostly cosmetic
-rw-r--r-- | nuttx/arch/arm/src/armv7-a/arm_head.S | 20 | ||||
-rw-r--r-- | nuttx/arch/arm/src/armv7-a/arm_pghead.S | 22 | ||||
-rw-r--r-- | nuttx/configs/sama5d3x-ek/README.txt | 21 |
3 files changed, 40 insertions, 23 deletions
diff --git a/nuttx/arch/arm/src/armv7-a/arm_head.S b/nuttx/arch/arm/src/armv7-a/arm_head.S index 8f64bdc2f..7209b5ed1 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_head.S +++ b/nuttx/arch/arm/src/armv7-a/arm_head.S @@ -243,6 +243,7 @@ __start: adr r0, .LCtextinfo /* Address of text info */ ldmia r0, {r1, r2, r3, r4} /* Load the text description */ +#ifndef CONFIG_IDENTITY_TEXTMAP /* Create identity mapping for first MB of the .text section to support * this start-up logic executing out of the physical address space. This * identity mapping will be removed by .Lvstart (see below). Of course, @@ -250,7 +251,6 @@ __start: * the identity mapping. */ -#ifndef CONFIG_IDENTITY_TEXTMAP orr r0, r1, r3 /* OR MMU flags into physical address */ str r0, [r5, r1, lsr #18] /* Identity mapping */ #endif @@ -429,52 +429,53 @@ __start: orr r0, r0, #(SCTLR_Z) #endif +#ifndef CONFIG_ARCH_LOWVECTORS /* Position vectors to 0xffff0000 if so configured. * * SCTLR_V Bit 13: High vectors */ -#ifndef CONFIG_ARCH_LOWVECTORS orr r0, r0, #(SCTLR_V) #endif +#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5) /* Round Robin cache replacement * * SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random * replacement strategy. */ -#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5) orr r0, r0, #(SCTLR_RR) #endif +#ifndef CPU_DCACHE_DISABLE /* Dcache enable * * SCTLR_C Bit 2: DCache enable */ -#ifndef CPU_DCACHE_DISABLE orr r0, r0, #(SCTLR_C) #endif +#ifndef CPU_ICACHE_DISABLE /* Icache enable * * SCTLR_I Bit 12: ICache enable */ -#ifndef CPU_ICACHE_DISABLE orr r0, r0, #(SCTLR_I) #endif +#ifdef ALIGNMENT_TRAP /* Alignment abort enable * * SCTLR_A Bit 1: Strict alignment enabled */ -#ifdef ALIGNMENT_TRAP orr r0, r0, #(SCTLR_A) #endif +#ifdef CONFIG_AFE_ENABLE /* AP[0:2] Permissions model * * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value). @@ -483,7 +484,6 @@ __start: * control. When AFE=0, AP[2:0] control access permissions. */ -#ifdef CONFIG_AFE_ENABLE orr r0, r0, #(SCTLR_AFE) #endif @@ -599,12 +599,12 @@ __start: .Lvstart: +#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_IDENTITY_TEXTMAP) /* Remove the temporary mapping (if one was made). The following assumes * that the total RAM size is > 1Mb and extends that initial mapping to * cover additional RAM sections. */ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_IDENTITY_TEXTMAP) ldr r5, .LCvpgtable /* r5=Virtual page table base address */ ldr r3, .LCptextbase /* r0=Physical base address of .text section */ mov r0, #0 /* flags + base = 0 */ @@ -616,13 +616,13 @@ __start: ldr sp, .Lstackpointer mov fp, #0 +#ifndef CONFIG_BOOT_SDRAM_DATA /* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is * ready to use. Other memory, such as SDRAM, must be initialized before * it can be used. up_boot() will perform that memory initialization and * .bss and .data can be initialized after up_boot() returns. */ -#ifndef CONFIG_BOOT_SDRAM_DATA bl arm_data_initialize #endif @@ -676,6 +676,7 @@ arm_data_initialize: strcc fp, [r0],#4 bcc 1b +#ifdef CONFIG_BOOT_RUNFROMFLASH /* If the .data section is in a separate, uninitialized address space, * then we will also need to copy the initial values of of the .data * section from the .text region into that .data region. This would @@ -685,7 +686,6 @@ arm_data_initialize: * address region. */ -#if defined(CONFIG_BOOT_RUNFROMFLASH) adr r3, .Ldatainit ldmia r3, {r0, r1, r2} diff --git a/nuttx/arch/arm/src/armv7-a/arm_pghead.S b/nuttx/arch/arm/src/armv7-a/arm_pghead.S index 7321f2f21..97bae3d3a 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_pghead.S +++ b/nuttx/arch/arm/src/armv7-a/arm_pghead.S @@ -257,6 +257,7 @@ __start: str r0, [r5, r2, lsr #18] /* Map using the virtual address as an index */ #endif +#ifndef CONFIG_IDENTITY_TEXTMAP /* Create identity mapping for first MB of the .text section to support * this start-up logic executing out of the physical address space. This * identity mapping will be removed by .Lvstart (see below). Of course, @@ -264,7 +265,6 @@ __start: * the identity mapping. */ -#ifndef CONFIG_IDENTITY_TEXTMAP ldr r0, .LCptextbase /* r0=phys. base address of .text section */ ldr r1, .LCtextflags /* R1=.text section MMU flags */ orr r3, r1, r0 /* r3=flags + base */ @@ -415,52 +415,53 @@ __start: orr r0, r0, #(SCTLR_Z) #endif +#ifndef CONFIG_ARCH_LOWVECTORS /* Position vectors to 0xffff0000 if so configured. * * SCTLR_V Bit 13: High vectors */ -#ifndef CONFIG_ARCH_LOWVECTORS orr r0, r0, #(SCTLR_V) #endif +#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5) /* Round Robin cache replacement * * SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random * replacement strategy. */ -#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5) orr r0, r0, #(SCTLR_RR) #endif +#ifndef CPU_DCACHE_DISABLE /* Dcache enable * * SCTLR_C Bit 2: DCache enable */ -#ifndef CPU_DCACHE_DISABLE orr r0, r0, #(SCTLR_C) #endif +#ifndef CPU_ICACHE_DISABLE /* Icache enable * * SCTLR_I Bit 12: ICache enable */ -#ifndef CPU_ICACHE_DISABLE orr r0, r0, #(SCTLR_I) #endif +#ifdef ALIGNMENT_TRAP /* Alignment abort enable * * SCTLR_A Bit 1: Strict alignment enabled */ -#ifdef ALIGNMENT_TRAP orr r0, r0, #(SCTLR_A) #endif +#ifdef CONFIG_AFE_ENABLE /* AP[0:2] Permissions model * * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value). @@ -469,7 +470,6 @@ __start: * control. When AFE=0, AP[2:0] control access permissions. */ -#ifdef CONFIG_AFE_ENABLE orr r0, r0, #(SCTLR_AFE) #endif @@ -600,12 +600,12 @@ __start: .Lvstart: +#ifndef CONFIG_IDENTITY_TEXTMAP /* Remove the temporary mapping (if one was made). The following assumes * that the total RAM size is > 1Mb and extends that initial mapping to * cover additional RAM sections. */ -#ifndef CONFIG_IDENTITY_TEXTMAP ldr r4, .LCvpgtable /* r4=virtual page table base address */ ldr r3, .LCvtextbase /* r0=virtual base address of .text section */ mov r0, #0 /* flags + base = 0 */ @@ -625,7 +625,6 @@ __start: pg_l2map r0, r1, r2, r3, r4 #ifdef CONFIG_BOOT_RUNFROMFLASH - /* Get R3 = Value of RAM L1 page table entry */ ldr r3, .LCprambase /* r3=Aligned Nuttx RAM address (physical) */ @@ -647,7 +646,6 @@ __start: add r3, r3, #SECTION_SIZE str r3, [r0], #4 .endr - #endif /* CONFIG_BOOT_RUNFROMFLASH */ /* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is @@ -661,13 +659,13 @@ __start: ldr sp, .Lstackpointer mov fp, #0 +#ifndef CONFIG_BOOT_SDRAM_DATA /* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is * ready to use. Other memory, such as SDRAM, must be initialized before * it can be used. up_boot() will perform that memory initialization and * .bss and .data can be initialized after up_boot() returns. */ -#ifndef CONFIG_BOOT_SDRAM_DATA bl arm_data_initialize #endif @@ -721,6 +719,7 @@ arm_data_initialize: strcc fp, [r0],#4 bcc 1b +#ifdef CONFIG_BOOT_RUNFROMFLASH /* If the .data section is in a separate, uninitialized address space, * then we will also need to copy the initial values of of the .data * section from the .text region into that .data region. This would @@ -730,7 +729,6 @@ arm_data_initialize: * address region. */ -#if defined(CONFIG_BOOT_RUNFROMFLASH) adr r3, .Ldatainit ldmia r3, {r0, r1, r2} diff --git a/nuttx/configs/sama5d3x-ek/README.txt b/nuttx/configs/sama5d3x-ek/README.txt index 6cde91a9b..936c272e9 100644 --- a/nuttx/configs/sama5d3x-ek/README.txt +++ b/nuttx/configs/sama5d3x-ek/README.txt @@ -3121,7 +3121,26 @@ To-Do List heap? UPDATE: If I turn memory management debug on, the crash does not - occur. This needs some further investigation and a little TLC. + occur: + + CONFIG_DEBUG=y + # CONFIG_DEBUG_VERBOSE is not set + CONFIG_DEBUG_MM=y + # ...(No other debug output enabled)... + CONFIG_DEBUG_FULLOPT=y + + Results in: + + mm_initialize: Heap: start=20001228 size=268430808 + mm_addregion: Region 1: base=20001228 size=268430800 + + NuttShell (NSH) + nsh> free + total used free largest + Mem: 268430800 6864 268423936 268423936 + nsh> + + This needs some further investigation and a little TLC. 5) HSCMI TX DMA support is currently commented out. |