diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-06 22:30:57 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-06 22:30:57 +0000 |
| commit | ceef9e3bece69f86e585b3bf00e5009551350e2b (patch) | |
| tree | 37ceee5fa56d32692bc5c804444ab9b78a5d1e61 | |
| parent | f7b7532a4114b831f5ef66ed992d28e65fb3973f (diff) | |
| download | px4-nuttx-ceef9e3bece69f86e585b3bf00e5009551350e2b.tar.gz px4-nuttx-ceef9e3bece69f86e585b3bf00e5009551350e2b.tar.bz2 px4-nuttx-ceef9e3bece69f86e585b3bf00e5009551350e2b.zip | |
Beginnings of support for the STM32F3Discovery board
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5616 42af7a65-404d-4744-a932-0658087f49c3
38 files changed, 8120 insertions, 33 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index f35ebdbec..97a0d7432 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4153,4 +4153,7 @@ task is canceled or restarted while it is waiting for a timed event, we can gracefully recover. We can't let the timer expire after the task has been deleted. - + * arch/arm/include/stm32 and arch/arm/src/stm32: Add support for + the STM32 F3 family (still missing some things). + * configs/stm32f3discovery: This will (eventually) be support for + the STM32F3Discovery board. diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h index 14d92ea3d..173093df9 100644 --- a/nuttx/arch/arm/include/stm32/chip.h +++ b/nuttx/arch/arm/include/stm32/chip.h @@ -67,6 +67,7 @@ # define CONFIG_STM32_VALUELINE 1 /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -97,6 +98,7 @@ # define CONFIG_STM32_VALUELINE 1 /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -130,6 +132,7 @@ # define CONFIG_STM32_VALUELINE 1 /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -161,6 +164,7 @@ # define CONFIG_STM32_VALUELINE 1 /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -189,33 +193,34 @@ */ #elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6) -# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ -# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ -# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ -# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ -# undef CONFIG_STM32_VALUELINE /* STM32F100x */ -# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ -# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ -# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2,3,4 */ -# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NTHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ +# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2,3,4 */ +# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ /* STM32 F103 High Density Family ***************************************************/ /* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and @@ -230,6 +235,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ @@ -263,6 +269,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ @@ -296,6 +303,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ @@ -326,6 +334,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ @@ -355,6 +364,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 1 /* One advanced timers TIM1 */ @@ -385,6 +395,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -408,6 +419,220 @@ # define STM32_NRNG 1 /* Random number generator (RNG) */ # define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ +/* STM23 F3 Family ******************************************************************/ +/* Part Numbering: STM32Fssscfxxx + * + * Where + * sss = 302 or 303 + * c = C (48pins) R (68 pins) V (100 pins) + * f = B (128KB FLASH), C (256KB FLASH) + * xxx = Package, temperature range, options (ignored here) + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1 */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1 */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1 */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ + +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ + +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) +# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 0 /* No FSMC */ + +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + /* STM23 F4 Family ******************************************************************/ #elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ # undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */ @@ -417,6 +642,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -448,6 +674,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -479,6 +706,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -510,6 +738,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -541,6 +770,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -572,6 +802,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -603,6 +834,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -634,6 +866,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -665,6 +898,7 @@ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ diff --git a/nuttx/arch/arm/include/stm32/irq.h b/nuttx/arch/arm/include/stm32/irq.h index 842183420..9bf6b3e3e 100644 --- a/nuttx/arch/arm/include/stm32/irq.h +++ b/nuttx/arch/arm/include/stm32/irq.h @@ -81,6 +81,8 @@ # include <arch/stm32/stm32f10xxx_irq.h> #elif defined(CONFIG_STM32_STM32F20XX) # include <arch/stm32/stm32f20xxx_irq.h> +#elif defined(CONFIG_STM32_STM32F30XX) +# include <arch/stm32/stm32f30xxx_irq.h> #elif defined(CONFIG_STM32_STM32F40XX) # include <arch/stm32/stm32f40xxx_irq.h> #else diff --git a/nuttx/arch/arm/include/stm32/stm32f30xxx_irq.h b/nuttx/arch/arm/include/stm32/stm32f30xxx_irq.h new file mode 100644 index 000000000..a1be95573 --- /dev/null +++ b/nuttx/arch/arm/include/stm32/stm32f30xxx_irq.h @@ -0,0 +1,193 @@ +/**************************************************************************************************** + * arch/arm/include/stm32s/stm32f30xxx_irq.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/irq.h> + +/**************************************************************************************************** + * Definitions + ****************************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in nuttx/arch/arm/include/stm32/irq.h + * + * External interrupts (vectors >= 16) + */ + +#define STM32_IRQ_WWDG (STM32_IRQ_INTERRUPTS+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_INTERRUPTS+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_INTERRUPTS+2) /* 2: Tamper interrupt, or */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_INTERRUPTS+2) /* 2: Time stamp interrupt */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_INTERRUPTS+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_INTERRUPTS+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_INTERRUPTS+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_INTERRUPTS+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_INTERRUPTS+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_INTERRUPTS+8) /* 8: EXTI Line 2 interrupt, or */ +#define STM32_IRQ_TSC (STM32_IRQ_INTERRUPTS+8) /* 8: TSC interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_INTERRUPTS+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_INTERRUPTS+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_INTERRUPTS+11) /* 11: DMA1 channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_INTERRUPTS+12) /* 12: DMA1 channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_INTERRUPTS+13) /* 13: DMA1 channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_INTERRUPTS+14) /* 14: DMA1 channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_INTERRUPTS+15) /* 15: DMA1 channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_INTERRUPTS+16) /* 16: DMA1 channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_INTERRUPTS+17) /* 17: DMA1 channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_INTERRUPTS+18) /* 18: ADC1/ADC2 global interrupt */ +#define STM32_IRQ_USBHP_1 (STM32_IRQ_INTERRUPTS+19) /* 19: USB High Priority interrupts (not remapped) */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_INTERRUPTS+19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_USBLP_1 (STM32_IRQ_INTERRUPTS+20) /* 20: USB Low Priority interrupt (not remapped) */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_INTERRUPTS+20) /* 20: CAN1 RX0 interrupts*/ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_INTERRUPTS+21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_INTERRUPTS+22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_INTERRUPTS+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_INTERRUPTS+24) /* 24: TIM1 Break interrupt, or */ +#define STM32_IRQ_TIM15 (STM32_IRQ_INTERRUPTS+24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_INTERRUPTS+25) /* 25: TIM1 Update interrupt, or */ +#define STM32_IRQ_TIM16 (STM32_IRQ_INTERRUPTS+25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_INTERRUPTS+26) /* 26: TIM1 Trigger and Commutation interrupts, or */ +#define STM32_IRQ_TIM17 (STM32_IRQ_INTERRUPTS+26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_INTERRUPTS+27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_INTERRUPTS+28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_INTERRUPTS+29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_INTERRUPTS+30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_INTERRUPTS+31) /* 31: I2C1 event interrupt, or */ +#define STM32_IRQ_EXTI23 (STM32_IRQ_INTERRUPTS+31) /* 31: EXTI Line23 interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_INTERRUPTS+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_INTERRUPTS+33) /* 33: I2C2 event interrupt, or */ +#define STM32_IRQ_EXTI24 (STM32_IRQ_INTERRUPTS+33) /* 33: EXTI Line24 interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_INTERRUPTS+34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_INTERRUPTS+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_INTERRUPTS+36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_INTERRUPTS+37) /* 37: USART1 global interrupt, or */ +#define STM32_IRQ_EXTI25 (STM32_IRQ_INTERRUPTS+37) /* 37: EXTI Line 25 interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_INTERRUPTS+38) /* 38: USART2 global interrupt, or */ +#define STM32_IRQ_EXTI26 (STM32_IRQ_INTERRUPTS+38) /* 38: EXTI Line 26 interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_INTERRUPTS+39) /* 39: USART3 global interrupt, or */ +#define STM32_IRQ_EXTI28 (STM32_IRQ_INTERRUPTS+39) /* 39: EXTI Line 28 interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_INTERRUPTS+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_INTERRUPTS+41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_USBWKUP_1 (STM32_IRQ_INTERRUPTS+42) /* 42: USB wakeup from suspend through EXTI line interrupt */ +#define STM32_IRQ_EXT18 (STM32_IRQ_INTERRUPTS+42) /* 42: EXTI Line 18 interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_INTERRUPTS+43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_INTERRUPTS+44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_INTERRUPTS+45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_INTERRUPTS+46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_INTERRUPTS+47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_RESERVED48 (STM32_IRQ_INTERRUPTS+48) /* 48: Reserved */ +#define STM32_IRQ_RESERVED49 (STM32_IRQ_INTERRUPTS+49) /* 49: Reserved */ +#define STM32_IRQ_RESERVED50 (STM32_IRQ_INTERRUPTS+50) /* 50: Reserved */ +#define STM32_IRQ_SPI3 (STM32_IRQ_INTERRUPTS+51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_INTERRUPTS+52) /* 52: UART4 global interrupt, or */ +#define STM32_IRQ_EXTI34 (STM32_IRQ_INTERRUPTS+52) /* 52: EXTI Line 34 interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_INTERRUPTS+53) /* 53: UART5 global interrupt, or */ +#define STM32_IRQ_EXTI35 (STM32_IRQ_INTERRUPTS+53) /* 53: EXTI Line 35 interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_INTERRUPTS+54) /* 54: TIM6 global interrupt, or */ +#define STM32_IRQ_DAC (STM32_IRQ_INTERRUPTS+54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_INTERRUPTS+55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_INTERRUPTS+56) /* 56: DMA2 channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_INTERRUPTS+57) /* 57: DMA2 channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_INTERRUPTS+58) /* 58: DMA2 channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_INTERRUPTS+59) /* 59: DMA2 channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_INTERRUPTS+60) /* 60: DMA2 channel 5 global interrupt */ +#define STM32_IRQ_ADC4 (STM32_IRQ_INTERRUPTS+61) /* 61: ADC4 global interrupt */ +#define STM32_IRQ_RESERVED62 (STM32_IRQ_INTERRUPTS+62) /* 62: Reserved */ +#define STM32_IRQ_RESERVED63 (STM32_IRQ_INTERRUPTS+63) /* 63: Reserved */ +#define STM32_IRQ_COMP123 (STM32_IRQ_INTERRUPTS+64) /* 64: COMP1 & COMP2 & COMP3 interrupts, or */ +#define STM32_IRQ_EXTI2129 (STM32_IRQ_INTERRUPTS+64) /* 64: EXTI Lines 21, 22 and 29 interrupts */ +#define STM32_IRQ_COMP456 (STM32_IRQ_INTERRUPTS+65) /* 65: COMP4 & COMP5 & COMP6 interrupts, or */ +#define STM32_IRQ_EXTI3012 (STM32_IRQ_INTERRUPTS+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */ +#define STM32_IRQ_COMP7 (STM32_IRQ_INTERRUPTS+66) /* 66: COMP7 interrupt, or */ +#define STM32_IRQ_EXTI35 (STM32_IRQ_INTERRUPTS+66) /* 66: EXTI Line 33 interrupt */ +#define STM32_IRQ_RESERVED67 (STM32_IRQ_INTERRUPTS+67) /* 67: Reserved */ +#define STM32_IRQ_RESERVED68 (STM32_IRQ_INTERRUPTS+68) /* 68: Reserved */ +#define STM32_IRQ_RESERVED69 (STM32_IRQ_INTERRUPTS+69) /* 69: Reserved */ +#define STM32_IRQ_RESERVED70 (STM32_IRQ_INTERRUPTS+70) /* 70: Reserved */ +#define STM32_IRQ_RESERVED71 (STM32_IRQ_INTERRUPTS+71) /* 71: Reserved */ +#define STM32_IRQ_RESERVED72 (STM32_IRQ_INTERRUPTS+72) /* 72: Reserved */ +#define STM32_IRQ_RESERVED73 (STM32_IRQ_INTERRUPTS+73) /* 73: Reserved */ +#define STM32_IRQ_USBHP_2 (STM32_IRQ_INTERRUPTS+74) /* 74: USB High priority interrupt (remapped) */ +#define STM32_IRQ_USBLP_2 (STM32_IRQ_INTERRUPTS+75) /* 75: USB Low priority interrupt remapped) */ +#define STM32_IRQ_USBWKUP_2 (STM32_IRQ_INTERRUPTS+76) /* 76: USB wakeup from suspend remapped) */ +#define STM32_IRQ_RESERVED77 (STM32_IRQ_INTERRUPTS+77) /* 77: Reserved */ +#define STM32_IRQ_RESERVED78 (STM32_IRQ_INTERRUPTS+78) /* 78: Reserved */ +#define STM32_IRQ_RESERVED79 (STM32_IRQ_INTERRUPTS+79) /* 79: Reserved */ +#define STM32_IRQ_RESERVED80 (STM32_IRQ_INTERRUPTS+80) /* 80: Reserved */ +#define STM32_IRQ_FPU (STM32_IRQ_INTERRUPTS+81) /* 81: FPU global interrupt */ + +#define NR_IRQS (STM32_IRQ_INTERRUPTS+82) + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data +****************************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ + diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 41724be2d..2e29af14f 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -128,6 +128,66 @@ config ARCH_CHIP_STM32F207IG select ARCH_CORTEXM3 select STM32_STM32F20XX +config ARCH_CHIP_STM32F302CB + bool "STM32F302CB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302CC + bool "STM32F302CC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302RB + bool "STM32F302RB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302RC + bool "STM32F302RC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302VB + bool "STM32F302VB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F302VC + bool "STM32F302VC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303CB + bool "STM32F303CB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303CC + bool "STM32F303CC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303RB + bool "STM32F303RB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303RC + bool "STM32F303RC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303VB + bool "STM32F303VB" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + +config ARCH_CHIP_STM32F303VC + bool "STM32F303VC" + select ARCH_CORTEXM4 + select STM32_STM32F30XX + config ARCH_CHIP_STM32F405RG bool "STM32F405RG" select ARCH_CORTEXM4 @@ -190,6 +250,9 @@ config STM32_CONNECTIVITYLINE config STM32_STM32F20XX bool +config STM32_STM32F30XX + bool + config STM32_STM32F40XX bool @@ -220,6 +283,12 @@ config STM32_ADC3 select STM32_ADC depends on !STM32_VALUELINE +config STM32_ADC4 + bool "ADC4" + default n + select STM32_ADC + depends on STM32_STM32F30XX + config STM32_BKP bool "BKP" default n @@ -441,17 +510,17 @@ config STM32_TIM14 config STM32_TIM15 bool "TIM15" default n - depends on STM32_VALUELINE + depends on STM32_VALUELINE || STM32_STM32F30XX config STM32_TIM16 bool "TIM16" default n - depends on STM32_VALUELINE + depends on STM32_VALUELINE || STM32_STM32F30XX config STM32_TIM17 bool "TIM17" default n - depends on STM32_VALUELINE + depends on STM32_VALUELINE || STM32_STM32F30XX config STM32_USART1 bool "USART1" @@ -468,18 +537,21 @@ config STM32_USART2 config STM32_USART3 bool "USART3" default n + depends on !STM32_STM32F30XX select ARCH_HAVE_USART3 select STM32_USART config STM32_UART4 bool "UART4" default n + depends on !STM32_STM32F30XX select ARCH_HAVE_UART4 select STM32_USART config STM32_UART5 bool "UART5" default n + depends on !STM32_STM32F30XX select ARCH_HAVE_UART5 select STM32_USART @@ -493,7 +565,7 @@ config STM32_USART6 config STM32_USB bool "USB Device" default n - depends on STM32_STM32F10XX && !STM32_VALUELINE + depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32F30XX select USBDEV config STM32_WWDG diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h index 41a87feae..6fc56f9af 100644 --- a/nuttx/arch/arm/src/stm32/chip.h +++ b/nuttx/arch/arm/src/stm32/chip.h @@ -49,6 +49,7 @@ /* Include the chip pin configuration file */ /* STM32 F1 Family ******************************************************************/ + #if defined(CONFIG_STM32_STM32F10XX) /* STM32F100 Value Line */ @@ -89,10 +90,17 @@ # endif /* STM32 F2 Family ******************************************************************/ + #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_pinmap.h" +/* STM32 F3 Family ******************************************************************/ + +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/stm32f30xxx_pinmap.h" + /* STM32 F4 Family ******************************************************************/ + #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_pinmap.h" #else @@ -108,6 +116,8 @@ # include "chip/stm32f10xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_vectors.h" +# elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/stm32f30xxx_vectors.h" # elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_vectors.h" # else diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h index 36813b565..d87cb0247 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h @@ -47,6 +47,8 @@ # include "chip/stm32f10xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/stm32f20xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/stm32f30xxx_memorymap.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/stm32f40xxx_memorymap.h" #else diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h new file mode 100644 index 000000000..88fe693f1 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h @@ -0,0 +1,155 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* STM32F40XXX Address Blocks *******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ + /* 0x60000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */ + /* 0x1fff7a10-0x1fff7fff: Reserved */ +#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */ + /* 0x1fffc008-0x1fffffff: Reserved */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */ + /* 0x4000a000-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */ + /* 0x40016c00-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x4007ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */ + /* 0x48001800-0x4fffFfff: Reserved */ +#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ +#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff TIM4 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ +#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */ +#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */ +#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff SPI3, or */ +#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff I2S3 */ +#define STM32_I2S3EXT_BASE 0x40004000 /* 0x40004000-0x400043ff I2S3ext */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ +#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff UART4 */ +#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff UART5 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ +#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */ +#define STM32_USBSRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ +#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */ +#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */ +#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ +#define STM32_TIM8_BASE 0x40013400 /* 0x40013400-0x400137ff TIM8 */ +#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ +#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ +#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ +#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ +#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */ +#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */ +#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */ +#define STM32_GPIOD_BASE 0X40000C00 /* 0x48000c00-0x48000fff: GPIO Port D */ +#define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */ +#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */ + +/* AHB3 Base Addresses **************************************************************/ + +#define STM32_ADC1_BASE 0x50000000 /* 0x5000004c-0x5000004c: Master ADC1 */ +#define STM32_ADC2_BASE 0x50000100 /* 0x5000014c-0x500001ff: Slave ADC2 */ +#define STM32_ADC12_BASE 0x50000300 /* 0x50000300-0x50000308: ADC12 Common */ +#define STM32_ADC3_BASE 0x50000400 /* 0x5000044c-0x5000044c: Master ADC3 */ +#define STM32_ADC4_BASE 0x50000500 /* 0x5000054c-0x500005ff: Slave ADC4 */ +#define STM32_ADC34_BASE 0x50000700 /* 0x50000700-0x50000708: ADC34 Common */ + +/* Cortex-M4 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this + * address range + */ + +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H */ + diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_vectors.h new file mode 100644 index 000000000..e28ecb591 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_vectors.h @@ -0,0 +1,149 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f30xxx_vectors.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by stm32_vectors.S. It provides the macro VECTOR that + * supplies each STM32F30xxx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f30xxx_irq.h. + * stm32_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 82 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 82 + +#else + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */ +VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */ + +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */ +VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */ +VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */ +VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */ +VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */ +VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */ +VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */ +VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* 18: ADC1/ADC2 global interrupt */ +VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: USB High Priority or CAN1 TX interrupts */ + +VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: USB Low Priority or CAN1 RX0 interrupts*/ +VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */ +VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* 24: TIM1 Break or TIM15 global interrupt */ +VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* 25: TIM1 Update or TIM16 global interrupt */ +VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* 26: TIM1 Trigger or TIM17 global interrupt */ +VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* 27: TIM1 Capture Compare interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */ + +VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */ +VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event or EXTI Line24 interrupt */ +VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */ +VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */ + +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */ +VECTOR(stm32_ext18, STM32_IRQ_EXT18) /* 42: USB wakeup or EXTI Line 18 interrupt */ +VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* 43: TIM8 Break interrupt */ +VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* 44: TIM8 Update interrupt */ +VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* 45: TIM8 Trigger and Commutation interrupts */ +VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* 46: TIM8 Capture Compare interrupt */ +VECTOR(stm32_adc3, STM32_IRQ_ADC3) /* 47: ADC3 global interrupt */ +UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */ +UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */ + +UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */ +VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 51: SPI3 global interrupt */ +VECTOR(stm32_uart4, STM32_IRQ_UART4) /* 52: UART4 global or EXTI Line 34 interrupt */ +VECTOR(stm32_uart5, STM32_IRQ_UART5) /* 53: UART5 global or EXTI Line 35 interrupt */ +VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 54: TIM6 global or DAC1/2 underrun interrupts */ +VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 55: TIM7 global interrupt */ +VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 56: DMA2 channel 1 global interrupt */ +VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 57: DMA2 channel 2 global interrupt */ +VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 58: DMA2 channel 3 global interrupt */ +VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 59: DMA2 channel 4 global interrupt */ + +VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 60: DMA2 channel 5 global interrupt */ +VECTOR(stm32_adc4, STM32_IRQ_ADC4) /* 61: ADC4 global interrupt */ +UNUSED(STM32_IRQ_RESERVED62) /* 62: Reserved */ +UNUSED(STM32_IRQ_RESERVED63) /* 63: Reserved */ +VECTOR(stm32_comp123, STM32_IRQ_COMP123) /* 64: COMP1-3 or EXTI Lines 21-2 and 29 interrupts */ +VECTOR(stm32_comp456, STM32_IRQ_COMP456) /* 65: COMP4-6 or EXTI Lines 30-2 interrupts */ +VECTOR(stm32_comp7, STM32_IRQ_COMP7) /* 66: COMP7 or EXTI Line 33 interrupt */ +UNUSED(STM32_IRQ_RESERVED67) /* 67: Reserved */ +UNUSED(STM32_IRQ_RESERVED68) /* 68: Reserved */ +UNUSED(STM32_IRQ_RESERVED69) /* 69: Reserved */ + +UNUSED(STM32_IRQ_RESERVED70) /* 70: Reserved */ +UNUSED(STM32_IRQ_RESERVED71) /* 71: Reserved */ +UNUSED(STM32_IRQ_RESERVED72) /* 72: Reserved */ +UNUSED(STM32_IRQ_RESERVED73) /* 73: Reserved */ +VECTOR(stm32_usbhp, STM32_IRQ_USBHP_2) /* 74: USB High priority interrupt */ +VECTOR(stm32_usblp, STM32_IRQ_USBLP_2) /* 75: USB Low priority interrupt */ +VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP_2) /* 76: USB wakeup from suspend through EXTI line interrupt*/ +UNUSED(STM32_IRQ_RESERVED77) /* 77: Reserved */ +UNUSED(STM32_IRQ_RESERVED78) /* 78: Reserved */ +UNUSED(STM32_IRQ_RESERVED79) /* 79: Reserved */ + +UNUSED(STM32_IRQ_RESERVED80) /* 80: Reserved */ +VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 81: FPU global interrupt */ + +#endif /* CONFIG_ARMV7M_CMNVECTOR */ diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S index c9b62d762..68a3e498b 100644 --- a/nuttx/arch/arm/src/stm32/stm32_vectors.S +++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S @@ -150,6 +150,8 @@ stm32_vectors: # include "chip/chip/stm32f10xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/chip/stm32f20xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/chip/stm32f30xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/chip/stm32f40xxx_vectors.h" #else @@ -186,6 +188,8 @@ handlers: # include "chip/chip/stm32f10xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F20XX) # include "chip/chip/stm32f20xxx_vectors.h" +#elif defined(CONFIG_STM32_STM32F30XX) +# include "chip/chip/stm32f30xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) # include "chip/chip/stm32f40xxx_vectors.h" #else diff --git a/nuttx/configs/stm32f3discovery/Kconfig b/nuttx/configs/stm32f3discovery/Kconfig new file mode 100644 index 000000000..8a761b1ae --- /dev/null +++ b/nuttx/configs/stm32f3discovery/Kconfig @@ -0,0 +1,57 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_STM32F3_DISCOVERY + +config PM_BUTTONS + bool "PM Button support" + default n + depends on PM && ARCH_IRQBUTTONS + ---help--- + Enable PM button EXTI interrupts to support PM testing + +config PM_BUTTON_ACTIVITY + int "Button PM activity weight" + default 10 + depends on PM_BUTTONS + ---help--- + The activity weight to report to the power management subsystem when a button is pressed. + +config PM_ALARM_SEC + int "PM_STANDBY delay (seconds)" + default 15 + depends on PM && RTC_ALARM + --help--- + Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_ALARM_NSEC + int "PM_STANDBY delay (nanoseconds)" + default 0 + depends on PM && RTC_ALARM + --help--- + Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_SLEEP_WAKEUP + bool "PM_SLEEP wake-up alarm" + default n + depends on PM && RTC_ALARM + --help--- + Wake-up of PM_SLEEP mode after a delay and resume normal operation. + +config PM_SLEEP_WAKEUP_SEC + int "PM_SLEEP delay (seconds)" + default 10 + depends on PM && RTC_ALARM + --help--- + Number of seconds to wait in PM_SLEEP before going to PM_STANDBY mode. + +config PM_SLEEP_WAKEUP_NSEC + int "PM_SLEEP delay (nanoseconds)" + default 0 + depends on PM && RTC_ALARM + --help--- + Number of additional nanoseconds to wait in PM_SLEEP before going to PM_STANDBY mode. + +endif diff --git a/nuttx/configs/stm32f3discovery/README.txt b/nuttx/configs/stm32f3discovery/README.txt new file mode 100644 index 000000000..1b86430b3 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/README.txt @@ -0,0 +1,1612 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the +STMicro STM32F3Discovery development board. + +Contents +======== + + - Development Environment + - GNU Toolchain Options + - IDEs + - NuttX EABI "buildroot" Toolchain + - NuttX OABI "buildroot" Toolchain + - NXFLAT Toolchain + - LEDs + - PWM + - UARTs + - Timer Inputs/Outputs + - FPU + - FSMC SRAM + - SSD1289 + - UG-2864AMBAG01 / UG-2964SWEG01 + - STM32F3Discovery-specific Configuration Options + - Configurations + +Development Environment +======================= + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment because the Raisonance R-Link emulatator and some RIDE7 development tools + were used and those tools works only under Windows. + +GNU Toolchain Options +===================== + + Toolchain Configurations + ------------------------ + The NuttX make system has been modified to support the following different + toolchain options. + + 1. The CodeSourcery GNU toolchain, + 2. The Atollic Toolchain, + 3. The devkitARM GNU toolchain, + 4. Raisonance GNU toolchain, or + 5. The NuttX buildroot Toolchain (see below). + + All testing has been conducted using the CodeSourcery toolchain for Windows. To use + the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to + add one of the following configuration options to your .config (or defconfig) + file: + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_STM32_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_STM32_ATOLLIC_LITE=y : The free, "Lite" version of Atollic toolchain under Windows + CONFIG_STM32_ATOLLIC_PRO=y : The paid, "Pro" version of Atollic toolchain under Windows + CONFIG_STM32_DEVKITARM=y : devkitARM under Windows + CONFIG_STM32_RAISONANCE=y : Raisonance RIDE7 under Windows + CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + + If you change the default toolchain, then you may also have to modify the PATH in + the setenv.h file if your make cannot find the tools. + + NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are + Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot + toolchains are Cygwin and/or Linux native toolchains. There are several limitations + to using a Windows based toolchain in a Cygwin environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had no effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + 3. Dependencies are not made when using Windows versions of the GCC. This is + because the dependencies are generated using Windows pathes which do not + work with the Cygwin make. + + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + + The CodeSourcery Toolchain (2009q1) + ----------------------------------- + The CodeSourcery toolchain (2009q1) does not work with default optimization + level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with + -Os. + + The Atollic "Pro" and "Lite" Toolchain + -------------------------------------- + One problem that I had with the Atollic toolchains is that the provide a gcc.exe + and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path + appears in your PATH variable before /usr/bin, then you will get the wrong gcc + when you try to build host executables. This will cause to strange, uninterpretable + errors build some host binaries in tools/ when you first make. + + Also, the Atollic toolchains are the only toolchains that have built-in support for + the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will + need to use the Atollic toolchain for now. See the FPU section below for more + information. + + The Atollic "Lite" Toolchain + ---------------------------- + The free, "Lite" version of the Atollic toolchain does not support C++ nor + does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" + toolchain, you will have to set: + + CONFIG_HAVE_CXX=n + + In order to compile successfully. Otherwise, you will get errors like: + + "C++ Compiler only available in TrueSTUDIO Professional" + + The make may then fail in some of the post link processing because of some of + the other missing tools. The Make.defs file replaces the ar and nm with + the default system x86 tool versions and these seem to work okay. Disable all + of the following to avoid using objcopy: + + CONFIG_RRLOAD_BINARY=n + CONFIG_INTELHEX_BINARY=n + CONFIG_MOTOROLA_SREC=n + CONFIG_RAW_BINARY=n + + devkitARM + --------- + The devkitARM toolchain includes a version of MSYS make. Make sure that the + the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM + path or will get the wrong version of make. + +IDEs +==== + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project. + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/stm32, + arch/arm/src/common, arch/arm/src/armv7-m, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX + one time from the Cygwin command line in order to obtain the pre-built + startup object needed by RIDE. + +NuttX EABI "buildroot" Toolchain +================================ + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M3 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX + SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in <some-dir>/nuttx. + + cd tools + ./configure.sh STM32F3Discovery/<sub-dir> + + 2. Download the latest buildroot package into <some-dir> + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot. + + 4. cd <some-dir>/buildroot + + 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + details PLUS some special instructions that you will need to follow if you are + building a Cortex-M3 toolchain for Cygwin under Windows. + + NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the + the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for + more information about this problem. If you plan to use NXFLAT, please do not + use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. + See instructions below. + +NuttX OABI "buildroot" Toolchain +================================ + + The older, OABI buildroot toolchain is also available. To use the OABI + toolchain: + + 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 + configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI + configuration such as cortexm3-defconfig-4.3.3 + + 2. Modify the Make.defs file to use the OABI conventions: + + +CROSSDEV = arm-nuttx-elf- + +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft + +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections + -CROSSDEV = arm-nuttx-eabi- + -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections + +NXFLAT Toolchain +================ + + If you are *not* using the NuttX buildroot toolchain and you want to use + the NXFLAT tools, then you will still have to build a portion of the buildroot + tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can + be downloaded from the NuttX SourceForge download site + (https://sourceforge.net/projects/nuttx/files/). + + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in <some-dir>/nuttx. + + cd tools + ./configure.sh lpcxpresso-lpc1768/<sub-dir> + + 2. Download the latest buildroot package into <some-dir> + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot. + + 4. cd <some-dir>/buildroot + + 5. cp configs/cortexm3-defconfig-nxflat .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly builtNXFLAT binaries. + +LEDs +==== + +The STM32F3Discovery board has four LEDs; green, organge, red and blue on the +board. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is +defined. In that case, the usage by the board port is defined in +include/board.h and src/up_leds.c. The LEDs are used to encode OS-related +events as follows: + + SYMBOL Meaning LED1* LED2 LED3 LED4 + green orange red blue + ------------------- ----------------------- ------- ------- ------- ------ + LED_STARTED NuttX has been started ON OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF + LED_IRQSENABLED Interrupts enabled ON ON OFF OFF + LED_STACKCREATED Idle stack created OFF OFF ON OFF + LED_INIRQ In an interrupt** ON N/C N/C OFF + LED_SIGNAL In a signal handler*** N/C ON N/C OFF + LED_ASSERTION An assertion failed ON ON N/C OFF + LED_PANIC The system has crashed N/C N/C N/C ON + LED_IDLE STM32 is is sleep mode (Optional, not used) + + * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot + and these LEDs will give you some indication of where the failure was + ** The normal state is LED3 ON and LED1 faintly glowing. This faint glow + is because of timer interupts that result in the LED being illuminated + on a small proportion of the time. +*** LED2 may also flicker normally if signals are processed. + +PWM +=== + +The STM32F3Discovery has no real on-board PWM devices, but the board can be +configured to output a pulse train using TIM4 CH2 on PD3. This pin is +available next to the audio jack. + +UARTs +===== + +UART/USART PINS +--------------- + +USART1 + CK PA8 + CTS PA11* + RTS PA12* + RX PA10*, PB7 + TX PA9*, PB6* +USART2 + CK PA4*, PD7 + CTS PA0*, PD3 + RTS PA1, PD4* + RX PA3, PD6 + TX PA2, PD5* +USART3 + CK PB12, PC12*, PD10 + CTS PB13, PD11 + RTS PB14, PD12* + RX PB11, PC11, PD9 + TX PB10*, PC10*, PD8 +UART4 + RX PA1, PC11 + TX PA0*, PC10* +UART5 + RX PD2 + TX PC12* +USART6 + CK PC8, PG7** + CTS PG13**, PG15** + RTS PG12**, PG8** + RX PC7*, PG9** + TX PC6, PG14** + + * Indicates pins that have other on-board functions and should be used only + with care (See table 5 in the STM32F3Discovery User Guide). The rest are + free I/O pins. +** Port G pins are not supported by the MCU + +Default USART/UART Configuration +-------------------------------- + +USART2 is enabled in all configurations (see */defconfig). RX and TX are +configured on pins PA3 and PA2, respectively (see include/board.h). + +Timer Inputs/Outputs +==================== + +TIM1 + CH1 PA8, PE9 + CH2 PA9*, PE11 + CH3 PA10*, PE13 + CH4 PA11*, PE14 +TIM2 + CH1 PA0*, PA15, PA5* + CH2 PA1, PB3* + CH3 PA2, PB10* + CH4 PA3, PB11 +TIM3 + CH1 PA6*, PB4, PC6 + CH2 PA7*, PB5, PC7* + CH3 PB0, PC8 + CH4 PB1, PC9 +TIM4 + CH1 PB6*, PD12* + CH2 PB7, PD13* + CH3 PB8, PD14* + CH4 PB9*, PD15* +TIM5 + CH1 PA0*, PH10** + CH2 PA1, PH11** + CH3 PA2, PH12** + CH4 PA3, PI0 +TIM8 + CH1 PC6, PI5 + CH2 PC7*, PI6 + CH3 PC8, PI7 + CH4 PC9, PI2 +TIM9 + CH1 PA2, PE5 + CH2 PA3, PE6 +TIM10 + CH1 PB8, PF6 +TIM11 + CH1 PB9*, PF7 +TIM12 + CH1 PH6**, PB14 + CH2 PC15, PH9** +TIM13 + CH1 PA6*, PF8 +TIM14 + CH1 PA7*, PF9 + + * Indicates pins that have other on-board functions and should be used only + with care (See table 5 in the STM32F3Discovery User Guide). The rest are + free I/O pins. +** Port H pins are not supported by the MCU + +Quadrature Encode Timer Inputs +------------------------------ + +If enabled (by setting CONFIG_QENCODER=y), then quadrature encoder will +use either TIM2 or TIM8 (see nsh/defconfig). If TIM2 is selected, the input +pins PA15 and PA1 for CH1 and CH2, respectively). If TIM8 is selected, then +PC6 and PI5 will be used for CH1 and CH2 (see include board.h for pin +definitions). + +FPU +=== + +FPU Configuration Options +------------------------- + +There are two version of the FPU support built into the STM32 port. + +1. Lazy Floating Point Register Save. + + This is an untested implementation that saves and restores FPU registers + only on context switches. This means: (1) floating point registers are + not stored on each context switch and, hence, possibly better interrupt + performance. But, (2) since floating point registers are not saved, + you cannot use floating point operations within interrupt handlers. + + This logic can be enabled by simply adding the following to your .config + file: + + CONFIG_ARCH_FPU=y + +2. Non-Lazy Floating Point Register Save + + Mike Smith has contributed an extensive re-write of the ARMv7-M exception + handling logic. This includes verified support for the FPU. These changes + have not yet been incorporated into the mainline and are still considered + experimental. These FPU logic can be enabled with: + + CONFIG_ARCH_FPU=y + CONFIG_ARMV7M_CMNVECTOR=y + + You will probably also changes to the ld.script in if this option is selected. + This should work: + + -ENTRY(_stext) + +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ + +EXTERN(_vectors) /* Force the vectors to be included in the output */ + +CFLAGS +------ + +Only the Atollic toolchain has built-in support for the Cortex-M4 FPU. You will see +the following lines in each Make.defs file: + + ifeq ($(CONFIG_STM32_ATOLLIC_LITE),y) + # Atollic toolchain under Windows + ... + ifeq ($(CONFIG_ARCH_FPU),y) + ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard + else + ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + endif + endif + +If you are using a toolchain other than the Atollic toolchain, then to use the FPU +you will also have to modify the CFLAGS to enable compiler support for the ARMv7-M +FPU. As of this writing, there are not many GCC toolchains that will support the +ARMv7-M FPU. + +As a minimum you will need to add CFLAG options to (1) enable hardware floating point +code generation, and to (2) select the FPU implementation. You might try the same +options as used with the Atollic toolchain in the Make.defs file: + + ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard + +FSMC SRAM +========= + +On-board SRAM +------------- +The STM32F3Discovery has no on-board SRAM. The information here is only for +reference in case you choose to add some. + +Configuration Options +--------------------- +Internal SRAM is available in all members of the STM32 family. The F4 family +also contains internal CCM SRAM. This SRAM is different because it cannot +be used for DMA. So if DMA needed, then the following should be defined +to exclude CCM SRAM from the heap: + + CONFIG_STM32_CCMEXCLUDE : Exclude CCM SRAM from the HEAP + +In addition to internal SRAM, SRAM may also be available through the FSMC. +In order to use FSMC SRAM, the following additional things need to be +present in the NuttX configuration file: + + CONFIG_STM32_FSMC=y : Enables the FSMC + CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the + FSMC (as opposed to an LCD or FLASH). + CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC + address space + CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC + address space + CONFIG_MM_REGIONS : Must be set to a large enough value to + include the FSMC SRAM + +SRAM Configurations +------------------- +There are 4 possible SRAM configurations: + + Configuration 1. System SRAM (only) + CONFIG_MM_REGIONS == 1 + CONFIG_STM32_FSMC_SRAM NOT defined + CONFIG_STM32_CCMEXCLUDE defined + Configuration 2. System SRAM and CCM SRAM + CONFIG_MM_REGIONS == 2 + CONFIG_STM32_FSMC_SRAM NOT defined + CONFIG_STM32_CCMEXCLUDE NOT defined + Configuration 3. System SRAM and FSMC SRAM + CONFIG_MM_REGIONS == 2 + CONFIG_STM32_FSMC_SRAM defined + CONFIG_STM32_CCMEXCLUDE defined + Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM + CONFIG_MM_REGIONS == 3 + CONFIG_STM32_FSMC_SRAM defined + CONFIG_STM32_CCMEXCLUDE NOT defined + +Configuration Changes +--------------------- + +Below are all of the configuration changes that I had to make to configs/stm3240g-eval/nsh2 +in order to successfully build NuttX using the Atollic toolchain WITH FPU support: + + -CONFIG_ARCH_FPU=n : Enable FPU support + +CONFIG_ARCH_FPU=y + + -CONFIG_STM32_CODESOURCERYW=y : Disable the CodeSourcery toolchain + +CONFIG_STM32_CODESOURCERYW=n + + -CONFIG_STM32_ATOLLIC_LITE=n : Enable *one* the Atollic toolchains + CONFIG_STM32_ATOLLIC_PRO=n + -CONFIG_STM32_ATOLLIC_LITE=y : The "Lite" version + CONFIG_STM32_ATOLLIC_PRO=n : The "Pro" version + + -CONFIG_INTELHEX_BINARY=y : Suppress generation FLASH download formats + +CONFIG_INTELHEX_BINARY=n : (Only necessary with the "Lite" version) + + -CONFIG_HAVE_CXX=y : Suppress generation of C++ code + +CONFIG_HAVE_CXX=n : (Only necessary with the "Lite" version) + +See the section above on Toolchains, NOTE 2, for explanations for some of +the configuration settings. Some of the usual settings are just not supported +by the "Lite" version of the Atollic toolchain. + +SSD1289 +======= + +I purchased an LCD display on eBay from China. The LCD is 320x240 RGB565 and +is based on an SSD1289 LCD controller and an XPT2046 touch IC. The pin out +from the 2x16 connect on the LCD is labeled as follows: + +LCD CONNECTOR: SSD1289 MPU INTERFACE PINS: + + +------+------+ DEN I Display enable pin +1 | GND | 3V3 | 2 VSYNC I Frame synchronization signal + +------+------+ HSYNC I Line synchronization signal +3 | D1 | D0 | 4 DOTCLK I Dot clock and OSC source + +------+------+ DC I Data or command +5 | D3 | D2 | 6 E (~RD) I Enable/Read strobe + +------+------+ R (~WR) I Read/Write strobe +7 | D5 | D4 | 8 D0-D17 IO For parallel mode, 8/9/16/18 bit interface + +------+------+ WSYNC O RAM write synchronizatin output +9 | D7 | D6 | 10 ~RES I System reset + +------+------+ ~CS I Chip select of serial interface +11 | D9 | D8 | 12 SCK I Clock of serial interface + +------+------+ SDI I Data input in serial mode +13 | D11 | D10 | 14 SDO O Data output in serial moce + +------+------+ +15 | D13 | D12 | 16 + +------+------+ +17 | D15 | D14 | 18 + +------+------+ +19 | RS | CS | 20 + +------+------+ +21 | RD | WR | 22 NOTES: + +------+------+ +23 |BL_CNT|RESET | 24 BL_CNT is the PWM backlight level control. + +------+------+ +25 |TP_RQ |TP_S0 | 26 These pins are for the touch panel: TP_REQ + +------+------+ TP_S0, TP_SI, TP_SCX, and TP_CS +27 | NC |TP_SI | 28 + +------+------+ +29 | NC |TP_SCX| 30 + +------+------+ +31 | NC |TP_CS | 32 + +------+------+ + +MAPPING TO STM32 F4: + + ---------------- -------------- ---------------------------------- + STM32 FUNCTION LCD PIN STM32F3Discovery PIN + ---------------- -------------- ---------------------------------- + FSMC_D0 D0 pin 4 PD14 P1 pin 46 Conflict (Note 1) + FSMC_D1 D1 pin 3 PD15 P1 pin 47 Conflict (Note 2) + FSMC_D2 D2 pin 6 PD0 P2 pin 36 Free I/O + FSMC_D3 D3 pin 5 PD1 P2 pin 33 Free I/O + FSMC_D4 D4 pin 8 PE7 P1 pin 25 Free I/O + FSMC_D5 D5 pin 7 PE8 P1 pin 26 Free I/O + FSMC_D6 D6 pin 10 PE9 P1 pin 27 Free I/O + FSMC_D7 D7 pin 9 PE10 P1 pin 28 Free I/O + FSMC_D8 D8 pin 12 PE11 P1 pin 29 Free I/O + FSMC_D9 D9 pin 11 PE12 P1 pin 30 Free I/O + FSMC_D10 D10 pin 14 PE13 P1 pin 31 Free I/O + FSMC_D11 D11 pin 13 PE14 P1 pin 32 Free I/O + FSMC_D12 D12 pin 16 PE15 P1 pin 33 Free I/O + FSMC_D13 D13 pin 15 PD8 P1 pin 40 Free I/O + FSMC_D14 D14 pin 18 PD9 P1 pin 41 Free I/O + FSMC_D15 D15 pin 17 PD10 P1 pin 42 Free I/O + FSMC_A16 RS pin 19 PD11 P1 pin 27 Free I/O + FSMC_NE1 ~CS pin 10 PD7 P2 pin 27 Free I/O + FSMC_NWE ~WR pin 22 PD5 P2 pin 29 Conflict (Note 3) + FSMC_NOE ~RD pin 21 PD4 P2 pin 32 Conflict (Note 4) + PC6 RESET pin 24 PC6 P2 pin 47 Free I/O + Timer ouput BL_CNT pin 23 (to be determined) + ---------------- -------------- ---------------------------------- + + 1 Used for the RED LED + 2 Used for the BLUE LED + 3 Used for the RED LED and for OTG FS Overcurrent. It may be okay to use + for the parallel interface if PC0 is held high (or floating). PC0 enables + the STMPS2141STR IC power switch that drives the OTG FS host VBUS. + 4 Also the reset pin for the CS43L22 audio Codec. + +NOTE: The configuration to test this LCD configuration is available at +configs/stm32f3discovery/nxlines. As of this writing, I have not seen the +LCD working so I probaby have some things wrong. + +I might need to use a bit-baning interface. Below is the pin configurationf +of a similar LCD to support a (write-only), bit banging interface: + + LCD PIN BOARD CONNECTION + LEDA 5V + VCC 5V + RD 3.3V + GND GND + DB0-7 Port C pins configured as outputs + DB8-15 Port A pins configured as outputs + RS Pin configured as output + WR Pin configured as output + CS Pin configured as output + RSET Pin configured as output + +The following summarize the bit banging oprations: + + /* Rese the LCD */ + void Reset(void) + { + Set RSET output + delay + Clear RSET output + delay + Set RSET output + } + + /* Write 16-bits of whatever */ + void Write16(uint8_t ms, uint8_t ls) + { + Set port A to ms + Set port B to ls + + Clear WR pin + Set WR pin + } + + /* Set the index register to an LCD register address */ + void Index(uint8_t address) + { + Clear RS + Write16(0, address); + } + + /* Write data to the LCD register or GRAM memory */ + void WriteData(uin16_t data) + { + Set RS + Write16(data >> 8, data & 0xff); + } + + /* Write to a register */ + void WriteRegister(uint8_t address, uint16_t data) + { + Index(address); + WriteData(data); + } + +UG-2864AMBAG01 / UG-2964SWEG01 +============================== + +I purchased an OLED display on eBay. The OLED is 128x64 monochrome and +is based on an UG-2864AMBAG01 OLED controller. The OLED can run in either +parallel or SPI mode. I am using SPI mode. In SPI mode, the OLED is +write only so the driver keeps a 128*64/8 = 1KB framebuffer to remember +the display contents: + +Here is how I have the OLED connected. But you can change this with the +settings in include/board.h and src/stm324fdiscovery-internal.h. Connector +pinout for the UG-2864AMBAG01 is specific to the theO.net display board +that I am using: + + --------------------------+---------------------------------------------- + Connector CON10 J1: | STM32F3Discovery + --------------+-----------+---------------------------------------------- + CON10 J1: | CON20 J2: | P1/P2: + --------------+-----------+---------------------------------------------- + 1 3v3 | 3,4 3v3 | P2 3V + 3 /RESET | 8 /RESET | P2 PB6 (Arbitrary selection) + 5 /CS | 7 /CS | P2 PB7 (Arbitrary selection) + 7 A0 | 9 A0 | P2 PB8 (Arbitrary selection) + 9 LED+ (N/C) | ----- | ----- + 2 5V Vcc | 1,2 Vcc | P2 5V + 4 DI | 18 D1/SI | P1 PA7 (GPIO_SPI1_MOSI == GPIO_SPI1_MOSI_1 (1)) + 6 SCLK | 19 D0/SCL | P1 PA5 (GPIO_SPI1_SCK == GPIO_SPI1_SCK_1 (1)) + 8 LED- (N/C) | ----- | ------ + 10 GND | 20 GND | P2 GND + --------------+-----------+---------------------------------------------- + (1) Required because of on-board MEMS + ------------------------------------------------------------------------- + +Darcy Gong recently added support for the UG-2964SWEG01 OLED which is also +an option with this configuratin. I have little technical information about +the UG-2964SWEG01 interface (see configs/stm32f3discovery/src/up_ug2864sweg01.c). + +STM32F3Discovery-specific Configuration Options +=============================================== + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM4=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=stm32 + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_CONFIG_ARCH_CHIP_STM32F303VC=y + + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock + configuration features. + + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=STM32F3Discovery (for the STM32F3Discovery development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_DRAM_SIZE=0x00010000 (64Kb) + + CONFIG_DRAM_START - The start address of installed DRAM + + CONFIG_DRAM_START=0x20000000 + + CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP + + In addition to internal SRAM, SRAM may also be available through the FSMC. + In order to use FSMC SRAM, the following additional things need to be + present in the NuttX configuration file: + + CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the + FSMC (as opposed to an LCD or FLASH). + + CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex) + + CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal) + + CONFIG_ARCH_IRQPRIO - The STM32F3Discovery supports interrupt prioritization + + CONFIG_ARCH_IRQPRIO=y + + CONFIG_ARCH_FPU - The STM32F3Discovery supports a floating point unit (FPU) + + CONFIG_ARCH_FPU=y + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + + AHB1 + ---- + CONFIG_STM32_CRC + CONFIG_STM32_BKPSRAM + CONFIG_STM32_CCMDATARAM + CONFIG_STM32_DMA1 + CONFIG_STM32_DMA2 + CONFIG_STM32_ETHMAC + CONFIG_STM32_OTGHS + + AHB2 + ---- + CONFIG_STM32_DCMI + CONFIG_STM32_CRYP + CONFIG_STM32_HASH + CONFIG_STM32_RNG + CONFIG_STM32_OTGFS + + AHB3 + ---- + CONFIG_STM32_FSMC + + APB1 + ---- + CONFIG_STM32_TIM2 + CONFIG_STM32_TIM3 + CONFIG_STM32_TIM4 + CONFIG_STM32_TIM5 + CONFIG_STM32_TIM6 + CONFIG_STM32_TIM7 + CONFIG_STM32_TIM12 + CONFIG_STM32_TIM13 + CONFIG_STM32_TIM14 + CONFIG_STM32_WWDG + CONFIG_STM32_IWDG + CONFIG_STM32_SPI2 + CONFIG_STM32_SPI3 + CONFIG_STM32_USART2 + CONFIG_STM32_USART3 + CONFIG_STM32_UART4 + CONFIG_STM32_UART5 + CONFIG_STM32_I2C1 + CONFIG_STM32_I2C2 + CONFIG_STM32_I2C3 + CONFIG_STM32_CAN1 + CONFIG_STM32_CAN2 + CONFIG_STM32_DAC1 + CONFIG_STM32_DAC2 + CONFIG_STM32_PWR -- Required for RTC + + APB2 + ---- + CONFIG_STM32_TIM1 + CONFIG_STM32_TIM8 + CONFIG_STM32_USART1 + CONFIG_STM32_USART6 + CONFIG_STM32_ADC1 + CONFIG_STM32_ADC2 + CONFIG_STM32_ADC3 + CONFIG_STM32_SDIO + CONFIG_STM32_SPI1 + CONFIG_STM32_SYSCFG + CONFIG_STM32_TIM9 + CONFIG_STM32_TIM10 + CONFIG_STM32_TIM11 + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn + is defined (as above) then the following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation, ADC conversion, + or DAC conversion. Note that ADC/DAC require two definition: Not only do you have + to assign the timer (n) for used by the ADC or DAC, but then you also have to + configure which ADC or DAC (m) it is assigned to. + + CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 + CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 + CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 + CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 + CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 + + For each timer that is enabled for PWM usage, we need the following additional + configuration settings: + + CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} + + NOTE: The STM32 timers are each capable of generating different signals on + each of the four channels with different duty cycles. That capability is + not supported by this driver: Only one output channel per timer. + + JTAG Enable settings (by default only SW-DP is enabled): + + CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) + CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP) + but without JNTRST. + CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled + + STM32F3Discovery specific device driver settings + + CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART + m (m=4,5) for the console and ttys0 (default is the USART1). + CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_U[S]ARTn_2STOP - Two stop bits + + STM32F3Discovery CAN Configuration + + CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or + CONFIG_STM32_CAN2 must also be defined) + CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default + Standard 11-bit IDs. + CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages. + Default: 8 + CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests. + Default: 4 + CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback + mode for testing. The STM32 CAN driver does support loopback mode. + CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 + CONFIG_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 + CONFIG_CAN_REGDEBUG - If CONFIG_DEBUG is set, this will generate an + dump of all CAN registers. + + STM32F3Discovery SPI Configuration + + CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI + support. Non-interrupt-driven, poll-waiting is recommended if the + interrupt rate would be to high in the interrupt driven case. + CONFIG_STM32_SPI_DMA - Use DMA to improve SPI transfer performance. + Cannot be used with CONFIG_STM32_SPI_INTERRUPT. + + STM32F3Discovery DMA Configuration + + CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO + and CONFIG_STM32_DMA2. + CONFIG_SDIO_PRI - Select SDIO interrupt prority. Default: 128 + CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. + Default: Medium + CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default: + 4-bit transfer mode. + + STM32 USB OTG FS Host Driver Support + + Pre-requisites + + CONFIG_USBDEV - Enable USB device support + CONFIG_USBHOST - Enable USB host support + CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + CONFIG_STM32_SYSCFG - Needed + CONFIG_SCHED_WORKQUEUE - Worker thread support is required + + Options: + + CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + Default 128 (512 bytes) + CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + in 32-bit words. Default 96 (384 bytes) + CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + words. Default 96 (384 bytes) + CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 + CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + want to do that? + CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access + debug. Depends on CONFIG_DEBUG. + CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + packets. Depends on CONFIG_DEBUG. + +Configurations +============== + +Each STM32F3Discovery configuration is maintained in a sub-directory and +can be selected as follow: + + cd tools + ./configure.sh STM32F3Discovery/<subdir> + cd - + . ./setenv.sh + +If this is a Windows native build, then configure.bat should be used +instead of configure.sh: + + configure.bat STM32F3Discovery\<subdir> + +Where <subdir> is one of the following: + + cxxtest: + ------- + + The C++ standard libary test at apps/examples/cxxtest configuration. This + test is used to verify the uClibc++ port to NuttX. This configuration may + be selected as follows: + + cd <nuttx-directory>/tools + ./configure.sh sim/cxxtest + + NOTES: + + 1. Before you can use this example, you must first install the uClibc++ + C++ library. This is located outside of the NuttX source tree at + misc/uClibc++ in SVN. See the README.txt file for instructions on + how to install uClibc++ + + 2. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 3. Ideally, you should build with a toolchain based on GLIBC or + uClibc++. It you use a toolchain based on newlib, you may see + an error like the following: + + .../lib/libsupc++.a(vterminate.o): In function `__gnu_cxx::__verbose_terminate_handler()': + vterminate.cc:(....): undefined reference to `_impure_ptr' + + Here is a quick'n'dirty fix: + + 1. Get the directory where you can find libsupc++: + + arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -print-file-name=libsupc++.a + + 2. Go to that directory and save a copy of vterminate.o (in case you + want to restore it later: + + cd <the-directory-containing-libsupc++.a> + arm-none-eabi-ar.exe -x libsupc++.a vterminate.o + + 3. Then remove vterminate.o from the library. At build time, the + uClibc++ package will provide a usable replacement vterminate.o. + + Steps 2 and 3 will require root privileges on most systems (not Cygwin). + + Now NuttX should link with no problem. If you want to restore the + vterminate.o that you removed from libsupc++, you can do that with: + + arm-none-eabi-ar.exe rcs libsupc++.a vterminate.o + + 4. Exceptions are enabled and workking (CONFIG_UCLIBCXX_EXCEPTIONS=y) + + elf: + --- + + This configuration derives from the ostest configuration. It has + been modified to us apps/examples/elf in order to test the ELF + loader. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + + CONFIG_HOST_WINDOWS=y : Windows + CONFIG_WINDOWS_CYGWIN=y : Cygwin environment on Windows + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + + 3. By default, this project assumes that you are *NOT* using the DFU + bootloader. + + 4. It appears that you cannot excute from CCM RAM. This is why the + following definition appears in the defconfig file: + + CONFIG_STM32_CCMEXCLUDE=y + + 5. This configuration requires that you have the genromfs tool installed + on your system and that you have the full path to the installed genromfs + executable in PATH variable (see apps/examples/README.txt) + + ostest: + ------ + This configuration directory, performs a simple OS test using + apps/examples/ostest. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default toolchain: + + CONFIG_STM32_CODESOURCERYL=y : CodeSourcery under Linux / Mac OS X + + 3. By default, this project assumes that you are *NOT* using the DFU + bootloader. + + 4. If you use the Atollic toolchain, then the FPU test can be enabled in the + examples/ostest by adding the following your NuttX configuration file: + + -CONFIG_ARCH_FPU=n : Enable FPU support + +CONFIG_ARCH_FPU=y + + -CONFIG_STM32_CODESOURCERYW=y : Disable the CodeSourcery toolchain + +CONFIG_STM32_CODESOURCERYW=n + + -CONFIG_STM32_ATOLLIC_LITE=n : Enable *one* the Atollic toolchains + CONFIG_STM32_ATOLLIC_PRO=n + -CONFIG_STM32_ATOLLIC_LITE=y : The "Lite" version + CONFIG_STM32_ATOLLIC_PRO=n : The "Pro" version + + -CONFIG_INTELHEX_BINARY=y : Suppress generation FLASH download formats + +CONFIG_INTELHEX_BINARY=n : (Only necessary with the "Lite" version) + + -CONFIG_HAVE_CXX=y : Suppress generation of C++ code + +CONFIG_HAVE_CXX=n : (Only necessary with the "Lite" version) + + -CONFIG_SCHED_WAITPID=y : Enable the waitpid() API needed by the FPU test + +CONFIG_SCHED_WAITPID=n + + The FPU test also needs to know the size of the FPU registers save area in + bytes (see arch/arm/include/armv7-m/irq_lazyfpu.h): + + -CONFIG_EXAMPLES_OSTEST_FPUSIZE=(4*33) + + nsh: + --- + Configures the NuttShell (nsh) located at apps/examples/nsh. The + Configuration enables the serial interfaces on UART2. Support for + builtin applications is enabled, but in the base configuration no + builtin applications are selected (see NOTES below). + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. By default, this configuration uses the CodeSourcery toolchain + for Windows and builds under Cygwin (or probably MSYS). That + can easily be reconfigured, of course. + + CONFIG_HOST_WINDOWS=y : Builds under Windows + CONFIG_WINDOWS_CYGWIN=y : Using Cygwin + CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows + + 3. This example supports the PWM test (apps/examples/pwm) but this must + be manually enabled by selecting: + + CONFIG_PWM=y : Enable the generic PWM infrastructure + CONFIG_STM32_TIM4=y : Enable TIM4 + CONFIG_STM32_TIM4_PWM=y : Use TIM4 to generate PWM output + + See also apps/examples/README.txt + + Special PWM-only debug options: + + CONFIG_DEBUG_PWM + + 5. This example supports the Quadrature Encode test (apps/examples/qencoder) + but this must be manually enabled by selecting: + + CONFIG_EXAMPLES_QENCODER=y : Enable the apps/examples/qencoder + CONFIG_SENSORS=y : Enable support for sensors + CONFIG_QENCODER=y : Enable the generic Quadrature Encoder infrastructure + CONFIG_STM32_TIM8=y : Enable TIM8 + CONFIG_STM32_TIM2=n : (Or optionally TIM2) + CONFIG_STM32_TIM8_QE=y : Use TIM8 as the quadrature encoder + CONFIG_STM32_TIM2_QE=y : (Or optionally TIM2) + + See also apps/examples/README.tx. Special PWM-only debug options: + + CONFIG_DEBUG_QENCODER + + 6. This example supports the watchdog timer test (apps/examples/watchdog) + but this must be manually enabled by selecting: + + CONFIG_EXAMPLES_WATCHDOG=y : Enable the apps/examples/watchdog + CONFIG_WATCHDOG=y : Enables watchdog timer driver support + CONFIG_STM32_WWDG=y : Enables the WWDG timer facility, OR + CONFIG_STM32_IWDG=y : Enables the IWDG timer facility (but not both) + + The WWDG watchdog is driven off the (fast) 42MHz PCLK1 and, as result, + has a maximum timeout value of 49 milliseconds. for WWDG watchdog, you + should also add the fillowing to the configuration file: + + CONFIG_EXAMPLES_WATCHDOG_PINGDELAY=20 + CONFIG_EXAMPLES_WATCHDOG_TIMEOUT=49 + + The IWDG timer has a range of about 35 seconds and should not be an issue. + + 7. USB Support (CDC/ACM device) + + CONFIG_STM32_OTGFS=y : STM32 OTG FS support + CONFIG_USBDEV=y : USB device support must be enabled + CONFIG_CDCACM=y : The CDC/ACM driver must be built + CONFIG_NSH_BUILTIN_APPS=y : NSH built-in application support must be enabled + CONFIG_NSH_ARCHINIT=y : To perform USB initialization + + 8. Using the USB console. + + The STM32F3Discovery NSH configuration can be set up to use a USB CDC/ACM + (or PL2303) USB console. The normal way that you would configure the + the USB console would be to change the .config file like this: + + CONFIG_STM32_OTGFS=y : STM32 OTG FS support + CONFIG_USART2_SERIAL_CONSOLE=n : Disable the USART2 console + CONFIG_DEV_CONSOLE=n : Inhibit use of /dev/console by other logic + CONFIG_USBDEV=y : USB device support must be enabled + CONFIG_CDCACM=y : The CDC/ACM driver must be built + CONFIG_CDCACM_CONSOLE=y : Enable the CDC/ACM USB console. + + NOTE: When you first start the USB console, you have hit ENTER a few + times before NSH starts. The logic does this to prevent sending USB data + before there is anything on the host side listening for USB serial input. + + 9. Here is an alternative USB console configuration. The following + configuration will also create a NSH USB console but this version + will use /dev/console. Instead, it will use the normal /dev/ttyACM0 + USB serial device for the console: + + CONFIG_STM32_OTGFS=y : STM32 OTG FS support + CONFIG_USART2_SERIAL_CONSOLE=y : Keep the USART2 console + CONFIG_DEV_CONSOLE=y : /dev/console exists (but NSH won't use it) + CONFIG_USBDEV=y : USB device support must be enabled + CONFIG_CDCACM=y : The CDC/ACM driver must be built + CONFIG_CDCACM_CONSOLE=n : Don't use the CDC/ACM USB console. + CONFIG_NSH_USBCONSOLE=y : Instead use some other USB device for the console + + The particular USB device that is used is: + + CONFIG_NSH_USBCONDEV="/dev/ttyACM0" + + The advantage of this configuration is only that it is easier to + bet working. This alternative does has some side effects: + + - When any other device other than /dev/console is used for a user + interface, linefeeds (\n) will not be expanded to carriage return / + linefeeds (\r\n). You will need to set your terminal program to account + for this. + + - /dev/console still exists and still refers to the serial port. So + you can still use certain kinds of debug output (see include/debug.h, all + of the interfaces based on lowsyslog will work in this configuration). + + - But don't enable USB debug output! Since USB is console is used for + USB debug output and you are using a USB console, there will be + infinite loops and deadlocks: Debug output generates USB debug + output which generatates USB debug output, etc. If you want USB + debug output, you should consider enabling USB trace + (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_SYSTEM_USBMONITOR). + + See the usbnsh configuration below for more information on configuring + USB trace output and the USB monitor. + + 10. USB OTG FS Host Support. The following changes will enable support for + a USB host on the STM32F3Discovery, including support for a mass storage + class driver: + + CONFIG_USBDEV=n : Make sure tht USB device support is disabled + CONFIG_USBHOST=y : Enable USB host support + CONFIG_STM32_OTGFS=y : Enable the STM32 USB OTG FS block + CONFIG_STM32_SYSCFG=y : Needed for all USB OTF FS support + CONFIG_SCHED_WORKQUEUE=y : Worker thread support is required for the mass + storage class driver. + CONFIG_NSH_ARCHINIT=y : Architecture specific USB initialization + is needed for NSH + CONFIG_FS_FAT=y : Needed by the USB host mass storage class. + + With those changes, you can use NSH with a FLASH pen driver as shown + belong. Here NSH is started with nothing in the USB host slot: + + NuttShell (NSH) NuttX-x.yy + nsh> ls /dev + /dev: + console + null + ttyS0 + + After inserting the FLASH drive, the /dev/sda appears and can be + mounted like this: + + nsh> ls /dev + /dev: + console + null + sda + ttyS0 + nsh> mount -t vfat /dev/sda /mnt/stuff + nsh> ls /mnt/stuff + /mnt/stuff: + -rw-rw-rw- 16236 filea.c + + And files on the FLASH can be manipulated to standard interfaces: + + nsh> echo "This is a test" >/mnt/stuff/atest.txt + nsh> ls /mnt/stuff + /mnt/stuff: + -rw-rw-rw- 16236 filea.c + -rw-rw-rw- 16 atest.txt + nsh> cat /mnt/stuff/atest.txt + This is a test + nsh> cp /mnt/stuff/filea.c fileb.c + nsh> ls /mnt/stuff + /mnt/stuff: + -rw-rw-rw- 16236 filea.c + -rw-rw-rw- 16 atest.txt + -rw-rw-rw- 16236 fileb.c + + To prevent data loss, don't forget to un-mount the FLASH drive + before removing it: + + nsh> umount /mnt/stuff + + nxlines: + ------ + An example using the NuttX graphics system (NX). This example focuses on + placing lines on the background in various orientations. + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LCD_LANDSCAPE=y : 320x240 landscape orientation + + The STM32F3Discovery board does not have any graphics capability. This + configuration assumes that you have connected an SD1289-based LCD as + described above under "SSD1289". NOTE: At present, it has not been + proven that the STM32F3Discovery can actually drive an LCD. There are + some issues with how some of the dedicated FSMC pins are used on the + boards. This configuration may not be useful and may only serve as + an illustration of how to build for th SSD1289 LCD. + + NOTES: + + 1. As of this writing, I have not seen the LCD work! + + 2. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 3. This configured can be re-configured to use either the + UG-2864AMBAG01 or UG-2864SWEG01 0.96 inch OLEDs by adding + or changing the following items in the configuration (using + 'make menuconfig'): + + +CONFIG_SPI_CMDDATA=y + + -CONFIG_LCD_MAXCONTRAST=1 + -CONFIG_LCD_MAXPOWER=255 + +CONFIG_LCD_MAXCONTRAST=255 + +CONFIG_LCD_MAXPOWER=1 + + -CONFIG_LCD_SSD1289=y + -CONFIG_SSD1289_PROFILE1=y + +CONFIG_LCD_UG2864AMBAG01=y : For the UG-2964AMBAG01 + +CONFIG_UG2864AMBAG01_SPIMODE=3 + +CONFIG_UG2864AMBAG01_FREQUENCY=3500000 + +CONFIG_UG2864AMBAG01_NINTERFACES=1 + + -CONFIG_NX_DISABLE_1BPP=y + +CONFIG_NX_DISABLE_16BPP=y + + -CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 + -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16 + -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 + -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 + -CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 + -CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb + -CONFIG_EXAMPLES_NXLINES_BPP=16 + +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x00 + +CONFIG_EXAMPLES_NXLINES_LINEWIDTH=4 + +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x01 + +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=2 + +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0x01 + +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x00 + +CONFIG_EXAMPLES_NXLINES_BPP=1 + +CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y + + There are some issues with with the presentation... some tuning of the + configuration could fix that. Lower resolution displays are also more + subject to the "fat, flat line bug" that I need to fix someday. See + http://www.nuttx.org/doku.php?id=wiki:graphics:nxgraphics for a description + of the fat, flat line bug. + + pm: + -- + This is a configuration that is used to test STM32 power management, i.e., + to test that the board can go into lower and lower states of power usage + as a result of inactivity. This configuration is based on the nsh2 + configuration with modifications for testing power management. This + configuration should provide some guideline for power management in your + STM32 application. + + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + + CONFIG_PM_CUSTOMINIT and CONFIG_IDLE_CUSTOM are necessary parts of the + PM configuration: + + CONFIG_PM_CUSTOMINIT=y + + CONFIG_PM_CUSTOMINIT moves the PM initialization from arch/arm/src/stm32/stm32_pminitialiaze.c + to configs/stm3210-eval/src/up_pm.c. This allows us to support board- + specific PM initialization. + + CONFIG_IDLE_CUSTOM=y + + The bulk of the PM activities occur in the IDLE loop. The IDLE loop is + special because it is what runs when there is no other task running. Therefore + when the IDLE executes, we can be assure that nothing else is going on; this + is the ideal condition for doing reduced power management. + + The configuration CONFIG_IDLE_CUSTOM allows us to "steal" the normal STM32 + IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace this with our own + custom IDLE loop (at configs/stm3210-eval/src/up_idle.c). + + Here are some additional things to note in the configuration: + + CONFIG_PM_BUTTONS=y + + CONFIG_PM_BUTTONS enables button support for PM testing. Buttons can drive + EXTI interrupts and EXTI interrrupts can be used to wakeup for certain reduced + power modes (STOP mode). The use of the buttons here is for PM testing purposes + only; buttons would normally be part the application code and CONFIG_PM_BUTTONS + would not be defined. + + CONFIG_RTC_ALARM=y + + The RTC alarm is used to wake up from STOP mode and to transition to + STANDBY mode. This used of the RTC alarm could conflict with other uses of + the RTC alarm in your application. + + posix_spawn: + ------------ + This configuration directory, performs a simple test os the posix_spawn + interface using apps/examples/posix_spawn. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default toolchain: + + CONFIG_HOST_WINDOWS=y : Builds under windows + CONFIG_WINDOWS_CYGWIN=y : Using Cygwin and + CONFIG_STM32_CODESOURCERYW=y : The native Windows CodeSourcery toolchain + + 3. By default, this project assumes that you are *NOT* using the DFU + bootloader. + + usbnsh: + ------- + + This is another NSH example. If differs from other 'nsh' configurations + in that this configurations uses a USB serial device for console I/O. + Such a configuration is useful on the stm32f3discovery which has no + builtin RS-232 drivers. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. By default, this configuration uses the CodeSourcery toolchain + for Windows and builds under Cygwin (or probably MSYS). That + can easily be reconfigured, of course. + + CONFIG_HOST_WINDOWS=y : Builds under Windows + CONFIG_WINDOWS_CYGWIN=y : Using Cygwin + CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows + + 3. This configuration does have UART2 output enabled and set up as + the system logging device: + + CONFIG_SYSLOG=y : Enable output to syslog, not console + CONFIG_SYSLOG_CHAR=y : Use a character device for system logging + CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0 + + However, there is nothing to generate SYLOG output in the default + configuration so nothing should appear on UART2 unless you enable + some debug output or enable the USB monitor. + + 4. Enabling USB monitor SYSLOG output. If tracing is enabled, the USB + device will save encoded trace output in in-memory buffer; if the + USB monitor is enabled, that trace buffer will be periodically + emptied and dumped to the system loggin device (UART2 in this + configuraion): + + CONFIG_USBDEV_TRACE=y : Enable USB trace feature + CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory + CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH + CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor + CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds + + CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y + CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y + CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y + CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + + 5. By default, this project assumes that you are *NOT* using the DFU + bootloader. + + Using the Prolifics PL2303 Emulation + ------------------------------------ + You could also use the non-standard PL2303 serial device instead of + the standard CDC/ACM serial device by changing: + + CONFIG_CDCACM=y : Disable the CDC/ACM serial device class + CONFIG_CDCACM_CONSOLE=y : The CDC/ACM serial device is NOT the console + CONFIG_PL2303=y : The Prolifics PL2303 emulation is enabled + CONFIG_PL2303_CONSOLE=y : The PL2303 serial device is the console + + winbuild: + -------- + + This is a version of the apps/example/ostest, but configure to build natively + in the Windows CMD shell. + + NOTES: + + 1. The beginnings of a Windows native build are in place but still not full + usable as of this writing. The windows native build logic is currently + separate and must be started by: + + make -f Makefile.win + + This build: + + - Uses all Windows style paths + - Uses primarily Windows batch commands from cmd.exe, with + - A few extensions from GNUWin32 (or MSYS is you prefer) + + In this build, you cannot use a Cygwin or MSYS shell. Rather the build must + be performed in a Windows console. Here is a better shell than than the + standard issue, CMD.exe shell: ConEmu which can be downloaded from: + http://code.google.com/p/conemu-maximus5/ + + CONFIG_HOST_WINDOWS=y : Windows + CONFIG_WINDOWS_NATIVE=y : Native Windows environment + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + + Build Tools. The build still relies on some Unix-like commands. I use + the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/. + The MSYS tools are probably also a option but are likely lower performance + since they are based on Cygwin 1.3. + + Host Compiler: I use the MingGW compiler which can be downloaded from + http://www.mingw.org/. If you are using GNUWin32, then it is recommended + the you not install the optional MSYS components as there may be conflicts. diff --git a/nuttx/configs/stm32f3discovery/include/board.h b/nuttx/configs/stm32f3discovery/include/board.h new file mode 100644 index 000000000..81794a52a --- /dev/null +++ b/nuttx/configs/stm32f3discovery/include/board.h @@ -0,0 +1,323 @@ +/************************************************************************************ + * configs/stm32f3discovery/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_STM32F3DISCOVERY_INCLUDE_BOARD_H +#define __CONFIG_STM32F3DISCOVERY_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#ifndef __ASSEMBLY__ +# include <stdint.h> +#endif + +#include "stm32_rcc.h" +#include "stm32_sdio.h" +#include "stm32_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* The STM32F3Discovery board features a single 8MHz crystal. Space is provided + * for a 32kHz RTC backup crystal, but it is not stuffed. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM27_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* LED definitions ******************************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with stm32_setled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_BLUE BOARD_LED4 + +/* LED bits for use with stm32_setleds() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the + * stm32f3discovery. The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions ***************************************************************/ +/* The STM32F3Discovery supports one button: */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ************************************************/ + +/* UART2: + * + * The STM32F3Discovery has no on-board serial devices, but the console is + * brought out to PA2 (TX) and PA3 (RX) for connection to an external serial device. + * (See the README.txt file for other options) + */ + +#define GPIO_USART2_RX GPIO_USART2_RX_1 +#define GPIO_USART2_TX GPIO_USART2_TX_1 + +/* PWM + * + * The STM32F3Discovery has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2 + +/* SPI - There is a MEMS device on SPI1 using these pins: */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* Timer Inputs/Outputs (see the README.txt file for options) */ + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_2 +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1 + +#define GPIO_TIM8_CH1IN GPIO_TIM8_CH1IN_1 +#define GPIO_TIM8_CH2IN GPIO_TIM8_CH2IN_1 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +EXTERN void stm32_boardinitialize(void); + +/************************************************************************************ + * Name: stm32_ledinit, stm32_setled, and stm32_setleds + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If + * CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to + * control the LEDs from user applications. + * + ************************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +EXTERN void stm32_ledinit(void); +EXTERN void stm32_setled(int led, bool ledon); +EXTERN void stm32_setleds(uint8_t ledset); +#endif + +/************************************************************************************ + * Button support. + * + * Description: + * up_buttoninit() must be called to initialize button resources. After + * that, up_buttons() may be called to collect the current state of all + * buttons or up_irqbutton() may be called to register button interrupt + * handlers. + * + * After up_buttoninit() has been called, up_buttons() may be called to + * collect the state of all buttons. up_buttons() returns an 8-bit bit set + * with each bit associated with a button. See the BUTTON_*_BIT + * definitions in board.h for the meaning of each bit. + * + * up_irqbutton() may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See the + * BUTTON_* definitions in board.h for the meaning of enumeration + * value. The previous interrupt handler address is returned (so that it may + * restored, if so desired). + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_BUTTONS +EXTERN void up_buttoninit(void); +EXTERN uint8_t up_buttons(void); +#ifdef CONFIG_ARCH_IRQBUTTONS +EXTERN xcpt_t up_irqbutton(int id, xcpt_t irqhandler); +#endif +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_STM32F3DISCOVERY_INCLUDE_BOARD_H */ diff --git a/nuttx/configs/stm32f3discovery/nsh/Make.defs b/nuttx/configs/stm32f3discovery/nsh/Make.defs new file mode 100644 index 000000000..0952fcc47 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/nsh/Make.defs @@ -0,0 +1,111 @@ +############################################################################ +# configs/stm32f3discovery/nsh/Make.defs +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/stm32f3discovery/nsh/defconfig b/nuttx/configs/stm32f3discovery/nsh/defconfig new file mode 100644 index 000000000..7e43a7e8b --- /dev/null +++ b/nuttx/configs/stm32f3discovery/nsh/defconfig @@ -0,0 +1,700 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM4=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F103RET6 is not set +# CONFIG_ARCH_CHIP_STM32F103VCT6 is not set +# CONFIG_ARCH_CHIP_STM32F103VET6 is not set +# CONFIG_ARCH_CHIP_STM32F103ZET6 is not set +# CONFIG_ARCH_CHIP_STM32F105VBT7 is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +CONFIG_ARCH_CHIP_CONFIG_ARCH_CHIP_STM32F303VC=y +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +CONFIG_STM32_STM32F30XX=y +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +# CONFIG_STM32_ETHMAC is not set +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_IWDG is not set +CONFIG_STM32_OTGFS=y +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +CONFIG_STM32_SPI1=y +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_WWDG is not set +CONFIG_STM32_SPI=y + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_STM32_USART=y + +# +# U[S]ART Configuration +# +# CONFIG_USART2_RS485 is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set + +# +# SPI Configuration +# +# CONFIG_STM32_SPI_INTERRUPTS is not set +# CONFIG_STM32_SPI_DMA is not set + +# +# USB Host Configuration +# + +# +# External Memory Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set + +# +# Board Settings +# +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=114688 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f3discovery" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_ARCH_HAVE_I2CRESET=y +CONFIG_SPI=y +# CONFIG_SPI_OWNBUS is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_USART2=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_BINFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +# CONFIG_LIB_KBDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/stm32f3discovery/nsh/setenv.sh b/nuttx/configs/stm32f3discovery/nsh/setenv.sh new file mode 100755 index 000000000..dea918b83 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/nsh/setenv.sh @@ -0,0 +1,75 @@ +#!/bin/bash +# configs/stm32f3discovery/nsh/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/stm32f3discovery/ostest/Make.defs b/nuttx/configs/stm32f3discovery/ostest/Make.defs new file mode 100644 index 000000000..a2a8adb24 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/ostest/Make.defs @@ -0,0 +1,122 @@ +############################################################################ +# configs/stm32f3discovery/ostest/Make.defs +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = +ifeq ($(CONFIG_HOST_WINDOWS),y) + HOSTEXEEXT = .exe +else + HOSTEXEEXT = +endif + +ifeq ($(WINTOOL),y) + # Windows-native host tools + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh +else + # Linux/Cygwin-native host tools + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +endif + diff --git a/nuttx/configs/stm32f3discovery/ostest/defconfig b/nuttx/configs/stm32f3discovery/ostest/defconfig new file mode 100644 index 000000000..80292fa7e --- /dev/null +++ b/nuttx/configs/stm32f3discovery/ostest/defconfig @@ -0,0 +1,583 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set +# CONFIG_WINDOWS_MKLINK is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM3S is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM4=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set +CONFIG_ARCH_IRQPRIO=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F103RET6 is not set +# CONFIG_ARCH_CHIP_STM32F103VCT6 is not set +# CONFIG_ARCH_CHIP_STM32F103VET6 is not set +# CONFIG_ARCH_CHIP_STM32F103ZET6 is not set +# CONFIG_ARCH_CHIP_STM32F105VBT7 is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +CONFIG_ARCH_CHIP_CONFIG_ARCH_CHIP_STM32F303VC=y +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +CONFIG_STM32_STM32F30XX=y +# CONFIG_STM32_CODESOURCERYW is not set +CONFIG_STM32_CODESOURCERYL=y +# CONFIG_STM32_ATOLLIC_LITE is not set +# CONFIG_STM32_ATOLLIC_PRO is not set +# CONFIG_STM32_DEVKITARM is not set +# CONFIG_STM32_RAISONANCE is not set +# CONFIG_STM32_BUILDROOT is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +# CONFIG_STM32_ETHMAC is not set +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_WWDG is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# USB Host Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_STACKDUMP=y + +# +# Board Settings +# +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=114688 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f3discovery" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2009 +CONFIG_START_MONTH=9 +CONFIG_START_DAY=21 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="ostest_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_POLL=y + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +# CONFIG_CUSTOM_STACK is not set +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_USART2=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_FS_RAMMAP is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Basic CXX Support +# +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Named Applications +# +# CONFIG_BUILTIN is not set + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WLAN is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/stm32f3discovery/ostest/setenv.sh b/nuttx/configs/stm32f3discovery/ostest/setenv.sh new file mode 100755 index 000000000..43e2a1b3e --- /dev/null +++ b/nuttx/configs/stm32f3discovery/ostest/setenv.sh @@ -0,0 +1,75 @@ +#!/bin/bash +# configs/stm32f3discovery/ostest/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/stm32f3discovery/scripts/gnu-elf.ld b/nuttx/configs/stm32f3discovery/scripts/gnu-elf.ld new file mode 100644 index 000000000..211a52100 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/scripts/gnu-elf.ld @@ -0,0 +1,129 @@ +/**************************************************************************** + * configs/stm32f3discovery/scripts/gnu-elf.ld + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +SECTIONS +{ + .text 0x00000000 : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + *(.ctors) /* Old ABI: Unallocated */ + *(.init_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .dtors : + { + _sdtors = . ; + *(.dtors) /* Old ABI: Unallocated */ + *(.fini_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/stm32f3discovery/scripts/ld.script b/nuttx/configs/stm32f3discovery/scripts/ld.script new file mode 100644 index 000000000..f3d649b98 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * configs/stm32f3discovery/scripts/ld.script + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/stm32f3discovery/src/Makefile b/nuttx/configs/stm32f3discovery/src/Makefile new file mode 100644 index 000000000..58ef88ce1 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/Makefile @@ -0,0 +1,122 @@ +############################################################################ +# configs/stm32f3discovery/src/Makefile +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CFLAGS += -I$(TOPDIR)/sched + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = up_boot.c up_spi.c + +ifeq ($(CONFIG_HAVE_CXX),y) +CSRCS += up_cxxinitialize.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += up_autoleds.c +else +CSRCS += up_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += up_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += up_usb.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += up_pwm.c +endif + +ifeq ($(CONFIG_QENCODER),y) +CSRCS += up_qencoder.c +endif + +ifeq ($(CONFIG_WATCHDOG),y) +CSRCS += up_watchdog.c +endif + +ifeq ($(CONFIG_NSH_ARCHINIT),y) +CSRCS += up_nsh.c +endif + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + CFLAGS += -I$(ARCH_SRCDIR)\chip -I$(ARCH_SRCDIR)\common -I$(ARCH_SRCDIR)\armv7-m +else +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" +else + CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m +endif +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/nuttx/configs/stm32f3discovery/src/stm32f3discovery-internal.h b/nuttx/configs/stm32f3discovery/src/stm32f3discovery-internal.h new file mode 100644 index 000000000..a26e7b61a --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/stm32f3discovery-internal.h @@ -0,0 +1,200 @@ +/**************************************************************************************************** + * configs/stm32f3discovery/src/stm32f3discovery-internal.h + * arch/arm/src/board/stm32f3discovery-internal.n + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __CONFIGS_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_INTERNAL_H +#define __CONFIGS_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_INTERNAL_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/compiler.h> +#include <stdint.h> + +/**************************************************************************************************** + * Definitions + ****************************************************************************************************/ +/* Configuration ************************************************************************************/ +/* How many SPI modules does this chip support? */ + +#if STM32_NSPI < 1 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 +#elif STM32_NSPI < 3 +# undef CONFIG_STM32_SPI3 +#endif + +/* STM32F3Discovery GPIOs **************************************************************************/ +/* LEDs */ + +#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN12) +#define GPIO_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13) +#define GPIO_LED3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN14) +#define GPIO_LED4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN15) + +/* BUTTONS -- NOTE that all have EXTI interrupts configured */ + +#define MIN_IRQBUTTON BUTTON_USER +#define MAX_IRQBUTTON BUTTON_USER +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0) + +/* PWM + * + * The STM32F3Discovery has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define STM32F3DISCOVERY_PWMTIMER 4 +#define STM32F3DISCOVERY_PWMCHANNEL 2 + +/* SPI chip selects */ + +#define GPIO_CS_MEMS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3) + +/* USB OTG FS + * + * PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED) + * PC0 OTG_FS_PowerSwitchOn + * PD5 OTG_FS_Overcurrent + */ + +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) + +#ifdef CONFIG_USBHOST +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) + +#else +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) +#endif + +/* UG-2864AMBAG01 or UG-2864HSWEG01 OLED Display (SPI 4-wire): + * + * --------------------------+---------------------------------------------- + * Connector CON10 J1: | STM32F3Discovery + * --------------+-----------+---------------------------------------------- + * CON10 J1: | CON20 J2: | P1/P2: + * --------------+-----------+---------------------------------------------- + * 1 3v3 | 3,4 3v3 | P2 3V + * 3 /RESET | 8 /RESET | P2 PB6 (Arbitrary selection) + * 5 /CS | 7 /CS | P2 PB7 (Arbitrary selection) + * 7 A0|D/C | 9 A0|D/C | P2 PB8 (Arbitrary selection) + * 9 LED+ (N/C) | ----- | ----- + * 2 5V Vcc | 1,2 Vcc | P2 5V + * 4 DI | 18 D1/SI | P1 PA7 (GPIO_SPI1_MOSI == GPIO_SPI1_MOSI_1 (1)) + * 6 SCLK | 19 D0/SCL | P1 PA5 (GPIO_SPI1_SCK == GPIO_SPI1_SCK_1 (1)) + * 8 LED- (N/C) | ----- | ------ + * 10 GND | 20 GND | P2 GND + * --------------+-----------+---------------------------------------------- + * (1) Required because of on-board MEMS + * ------------------------------------------------------------------------- + */ + +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) +# define GPIO_OLED_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6) +# define GPIO_OLED_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7) +# define GPIO_OLED_A0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_OLED_DC GPIO_OLED_A0 +#endif + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public data + ****************************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +/**************************************************************************************************** + * Name: stm32_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f3discovery board. + * + ****************************************************************************************************/ + +void weak_function stm32_spiinitialize(void); + +/**************************************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the STM32F3Discovery board. + * + ****************************************************************************************************/ + +#ifdef CONFIG_STM32_OTGFS +void weak_function stm32_usbinitialize(void); +#endif + +/**************************************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. This function will + * start a thread that will monitor for device connection/disconnection events. + * + ****************************************************************************************************/ + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) +int stm32_usbhost_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_INTERNAL_H */ + diff --git a/nuttx/configs/stm32f3discovery/src/up_autoleds.c b/nuttx/configs/stm32f3discovery/src/up_autoleds.c new file mode 100644 index 000000000..4becd6e52 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_autoleds.c @@ -0,0 +1,260 @@ +/**************************************************************************** + * configs/stm32f3discovery/src/up_autoleds.c + * arch/arm/src/board/up_autoleds.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <debug.h> + +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "stm32_internal.h" +#include "stm32f3discovery-internal.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG with + * CONFIG_DEBUG_VERBOSE too) + */ + +#undef LED_DEBUG /* Define to enable debug */ + +#ifdef LED_DEBUG +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM32F3_LED1 (1 << 0) +#define STM32F3_LED2 (1 << 1) +#define STM32F3_LED3 (1 << 2) +#define STM32F3_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM32F3_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM32F3_LED2|STM32F3_LED3|STM32F3_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM32F3_LED1|STM32F3_LED2|STM32F3_LED3|STM32F3_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F3_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F3_LED1|STM32F3_LED3|STM32F3_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F3_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F3_LED2|STM32F3_LED3|STM32F3_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM32F3_LED1|STM32F3_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM32F3_LED3|STM32F3_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM32F3_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F3_LED1|STM32F3_LED3|STM32F3_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM32F3_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM32F3_LED1|STM32F3_LED2|STM32F3_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM32F3_LED1|STM32F3_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM32F3_LED3|STM32F3_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM32F3_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM32F3_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM32F3_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM32F3_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM32F3_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM32F3_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM32F3_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM32F3_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM32F3_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM32F3_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM32F3_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM32F3_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM32F3_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM32F3_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM32F3_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM32F3_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_ledinit + ****************************************************************************/ + +void up_ledinit(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: up_ledon + ****************************************************************************/ + +void up_ledon(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: up_ledoff + ****************************************************************************/ + +void up_ledoff(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/stm32f3discovery/src/up_boot.c b/nuttx/configs/stm32f3discovery/src/up_boot.c new file mode 100644 index 000000000..73c0a0cf7 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_boot.c @@ -0,0 +1,103 @@ +/************************************************************************************ + * configs/stm32f3discovery/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include <arch/board/board.h> + +#include "up_arch.h" +#include "stm32f3discovery-internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function + * stm32_spiinitialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spiinitialize) + { + stm32_spiinitialize(); + } +#endif + + /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) + * disabled, and 3) the weak function stm32_usbinitialize() has been brought + * the weak function stm32_usbinitialize() has been brought into the build. + * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/nuttx/configs/stm32f3discovery/src/up_buttons.c b/nuttx/configs/stm32f3discovery/src/up_buttons.c new file mode 100644 index 000000000..5ae8ec679 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * configs/stm32f3discovery/src/up_buttons.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> + +#include <arch/board/board.h> +#include "stm32f3discovery-internal.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint16_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_buttoninit + * + * Description: + * up_buttoninit() must be called to initialize button resources. After + * that, up_buttons() may be called to collect the current state of all + * buttons or up_irqbutton() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void up_buttoninit(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } +} + +/**************************************************************************** + * Name: up_buttons + ****************************************************************************/ + +uint8_t up_buttons(void) +{ + uint8_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. + */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/************************************************************************************ + * Button support. + * + * Description: + * up_buttoninit() must be called to initialize button resources. After + * that, up_buttons() may be called to collect the current state of all + * buttons or up_irqbutton() may be called to register button interrupt + * handlers. + * + * After up_buttoninit() has been called, up_buttons() may be called to + * collect the state of all buttons. up_buttons() returns an 8-bit bit set + * with each bit associated with a button. See the BUTTON_*_BIT + * definitions in board.h for the meaning of each bit. + * + * up_irqbutton() may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See the + * BUTTON_* definitions in board.h for the meaning of enumeration + * value. The previous interrupt handler address is returned (so that it may + * restored, if so desired). + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +xcpt_t up_irqbutton(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler = NULL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + } + return oldhandler; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/nuttx/configs/stm32f3discovery/src/up_cxxinitialize.c b/nuttx/configs/stm32f3discovery/src/up_cxxinitialize.c new file mode 100644 index 000000000..a7d975bb2 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_cxxinitialize.c @@ -0,0 +1,155 @@ +/************************************************************************************ + * configs/stm32f3discovery/src/up_cxxinitialize.c + * arch/arm/src/board/up_cxxinitialize.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include <nuttx/arch.h> + +#include <arch/stm32/chip.h> +#include "chip.h" + +#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE) + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Debug ****************************************************************************/ +/* Non-standard debug that may be enabled just for testing the static constructors */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_CXX +#endif + +#ifdef CONFIG_DEBUG_CXX +# define cxxdbg dbg +# define cxxlldbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define cxxvdbg vdbg +# define cxxllvdbg llvdbg +# else +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +# endif +#else +# define cxxdbg(x...) +# define cxxlldbg(x...) +# define cxxvdbg(x...) +# define cxxllvdbg(x...) +#endif + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* This type defines one entry in initialization array */ + +typedef void (*initializer_t)(void); + +/************************************************************************************ + * External references + ************************************************************************************/ +/* _sinit and _einit are symbols exported by the linker script that mark the + * beginning and the end of the C++ initialization section. + */ + +extern initializer_t _sinit; +extern initializer_t _einit; + +/* _stext and _etext are symbols exported by the linker script that mark the + * beginning and the end of text. + */ + +extern uint32_t _stext; +extern uint32_t _etext; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: up_cxxinitialize + * + * Description: + * If C++ and C++ static constructors are supported, then this function + * must be provided by board-specific logic in order to perform + * initialization of the static C++ class instances. + * + * This function should then be called in the application-specific + * user_start logic in order to perform the C++ initialization. NOTE + * that no component of the core NuttX RTOS logic is involved; This + * function defintion only provides the 'contract' between application + * specific C++ code and platform-specific toolchain support + * + ***************************************************************************/ + +void up_cxxinitialize(void) +{ + initializer_t *initp; + + cxxdbg("_sinit: %p _einit: %p _stext: %p _etext: %p\n", + &_sinit, &_einit, &_stext, &_etext); + + /* Visit each entry in the initialzation table */ + + for (initp = &_sinit; initp != &_einit; initp++) + { + initializer_t initializer = *initp; + cxxdbg("initp: %p initializer: %p\n", initp, initializer); + + /* Make sure that the address is non-NULL and lies in the text region + * defined by the linker script. Some toolchains may put NULL values + * or counts in the initialization table + */ + + if ((void*)initializer > (void*)&_stext && (void*)initializer < (void*)&_etext) + { + cxxdbg("Calling %p\n", initializer); + initializer(); + } + } +} + +#endif /* CONFIG_HAVE_CXX && CONFIG_HAVE_CXXINITIALIZE */ + diff --git a/nuttx/configs/stm32f3discovery/src/up_nsh.c b/nuttx/configs/stm32f3discovery/src/up_nsh.c new file mode 100644 index 000000000..c7392f47c --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_nsh.c @@ -0,0 +1,159 @@ +/**************************************************************************** + * config/stm32f3discovery/src/up_nsh.c + * arch/arm/src/board/up_nsh.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <stdio.h> +#include <debug.h> +#include <errno.h> + +#ifdef CONFIG_STM32_SDIO +# include <nuttx/sdio.h> +# include <nuttx/mmcsd.h> +#endif + +#ifdef CONFIG_SYSTEM_USBMONITOR +# include <apps/usbmonitor.h> +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32_internal.h" +#include "stm32f3discovery-internal.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +# undef HAVE_USBMONITOR +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_CPP_HAVE_VARARGS +# ifdef CONFIG_DEBUG +# define message(...) lowsyslog(__VA_ARGS__) +# else +# define message(...) printf(__VA_ARGS__) +# endif +#else +# ifdef CONFIG_DEBUG +# define message lowsyslog +# else +# define message printf +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_archinitialize + * + * Description: + * Perform architecture specific initialization + * + ****************************************************************************/ + +int nsh_archinitialize(void) +{ +#if defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) + int ret; +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread + * will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + message("nsh_archinitialize: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(0, NULL); + if (ret != OK) + { + message("nsh_archinitialize: Start USB monitor: %d\n", ret); + } +#endif + + return OK; +} diff --git a/nuttx/configs/stm32f3discovery/src/up_pwm.c b/nuttx/configs/stm32f3discovery/src/up_pwm.c new file mode 100644 index 000000000..3c7fe0772 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_pwm.c @@ -0,0 +1,142 @@ +/************************************************************************************ + * configs/stm32f3discovery/src/up_pwm.c + * arch/arm/src/board/up_pwm.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <errno.h> +#include <debug.h> + +#include <nuttx/pwm.h> +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" +#include "stm32_pwm.h" +#include "stm32f3discovery-internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ +/* PWM + * + * The stm32f3discovery has no real on-board PWM devices, but the board can be configured to output + * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this + * purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +#ifdef HAVE_PWM + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: pwm_devinit + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/pwm. + * + ************************************************************************************/ + +int pwm_devinit(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); + if (!pwm) + { + dbg("Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + adbg("pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_PWM */ diff --git a/nuttx/configs/stm32f3discovery/src/up_qencoder.c b/nuttx/configs/stm32f3discovery/src/up_qencoder.c new file mode 100644 index 000000000..8baaa64e0 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_qencoder.c @@ -0,0 +1,187 @@ +/************************************************************************************ + * configs/stm32f3discovery/src/up_qencoder.c + * arch/arm/src/board/up_qencoder.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <errno.h> +#include <debug.h> + +#include <nuttx/sensors/qencoder.h> +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" +#include "stm32_qencoder.h" +#include "stm32f3discovery-internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ +/* Check if we have a timer configured for quadrature encoder -- assume YES. */ + +#define HAVE_QENCODER 1 + +/* If TIMn is not enabled (via CONFIG_STM32_TIMn), then the configuration cannot + * specify TIMn as a quadrature encoder (via CONFIG_STM32_TIMn_QE). + */ + +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE +#endif +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE +#endif +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE +#endif + +/* If the upper-half quadrature encoder driver is not enabled, then we cannot + * support the quadrature encoder. + */ + +#ifndef CONFIG_QENCODER +# undef HAVE_QENCODER +#endif + +/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are + * configured as quadrature encoders, this logic will arbitrarily select + * the lowest numbered timer. + * + * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured + * as a quadrature encoder in order to support the lower half quadrature + * encoder driver. The above check assures that if CONFIG_STM32_TIMn_QE + * is defined, then the correspdonding TIMn is also enabled. + */ + +#if defined CONFIG_STM32_TIM1_QE +# define TIMID 1 +#elif defined CONFIG_STM32_TIM2_QE +# define TIMID 2 +#elif defined CONFIG_STM32_TIM3_QE +# define TIMID 3 +#elif defined CONFIG_STM32_TIM4_QE +# define TIMID 4 +#elif defined CONFIG_STM32_TIM5_QE +# define TIMID 5 +#elif defined CONFIG_STM32_TIM8_QE +# define TIMID 8 +#else +# undef HAVE_QENCODER +#endif + +#ifdef HAVE_QENCODER + +/* Debug ***************************************************************************/ +/* Non-standard debug that may be enabled just for testing the quadrature encoder */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_QENCODER +#endif + +#ifdef CONFIG_DEBUG_QENCODER +# define qedbg dbg +# define qelldbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define qevdbg vdbg +# define qellvdbg llvdbg +# else +# define qevdbg(x...) +# define qellvdbg(x...) +# endif +#else +# define qedbg(x...) +# define qelldbg(x...) +# define qevdbg(x...) +# define qellvdbg(x...) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: qe_devinit + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/qencoder. + * + ************************************************************************************/ + +int qe_devinit(void) +{ + static bool initialized = false; + int ret; + + /* Check if we are already initialized */ + + if (!initialized) + { + /* Initialize a quadrature encoder interface. */ + + qevdbg("Initializing the quadrature encoder using TIM%d\n", TIMID); + ret = stm32_qeinitialize("/dev/qe0", TIMID); + if (ret < 0) + { + qedbg("stm32_qeinitialize failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_QENCODER */ diff --git a/nuttx/configs/stm32f3discovery/src/up_spi.c b/nuttx/configs/stm32f3discovery/src/up_spi.c new file mode 100644 index 000000000..f578cbb35 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_spi.c @@ -0,0 +1,251 @@ +/************************************************************************************ + * configs/stm32f3discovery/src/up_spi.c + * arch/arm/src/board/up_spi.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/spi.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "chip.h" +#include "stm32_internal.h" +#include "stm32f3discovery-internal.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SPI_DEBUG /* Define to enable debug */ +#undef SPI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SPI_DEBUG +# define spidbg lldbg +# ifdef SPI_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# undef SPI_VERBOSE +# define spidbg(x...) +# define spivdbg(x...) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f3discovery board. + * + ************************************************************************************/ + +void weak_function stm32_spiinitialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + (void)stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ +#endif +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) + (void)stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ +# if defined(CONFIG_LCD_UG2864AMBAG01) + (void)stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */ +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) + (void)stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ +# endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be + * provided by board-specific logic. They are implementations of the select + * and status methods of the SPI interface defined by struct spi_ops_s (see + * include/nuttx/spi.h). All other methods (including up_spiinitialize()) + * are provided by common STM32 logic. To use this common SPI logic on your + * board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your + * board-specific logic. These functions will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 3. Add a calls to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) + if (devid == SPIDEV_DISPLAY) + { + stm32_gpiowrite(GPIO_OLED_CS, !selected); + } + else +#endif + { + stm32_gpiowrite(GPIO_CS_MEMS, !selected); + } +} + +uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +{ +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) + if (devid == SPIDEV_DISPLAY) + { + /* "This is the Data/Command control pad which determines whether the + * data bits are data or a command. + * + * A0 = "H": the inputs at D0 to D7 are treated as display data. + * A0 = "L": the inputs at D0 to D7 are transferred to the command + * registers." + */ + +# if defined(CONFIG_LCD_UG2864AMBAG01) + (void)stm32_gpiowrite(GPIO_OLED_A0, !cmd); +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) + (void)stm32_gpiowrite(GPIO_OLED_DC, !cmd); +# endif + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/nuttx/configs/stm32f3discovery/src/up_usb.c b/nuttx/configs/stm32f3discovery/src/up_usb.c new file mode 100644 index 000000000..8dfb2840b --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_usb.c @@ -0,0 +1,294 @@ +/************************************************************************************ + * configs/stm32f3discovery/src/up_usbdev.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <sched.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/usb/usbdev.h> +#include <nuttx/usb/usbhost.h> +#include <nuttx/usb/usbdev_trace.h> + +#include "up_arch.h" +#include "stm32_internal.h" +#include "stm32f3discovery-internal.h" + +#ifdef CONFIG_STM32_OTGFS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# define CONFIG_USBHOST_STACKSIZE 1024 +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_driver_s *g_drvr; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + bool connected = false; + int ret; + + uvdbg("Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + ret = DRVR_WAIT(g_drvr, connected); + DEBUGASSERT(ret == OK); + + connected = !connected; + uvdbg("%s\n", connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)DRVR_ENUMERATE(g_drvr); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the STM32F3Discovery board. + * + ************************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ + + /* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/*********************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uvdbg("Register class drivers\n"); + ret = usbhost_storageinit(); + if (ret != OK) + { + udbg("Failed to register the mass storage class\n"); + } + + /* Then get an instance of the USB host interface */ + + uvdbg("Initialize USB host\n"); + g_drvr = usbhost_initialize(0); + if (g_drvr) + { + /* Start a thread to handle device connection. */ + + uvdbg("Start usbhost_waiter\n"); + + pid = TASK_CREATE("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + (main_t)usbhost_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/*********************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided be + * each platform that implements the STM32 OTG FS host interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump + * or, if 5 V are available on the application board, a basic power switch, must + * be added externally to drive the 5 V VBUS line. The external charge pump can + * be driven by any GPIO output. When the application decides to power on VBUS + * using the chosen GPIO, it must also set the port power bit in the host port + * control and status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the core + * clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/************************************************************************************ + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition is + * detected. + * + * Input paramter: + * handler - New overcurrent interrupt handler + * + * Returned value: + * Old overcurrent interrupt handler + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +xcpt_t stm32_setup_overcurrent(xcpt_t handler) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); +} +#endif + +/************************************************************************************ + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + ulldbg("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ + + + diff --git a/nuttx/configs/stm32f3discovery/src/up_userleds.c b/nuttx/configs/stm32f3discovery/src/up_userleds.c new file mode 100644 index 000000000..3b7bfa08f --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_userleds.c @@ -0,0 +1,248 @@ +/**************************************************************************** + * configs/stm32f3discovery/src/up_leds.c + * arch/arm/src/board/up_leds.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <debug.h> + +#include <arch/board/board.h> +#include <nuttx/power/pm.h> + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "stm32_internal.h" +#include "stm32f3discovery-internal.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG with + * CONFIG_DEBUG_VERBOSE too) + */ + +#undef LED_DEBUG /* Define to enable debug */ + +#ifdef LED_DEBUG +# define leddbg lldbg +# define ledvdbg llvdbg +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, enum pm_state_e pmstate); +#endif + + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb , enum pm_state_e pmstate) +{ + switch (pmstate) + { + case(PM_NORMAL): + { + /* Restore normal LEDs operation */ + + } + break; + + case(PM_IDLE): + { + /* Entering IDLE mode - Turn leds off */ + + } + break; + + case(PM_STANDBY): + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + + } + break; + + case(PM_SLEEP): + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + + } + break; + + default: + { + /* Should not get here */ + + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb , enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ledinit + ****************************************************************************/ + +void stm32_ledinit(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: stm32_setled + ****************************************************************************/ + +void stm32_setled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: stm32_setleds + ****************************************************************************/ + +void stm32_setleds(uint8_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +/**************************************************************************** + * Name: up_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void up_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + up_ledon(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/nuttx/configs/stm32f3discovery/src/up_watchdog.c b/nuttx/configs/stm32f3discovery/src/up_watchdog.c new file mode 100644 index 000000000..603c21f7c --- /dev/null +++ b/nuttx/configs/stm32f3discovery/src/up_watchdog.c @@ -0,0 +1,136 @@ +/************************************************************************************ + * configs/stm32f3discovery/src/up_watchdog.c + * arch/arm/src/board/up_watchdog.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <errno.h> +#include <debug.h> + +#include <nuttx/watchdog.h> +#include <arch/board/board.h> + +#include "stm32_wdg.h" + +#ifdef CONFIG_WATCHDOG + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ +/* Wathdog hardware should be enabled */ + +#if !defined(CONFIG_STM32_WWDG) && !defined(CONFIG_STM32_IWDG) +# warning "One of CONFIG_STM32_WWDG or CONFIG_STM32_IWDG must be defined" +#endif + +/* Select the path to the registered watchdog timer device */ + +#ifndef CONFIG_STM32_WDG_DEVPATH +# ifdef CONFIG_EXAMPLES_WATCHDOG_DEVPATH +# define CONFIG_STM32_WDG_DEVPATH CONFIG_EXAMPLES_WATCHDOG_DEVPATH +# else +# define CONFIG_STM32_WDG_DEVPATH "/dev/watchdog0" +# endif +#endif + +/* Use the un-calibrated LSI frequency if we have nothing better */ + +#if defined(CONFIG_STM32_IWDG) && !defined(CONFIG_STM32_LSIFREQ) +# define CONFIG_STM32_LSIFREQ STM32_LSI_FREQUENCY +#endif + +/* Debug ***************************************************************************/ +/* Non-standard debug that may be enabled just for testing the watchdog timer */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_WATCHDOG +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG +# define wdgdbg dbg +# define wdglldbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define wdgvdbg vdbg +# define wdgllvdbg llvdbg +# else +# define wdgvdbg(x...) +# define wdgllvdbg(x...) +# endif +#else +# define wdgdbg(x...) +# define wdglldbg(x...) +# define wdgvdbg(x...) +# define wdgllvdbg(x...) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: up_wdginitialize() + * + * Description: + * Perform architecuture-specific initialization of the Watchdog hardware. + * This interface must be provided by all configurations using + * apps/examples/watchdog + * + ****************************************************************************/ + +int up_wdginitialize(void) +{ + /* Initialize tha register the watchdog timer device */ + +#if defined(CONFIG_STM32_WWDG) + stm32_wwdginitialize(CONFIG_STM32_WDG_DEVPATH); + return OK; +#elif defined(CONFIG_STM32_IWDG) + stm32_iwdginitialize(CONFIG_STM32_WDG_DEVPATH, CONFIG_STM32_LSIFREQ); + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_WATCHDOG */ diff --git a/nuttx/configs/stm32f3discovery/usbnsh/Make.defs b/nuttx/configs/stm32f3discovery/usbnsh/Make.defs new file mode 100644 index 000000000..367162aca --- /dev/null +++ b/nuttx/configs/stm32f3discovery/usbnsh/Make.defs @@ -0,0 +1,111 @@ +############################################################################ +# configs/stm32f3discovery/usbnsh/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/stm32f3discovery/usbnsh/defconfig b/nuttx/configs/stm32f3discovery/usbnsh/defconfig new file mode 100644 index 000000000..83757c294 --- /dev/null +++ b/nuttx/configs/stm32f3discovery/usbnsh/defconfig @@ -0,0 +1,746 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM4=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F103RET6 is not set +# CONFIG_ARCH_CHIP_STM32F103VCT6 is not set +# CONFIG_ARCH_CHIP_STM32F103VET6 is not set +# CONFIG_ARCH_CHIP_STM32F103ZET6 is not set +# CONFIG_ARCH_CHIP_STM32F105VBT7 is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +CONFIG_ARCH_CHIP_CONFIG_ARCH_CHIP_STM32F303VC=y +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +CONFIG_STM32_STM32F30XX=y +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +# CONFIG_STM32_ETHMAC is not set +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_IWDG is not set +CONFIG_STM32_OTGFS=y +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +CONFIG_STM32_SPI1=y +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_WWDG is not set +CONFIG_STM32_SPI=y + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_STM32_USART=y + +# +# U[S]ART Configuration +# +# CONFIG_USART2_RS485 is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set + +# +# SPI Configuration +# +# CONFIG_STM32_SPI_INTERRUPTS is not set +# CONFIG_STM32_SPI_DMA is not set + +# +# USB Host Configuration +# + +# +# External Memory Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set + +# +# Board Settings +# +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=114688 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f3discovery" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=27 +# CONFIG_DEV_CONSOLE is not set +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_ARCH_HAVE_I2CRESET=y +CONFIG_SPI=y +# CONFIG_SPI_OWNBUS is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +CONFIG_SERIAL_REMOVABLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_USART2=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_USART2_SERIAL_CONSOLE is not set +CONFIG_NO_SERIAL_CONSOLE=y + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=256 +CONFIG_USART2_TXBUFSIZE=256 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +CONFIG_USBDEV=y + +# +# Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +# CONFIG_USBDEV_DUALSPEED is not set +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +# CONFIG_USBDEV_DMA is not set +# CONFIG_USBDEV_TRACE is not set +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_CDCACM_VENDORID=0x0525 +CONFIG_CDCACM_PRODUCTID=0xa4a7 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_BINFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG_ENABLE is not set +CONFIG_SYSLOG=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +# CONFIG_LIB_KBDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_USBCONSOLE is not set + +# +# USB Trace Support +# +# CONFIG_NSH_CONDEV is not set +CONFIG_NSH_ARCHINIT=y + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# USB Monitor +# diff --git a/nuttx/configs/stm32f3discovery/usbnsh/setenv.sh b/nuttx/configs/stm32f3discovery/usbnsh/setenv.sh new file mode 100755 index 000000000..52d93ed6e --- /dev/null +++ b/nuttx/configs/stm32f3discovery/usbnsh/setenv.sh @@ -0,0 +1,75 @@ +#!/bin/bash +# configs/stm32f3discovery/usbnsh/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt index 5629d8c4a..3ca5acad6 100644 --- a/nuttx/configs/stm32f4discovery/README.txt +++ b/nuttx/configs/stm32f4discovery/README.txt @@ -635,7 +635,7 @@ MAPPING TO STM32 F4: 4 Also the reset pin for the CS43L22 audio Codec. NOTE: The configuration to test this LCD configuration is available at -configs/stm32f4discover/nxlines. As of this writing, I have not seen the +configs/stm32f4discovery/nxlines. As of this writing, I have not seen the LCD working so I probaby have some things wrong. I might need to use a bit-baning interface. Below is the pin configurationf |