diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-06-19 19:09:14 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-06-19 19:09:14 +0000 |
| commit | ec7a135dd37dbf5d8fd5da72f0cf1ebf1f75f982 (patch) | |
| tree | bd462ed545551d8166e99240ea8714f6eccbce42 | |
| parent | 3c607301046611f4fc12b4a172bfcce94d608865 (diff) | |
| download | px4-nuttx-ec7a135dd37dbf5d8fd5da72f0cf1ebf1f75f982.tar.gz px4-nuttx-ec7a135dd37dbf5d8fd5da72f0cf1ebf1f75f982.tar.bz2 px4-nuttx-ec7a135dd37dbf5d8fd5da72f0cf1ebf1f75f982.zip | |
Add support for PIC32 MX1 and MX2 families
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4851 42af7a65-404d-4744-a932-0658087f49c3
28 files changed, 3814 insertions, 1942 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index a7fc1633d..c5c1d2aa0 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -2910,3 +2910,5 @@ particular. * Documentation/NfsHowTo.html: Add a How-To document for the new NFS client feature. + * arch/mips/include/pic32mx and arch/mips/src/pic32mx: Add support for the + PIC32MX1 and PIC32MX2 families. diff --git a/nuttx/Documentation/NuttXDocumentation.html b/nuttx/Documentation/NuttXDocumentation.html index cec713135..b26c83175 100644 --- a/nuttx/Documentation/NuttXDocumentation.html +++ b/nuttx/Documentation/NuttXDocumentation.html @@ -35,7 +35,7 @@ <li><a href="NuttXNxFlat.html" target="main">NXFLAT</a></li> <li><a href="NXGraphicsSubsystem.html" target="main">NX Graphics</a></li> <li><a href="NxWidgets.html" target="main">NxWidgets</a></li> - <li><a href="NfsHowTo.html" target="main">NFS How-To</a></li> + <li><a href="NfsHowto.html" target="main">NFS How-To</a></li> <li><a href="NuttXDemandPaging.html" target="main">Demand Paging</a></li> <li><a href="UsbTrace.html" target="main">USB Trace</a></li> <li><a href="README.html" target="main">README Files</a></li> diff --git a/nuttx/arch/mips/include/mips32/cp0.h b/nuttx/arch/mips/include/mips32/cp0.h index 91f6d2d0e..91f6d2d0e 100755..100644 --- a/nuttx/arch/mips/include/mips32/cp0.h +++ b/nuttx/arch/mips/include/mips32/cp0.h diff --git a/nuttx/arch/mips/include/mips32/irq.h b/nuttx/arch/mips/include/mips32/irq.h index 01a50029f..01a50029f 100755..100644 --- a/nuttx/arch/mips/include/mips32/irq.h +++ b/nuttx/arch/mips/include/mips32/irq.h diff --git a/nuttx/arch/mips/include/mips32/registers.h b/nuttx/arch/mips/include/mips32/registers.h index e541a8e53..e541a8e53 100755..100644 --- a/nuttx/arch/mips/include/mips32/registers.h +++ b/nuttx/arch/mips/include/mips32/registers.h diff --git a/nuttx/arch/mips/include/pic32mx/chip.h b/nuttx/arch/mips/include/pic32mx/chip.h index 834bb25fa..b997c4fc4 100644 --- a/nuttx/arch/mips/include/pic32mx/chip.h +++ b/nuttx/arch/mips/include/pic32mx/chip.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/include/pic32mx/chip.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -47,7 +47,825 @@ ****************************************************************************/ /* Configuration ************************************************************/ -#if defined(CONFIG_ARCH_CHIP_PIC32MX320F032H) +#if defined(PIC32MX110F016B) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */ +# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 10 /* 10 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX110F016C) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */ +# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX110F016D) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */ +# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX120F032B) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 10 /* 10 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX120F032C) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX120F032D) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX130F064B) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 10 /* 10 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX130F064C) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX130F064D) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX150F128B) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 10 /* 10 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX150F128C) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX150F128D) +# define CHIP_PIC32MX1 1 +# undef CHIP_PIC32MX2 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 /* No dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 0 /* No USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX210F016B) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */ +# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 9 /* 9 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX210F016C) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */ +# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX210F016D) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 16 /* 16Kb program FLASH */ +# define CHIP_DATAMEM_KB 4 /* 4Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX220F032B) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 9 /* 9 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX220F032C) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX220F032D) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX230F064B) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 9 /* 9 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX230F064C) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX230F064D) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX250F128B) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 28 /* Package SOIC, SSOP, SPDIP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 9 /* 9 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX250F128C) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 36 /* Package VTLA */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 12 /* 12 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(PIC32MX250F128D) +# undef CHIP_PIC32MX1 +# define CHIP_PIC32MX2 1 +# undef CHIP_PIC32MX3 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 44 /* Package VTLA, TQFP, QFN */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 3 /* 3Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 /* 2 dedicated DMA channels */ +# define CHIP_CTMU 1 /* Has CTMU */ +# deine CHIP_VRFSEL 1 /* Comparator voltage reference selection */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 2 /* 2 SPI/I2S interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 13 /* 13 10-bit ADC channels */ +# define CHIP_NCM 3 /* 3 Analog comparators */ +# define CHIP_USBOTG 1 /* Has USB OTG */ +# define CHIP_RTCC 1 /* Has RTCC */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 0 /* No parallel slave port (?) */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG 1 /* Has JTAG */ +#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F032H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # define CHIP_PIC32MX3 1 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -64,7 +882,6 @@ # define CHIP_NDMACH 0 /* No programmable DMA channels */ # define CHIP_NUSBDMACHAN 0 # undef CHIP_VRFSEL /* No comparator voltage reference selection */ - # undef CHIP_TRACE /* No trace capability */ # define CHIP_NUARTS 2 /* 2 UARTS */ # define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */ @@ -78,6 +895,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX320F064H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # define CHIP_PIC32MX3 1 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -94,7 +913,6 @@ # define CHIP_NDMACH 0 /* No programmable DMA channels */ # define CHIP_NUSBDMACHAN 0 # undef CHIP_VRFSEL /* No comparator voltage reference selection */ - # undef CHIP_TRACE /* No trace capability */ # define CHIP_NUARTS 2 /* 2 UARTS */ # define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */ @@ -108,6 +926,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # define CHIP_PIC32MX3 1 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -124,7 +944,6 @@ # define CHIP_NDMACH 0 /* No programmable DMA channels */ # define CHIP_NUSBDMACHAN 0 # undef CHIP_VRFSEL /* No comparator voltage reference selection */ - # undef CHIP_TRACE /* No trace capability */ # define CHIP_NUARTS 2 /* 2 UARTS */ # define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */ @@ -138,6 +957,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # define CHIP_PIC32MX3 1 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -167,6 +988,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX340F256H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # define CHIP_PIC32MX3 1 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -196,6 +1019,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX340F512H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # define CHIP_PIC32MX3 1 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -225,6 +1050,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # define CHIP_PIC32MX3 1 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -254,6 +1081,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -283,6 +1112,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX360F256L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -312,6 +1143,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX360F512L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -341,6 +1174,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX420F032H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -370,6 +1205,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -399,6 +1236,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX440F256H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -428,6 +1267,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX440F512H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -457,6 +1298,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -486,6 +1329,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX460F256L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -515,6 +1360,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX460F512L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # define CHIP_PIC32MX4 1 # undef CHIP_PIC32MX5 @@ -544,6 +1391,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -573,6 +1422,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -602,6 +1453,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -631,6 +1484,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -660,6 +1515,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -689,6 +1546,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -718,6 +1577,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -747,6 +1608,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -776,6 +1639,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -805,6 +1670,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # define CHIP_PIC32MX5 1 @@ -834,6 +1701,8 @@ # define CHIP_NETHERNET 0 /* No Ethernet */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -863,6 +1732,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -892,6 +1763,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -921,6 +1794,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -950,6 +1825,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -979,6 +1856,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1008,6 +1887,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1037,6 +1918,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1066,6 +1949,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1095,6 +1980,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1124,6 +2011,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1153,6 +2042,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1182,6 +2073,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1211,6 +2104,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512H) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1240,6 +2135,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1269,6 +2166,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1298,6 +2197,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 @@ -1327,6 +2228,8 @@ # define CHIP_NETHERNET 1 /* 1 Ethernet interface */ # define CHIP_JTAG #elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512L) +# undef CHIP_PIC32MX1 +# undef CHIP_PIC32MX2 # undef CHIP_PIC32MX3 # undef CHIP_PIC32MX4 # undef CHIP_PIC32MX5 diff --git a/nuttx/arch/mips/include/pic32mx/cp0.h b/nuttx/arch/mips/include/pic32mx/cp0.h index 67ced8a2c..67ced8a2c 100755..100644 --- a/nuttx/arch/mips/include/pic32mx/cp0.h +++ b/nuttx/arch/mips/include/pic32mx/cp0.h diff --git a/nuttx/arch/mips/include/pic32mx/irq.h b/nuttx/arch/mips/include/pic32mx/irq.h index de0970630..91fde196d 100755..100644 --- a/nuttx/arch/mips/include/pic32mx/irq.h +++ b/nuttx/arch/mips/include/pic32mx/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/include/pic32mx/irq.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -45,7 +45,9 @@ ****************************************************************************/ #include <arch/pic32mx/chip.h> -#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# include <arch/pic32mx/irq_1xx2xx.h> +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) # include <arch/pic32mx/irq_3xx4xx.h> #elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) # include <arch/pic32mx/irq_5xx6xx7xx.h> diff --git a/nuttx/arch/mips/include/pic32mx/irq_1xx2xx.h b/nuttx/arch/mips/include/pic32mx/irq_1xx2xx.h new file mode 100644 index 000000000..9ca71690b --- /dev/null +++ b/nuttx/arch/mips/include/pic32mx/irq_1xx2xx.h @@ -0,0 +1,215 @@ +/**************************************************************************** + * arch/mips/include/pic32mx/irq_1xx2xx.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H +#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt vector numbers. These should be used to attach to interrupts + * and to change interrupt priorities. + */ + +#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */ +#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */ +#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */ +#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */ +#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */ +#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */ +#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */ +#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */ +#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */ +#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */ +#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */ +#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */ +#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */ +#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */ +#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */ +#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */ +#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */ +#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */ +#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */ +#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */ +#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */ +#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */ +#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */ +#define PIC32MX_IRQ_AD1 23 /* Vector: 23, ADC1 Convert Done */ +#define PIC32MX_IRQ_FSCM 24 /* Vector: 24, Fail-Safe Clock Monitor */ +#define PIC32MX_IRQ_RTCC 25 /* Vector: 25, Real-Time Clock and Calendar */ +#define PIC32MX_IRQ_FCE 26 /* Vector: 26, Flash Control Event */ +#define PIC32MX_IRQ_CMP1 27 /* Vector: 27, Comparator 1 */ +#define PIC32MX_IRQ_CMP2 28 /* Vector: 28, Comparator 2 */ +#define PIC32MX_IRQ_CMP3 29 /* Vector: 29, Comparator 3 */ +#define PIC32MX_IRQ_USB 30 /* Vector: 30, USB */ +#define PIC32MX_IRQ_SPI1 31 /* Vector: 31, SPI1 */ +#define PIC32MX_IRQ_U1 32 /* Vector: 32, UART1 */ +#define PIC32MX_IRQ_I2C1 33 /* Vector: 33, I2C1 */ +#define PIC32MX_IRQ_CN 34 /* Vector: 34, Input Change */ +#define PIC32MX_IRQ_PMP 35 /* Vector: 35, Parallel Master Port */ +#define PIC32MX_IRQ_SPI2 36 /* Vector: 36, SPI2 */ +#define PIC32MX_IRQ_U2 37 /* Vector: 37, UART2 */ +#define PIC32MX_IRQ_I2C2 38 /* Vector: 38, I2C2 */ +#define PIC32MX_IRQ_CTMU 39 /* Vector: 39, CTMU */ +#define PIC32MX_IRQ_DMA0 40 /* Vector: 40, DMA Channel 0 */ +#define PIC32MX_IRQ_DMA1 41 /* Vector: 41, DMA Channel 1 */ +#define PIC32MX_IRQ_DMA2 42 /* Vector: 42, DMA Channel 2 */ +#define PIC32MX_IRQ_DMA3 43 /* Vector: 43, DMA Channel 3 */ + +#define PIC32MX_IRQ_BAD 44 /* Not a real IRQ number */ +#define NR_IRQS 44 + +/* Interrupt numbers. These should be used for enabling and disabling + * interrupt sources. Note that there are more interrupt sources than + * interrupt vectors and interrupt priorities. An offset of 128 is + * used so that there is no overlap with the IRQ numbers and to avoid + * errors due to misuse. + */ + +#define PIC32MX_IRQSRC0_FIRST (128+0) +#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */ +#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */ +#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */ +#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */ +#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */ +#define PIC32MX_IRQSRC_IC1E (128+5) /* Vector: 5, Input Capture 1 Error */ +#define PIC32MX_IRQSRC_IC1 (128+6) /* Vector: 5, Input Capture 1 */ +#define PIC32MX_IRQSRC_OC1 (128+7) /* Vector: 6, Output Compare 1 */ +#define PIC32MX_IRQSRC_INT1 (128+8) /* Vector: 7, External Interrupt 1 */ +#define PIC32MX_IRQSRC_T2 (128+9) /* Vector: 8, Timer 2 */ +#define PIC32MX_IRQSRC_IC2E (128+10) /* Vector: 9, Input Capture 2 Error */ +#define PIC32MX_IRQSRC_IC2 (128+11) /* Vector: 9, Input Capture 2 */ +#define PIC32MX_IRQSRC_OC2 (128+12) /* Vector: 10, Output Compare 2 */ +#define PIC32MX_IRQSRC_INT2 (128+13) /* Vector: 11, External Interrupt 2 */ +#define PIC32MX_IRQSRC_T3 (128+14) /* Vector: 12, Timer 3 */ +#define PIC32MX_IRQSRC_IC3E (128+15) /* Vector: 13, Input Capture 3 Error */ +#define PIC32MX_IRQSRC_IC3 (128+16) /* Vector: 13, Input Capture 3 */ +#define PIC32MX_IRQSRC_OC3 (128+17) /* Vector: 14, Output Compare 3 */ +#define PIC32MX_IRQSRC_INT3 (128+18) /* Vector: 15, External Interrupt 3 */ +#define PIC32MX_IRQSRC_T4 (128+19) /* Vector: 16, Timer 4 */ +#define PIC32MX_IRQSRC_IC4E (128+20) /* Vector: 17, Input Capture 4 Error */ +#define PIC32MX_IRQSRC_IC4 (128+21) /* Vector: 17, Input Capture 4 */ +#define PIC32MX_IRQSRC_OC4 (128+22) /* Vector: 18, Output Compare 4 */ +#define PIC32MX_IRQSRC_INT4 (128+23) /* Vector: 19, External Interrupt 4 */ +#define PIC32MX_IRQSRC_T5 (128+24) /* Vector: 20, Timer 5 */ +#define PIC32MX_IRQSRC_IC5E (128+25) /* Vector: 21, Input Capture 5 Error */ +#define PIC32MX_IRQSRC_IC5 (128+26) /* Vector: 21, Input Capture 5 */ +#define PIC32MX_IRQSRC_OC5 (128+27) /* Vector: 22, Output Compare 5 */ +#define PIC32MX_IRQSRC_AD1 (128+28) /* Vector: 23, ADC1 Convert Done */ +#define PIC32MX_IRQSRC_FSCM (128+29) /* Vector: 24, Fail-Safe Clock Monitor */ +#define PIC32MX_IRQSRC_RTCC (128+30) /* Vector: 25, Real-Time Clock and Calendar */ +#define PIC32MX_IRQSRC_FCE (128+31) /* Vector: 26, Flash Control Event */ +#define PIC32MX_IRQSRC0_LAST (128+31) + +#define PIC32MX_IRQSRC1_FIRST (128+32) +#define PIC32MX_IRQSRC_CMP1 (128+32) /* Vector: 27, Comparator 1 Interrupt */ +#define PIC32MX_IRQSRC_CMP2 (128+33) /* Vector: 28, Comparator 2 Interrupt */ +#define PIC32MX_IRQSRC_CMP2 (128+34) /* Vector: 29, Comparator 3 Interrupt */ +#define PIC32MX_IRQSRC_USB (128+35) /* Vector: 30, USB */ +#define PIC32MX_IRQSRC_SPI1E (128+36) /* Vector: 31, SPI1 */ +#define PIC32MX_IRQSRC_SPI1TX (128+37) /* Vector: 31, " " */ +#define PIC32MX_IRQSRC_SPI1RX (128+38) /* Vector: 31, " " */ +#define PIC32MX_IRQSRC_U1E (128+39) /* Vector: 32, UART1 */ +#define PIC32MX_IRQSRC_U1RX (128+40) /* Vector: 32, " " */ +#define PIC32MX_IRQSRC_U1TX (128+41) /* Vector: 32, " " */ +#define PIC32MX_IRQSRC_I2C1B (128+42) /* Vector: 33, I2C1 */ +#define PIC32MX_IRQSRC_I2C1S (128+43) /* Vector: 33, " " */ +#define PIC32MX_IRQSRC_I2C1M (128+44) /* Vector: 33, " " */ +#define PIC32MX_IRQSRC_CNA (128+45) /* Vector: 34, Input Change Interrupt */ +#define PIC32MX_IRQSRC_CNB (128+46) /* Vector: 34, Input Change Interrupt */ +#define PIC32MX_IRQSRC_CNC (128+47) /* Vector: 34, Input Change Interrupt */ +#define PIC32MX_IRQSRC_PMP (128+48) /* Vector: 35, Parallel Master Port */ +#define PIC32MX_IRQSRC_PMPE (128+49) /* Vector: 35, Parallel Master Port */ +#define PIC32MX_IRQSRC_SPI2E (128+50) /* Vector: 36, SPI2 */ +#define PIC32MX_IRQSRC_SPI2TX (128+51) /* Vector: 36, " " */ +#define PIC32MX_IRQSRC_SPI2RX (128+52) /* Vector: 36, " " */ +#define PIC32MX_IRQSRC_U2E (128+53) /* Vector: 37, UART2 */ +#define PIC32MX_IRQSRC_U2RX (128+54) /* Vector: 37, " " */ +#define PIC32MX_IRQSRC_U2TX (128+55) /* Vector: 37, " " */ +#define PIC32MX_IRQSRC_I2C2B (128+56) /* Vector: 38, I2C2 */ +#define PIC32MX_IRQSRC_I2C2S (128+57) /* Vector: 38, " " */ +#define PIC32MX_IRQSRC_I2C2M (128+58) /* Vector: 38, " " */ +#define PIC32MX_IRQSRC_CTMU (128+59) /* Vector: 39, CTMU */ +#define PIC32MX_IRQSRC_DMA0 (128+60) /* Vector: 40, DMA Channel 0 */ +#define PIC32MX_IRQSRC_DMA1 (128+61) /* Vector: 41, DMA Channel 1 */ +#define PIC32MX_IRQSRC_DMA2 (128+62) /* Vector: 42, DMA Channel 2 */ +#define PIC32MX_IRQSRC_DMA3 (128+63) /* Vector: 43, DMA Channel 3 */ +#define PIC32MX_IRQSRC1_LAST (128+63) + +#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST +#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC1_LAST + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H */ + diff --git a/nuttx/arch/mips/include/pic32mx/irq_3xx4xx.h b/nuttx/arch/mips/include/pic32mx/irq_3xx4xx.h index 36b1b2418..36b1b2418 100755..100644 --- a/nuttx/arch/mips/include/pic32mx/irq_3xx4xx.h +++ b/nuttx/arch/mips/include/pic32mx/irq_3xx4xx.h diff --git a/nuttx/arch/mips/include/pic32mx/irq_5xx6xx7xx.h b/nuttx/arch/mips/include/pic32mx/irq_5xx6xx7xx.h index e94079314..e94079314 100755..100644 --- a/nuttx/arch/mips/include/pic32mx/irq_5xx6xx7xx.h +++ b/nuttx/arch/mips/include/pic32mx/irq_5xx6xx7xx.h diff --git a/nuttx/arch/mips/src/common/up_etherstub.c b/nuttx/arch/mips/src/common/up_etherstub.c index 1781c8c80..1781c8c80 100755..100644 --- a/nuttx/arch/mips/src/common/up_etherstub.c +++ b/nuttx/arch/mips/src/common/up_etherstub.c diff --git a/nuttx/arch/mips/src/common/up_internal.h b/nuttx/arch/mips/src/common/up_internal.h index 62f9b8402..62f9b8402 100755..100644 --- a/nuttx/arch/mips/src/common/up_internal.h +++ b/nuttx/arch/mips/src/common/up_internal.h diff --git a/nuttx/arch/mips/src/mips32/mips32-memorymap.h b/nuttx/arch/mips/src/mips32/mips32-memorymap.h index f4a0fed7d..f4a0fed7d 100755..100644 --- a/nuttx/arch/mips/src/mips32/mips32-memorymap.h +++ b/nuttx/arch/mips/src/mips32/mips32-memorymap.h diff --git a/nuttx/arch/mips/src/mips32/up_blocktask.c b/nuttx/arch/mips/src/mips32/up_blocktask.c index 47fd4024b..47fd4024b 100755..100644 --- a/nuttx/arch/mips/src/mips32/up_blocktask.c +++ b/nuttx/arch/mips/src/mips32/up_blocktask.c diff --git a/nuttx/arch/mips/src/mips32/up_releasepending.c b/nuttx/arch/mips/src/mips32/up_releasepending.c index 978df0c7d..978df0c7d 100755..100644 --- a/nuttx/arch/mips/src/mips32/up_releasepending.c +++ b/nuttx/arch/mips/src/mips32/up_releasepending.c diff --git a/nuttx/arch/mips/src/mips32/up_reprioritizertr.c b/nuttx/arch/mips/src/mips32/up_reprioritizertr.c index 24e33693c..24e33693c 100755..100644 --- a/nuttx/arch/mips/src/mips32/up_reprioritizertr.c +++ b/nuttx/arch/mips/src/mips32/up_reprioritizertr.c diff --git a/nuttx/arch/mips/src/mips32/up_unblocktask.c b/nuttx/arch/mips/src/mips32/up_unblocktask.c index ba29cb736..ba29cb736 100755..100644 --- a/nuttx/arch/mips/src/mips32/up_unblocktask.c +++ b/nuttx/arch/mips/src/mips32/up_unblocktask.c diff --git a/nuttx/arch/mips/src/pic32mx/Kconfig b/nuttx/arch/mips/src/pic32mx/Kconfig index e4ced546b..9597e1eb1 100644 --- a/nuttx/arch/mips/src/pic32mx/Kconfig +++ b/nuttx/arch/mips/src/pic32mx/Kconfig @@ -9,6 +9,126 @@ choice prompt "PIC32MX chip selection" default ARCH_CHIP_PIC32MX460F512L +config ARCH_CHIP_PIC32MX110F016B + bool "PIC32MX110F016B" + ---help--- + Microchip PIC32MX110F016B (MIPS32) + +config ARCH_CHIP_PIC32MX110F016C + bool "PIC32MX110F016C" + ---help--- + Microchip PIC32MX110F016C (MIPS32) + +config ARCH_CHIP_PIC32MX110F016D + bool "PIC32MX110F016D" + ---help--- + Microchip PIC32MX110F016D (MIPS32) + +config ARCH_CHIP_PIC32MX120F032B + bool "PIC32MX120F032B" + ---help--- + Microchip PIC32MX120F032B (MIPS32) + +config ARCH_CHIP_PIC32MX120F032C + bool "PIC32MX120F032C" + ---help--- + Microchip PIC32MX120F032C (MIPS32) + +config ARCH_CHIP_PIC32MX120F032D + bool "PIC32MX120F032D" + ---help--- + Microchip PIC32MX120F032D (MIPS32) + +config ARCH_CHIP_PIC32MX130F064B + bool "PIC32MX130F064B" + ---help--- + Microchip PIC32MX130F064B (MIPS32) + +config ARCH_CHIP_PIC32MX130F064C + bool "PIC32MX130F064C" + ---help--- + Microchip PIC32MX130F064C (MIPS32) + +config ARCH_CHIP_PIC32MX130F064D + bool "PIC32MX130F064D" + ---help--- + Microchip PIC32MX130F064D (MIPS32) + +config ARCH_CHIP_PIC32MX150F128B + bool "PIC32MX150F128B" + ---help--- + Microchip PIC32MX150F128B (MIPS32) + +config ARCH_CHIP_PIC32MX150F128C + bool "PIC32MX150F128C" + ---help--- + Microchip PIC32MX150F128C (MIPS32) + +config ARCH_CHIP_PIC32MX150F128D + bool "PIC32MX150F128D" + ---help--- + Microchip PIC32MX150F128D (MIPS32) + +config ARCH_CHIP_PIC32MX210F016B + bool "PIC32MX210F016B" + ---help--- + Microchip PIC32MX210F016B (MIPS32) + +config ARCH_CHIP_PIC32MX210F016C + bool "PIC32MX210F016C" + ---help--- + Microchip PIC32MX210F016C (MIPS32) + +config ARCH_CHIP_PIC32MX210F016D + bool "PIC32MX210F016D" + ---help--- + Microchip PIC32MX210F016D (MIPS32) + +config ARCH_CHIP_PIC32MX220F032B + bool "PIC32MX220F032B" + ---help--- + Microchip PIC32MX220F032B (MIPS32) + +config ARCH_CHIP_PIC32MX220F032C + bool "PIC32MX220F032C" + ---help--- + Microchip PIC32MX220F032C (MIPS32) + +config ARCH_CHIP_PIC32MX220F032D + bool "PIC32MX220F032D" + ---help--- + Microchip PIC32MX220F032D (MIPS32) + +config ARCH_CHIP_PIC32MX230F064B + bool "PIC32MX230F064B" + ---help--- + Microchip PIC32MX230F064B (MIPS32) + +config ARCH_CHIP_PIC32MX230F064C + bool "PIC32MX230F064C" + ---help--- + Microchip PIC32MX230F064C (MIPS32) + +config ARCH_CHIP_PIC32MX230F064D + bool "PIC32MX230F064D" + ---help--- + Microchip PIC32MX230F064D (MIPS32) + +config ARCH_CHIP_PIC32MX250F128B + bool "PIC32MX250F128B" + ---help--- + Microchip PIC32MX250F128B (MIPS32) + +config ARCH_CHIP_PIC32MX250F128C + bool "PIC32MX250F128C" + ---help--- + Microchip PIC32MX250F128C (MIPS32) + +config ARCH_CHIP_PIC32MX250F128D + bool "PIC32MX250F128D" + ---help--- + Microchip PIC32MX250F128D (MIPS32) + config ARCH_CHIP_PIC32MX320F032H bool "PIC32MX320F032H" ---help--- @@ -236,10 +356,18 @@ config ARCH_CHIP_PIC32MX795F512L endchoice +config ARCH_CHIP_PIC322MX1 + bool + default y if ARCH_CHIP_PIC32MX110F016B || ARCH_CHIP_PIC32MX110F016C || ARCH_CHIP_PIC32MX110F016D || ARCH_CHIP_PIC32MX120F032B || ARCH_CHIP_PIC32MX120F032C || ARCH_CHIP_PIC32MX120F032D || ARCH_CHIP_PIC32MX130F064B || ARCH_CHIP_PIC32MX130F064C || ARCH_CHIP_PIC32MX130F064D || ARCH_CHIP_PIC32MX150F128B || ARCH_CHIP_PIC32MX150F128C || ARCH_CHIP_PIC32MX150F128D + +config ARCH_CHIP_PIC322MX2 + bool + default y if ARCH_CHIP_PIC32MX210F016B || ARCH_CHIP_PIC32MX210F016C || ARCH_CHIP_PIC32MX210F016D || ARCH_CHIP_PIC32MX220F032B || ARCH_CHIP_PIC32MX220F032C || ARCH_CHIP_PIC32MX220F032D || ARCH_CHIP_PIC32MX230F064B || ARCH_CHIP_PIC32MX230F064C || ARCH_CHIP_PIC32MX230F064D || ARCH_CHIP_PIC32MX250F128B || ARCH_CHIP_PIC32MX250F128C || ARCH_CHIP_PIC32MX250F128D + config ARCH_CHIP_PIC322MX3 bool default y if ARCH_CHIP_PIC32MX320F032H || ARCH_CHIP_PIC32MX320F064H || ARCH_CHIP_PIC32MX320F128H || ARCH_CHIP_PIC32MX320F128L || ARCH_CHIP_PIC32MX340F128H || ARCH_CHIP_PIC32MX340F256H || ARCH_CHIP_PIC32MX340F512H || ARCH_CHIP_PIC32MX340F128L || ARCH_CHIP_PIC32MX360F256L || ARCH_CHIP_PIC32MX360F512L - + config ARCH_CHIP_PIC322MX4 bool default y if ARCH_CHIP_PIC32MX420F032H || ARCH_CHIP_PIC32MX440F128H || ARCH_CHIP_PIC32MX440F128L || ARCH_CHIP_PIC32MX440F256H || ARCH_CHIP_PIC32MX440F512H || ARCH_CHIP_PIC32MX460F256L || ARCH_CHIP_PIC32MX460F512L @@ -434,6 +562,10 @@ config PIC32MX_ETHERNET bool "Ethernet" default n +config PIC32MX_CTMU + bool "Charge Time Measurement Unit (CMTU)" + default n + endmenu menu "PIC32MX Peripheral Interrupt Priorities" diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-config.h b/nuttx/arch/mips/src/pic32mx/pic32mx-config.h index 4ef88508d..fc2a40fb5 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-config.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-config.h @@ -55,7 +55,7 @@ /* Interrupt Priorities *************************************************************/ #ifndef CONFIG_PIC32MX_CTPRIO /* Core Timer Interrupt */ -# define CONFIG_PIC32MX_CTPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_CTPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_CTPRIO < 4 # error "CONFIG_PIC32MX_CTPRIO is too small" @@ -65,7 +65,7 @@ #endif #ifndef CONFIG_PIC32MX_CS0PRIO /* Core Software Interrupt 0 */ -# define CONFIG_PIC32MX_CS0PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_CS0PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_CS0PRIO < 4 # error "CONFIG_PIC32MX_CS0PRIO is too small" @@ -75,7 +75,7 @@ #endif #ifndef CONFIG_PIC32MX_CS1PRIO /* Core Software Interrupt 1 */ -# define CONFIG_PIC32MX_CS1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_CS1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_CS1PRIO < 4 # error "CONFIG_PIC32MX_CS1PRIO is too small" @@ -85,7 +85,7 @@ #endif #ifndef CONFIG_PIC32MX_INT0PRIO /* External interrupt 0 */ -# define CONFIG_PIC32MX_INT0PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_INT0PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_INT0PRIO < 4 # error "CONFIG_PIC32MX_INT0PRIO is too small" @@ -95,7 +95,7 @@ #endif #ifndef CONFIG_PIC32MX_INT1PRIO /* External interrupt 1 */ -# define CONFIG_PIC32MX_INT1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_INT1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_INT1PRIO < 4 # error "CONFIG_PIC32MX_INT1PRIO is too small" @@ -105,7 +105,7 @@ #endif #ifndef CONFIG_PIC32MX_INT2PRIO /* External interrupt 2 */ -# define CONFIG_PIC32MX_INT2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_INT2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_INT2PRIO < 4 # error "CONFIG_PIC32MX_INT2PRIO is too small" @@ -115,7 +115,7 @@ #endif #ifndef CONFIG_PIC32MX_INT3PRIO /* External interrupt 3 */ -# define CONFIG_PIC32MX_INT3PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_INT3PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_INT3PRIO < 4 # error "CONFIG_PIC32MX_INT3PRIO is too small" @@ -125,7 +125,7 @@ #endif #ifndef CONFIG_PIC32MX_INT4PRIO /* External interrupt 4 */ -# define CONFIG_PIC32MX_INT4PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_INT4PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_INT4PRIO < 4 # error "CONFIG_PIC32MX_INT4PRIO is too small" @@ -135,7 +135,7 @@ #endif #ifndef CONFIG_PIC32MX_FSCMPRIO /* Fail-Safe Clock Monitor */ -# define CONFIG_PIC32MX_FSCMPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_FSCMPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_FSCMPRIO < 4 # error "CONFIG_PIC32MX_FSCMPRIO is too small" @@ -145,7 +145,7 @@ #endif #ifndef CONFIG_PIC32MX_T1PRIO /* Timer 1 (System timer) priority */ -# define CONFIG_PIC32MX_T1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_T1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_T1PRIO < 4 # error "CONFIG_PIC32MX_T1PRIO is too small" @@ -155,7 +155,7 @@ #endif #ifndef CONFIG_PIC32MX_T2PRIO /* Timer 2 priority */ -# define CONFIG_PIC32MX_T2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_T2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_T2PRIO < 4 # error "CONFIG_PIC32MX_T2PRIO is too small" @@ -165,7 +165,7 @@ #endif #ifndef CONFIG_PIC32MX_T3PRIO /* Timer 3 priority */ -# define CONFIG_PIC32MX_T3PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_T3PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_T3PRIO < 4 # error "CONFIG_PIC32MX_T3PRIO is too small" @@ -175,7 +175,7 @@ #endif #ifndef CONFIG_PIC32MX_T4PRIO /* Timer 4 priority */ -# define CONFIG_PIC32MX_T4PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_T4PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_T4PRIO < 4 # error "CONFIG_PIC32MX_T4PRIO is too small" @@ -185,7 +185,7 @@ #endif #ifndef CONFIG_PIC32MX_T5PRIO /* Timer 5 priority */ -# define CONFIG_PIC32MX_T5PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_T5PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_T5PRIO < 4 # error "CONFIG_PIC32MX_T5PRIO is too small" @@ -195,7 +195,7 @@ #endif #ifndef CONFIG_PIC32MX_IC1PRIO /* Input Capture 1 */ -# define CONFIG_PIC32MX_IC1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_IC1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_IC1PRIO < 4 # error "CONFIG_PIC32MX_IC1PRIO is too small" @@ -205,7 +205,7 @@ #endif #ifndef CONFIG_PIC32MX_IC2PRIO /* Input Capture 2 */ -# define CONFIG_PIC32MX_IC2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_IC2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_IC2PRIO < 4 # error "CONFIG_PIC32MX_IC2PRIO is too small" @@ -215,7 +215,7 @@ #endif #ifndef CONFIG_PIC32MX_IC3PRIO /* Input Capture 3 */ -# define CONFIG_PIC32MX_IC3PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_IC3PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_IC3PRIO < 4 # error "CONFIG_PIC32MX_IC3PRIO is too small" @@ -225,7 +225,7 @@ #endif #ifndef CONFIG_PIC32MX_IC4PRIO /* Input Capture 4 */ -# define CONFIG_PIC32MX_IC4PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_IC4PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_IC4PRIO < 4 # error "CONFIG_PIC32MX_IC4PRIO is too small" @@ -235,7 +235,7 @@ #endif #ifndef CONFIG_PIC32MX_IC5PRIO /* Input Capture 5 */ -# define CONFIG_PIC32MX_IC5PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_IC5PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_IC5PRIO < 4 # error "CONFIG_PIC32MX_IC5PRIO is too small" @@ -245,7 +245,7 @@ #endif #ifndef CONFIG_PIC32MX_OC1PRIO /* Output Compare 1 */ -# define CONFIG_PIC32MX_OC1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_OC1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_OC1PRIO < 4 # error "CONFIG_PIC32MX_OC1PRIO is too small" @@ -255,7 +255,7 @@ #endif #ifndef CONFIG_PIC32MX_OC2PRIO /* Output Compare 2 */ -# define CONFIG_PIC32MX_OC2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_OC2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_OC2PRIO < 4 # error "CONFIG_PIC32MX_OC2PRIO is too small" @@ -265,7 +265,7 @@ #endif #ifndef CONFIG_PIC32MX_OC3PRIO /* Output Compare 3 */ -# define CONFIG_PIC32MX_OC3PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_OC3PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_OC3PRIO < 4 # error "CONFIG_PIC32MX_OC3PRIO is too small" @@ -275,7 +275,7 @@ #endif #ifndef CONFIG_PIC32MX_OC4PRIO /* Output Compare 4 */ -# define CONFIG_PIC32MX_OC4PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_OC4PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_OC4PRIO < 4 # error "CONFIG_PIC32MX_OC4PRIO is too small" @@ -285,7 +285,7 @@ #endif #ifndef CONFIG_PIC32MX_OC5PRIO /* Output Compare 5 */ -# define CONFIG_PIC32MX_OC5PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_OC5PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_OC5PRIO < 4 # error "CONFIG_PIC32MX_OC5PRIO is too small" @@ -295,7 +295,7 @@ #endif #ifndef CONFIG_PIC32MX_I2C1PRIO /* I2C 1 */ -# define CONFIG_PIC32MX_I2C1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_I2C1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_I2C1PRIO < 4 # error "CONFIG_PIC32MX_I2C1PRIO is too small" @@ -305,7 +305,7 @@ #endif #ifndef CONFIG_PIC32MX_I2C2PRIO /* I2C 2 */ -# define CONFIG_PIC32MX_I2C2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_I2C2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_I2C2PRIO < 4 # error "CONFIG_PIC32MX_I2C2PRIO is too small" @@ -315,7 +315,7 @@ #endif #ifndef CONFIG_PIC32MX_SPI1PRIO /* SPI 1 */ -# define CONFIG_PIC32MX_SPI1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_SPI1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_SPI1PRIO < 4 # error "CONFIG_PIC32MX_SPI1PRIO is too small" @@ -325,7 +325,7 @@ #endif #ifndef CONFIG_PIC32MX_SPI2PRIO /* SPI 2 */ -# define CONFIG_PIC32MX_SPI2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_SPI2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_SPI2PRIO < 4 # error "CONFIG_PIC32MX_SPI2PRIO is too small" @@ -335,7 +335,7 @@ #endif #ifndef CONFIG_PIC32MX_UART1PRIO /* UART 1 */ -# define CONFIG_PIC32MX_UART1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_UART1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_UART1PRIO < 4 # error "CONFIG_PIC32MX_UART1PRIO is too small" @@ -345,7 +345,7 @@ #endif #ifndef CONFIG_PIC32MX_UART2PRIO /* UART 2 */ -# define CONFIG_PIC32MX_UART2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_UART2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_UART2PRIO < 4 # error "CONFIG_PIC32MX_UART2PRIO is too small" @@ -355,7 +355,7 @@ #endif #ifndef CONFIG_PIC32MX_CNPRIO /* Input Change Interrupt */ -# define CONFIG_PIC32MX_CNPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_CNPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_CNPRIO < 4 # error "CONFIG_PIC32MX_CNPRIO is too small" @@ -365,7 +365,7 @@ #endif #ifndef CONFIG_PIC32MX_ADCPRIO /* ADC1 Convert Done */ -# define CONFIG_PIC32MX_ADCPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_ADCPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_ADCPRIO < 4 # error "CONFIG_PIC32MX_ADCPRIO is too small" @@ -375,7 +375,7 @@ #endif #ifndef CONFIG_PIC32MX_PMPPRIO /* Parallel Master Port */ -# define CONFIG_PIC32MX_PMPPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_PMPPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_PMPPRIO < 4 # error "CONFIG_PIC32MX_PMPPRIO is too small" @@ -385,7 +385,7 @@ #endif #ifndef CONFIG_PIC32MX_CM1PRIO /* Comparator 1 */ -# define CONFIG_PIC32MX_CM1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_CM1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_CM1PRIO < 4 # error "CONFIG_PIC32MX_CM1PRIO is too small" @@ -395,7 +395,7 @@ #endif #ifndef CONFIG_PIC32MX_CM2PRIO /* Comparator 2 */ -# define CONFIG_PIC32MX_CM2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_CM2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_CM2PRIO < 4 # error "CONFIG_PIC32MX_CM2PRIO is too small" @@ -405,7 +405,7 @@ #endif #ifndef CONFIG_PIC32MX_FSCMPRIO /* Fail-Safe Clock Monitor */ -# define CONFIG_PIC32MX_FSCMPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_FSCMPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_FSCMPRIO < 4 # error "CONFIG_PIC32MX_FSCMPRIO is too small" @@ -415,7 +415,7 @@ #endif #ifndef CONFIG_PIC32MX_RTCCPRIO /* Real-Time Clock and Calendar */ -# define CONFIG_PIC32MX_RTCCPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_RTCCPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_RTCCPRIO < 4 # error "CONFIG_PIC32MX_RTCCPRIO is too small" @@ -425,7 +425,7 @@ #endif #ifndef CONFIG_PIC32MX_DMA0PRIO /* DMA Channel 0 */ -# define CONFIG_PIC32MX_DMA0PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_DMA0PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_DMA0PRIO < 4 # error "CONFIG_PIC32MX_DMA0PRIO is too small" @@ -435,7 +435,7 @@ #endif #ifndef CONFIG_PIC32MX_DMA1PRIO /* DMA Channel 1 */ -# define CONFIG_PIC32MX_DMA1PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_DMA1PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_DMA1PRIO < 4 # error "CONFIG_PIC32MX_DMA1PRIO is too small" @@ -445,7 +445,7 @@ #endif #ifndef CONFIG_PIC32MX_DMA2PRIO /* DMA Channel 2 */ -# define CONFIG_PIC32MX_DMA2PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_DMA2PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_DMA2PRIO < 4 # error "CONFIG_PIC32MX_DMA2PRIO is too small" @@ -455,7 +455,7 @@ #endif #ifndef CONFIG_PIC32MX_DMA3PRIO /* DMA Channel 3 */ -# define CONFIG_PIC32MX_DMA3PRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_DMA3PRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_DMA3PRIO < 4 # error "CONFIG_PIC32MX_DMA3PRIO is too small" @@ -465,7 +465,7 @@ #endif #ifndef CONFIG_PIC32MX_FCEPRIO /* Flash Control Event */ -# define CONFIG_PIC32MX_FCEPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_FCEPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_FCEPRIO < 4 # error "CONFIG_PIC32MX_FCEPRIO is too small" @@ -475,7 +475,7 @@ #endif #ifndef CONFIG_PIC32MX_USBPRIO /* USB */ -# define CONFIG_PIC32MX_USBPRIO (INT_ICP_MID_PRIORITY << 2) +# define CONFIG_PIC32MX_USBPRIO (INT_IPC_MID_PRIORITY << 2) #endif #if CONFIG_PIC32MX_USBPRIO < 4 # error "CONFIG_PIC32MX_USBPRIO is too small" @@ -602,7 +602,7 @@ #endif #ifndef CONFIG_PIC32MX_SRSSEL /* Shadow register interrupt priority */ -# define CONFIG_PIC32MX_SRSSEL INT_ICP_MIN_PRIORITY +# define CONFIG_PIC32MX_SRSSEL INT_IPC_MIN_PRIORITY #endif /* Unless overridden in the .config file, all pins are in the default setting */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h b/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h index e7224747f..410286d74 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-devcfg.h @@ -1,237 +1,256 @@ -/****************************************************************************
- * arch/mips/src/pic32mx/pic32mx-devcfg.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
-/****************************************************************************
- * Pre-Processor Definitions
- ****************************************************************************/
-/* Register Offsets *********************************************************/
-
-#define PIC32MX_DEVCFG3_OFFSET 0x0000 /* Device configuration word 3 */
-#define PIC32MX_DEVCFG2_OFFSET 0x0004 /* Device configuration word 2 */
-#define PIC32MX_DEVCFG1_OFFSET 0x0008 /* Device configuration word 1 */
-#define PIC32MX_DEVCFG0_OFFSET 0x000c /* Device configuration word 0 */
-
-/* Register Addresses *******************************************************/
-
-#define PIC32MX_DEVCFG3 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG3_OFFSET)
-#define PIC32MX_DEVCFG2 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG2_OFFSET)
-#define PIC32MX_DEVCFG1 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG1_OFFSET)
-#define PIC32MX_DEVCFG0 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG0_OFFSET)
-
-/* Register Bit-Field Definitions *******************************************/
-
-/* Device configuration word 3 */
-
-#define DEVCFG3_USERID_SHIFT (0) /* Bits 0-15: User-defined, readable via ICSP™ and JTAG */
-#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT)
-#define DEVCFG3_FSRSSEL_SHIFT (16) /* Bits 16-18: SRS select */
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-# define DEVCFG3_UNUSED 0xffff0000 /* Bits 16-31 */
-
-#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define DEVCFG3_FSRSSEL_MASK (7 << DEVCFG3_FSRSSEL_SHIFT)
-# define DEVCFG3_FMIIEN (1 << 24) /* Bit 24: Ethernet MII enable */
-# define DEVCFG3_FETHIO (1 << 25) /* Bit 25: Ethernet I/O pin selection */
-# define DEVCFG3_FCANIO (1 << 26) /* Bit 26: CAN I/O pin selection */
-# define DEVCFG3_FSCM1IO (1 << 29) /* Bit 29: SCM1 pin C selection */
-# define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID selection */
-# define DEVCFG3_FVBUSIO (1 << 31) /* Bit 31: USB VBUSON selection */
-# define DEVCFG3_UNUSED 0x18f80000 /* Bits 19-23, 27-28 */
-
-#endif
-
-/* Device configuration word 2 */
-
-#define DEVCFG2_FPLLIDIV_SHIFT (0) /* Bits 0-2: PLL input divider value */
-#define DEVCFG2_FPLLIDIV_MASK (7 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV1 (0 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV2 (1 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV3 (2 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV4 (3 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV5 (4 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV6 (5 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV10 (6 << DEVCFG2_FPLLIDIV_SHIFT)
-# define DEVCFG2_FPLLIDIV_DIV12 (7 << DEVCFG2_FPLLIDIV_SHIFT)
-#define DEVCFG2_FPLLMULT_SHIFT (4) /* Bits 4-6: Initial PLL multiplier value */
-#define DEVCFG2_FPLLMULT_MASK (7 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL15 (0 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL16 (1 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL17 (2 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL18 (3 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL19 (4 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL20 (5 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL21 (6 << DEVCFG2_FPLLMULT_SHIFT)
-# define DEVCFG2_FPLLMULT_MUL24 (7 << DEVCFG2_FPLLMULT_SHIFT)
-#define DEVCFG2_FUPLLIDIV_SHIFT (8) /* Bits 8-10: PLL input divider */
-#define DEVCFG2_FUPLLIDIV_MASK (7 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV1 (0 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV2 (1 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV3 (2 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV4 (3 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV5 (4 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV6 (5 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV10 (6 << DEVCFG2_FUPLLIDIV_SHIFT)
-# define DEVCFG2_FUPLLIDIV_DIV12 (7 << DEVCFG2_FUPLLIDIV_SHIFT)
-#define DEVCFG2_FUPLLEN (1 << 15) /* Bit 15: USB PLL enable */
-#define DEVCFG2_FPLLODIV_SHIFT (16) /* Bits 16-18: Default postscaler for PLL bits */
-#define DEVCFG2_FPLLODIV_MASK (7 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV1 (0 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV2 (1 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV4 (2 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV8 (3 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV16 (4 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV32 (5 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV64 (6 << DEVCFG2_FPLLODIV_SHIFT)
-# define DEVCFG2_FPLLODIV_DIV256 (7 << DEVCFG2_FPLLODIV_SHIFT)
-#define DEVCFG2_UNUSED 0xfff87888 /* Bits 3, 7, 11-14, 19-31 */
-
-/* Device configuration word 1 */
-
-#define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator selection */
-#define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT)
-# define DEVCFG1_FNOSC_FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC oscillator */
-# define DEVCFG1_FNOSC_FRCPLL (1 << DEVCFG1_FNOSC_SHIFT) /* FRC w/PLL module */
-# define DEVCFG1_FNOSC_POSC (2 << DEVCFG1_FNOSC_SHIFT) /* Primary oscillator */
-# define DEVCFG1_FNOSC_POSCPLL (3 << DEVCFG1_FNOSC_SHIFT) /* Primary oscillator w/PLL */
-# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* Secondary oscillator */
-# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* Low power RC oscillator */
-# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC oscillator with FRCDIV */
-#define DEVCFG1_FSOSCEN (1 << 5) /* Bit 5: Secondary oscillator (sosc) enable bit */
-#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal external switch over */
-#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary oscillator (posc) configuration */
-#define DEVCFG1_POSCMOD_MASK (3 << DEVCFG1_POSCMOD_SHIFT)
-# define DEVCFG1_POSCMOD_EC (0 << DEVCFG1_POSCMOD_SHIFT) /* EC mode */
-# define DEVCFG1_POSCMOD_XT (1 << DEVCFG1_POSCMOD_SHIFT) /* XT mode */
-# define DEVCFG1_POSCMOD_HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS mode */
-# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* Primary Oscillator disabled */
-#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO (clock-out) enable configuration */
-#define DEVCFG1_FPBDIV_SHIFT (12) /* Bits 12-13: Peripheral bus clock divisor default value */
-#define DEVCFG1_FPBDIV_MASK (3 << DEVCFG1_FPBDIV_SHIFT)
-# define DEVCFG1_FPBDIV_DIV1 (0 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/1 */
-# define DEVCFG1_FPBDIV_DIV2 (1 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/2 */
-# define DEVCFG1_FPBDIV_DIV4 (2 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/4 */
-# define DEVCFG1_FPBDIV_DIV8 (3 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK /8 */
-#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock switching and monitor selection configuration */
-#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT)
-# define DEVCFG1_FCKSM_BOTH (0 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are enabled */
-# define DEVCFG1_FCKSM_CSONLY (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching is enabled, FSCM is disabled */
-# define DEVCFG1_FCKSM_NONE (3 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are disabled */
-#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: WDT postscaler select */
-#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT)
-# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */
-# define DEVCFG1_WDTPS_2 (1 << DEVCFG1_WDTPS_SHIFT) /* 1:2 */
-# define DEVCFG1_WDTPS_4 (2 << DEVCFG1_WDTPS_SHIFT) /* 1:4 */
-# define DEVCFG1_WDTPS_8 (3 << DEVCFG1_WDTPS_SHIFT) /* 1:8 */
-# define DEVCFG1_WDTPS_16 (4 << DEVCFG1_WDTPS_SHIFT) /* 1:16 */
-# define DEVCFG1_WDTPS_32 (5 << DEVCFG1_WDTPS_SHIFT) /* 1:32 */
-# define DEVCFG1_WDTPS_64 (6 << DEVCFG1_WDTPS_SHIFT) /* 1:64 */
-# define DEVCFG1_WDTPS_128 (7 << DEVCFG1_WDTPS_SHIFT) /* 1:128 */
-# define DEVCFG1_WDTPS_256 (8 << DEVCFG1_WDTPS_SHIFT) /* 1:256 */
-# define DEVCFG1_WDTPS_512 (9 << DEVCFG1_WDTPS_SHIFT) /* 1:512 */
-# define DEVCFG1_WDTPS_1024 (10 << DEVCFG1_WDTPS_SHIFT) /* 1:1024 */
-# define DEVCFG1_WDTPS_2048 (11 << DEVCFG1_WDTPS_SHIFT) /* 1:2048 */
-# define DEVCFG1_WDTPS_4096 (12 << DEVCFG1_WDTPS_SHIFT) /* 1:4096 */
-# define DEVCFG1_WDTPS_8192 (13 << DEVCFG1_WDTPS_SHIFT) /* 1:8192 */
-# define DEVCFG1_WDTPS_16384 (14 << DEVCFG1_WDTPS_SHIFT) /* 1:16384 */
-# define DEVCFG1_WDTPS_32768 (15 << DEVCFG1_WDTPS_SHIFT) /* 1:32768 */
-# define DEVCFG1_WDTPS_65536 (16 << DEVCFG1_WDTPS_SHIFT) /* 1:65536 */
-# define DEVCFG1_WDTPS_131072 (17 << DEVCFG1_WDTPS_SHIFT) /* 1:131072 */
-# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
-# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
-# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
-#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Windowed watchdog timer enable */
-#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: WDT enable */
-#define DEVCFG1_UNUSED 0xff200858 /* Bits 3-4, 6, 11, 21, 24-31 */
-
-/* Device configuration word 0 */
-
-#define PWP_CODE(a) (((~((a) >> 12)) - 1) & 0xff)
-
-#define DEVCFG0_DEBUG_SHIFT (0) /* Bits 0-1: Background debugger enable */
-#define DEVCFG0_DEBUG_MASK (3 << DEVCFG0_DEBUG_SHIFT)
-# define DEVCFG0_DEBUG_ENABLED (2 << DEVCFG0_DEBUG_SHIFT)
-# define DEVCFG0_DEBUG_DISABLED (3 << DEVCFG0_DEBUG_SHIFT)
-#define DEVCFG0_ICESEL (1 << 3) /* Bit 3: ICE/debugger channel select */
-#define DEVCFG0_PWP_SHIFT (12) /* Bits 12-19: Program flash write-protect */
-#define DEVCFG0_PWP_MASK (0xff << DEVCFG0_PWP_SHIFT)
-# define DEVCFG0_PWP_DISABLE (0xff << DEVCFG0_PWP_SHIFT)
-# define DEVCFG0_PWP(code) ((code) << DEVCFG0_PWP_SHIFT) /* See PWP_CODE above */
-#define DEVCFG0_BWP (1 << 24) /* Bit 24: Boot flash write-protect */
-#define DEVCFG0_CP (1 << 28) /* Bit 28: Code-protect */
-#define DEVCFG0_SIGN (1 << 31) /* Bit 31: Signature */
-#define DEVCFG0_UNUSED 0x6ef00ff0 /* Bits 4-11, 20-23, 25-27, 29-30 */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H */
+/**************************************************************************** + * arch/mips/src/pic32mx/pic32mx-devcfg.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Register Offsets *********************************************************/ + +#define PIC32MX_DEVCFG3_OFFSET 0x0000 /* Device configuration word 3 */ +#define PIC32MX_DEVCFG2_OFFSET 0x0004 /* Device configuration word 2 */ +#define PIC32MX_DEVCFG1_OFFSET 0x0008 /* Device configuration word 1 */ +#define PIC32MX_DEVCFG0_OFFSET 0x000c /* Device configuration word 0 */ + +/* Register Addresses *******************************************************/ + +#define PIC32MX_DEVCFG3 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG3_OFFSET) +#define PIC32MX_DEVCFG2 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG2_OFFSET) +#define PIC32MX_DEVCFG1 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG1_OFFSET) +#define PIC32MX_DEVCFG0 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG0_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* Device configuration word 3 */ + +#define DEVCFG3_USERID_SHIFT (0) /* Bits 0-15: User-defined, readable via ICSP™ and JTAG */ +#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT) + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +# define DEVCFG3_PMDL1WAY (1 << 28) /* Bit 28: Peripheral Module Disable Configuration */ +# define DEVCFG3_IOL1WAY (1 << 29) /* Bit 29: Peripheral Pin Select Configuration */ +# define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID selection */ +# define DEVCFG3_FVBUSIO (1 << 31) /* Bit 31: USB VBUSON selection */ +# define DEVCFG3_UNUSED 0x0fff0000 /* Bits 16-28 */ + +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +# define DEVCFG3_UNUSED 0xffff0000 /* Bits 16-31 */ + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define DEVCFG3_FSRSSEL_SHIFT (16) /* Bits 16-18: SRS select */ +# define DEVCFG3_FSRSSEL_MASK (7 << DEVCFG3_FSRSSEL_SHIFT) +# define DEVCFG3_FMIIEN (1 << 24) /* Bit 24: Ethernet MII enable */ +# define DEVCFG3_FETHIO (1 << 25) /* Bit 25: Ethernet I/O pin selection */ +# define DEVCFG3_FCANIO (1 << 26) /* Bit 26: CAN I/O pin selection */ +# define DEVCFG3_FSCM1IO (1 << 29) /* Bit 29: SCM1 pin C selection */ +# define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID selection */ +# define DEVCFG3_FVBUSIO (1 << 31) /* Bit 31: USB VBUSON selection */ +# define DEVCFG3_UNUSED 0x18f80000 /* Bits 19-23, 27-28 */ + +#endif + +/* Device configuration word 2 */ + +#define DEVCFG2_FPLLIDIV_SHIFT (0) /* Bits 0-2: PLL input divider value */ +#define DEVCFG2_FPLLIDIV_MASK (7 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV1 (0 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV2 (1 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV3 (2 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV4 (3 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV5 (4 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV6 (5 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV10 (6 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV_DIV12 (7 << DEVCFG2_FPLLIDIV_SHIFT) +#define DEVCFG2_FPLLMULT_SHIFT (4) /* Bits 4-6: Initial PLL multiplier value */ +#define DEVCFG2_FPLLMULT_MASK (7 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL15 (0 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL16 (1 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL17 (2 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL18 (3 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL19 (4 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL20 (5 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL21 (6 << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT_MUL24 (7 << DEVCFG2_FPLLMULT_SHIFT) +#define DEVCFG2_FUPLLIDIV_SHIFT (8) /* Bits 8-10: PLL input divider */ +#define DEVCFG2_FUPLLIDIV_MASK (7 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV1 (0 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV2 (1 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV3 (2 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV4 (3 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV5 (4 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV6 (5 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV10 (6 << DEVCFG2_FUPLLIDIV_SHIFT) +# define DEVCFG2_FUPLLIDIV_DIV12 (7 << DEVCFG2_FUPLLIDIV_SHIFT) +#define DEVCFG2_FUPLLEN (1 << 15) /* Bit 15: USB PLL enable */ +#define DEVCFG2_FPLLODIV_SHIFT (16) /* Bits 16-18: Default postscaler for PLL bits */ +#define DEVCFG2_FPLLODIV_MASK (7 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV1 (0 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV2 (1 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV4 (2 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV8 (3 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV16 (4 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV32 (5 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV64 (6 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_DIV256 (7 << DEVCFG2_FPLLODIV_SHIFT) +#define DEVCFG2_UNUSED 0xfff87888 /* Bits 3, 7, 11-14, 19-31 */ + +/* Device configuration word 1 */ + +#define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator selection */ +#define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT) +# define DEVCFG1_FNOSC_FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC oscillator */ +# define DEVCFG1_FNOSC_FRCPLL (1 << DEVCFG1_FNOSC_SHIFT) /* FRC w/PLL module */ +# define DEVCFG1_FNOSC_POSC (2 << DEVCFG1_FNOSC_SHIFT) /* Primary oscillator */ +# define DEVCFG1_FNOSC_POSCPLL (3 << DEVCFG1_FNOSC_SHIFT) /* Primary oscillator w/PLL */ +# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* Secondary oscillator */ +# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* Low power RC oscillator */ +# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC oscillator with FRCDIV */ +#define DEVCFG1_FSOSCEN (1 << 5) /* Bit 5: Secondary oscillator (sosc) enable bit */ +#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal external switch over */ +#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary oscillator (posc) configuration */ +#define DEVCFG1_POSCMOD_MASK (3 << DEVCFG1_POSCMOD_SHIFT) +# define DEVCFG1_POSCMOD_EC (0 << DEVCFG1_POSCMOD_SHIFT) /* EC mode */ +# define DEVCFG1_POSCMOD_XT (1 << DEVCFG1_POSCMOD_SHIFT) /* XT mode */ +# define DEVCFG1_POSCMOD_HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS mode */ +# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* Primary Oscillator disabled */ +#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO (clock-out) enable configuration */ +#define DEVCFG1_FPBDIV_SHIFT (12) /* Bits 12-13: Peripheral bus clock divisor default value */ +#define DEVCFG1_FPBDIV_MASK (3 << DEVCFG1_FPBDIV_SHIFT) +# define DEVCFG1_FPBDIV_DIV1 (0 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/1 */ +# define DEVCFG1_FPBDIV_DIV2 (1 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/2 */ +# define DEVCFG1_FPBDIV_DIV4 (2 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/4 */ +# define DEVCFG1_FPBDIV_DIV8 (3 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK /8 */ +#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock switching and monitor selection configuration */ +#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT) +# define DEVCFG1_FCKSM_BOTH (0 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are enabled */ +# define DEVCFG1_FCKSM_CSONLY (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching is enabled, FSCM is disabled */ +# define DEVCFG1_FCKSM_NONE (3 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are disabled */ +#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: WDT postscaler select */ +#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT) +# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */ +# define DEVCFG1_WDTPS_2 (1 << DEVCFG1_WDTPS_SHIFT) /* 1:2 */ +# define DEVCFG1_WDTPS_4 (2 << DEVCFG1_WDTPS_SHIFT) /* 1:4 */ +# define DEVCFG1_WDTPS_8 (3 << DEVCFG1_WDTPS_SHIFT) /* 1:8 */ +# define DEVCFG1_WDTPS_16 (4 << DEVCFG1_WDTPS_SHIFT) /* 1:16 */ +# define DEVCFG1_WDTPS_32 (5 << DEVCFG1_WDTPS_SHIFT) /* 1:32 */ +# define DEVCFG1_WDTPS_64 (6 << DEVCFG1_WDTPS_SHIFT) /* 1:64 */ +# define DEVCFG1_WDTPS_128 (7 << DEVCFG1_WDTPS_SHIFT) /* 1:128 */ +# define DEVCFG1_WDTPS_256 (8 << DEVCFG1_WDTPS_SHIFT) /* 1:256 */ +# define DEVCFG1_WDTPS_512 (9 << DEVCFG1_WDTPS_SHIFT) /* 1:512 */ +# define DEVCFG1_WDTPS_1024 (10 << DEVCFG1_WDTPS_SHIFT) /* 1:1024 */ +# define DEVCFG1_WDTPS_2048 (11 << DEVCFG1_WDTPS_SHIFT) /* 1:2048 */ +# define DEVCFG1_WDTPS_4096 (12 << DEVCFG1_WDTPS_SHIFT) /* 1:4096 */ +# define DEVCFG1_WDTPS_8192 (13 << DEVCFG1_WDTPS_SHIFT) /* 1:8192 */ +# define DEVCFG1_WDTPS_16384 (14 << DEVCFG1_WDTPS_SHIFT) /* 1:16384 */ +# define DEVCFG1_WDTPS_32768 (15 << DEVCFG1_WDTPS_SHIFT) /* 1:32768 */ +# define DEVCFG1_WDTPS_65536 (16 << DEVCFG1_WDTPS_SHIFT) /* 1:65536 */ +# define DEVCFG1_WDTPS_131072 (17 << DEVCFG1_WDTPS_SHIFT) /* 1:131072 */ +# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */ +# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */ +# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */ +#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Windowed watchdog timer enable */ +#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: WDT enable */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */ +# define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT) +# define DEVCFG1_FWDTWINSZ_25 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* 25% */ +# define DEVCFG1_FWDTWINSZ_37p5 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* 37.5% */ +# define DEVCFG1_FWDTWINSZ_50 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* 50% */ +# define DEVCFG1_FWDTWINSZ_75 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* 75% */ +# define DEVCFG1_UNUSED 0xfc200858 /* Bits 3-4, 6, 11, 21, 26-31 */ +#else +# define DEVCFG1_UNUSED 0xff200858 /* Bits 3-4, 6, 11, 21, 24-31 */ +#endif + +/* Device configuration word 0 */ + +#define PWP_CODE(a) (((~((a) >> 12)) - 1) & 0xff) + +#define DEVCFG0_DEBUG_SHIFT (0) /* Bits 0-1: Background debugger enable */ +#define DEVCFG0_DEBUG_MASK (3 << DEVCFG0_DEBUG_SHIFT) +# define DEVCFG0_DEBUG_ENABLED (2 << DEVCFG0_DEBUG_SHIFT) +# define DEVCFG0_DEBUG_DISABLED (3 << DEVCFG0_DEBUG_SHIFT) +#define DEVCFG0_ICESEL (1 << 3) /* Bit 3: ICE/debugger channel select */ +#define DEVCFG0_PWP_SHIFT (12) /* Bits 12-19: Program flash write-protect */ +#define DEVCFG0_PWP_MASK (0xff << DEVCFG0_PWP_SHIFT) +# define DEVCFG0_PWP_DISABLE (0xff << DEVCFG0_PWP_SHIFT) +# define DEVCFG0_PWP(code) ((code) << DEVCFG0_PWP_SHIFT) /* See PWP_CODE above */ +#define DEVCFG0_BWP (1 << 24) /* Bit 24: Boot flash write-protect */ +#define DEVCFG0_CP (1 << 28) /* Bit 28: Code-protect */ +#define DEVCFG0_SIGN (1 << 31) /* Bit 31: Signature */ +#define DEVCFG0_UNUSED 0x6ef00ff0 /* Bits 4-11, 20-23, 25-27, 29-30 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h b/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h index fd8af3087..ae96c35d7 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-dma.h @@ -1,687 +1,696 @@ -/********************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-dma.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H
-
-/********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "pic32mx-memorymap.h"
-
-#if CHIP_NDMACH > 0
-
-/********************************************************************************************
- * Pre-Processor Definitions
- ********************************************************************************************/
-/* Register Offsets *************************************************************************/
-/* Global DMA Registers */
-
-#define PIC32MX_DMA_CON_OFFSET 0x0000 /* DMA Controller Control Register */
-#define PIC32MX_DMA_CONCLR_OFFSET 0x0004 /* DMA Controller Control Clear Register */
-#define PIC32MX_DMA_CONSET_OFFSET 0x0008 /* DMA Controller Control Set Register */
-#define PIC32MX_DMA_CONINV_OFFSET 0x000c /* DMA Controller Control Invert Register */
-#define PIC32MX_DMA_STAT_OFFSET 0x0010 /* DMA Status Register */
-#define PIC32MX_DMA_ADD_OFFSETR 0x0020 /* DMA Address Register */
-#define PIC32MX_DMA_CRCCON_OFFSET 0x0030 /* DMA CRC Control Register */
-#define PIC32MX_DMA_CRCCONCLR_OFFSET 0x0034 /* DMA CRC Control Clear Register */
-#define PIC32MX_DMA_CRCCONSET_OFFSET 0x0038 /* DMA CRC Control Set Register */
-#define PIC32MX_DMA_CRCCONINV_OFFSET 0x003c /* DMA CRC Control Invert Register */
-#define PIC32MX_DMA_CRCDATA_OFFSET 0x0040 /* DMA CRC Data Register */
-#define PIC32MX_DMA_CRCDATACLR_OFFSET 0x0044 /* DMA CRC Data Clear Register */
-#define PIC32MX_DMA_CRCDATASET_OFFSET 0x0048 /* DMA CRC Data Set Register */
-#define PIC32MX_DMA_CRCDATAINV_OFFSET 0x004c /* DMA CRC Data Invert Register */
-#define PIC32MX_DMA_CRCXOR_OFFSET 0x0050 /* DMA CRCXOR Enable Register */
-#define PIC32MX_DMA_CRCXORCLR_OFFSET 0x0054 /* DMA CRCXOR Enable Clear Register */
-#define PIC32MX_DMA_CRCXORSET_OFFSET 0x0058 /* DMA CRCXOR Enable Set Register */
-#define PIC32MX_DMA_CRCXORINV_OFFSET 0x005c /* DMA CRCXOR Enable Invert Register */
-
-/* Per-Channel DMA Registers */
-
-#define PIC32MX_DMACH_CON_OFFSET 0x0000 /* DMA Channel Control Register */
-#define PIC32MX_DMACH_CONCLR_OFFSET 0x0004 /* DMA Channel Control Clear Register */
-#define PIC32MX_DMACH_CONSET_OFFSET 0x0008 /* DMA Channel Control Set Register */
-#define PIC32MX_DMACH_CONINV_OFFSET 0x000c /* DMA Channel Control Invert Register */
-#define PIC32MX_DMACH_ECON_OFFSET 0x0010 /* DMA Channel Event Control Register */
-#define PIC32MX_DMACH_ECONCLR_OFFSET 0x0014 /* DMA Channel Event Control Clear Register */
-#define PIC32MX_DMACH_ECONSET_OFFSET 0x0018 /* DMA Channel Event Control Set Register */
-#define PIC32MX_DMACH_ECONINV_OFFSET 0x001c /* DMA Channel Event Control Invert Register */
-#define PIC32MX_DMACH_INT_OFFSET 0x0020 /* DMA Channel Interrupt Control Register */
-#define PIC32MX_DMACH_INTCLR_OFFSET 0x0024 /* DMA Channel Interrupt Control Clear Register */
-#define PIC32MX_DMACH_INTSET_OFFSET 0x0028 /* DMA Channel Interrupt Control Set Register */
-#define PIC32MX_DMACH_INTINV_OFFSET 0x002c /* DMA Channel Interrupt Control Invert Register */
-#define PIC32MX_DMACH_SSA_OFFSET 0x0030 /* DMA Channel Source Start Address Register */
-#define PIC32MX_DMACH_SSACLR_OFFSET 0x0034 /* DMA Channel Source Start Address Clear Register */
-#define PIC32MX_DMACH_SSASET_OFFSET 0x0038 /* DMA Channel Source Start Address Set Register */
-#define PIC32MX_DMACH_SSAINV_OFFSET 0x003c /* DMA Channel Source Start Address Invert Register */
-#define PIC32MX_DMACH_DSA_OFFSET 0x0040 /* DMA Channel Destination Start Address Register */
-#define PIC32MX_DMACH_DSACLR_OFFSET 0x0044 /* DMA Channel Destination Start Address Clear Register */
-#define PIC32MX_DMACH_DSASET_OFFSET 0x0048 /* DMA Channel Destination Start Address Set Register */
-#define PIC32MX_DMACH_DSAINV_OFFSET 0x004c /* DMA Channel Destination Start Address Invert Register */
-#define PIC32MX_DMACH_SSIZ_OFFSET 0x0050 /* DMA Channel Source Size Register */
-#define PIC32MX_DMACH_SSIZCLR_OFFSET 0x0054 /* DMA Channel Source Size Clear Register */
-#define PIC32MX_DMACH_SSIZSET_OFFSET 0x0058 /* DMA Channel Source Size Set Register */
-#define PIC32MX_DMACH_SSIZINV_OFFSET 0x005c /* DMA Channel Source Size Invert Register */
-#define PIC32MX_DMACH_DSIZ_OFFSET 0x0060 /* DMA Channel Destination Size Register */
-#define PIC32MX_DMACH_DSIZCLR_OFFSET 0x0064 /* DMA Channel Destination Size Clear Register */
-#define PIC32MX_DMACH_DSIZSET_OFFSET 0x0068 /* DMA Channel Destination Size Set Register */
-#define PIC32MX_DMACH_DSIZINV_OFFSET 0x006c /* DMA Channel Destination Size Invert Register */
-#define PIC32MX_DMACH_SPTR_OFFSET 0x0070 /* DMA Channel Source Pointer Register */
-#define PIC32MX_DMACH_DPTR_OFFSET 0x0080 /* DMA Channel Destination Pointer Register */
-#define PIC32MX_DMACH_CSIZ_OFFSET 0x0090 /* DMA Channel Cell-Size Register */
-#define PIC32MX_DMACH_CSIZCLR_OFFSET 0x0094 /* DMA Channel Cell-Size Clear Register */
-#define PIC32MX_DMACH_CSIZSET_OFFSET 0x0098 /* DMA Channel Cell-Size Set Register */
-#define PIC32MX_DMACH_CSIZINV_OFFSET 0x009c /* DMA Channel Cell-Size Invert Register */
-#define PIC32MX_DMACH_CPTR_OFFSET 0x00a0 /* DMA Channel Cell Pointer Register */
-#define PIC32MX_DMACH_DAT_OFFSET 0x00b0 /* DMA Channel Pattern Data Register */
-#define PIC32MX_DMACH_DATCLR_OFFSET 0x00b4 /* DMA Channel Pattern Data Clear Register */
-#define PIC32MX_DMACH_DATSET_OFFSET 0x00b8 /* DMA Channel Pattern Data Set Register */
-#define PIC32MX_DMACH_DATINV_OFFSET 0x00bc /* DMA Channel Pattern Data Invert Register */
-
-/* Register Addresses ***********************************************************************/
-/* Global DMA Registers */
-
-#define PIC32MX_DMA_CON (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CON_OFFSET)
-#define PIC32MX_DMA_CONCLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CONCLR_OFFSET)
-#define PIC32MX_DMA_CONSET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CONSET_OFFSET)
-#define PIC32MX_DMA_CONINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CONINV_OFFSET)
-#define PIC32MX_DMA_STAT (PIC32MX_DMA_K1BASE+PIC32MX_DMA_STAT_OFFSET)
-#define PIC32MX_DMA_ADDR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_ADDR_OFFSET)
-#define PIC32MX_DMA_CRCCON (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCON_OFFSET)
-#define PIC32MX_DMA_CRCCONCLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCONCLR_OFFSET)
-#define PIC32MX_DMA_CRCCONSET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCONSET_OFFSET)
-#define PIC32MX_DMA_CRCCONINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCONINV_OFFSET)
-#define PIC32MX_DMA_CRCDATA (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATA_OFFSET)
-#define PIC32MX_DMA_CRCDATACLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATACLR_OFFSET)
-#define PIC32MX_DMA_CRCDATASET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATASET_OFFSET)
-#define PIC32MX_DMA_CRCDATAINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATAINV_OFFSET)
-#define PIC32MX_DMA_CRCXOR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXOR_OFFSET)
-#define PIC32MX_DMA_CRCXORCLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXORCLR_OFFSET)
-#define PIC32MX_DMA_CRCXORSET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXORSET_OFFSET)
-#define PIC32MX_DMA_CRCXORINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXORINV_OFFSET)
-
-/* Per-Channel DMA Registers */
-
-#define PIC32MX_DMACH_CON(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CON_OFFSET)
-#define PIC32MX_DMACH_CONCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CONCLR_OFFSET)
-#define PIC32MX_DMACH_CONSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CONSET_OFFSET)
-#define PIC32MX_DMACH_CONINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CONINV_OFFSET)
-#define PIC32MX_DMACH_ECON(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECON_OFFSET)
-#define PIC32MX_DMACH_ECONCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECONCLR_OFFSET)
-#define PIC32MX_DMACH_ECONSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECONSET_OFFSET)
-#define PIC32MX_DMACH_ECONINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECONINV_OFFSET)
-#define PIC32MX_DMACH_INT(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INT_OFFSET)
-#define PIC32MX_DMACH_INTCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INTCLR_OFFSET)
-#define PIC32MX_DMACH_INTSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INTSET_OFFSET)
-#define PIC32MX_DMACH_INTINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INTINV_OFFSET)
-#define PIC32MX_DMACH_SSA(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSA_OFFSET)
-#define PIC32MX_DMACH_SSACLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSACLR_OFFSET)
-#define PIC32MX_DMACH_SSASET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSASET_OFFSET)
-#define PIC32MX_DMACH_SSAINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSAINV_OFFSET)
-#define PIC32MX_DMACH_DSA(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSA_OFFSET)
-#define PIC32MX_DMACH_DSACLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSACLR_OFFSET)
-#define PIC32MX_DMACH_DSASET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSASET_OFFSET)
-#define PIC32MX_DMACH_DSAINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSAINV_OFFSET)
-#define PIC32MX_DMACH_SSIZ(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZ_OFFSET)
-#define PIC32MX_DMACH_SSIZCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZCLR_OFFSET)
-#define PIC32MX_DMACH_SSIZSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZSET_OFFSET)
-#define PIC32MX_DMACH_SSIZINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZINV_OFFSET)
-#define PIC32MX_DMACH_DSIZ(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZ_OFFSET)
-#define PIC32MX_DMACH_DSIZCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZCLR_OFFSET)
-#define PIC32MX_DMACH_DSIZSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZSET_OFFSET)
-#define PIC32MX_DMACH_DSIZINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZINV_OFFSET)
-#define PIC32MX_DMACH_SPTR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SPTR_OFFSET)
-#define PIC32MX_DMACH_DPTR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DPTR_OFFSET)
-#define PIC32MX_DMACH_CSIZ(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZ_OFFSET)
-#define PIC32MX_DMACH_CSIZCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZCLR_OFFSET)
-#define PIC32MX_DMACH_CSIZSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZSET_OFFSET)
-#define PIC32MX_DMACH_CSIZINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZINV_OFFSET)
-#define PIC32MX_DMACH_CPTR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CPTR_OFFSET)
-#define PIC32MX_DMACH_DAT(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DAT_OFFSET)
-#define PIC32MX_DMACH_DATCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATCLR_OFFSET)
-#define PIC32MX_DMACH_DATSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATSET_OFFSET)
-#define PIC32MX_DMACH_DATINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATINV_OFFSET)
-
-#if CHIP_NDMACH > 0
-# define PIC32MX_DMACH0_CON (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH0_CONCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH0_CONSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH0_CONINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH0_ECON (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH0_ECONCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH0_ECONSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH0_ECONINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH0_INT (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH0_INTCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH0_INTSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH0_INTINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH0_SSA (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH0_SSACLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH0_SSASET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH0_SSAINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH0_DSA (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH0_DSACLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH0_DSASET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH0_DSAINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH0_SSIZ (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH0_SSIZCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH0_SSIZSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH0_SSIZINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH0_DSIZ (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH0_DSIZCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH0_DSIZSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH0_DSIZINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH0_SPTR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH0_DPTR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH0_CSIZ (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH0_CSIZCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH0_CSIZSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH0_CSIZINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH0_CPTR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH0_DAT (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH0_DATCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH0_DATSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH0_DATINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-#endif
-
-#if CHIP_NDMACH > 1
-# define PIC32MX_DMACH1_CON (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH1_CONCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH1_CONSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH1_CONINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH1_ECON (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH1_ECONCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH1_ECONSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH1_ECONINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH1_INT (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH1_INTCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH1_INTSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH1_INTINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH1_SSA (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH1_SSACLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH1_SSASET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH1_SSAINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH1_DSA (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH1_DSACLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH1_DSASET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH1_DSAINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH1_SSIZ (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH1_SSIZCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH1_SSIZSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH1_SSIZINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH1_DSIZ (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH1_DSIZCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH1_DSIZSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH1_DSIZINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH1_SPTR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH1_DPTR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH1_CSIZ (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH1_CSIZCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH1_CSIZSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH1_CSIZINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH1_CPTR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH1_DAT (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH1_DATCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH1_DATSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH1_DATINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-#endif
-
-#if CHIP_NDMACH > 2
-# define PIC32MX_DMACH2_CON (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH2_CONCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH2_CONSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH2_CONINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH2_ECON (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH2_ECONCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH2_ECONSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH2_ECONINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH2_INT (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH2_INTCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH2_INTSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH2_INTINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH2_SSA (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH2_SSACLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH2_SSASET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH2_SSAINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH2_DSA (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH2_DSACLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH2_DSASET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH2_DSAINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH2_SSIZ (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH2_SSIZCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH2_SSIZSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH2_SSIZINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH2_DSIZ (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH2_DSIZCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH2_DSIZSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH2_DSIZINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH2_SPTR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH2_DPTR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH2_CSIZ (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH2_CSIZCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH2_CSIZSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH2_CSIZINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH2_CPTR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH2_DAT (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH2_DATCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH2_DATSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH2_DATINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-
-#if CHIP_NDMACH > 3
-# define PIC32MX_DMACH3_CON (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH3_CONCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH3_CONSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH3_CONINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH3_ECON (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH3_ECONCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH3_ECONSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH3_ECONINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH3_INT (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH3_INTCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH3_INTSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH3_INTINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH3_SSA (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH3_SSACLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH3_SSASET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH3_SSAINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH3_DSA (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH3_DSACLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH3_DSASET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH3_DSAINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH3_SSIZ (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH3_SSIZCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH3_SSIZSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH3_SSIZINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH3_DSIZ (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH3_DSIZCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH3_DSIZSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH3_DSIZINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH3_SPTR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH3_DPTR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH3_CSIZ (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH3_CSIZCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH3_CSIZSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH3_CSIZINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH3_CPTR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH3_DAT (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH3_DATCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH3_DATSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH3_DATINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-#endif
-
-#if CHIP_NDMACH > 4
-# define PIC32MX_DMACH4_CON (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH4_CONCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH4_CONSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH4_CONINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH4_ECON (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH4_ECONCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH4_ECONSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH4_ECONINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH4_INT (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH4_INTCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH4_INTSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH4_INTINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH4_SSA (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH4_SSACLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH4_SSASET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH4_SSAINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH4_DSA (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH4_DSACLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH4_DSASET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH4_DSAINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH4_SSIZ (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH4_SSIZCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH4_SSIZSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH4_SSIZINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH4_DSIZ (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH4_DSIZCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH4_DSIZSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH4_DSIZINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH4_SPTR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH4_DPTR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH4_CSIZ (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH4_CSIZCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH4_CSIZSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH4_CSIZINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH4_CPTR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH4_DAT (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH4_DATCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH4_DATSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH4_DATINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-#endif
-
-#if CHIP_NDMACH > 5
-# define PIC32MX_DMACH5_CON (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH5_CONCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH5_CONSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH5_CONINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH5_ECON (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH5_ECONCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH5_ECONSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH5_ECONINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH5_INT (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH5_INTCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH5_INTSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH5_INTINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH5_SSA (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH5_SSACLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH5_SSASET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH5_SSAINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH5_DSA (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH5_DSACLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH5_DSASET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH5_DSAINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH5_SSIZ (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH5_SSIZCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH5_SSIZSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH5_SSIZINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH5_DSIZ (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH5_DSIZCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH5_DSIZSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH5_DSIZINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH5_SPTR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH5_DPTR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH5_CSIZ (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH5_CSIZCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH5_CSIZSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH5_CSIZINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH5_CPTR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH5_DAT (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH5_DATCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH5_DATSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH5_DATINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-#endif
-
-#if CHIP_NDMACH > 6
-# define PIC32MX_DMACH6_CON (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH6_CONCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH6_CONSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH6_CONINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH6_ECON (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH6_ECONCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH6_ECONSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH6_ECONINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH6_INT (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH6_INTCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH6_INTSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH6_INTINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH6_SSA (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH6_SSACLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH6_SSASET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH6_SSAINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH6_DSA (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH6_DSACLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH6_DSASET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH6_DSAINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH6_SSIZ (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH6_SSIZCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH6_SSIZSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH6_SSIZINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH6_DSIZ (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH6_DSIZCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH6_DSIZSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH6_DSIZINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH6_SPTR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH6_DPTR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH6_CSIZ (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH6_CSIZCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH6_CSIZSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH6_CSIZINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH6_CPTR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH6_DAT (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH6_DATCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH6_DATSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH6_DATINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-#endif
-
-#if CHIP_NDMACH > 7
-# define PIC32MX_DMACH7_CON (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CON_OFFSET)
-# define PIC32MX_DMACH7_CONCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET)
-# define PIC32MX_DMACH7_CONSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONSET_OFFSET)
-# define PIC32MX_DMACH7_CONINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONINV_OFFSET)
-# define PIC32MX_DMACH7_ECON (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECON_OFFSET)
-# define PIC32MX_DMACH7_ECONCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET)
-# define PIC32MX_DMACH7_ECONSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET)
-# define PIC32MX_DMACH7_ECONINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET)
-# define PIC32MX_DMACH7_INT (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INT_OFFSET)
-# define PIC32MX_DMACH7_INTCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET)
-# define PIC32MX_DMACH7_INTSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTSET_OFFSET)
-# define PIC32MX_DMACH7_INTINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTINV_OFFSET)
-# define PIC32MX_DMACH7_SSA (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSA_OFFSET)
-# define PIC32MX_DMACH7_SSACLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET)
-# define PIC32MX_DMACH7_SSASET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSASET_OFFSET)
-# define PIC32MX_DMACH7_SSAINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET)
-# define PIC32MX_DMACH7_DSA (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSA_OFFSET)
-# define PIC32MX_DMACH7_DSACLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET)
-# define PIC32MX_DMACH7_DSASET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSASET_OFFSET)
-# define PIC32MX_DMACH7_DSAINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET)
-# define PIC32MX_DMACH7_SSIZ (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET)
-# define PIC32MX_DMACH7_SSIZCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET)
-# define PIC32MX_DMACH7_SSIZSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET)
-# define PIC32MX_DMACH7_SSIZINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET)
-# define PIC32MX_DMACH7_DSIZ (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET)
-# define PIC32MX_DMACH7_DSIZCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET)
-# define PIC32MX_DMACH7_DSIZSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET)
-# define PIC32MX_DMACH7_DSIZINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET)
-# define PIC32MX_DMACH7_SPTR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SPTR_OFFSET)
-# define PIC32MX_DMACH7_DPTR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DPTR_OFFSET)
-# define PIC32MX_DMACH7_CSIZ (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET)
-# define PIC32MX_DMACH7_CSIZCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET)
-# define PIC32MX_DMACH7_CSIZSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET)
-# define PIC32MX_DMACH7_CSIZINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET)
-# define PIC32MX_DMACH7_CPTR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CPTR_OFFSET)
-# define PIC32MX_DMACH7_DAT (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DAT_OFFSET)
-# define PIC32MX_DMACH7_DATCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET)
-# define PIC32MX_DMACH7_DATSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATSET_OFFSET)
-# define PIC32MX_DMACH7_DATINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
-#endif
-
-/* Register Bit-Field Definitions ***********************************************************/
-/* Global DMA Registers */
-/* DMA Controller Control Register */
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-# define DMA_CON_SUSPEND (1 << 12) /* Bit 12: DMA suspend */
-# define DMA_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
-# define DMA_CON_FRZ (1 << 14) /* Bit 14: DMA freeze */
-# define DMA_CON_ON (1 << 15) /* Bit 15: DMA on */
-
-#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define DMA_CON_DMABUSY (1 << 11) /* Bit 15: DMA module busy */
-# define DMA_CON_SUSPEND (1 << 12) /* Bit 12: DMA suspend */
-# define DMA_CON_FRZ (1 << 14) /* Bit 14: DMA freeze */
-# define DMA_CON_ON (1 << 15) /* Bit 15: DMA on */
-
-#endif
-
-/* DMA Status Register */
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-# define DMA_STAT_DMACH_SHIFT (0) /* Bits 0-1: DMA channel */
-# define DMA_STAT_DMACH_MASK (3 << DMA_STAT_DMACH_SHIFT)
-# define DMA_STAT_RDWR (1 << 3) /* Bit 3: Read/write status */
-
-#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define DMA_STAT_DMACH_SHIFT (0) /* Bits 0-2: DMA channel */
-# define DMA_STAT_DMACH_MASK (7 << DMA_STAT_DMACH_SHIFT)
-# define DMA_STAT_RDWR (1 << 3) /* Bit 3: Read/write status */
-
-#endif
-
-/* DMA Address Register -- This register contains a 32-bit address value */
-
-/* DMA CRC Control Register */
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-# define DMA_CRCCON_CRCCH_SHIFT (0) /* Bits 0-1: CRC channel select */
-# define DMA_CRCCON_CRCCH_MASK (3 << DMA_CRCCON_CRCCH_SHIFT)
-# define DMA_CRCCON_CRCAPP (1 << 6) /* Bit 6: CRC append mode */
-# define DMA_CRCCON_CRCEN (1 << 7) /* Bit 7: CRC enable */
-# define DMA_CRCCON_PLEN_SHIFT (8) /* Bits 8-11: Polynomial length */
-# define DMA_CRCCON_PLEN_MASK (15 << DMA_CRCCON_PLEN_SHIFT)
-
-#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define DMA_CRCCON_CRCCH_SHIFT (0) /* Bits 0-1: CRC channel select */
-# define DMA_CRCCON_CRCCH_MASK (3 << DMA_CRCCON_CRCCH_SHIFT)
-# define DMA_CRCCON_CRCTYP (1 << 5) /* Bit 5: CRC type selection */
-# define DMA_CRCCON_CRCAPP (1 << 6) /* Bit 6: CRC append mode */
-# define DMA_CRCCON_CRCEN (1 << 7) /* Bit 7: CRC enable */
-# define DMA_CRCCON_PLEN_SHIFT (8) /* Bits 8-11: Polynomial length */
-# define DMA_CRCCON_PLEN_MASK (15 << DMA_CRCCON_PLEN_SHIFT)
-# define DMA_CRCCON_BITO (1 << 24) /* Bit 24: CRC bit order selection */
-# define DMA_CRCCON_WBO (1 << 27) /* Bit 27: CRC write byte order selection */
-# define DMA_CRCCON_BYTO_SHIFT (28) /* Bits 28-29: CRC byte order selection */
-# define DMA_CRCCON_BYTO_MASK (3 << DMA_CRCCON_BYTO_SHIFT)
-# define DMA_CRCCON_BYTO_SRCORDER (0 << DMA_CRCCON_BYTO_SHIFT) /* No swapping (i.e., source byte order) */
-# define DMA_CRCCON_BYTO_SWAP32 (1 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on word boundaries */
-# define DMA_CRCCON_BYTO_SWAP32H (2 << DMA_CRCCON_BYTO_SHIFT) /* Swap half-words on word boundaries */
-# define DMA_CRCCON_BYTO_SWAP16 (3 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on half-word boundaries */
-
-#endif
-
-/* DMA CRC Data Register -- 16 or 32-bits of data */
-
-/* DMA CRCXOR Enable Register -- 16 or 32-bits of data */
-
-/* Per-Channel DMA Registers */
-/* DMA Channel Control Register */
-
-#define DMACH_CON_CHPRI_SHIFT (0) /* Bits 0-1: Channel priority */
-#define DMACH_CON_CHPRI_MASK (3 << DMACH_CON_CHPRI_SHIFT)
-# define DMACH_CON_CHPRI(n) ((n) << DMACH_CON_CHPRI_SHIFT)
-#define DMACH_CON_CHEDET (1 << 2) /* Bit 2: Channel event detected */
-#define DMACH_CON_CHAEN (1 << 4) /* Bit 4: Channel automatic enable */
-#define DMACH_CON_CHCHN (1 << 5) /* Bit 5: Channel chain enable */
-#define DMACH_CON_CHAED (1 << 6) /* Bit 6: Channel allow events if disabled */
-#define DMACH_CON_CHEN (1 << 7) /* Bit 7: Channel enable */
-#define DMACH_CON_CHCHNS (1 << 8) /* Bit 8: Chain channel selection */
-
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define DMACH_CON_CHBUSY (1 << 15) /* Bit 15: Channel busy */
-#endif
-
-/* DMA Channel Event Control Register */
-
-#define DMACH_ECON_AIRQEN (1 << 3) /* Bit 3: Channel abort IRQ enable */
-#define DMACH_ECON_SIRQEN (1 << 4) /* Bit 4: Channel start IRQ enable */
-#define DMACH_ECON_PATEN (1 << 5) /* Bit 5: Channel pattern match abort enable */
-#define DMACH_ECON_CABORT (1 << 6) /* Bit 6: DMA abort transfer */
-#define DMACH_ECON_CFORCE (1 << 7) /* Bit 7: DMA forced transfer */
-#define DMACH_ECON_CHSIRQ_SHIFT (8) /* Bits 8-15: Channel Transfer Start IRQ */
-#define DMACH_ECON_CHSIRQ_MASK (0xff << DMACH_ECON_CHSIRQ_SHIFT)
-# define DMACH_ECON_CHSIRQ(n) ((n) << DMACH_ECON_CHSIRQ_SHIFT) /* Interrupt n will initiate a DMA transfer */
-#define DMACH_ECON_CHAIRQ_SHIFT (16) /* Bits 16-23: Channel transfer abort irq */
-#define DMACH_ECON_CHAIRQ_MASK (0xff << DMACH_ECON_CHAIRQ_SHIFT)
-# define DMACH_ECON_CHAIRQ(n) ((n) << DMACH_ECON_CHAIRQ_SHIFT) /* Interrupt n will abort any transfers in progress and set CHAIF */
-
-/* DMA Channel Interrupt Control Register */
-
-#define DMACH_INT_CHERIF (1 << 0) /* Bit 0: Channel address error interrupt flag */
-#define DMACH_INT_CHTAIF (1 << 1) /* Bit 1: Channel transfer abort interrupt flag */
-#define DMACH_INT_CHCCIF (1 << 2) /* Bit 2: Channel cell transfer complete interrupt flag */
-#define DMACH_INT_CHBCIF (1 << 3) /* Bit 3: Channel block transfer complete interrupt flag */
-#define DMACH_INT_CHDHIF (1 << 4) /* Bit 4: Channel destination half full interrupt flag */
-#define DMACH_INT_CHDDIF (1 << 5) /* Bit 5: Channel destination done interrupt flag */
-#define DMACH_INT_CHSHIF (1 << 6) /* Bit 6: Channel source half empty interrupt flag */
-#define DMACH_INT_CHSDIF (1 << 7) /* Bit 7: Channel source done interrupt flag */
-#define DMACH_INT_CHERIE (1 << 16) /* Bit 16: Channel address error interrupt enable */
-#define DMACH_INT_CHTAIE (1 << 17) /* Bit 17: Channel transfer abort interrupt enable */
-#define DMACH_INT_CHCCIE (1 << 18) /* Bit 18: Channel cell transfer complete interrupt enable */
-#define DMACH_INT_CHBCIE (1 << 19) /* Bit 19: Channel block transfer complete interrupt enable */
-#define DMACH_INT_CHDHIE (1 << 20) /* Bit 20: Channel destination half full interrupt enable */
-#define DMACH_INT_CHDDIE (1 << 21) /* Bit 21: Channel destination done interrupt enable */
-#define DMACH_INT_CHSHIE (1 << 22) /* Bit 22: Channel source half empty interrupt enable */
-#define DMACH_INT_CHSDIE (1 << 23) /* Bit 23: Channel source done interrupt enable */
-
-/* DMA Channel Source Start Address Register -- This register contains a 32-bit address value */
-
-/* DMA Channel Destination Start Address Register -- This register contains a 32-bit address value */
-
-/* DMA Channel Source Size Register -- 8 or 16 bits of byte size data */
-
-/* DMA Channel Destination Size Register -- 8 or 16 bits of byte size data */
-
-/* DMA Channel Source Pointer Register -- 8 or 16 bits of byte index data */
-
-/* DMA Channel Destination Pointer Register -- 8 or 16 bits of byte index data */
-
-/* DMA Channel Cell-Size Register -- 8 or 16 bits of byte transferred data */
-
-/* DMA Channel Cell Pointer Register -- 8 or 16 bits of byte transferred data */
-
-/* DMA Channel Pattern Data Register -- 8-bits of pattern data */
-
-#define DMACH_DAT_MASK 0xff
-
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/********************************************************************************************
- * Inline Functions
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Function Prototypes
- ********************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* CHIP_NDMACH > 0 */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H */
+/******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-dma.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "pic32mx-memorymap.h" + +#if CHIP_NDMACH > 0 + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ +/* Global DMA Registers */ + +#define PIC32MX_DMA_CON_OFFSET 0x0000 /* DMA Controller Control Register */ +#define PIC32MX_DMA_CONCLR_OFFSET 0x0004 /* DMA Controller Control Clear Register */ +#define PIC32MX_DMA_CONSET_OFFSET 0x0008 /* DMA Controller Control Set Register */ +#define PIC32MX_DMA_CONINV_OFFSET 0x000c /* DMA Controller Control Invert Register */ +#define PIC32MX_DMA_STAT_OFFSET 0x0010 /* DMA Status Register */ +#define PIC32MX_DMA_ADDR_OFFSET 0x0020 /* DMA Address Register */ +#define PIC32MX_DMA_CRCCON_OFFSET 0x0030 /* DMA CRC Control Register */ +#define PIC32MX_DMA_CRCCONCLR_OFFSET 0x0034 /* DMA CRC Control Clear Register */ +#define PIC32MX_DMA_CRCCONSET_OFFSET 0x0038 /* DMA CRC Control Set Register */ +#define PIC32MX_DMA_CRCCONINV_OFFSET 0x003c /* DMA CRC Control Invert Register */ +#define PIC32MX_DMA_CRCDATA_OFFSET 0x0040 /* DMA CRC Data Register */ +#define PIC32MX_DMA_CRCDATACLR_OFFSET 0x0044 /* DMA CRC Data Clear Register */ +#define PIC32MX_DMA_CRCDATASET_OFFSET 0x0048 /* DMA CRC Data Set Register */ +#define PIC32MX_DMA_CRCDATAINV_OFFSET 0x004c /* DMA CRC Data Invert Register */ +#define PIC32MX_DMA_CRCXOR_OFFSET 0x0050 /* DMA CRCXOR Enable Register */ +#define PIC32MX_DMA_CRCXORCLR_OFFSET 0x0054 /* DMA CRCXOR Enable Clear Register */ +#define PIC32MX_DMA_CRCXORSET_OFFSET 0x0058 /* DMA CRCXOR Enable Set Register */ +#define PIC32MX_DMA_CRCXORINV_OFFSET 0x005c /* DMA CRCXOR Enable Invert Register */ + +/* Per-Channel DMA Registers */ + +#define PIC32MX_DMACH_CON_OFFSET 0x0000 /* DMA Channel Control Register */ +#define PIC32MX_DMACH_CONCLR_OFFSET 0x0004 /* DMA Channel Control Clear Register */ +#define PIC32MX_DMACH_CONSET_OFFSET 0x0008 /* DMA Channel Control Set Register */ +#define PIC32MX_DMACH_CONINV_OFFSET 0x000c /* DMA Channel Control Invert Register */ +#define PIC32MX_DMACH_ECON_OFFSET 0x0010 /* DMA Channel Event Control Register */ +#define PIC32MX_DMACH_ECONCLR_OFFSET 0x0014 /* DMA Channel Event Control Clear Register */ +#define PIC32MX_DMACH_ECONSET_OFFSET 0x0018 /* DMA Channel Event Control Set Register */ +#define PIC32MX_DMACH_ECONINV_OFFSET 0x001c /* DMA Channel Event Control Invert Register */ +#define PIC32MX_DMACH_INT_OFFSET 0x0020 /* DMA Channel Interrupt Control Register */ +#define PIC32MX_DMACH_INTCLR_OFFSET 0x0024 /* DMA Channel Interrupt Control Clear Register */ +#define PIC32MX_DMACH_INTSET_OFFSET 0x0028 /* DMA Channel Interrupt Control Set Register */ +#define PIC32MX_DMACH_INTINV_OFFSET 0x002c /* DMA Channel Interrupt Control Invert Register */ +#define PIC32MX_DMACH_SSA_OFFSET 0x0030 /* DMA Channel Source Start Address Register */ +#define PIC32MX_DMACH_SSACLR_OFFSET 0x0034 /* DMA Channel Source Start Address Clear Register */ +#define PIC32MX_DMACH_SSASET_OFFSET 0x0038 /* DMA Channel Source Start Address Set Register */ +#define PIC32MX_DMACH_SSAINV_OFFSET 0x003c /* DMA Channel Source Start Address Invert Register */ +#define PIC32MX_DMACH_DSA_OFFSET 0x0040 /* DMA Channel Destination Start Address Register */ +#define PIC32MX_DMACH_DSACLR_OFFSET 0x0044 /* DMA Channel Destination Start Address Clear Register */ +#define PIC32MX_DMACH_DSASET_OFFSET 0x0048 /* DMA Channel Destination Start Address Set Register */ +#define PIC32MX_DMACH_DSAINV_OFFSET 0x004c /* DMA Channel Destination Start Address Invert Register */ +#define PIC32MX_DMACH_SSIZ_OFFSET 0x0050 /* DMA Channel Source Size Register */ +#define PIC32MX_DMACH_SSIZCLR_OFFSET 0x0054 /* DMA Channel Source Size Clear Register */ +#define PIC32MX_DMACH_SSIZSET_OFFSET 0x0058 /* DMA Channel Source Size Set Register */ +#define PIC32MX_DMACH_SSIZINV_OFFSET 0x005c /* DMA Channel Source Size Invert Register */ +#define PIC32MX_DMACH_DSIZ_OFFSET 0x0060 /* DMA Channel Destination Size Register */ +#define PIC32MX_DMACH_DSIZCLR_OFFSET 0x0064 /* DMA Channel Destination Size Clear Register */ +#define PIC32MX_DMACH_DSIZSET_OFFSET 0x0068 /* DMA Channel Destination Size Set Register */ +#define PIC32MX_DMACH_DSIZINV_OFFSET 0x006c /* DMA Channel Destination Size Invert Register */ +#define PIC32MX_DMACH_SPTR_OFFSET 0x0070 /* DMA Channel Source Pointer Register */ +#define PIC32MX_DMACH_DPTR_OFFSET 0x0080 /* DMA Channel Destination Pointer Register */ +#define PIC32MX_DMACH_CSIZ_OFFSET 0x0090 /* DMA Channel Cell-Size Register */ +#define PIC32MX_DMACH_CSIZCLR_OFFSET 0x0094 /* DMA Channel Cell-Size Clear Register */ +#define PIC32MX_DMACH_CSIZSET_OFFSET 0x0098 /* DMA Channel Cell-Size Set Register */ +#define PIC32MX_DMACH_CSIZINV_OFFSET 0x009c /* DMA Channel Cell-Size Invert Register */ +#define PIC32MX_DMACH_CPTR_OFFSET 0x00a0 /* DMA Channel Cell Pointer Register */ +#define PIC32MX_DMACH_DAT_OFFSET 0x00b0 /* DMA Channel Pattern Data Register */ +#define PIC32MX_DMACH_DATCLR_OFFSET 0x00b4 /* DMA Channel Pattern Data Clear Register */ +#define PIC32MX_DMACH_DATSET_OFFSET 0x00b8 /* DMA Channel Pattern Data Set Register */ +#define PIC32MX_DMACH_DATINV_OFFSET 0x00bc /* DMA Channel Pattern Data Invert Register */ + +/* Register Addresses ***********************************************************************/ +/* Global DMA Registers */ + +#define PIC32MX_DMA_CON (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CON_OFFSET) +#define PIC32MX_DMA_CONCLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CONCLR_OFFSET) +#define PIC32MX_DMA_CONSET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CONSET_OFFSET) +#define PIC32MX_DMA_CONINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CONINV_OFFSET) +#define PIC32MX_DMA_STAT (PIC32MX_DMA_K1BASE+PIC32MX_DMA_STAT_OFFSET) +#define PIC32MX_DMA_ADDR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_ADDR_OFFSET) +#define PIC32MX_DMA_CRCCON (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCON_OFFSET) +#define PIC32MX_DMA_CRCCONCLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCONCLR_OFFSET) +#define PIC32MX_DMA_CRCCONSET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCONSET_OFFSET) +#define PIC32MX_DMA_CRCCONINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCCONINV_OFFSET) +#define PIC32MX_DMA_CRCDATA (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATA_OFFSET) +#define PIC32MX_DMA_CRCDATACLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATACLR_OFFSET) +#define PIC32MX_DMA_CRCDATASET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATASET_OFFSET) +#define PIC32MX_DMA_CRCDATAINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCDATAINV_OFFSET) +#define PIC32MX_DMA_CRCXOR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXOR_OFFSET) +#define PIC32MX_DMA_CRCXORCLR (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXORCLR_OFFSET) +#define PIC32MX_DMA_CRCXORSET (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXORSET_OFFSET) +#define PIC32MX_DMA_CRCXORINV (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CRCXORINV_OFFSET) + +/* Per-Channel DMA Registers */ + +#define PIC32MX_DMACH_CON(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CON_OFFSET) +#define PIC32MX_DMACH_CONCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CONCLR_OFFSET) +#define PIC32MX_DMACH_CONSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CONSET_OFFSET) +#define PIC32MX_DMACH_CONINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CONINV_OFFSET) +#define PIC32MX_DMACH_ECON(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECON_OFFSET) +#define PIC32MX_DMACH_ECONCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECONCLR_OFFSET) +#define PIC32MX_DMACH_ECONSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECONSET_OFFSET) +#define PIC32MX_DMACH_ECONINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_ECONINV_OFFSET) +#define PIC32MX_DMACH_INT(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INT_OFFSET) +#define PIC32MX_DMACH_INTCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INTCLR_OFFSET) +#define PIC32MX_DMACH_INTSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INTSET_OFFSET) +#define PIC32MX_DMACH_INTINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_INTINV_OFFSET) +#define PIC32MX_DMACH_SSA(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSA_OFFSET) +#define PIC32MX_DMACH_SSACLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSACLR_OFFSET) +#define PIC32MX_DMACH_SSASET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSASET_OFFSET) +#define PIC32MX_DMACH_SSAINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSAINV_OFFSET) +#define PIC32MX_DMACH_DSA(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSA_OFFSET) +#define PIC32MX_DMACH_DSACLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSACLR_OFFSET) +#define PIC32MX_DMACH_DSASET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSASET_OFFSET) +#define PIC32MX_DMACH_DSAINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSAINV_OFFSET) +#define PIC32MX_DMACH_SSIZ(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZ_OFFSET) +#define PIC32MX_DMACH_SSIZCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZCLR_OFFSET) +#define PIC32MX_DMACH_SSIZSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZSET_OFFSET) +#define PIC32MX_DMACH_SSIZINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SSIZINV_OFFSET) +#define PIC32MX_DMACH_DSIZ(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZ_OFFSET) +#define PIC32MX_DMACH_DSIZCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZCLR_OFFSET) +#define PIC32MX_DMACH_DSIZSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZSET_OFFSET) +#define PIC32MX_DMACH_DSIZINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DSIZINV_OFFSET) +#define PIC32MX_DMACH_SPTR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_SPTR_OFFSET) +#define PIC32MX_DMACH_DPTR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DPTR_OFFSET) +#define PIC32MX_DMACH_CSIZ(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZ_OFFSET) +#define PIC32MX_DMACH_CSIZCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZCLR_OFFSET) +#define PIC32MX_DMACH_CSIZSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZSET_OFFSET) +#define PIC32MX_DMACH_CSIZINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CSIZINV_OFFSET) +#define PIC32MX_DMACH_CPTR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_CPTR_OFFSET) +#define PIC32MX_DMACH_DAT(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DAT_OFFSET) +#define PIC32MX_DMACH_DATCLR(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATCLR_OFFSET) +#define PIC32MX_DMACH_DATSET(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATSET_OFFSET) +#define PIC32MX_DMACH_DATINV(n) (PIC32MX_DMACH_K1BASE(n)+PIC32MX_DMACH_DATINV_OFFSET) + +#if CHIP_NDMACH > 0 +# define PIC32MX_DMACH0_CON (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH0_CONCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH0_CONSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH0_CONINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH0_ECON (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH0_ECONCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH0_ECONSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH0_ECONINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH0_INT (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH0_INTCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH0_INTSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH0_INTINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH0_SSA (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH0_SSACLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH0_SSASET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH0_SSAINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH0_DSA (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH0_DSACLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH0_DSASET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH0_DSAINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH0_SSIZ (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH0_SSIZCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH0_SSIZSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH0_SSIZINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH0_DSIZ (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH0_DSIZCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH0_DSIZSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH0_DSIZINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH0_SPTR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH0_DPTR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH0_CSIZ (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH0_CSIZCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH0_CSIZSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH0_CSIZINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH0_CPTR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH0_DAT (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH0_DATCLR (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH0_DATSET (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH0_DATINV (PIC32MX_DMACH0_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) +#endif + +#if CHIP_NDMACH > 1 +# define PIC32MX_DMACH1_CON (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH1_CONCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH1_CONSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH1_CONINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH1_ECON (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH1_ECONCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH1_ECONSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH1_ECONINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH1_INT (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH1_INTCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH1_INTSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH1_INTINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH1_SSA (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH1_SSACLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH1_SSASET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH1_SSAINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH1_DSA (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH1_DSACLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH1_DSASET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH1_DSAINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH1_SSIZ (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH1_SSIZCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH1_SSIZSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH1_SSIZINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH1_DSIZ (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH1_DSIZCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH1_DSIZSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH1_DSIZINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH1_SPTR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH1_DPTR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH1_CSIZ (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH1_CSIZCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH1_CSIZSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH1_CSIZINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH1_CPTR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH1_DAT (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH1_DATCLR (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH1_DATSET (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH1_DATINV (PIC32MX_DMACH1_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) +#endif + +#if CHIP_NDMACH > 2 +# define PIC32MX_DMACH2_CON (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH2_CONCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH2_CONSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH2_CONINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH2_ECON (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH2_ECONCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH2_ECONSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH2_ECONINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH2_INT (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH2_INTCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH2_INTSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH2_INTINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH2_SSA (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH2_SSACLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH2_SSASET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH2_SSAINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH2_DSA (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH2_DSACLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH2_DSASET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH2_DSAINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH2_SSIZ (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH2_SSIZCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH2_SSIZSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH2_SSIZINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH2_DSIZ (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH2_DSIZCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH2_DSIZSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH2_DSIZINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH2_SPTR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH2_DPTR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH2_CSIZ (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH2_CSIZCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH2_CSIZSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH2_CSIZINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH2_CPTR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH2_DAT (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH2_DATCLR (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH2_DATSET (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH2_DATINV (PIC32MX_DMACH2_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) + +#if CHIP_NDMACH > 3 +# define PIC32MX_DMACH3_CON (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH3_CONCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH3_CONSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH3_CONINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH3_ECON (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH3_ECONCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH3_ECONSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH3_ECONINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH3_INT (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH3_INTCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH3_INTSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH3_INTINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH3_SSA (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH3_SSACLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH3_SSASET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH3_SSAINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH3_DSA (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH3_DSACLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH3_DSASET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH3_DSAINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH3_SSIZ (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH3_SSIZCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH3_SSIZSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH3_SSIZINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH3_DSIZ (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH3_DSIZCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH3_DSIZSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH3_DSIZINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH3_SPTR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH3_DPTR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH3_CSIZ (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH3_CSIZCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH3_CSIZSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH3_CSIZINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH3_CPTR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH3_DAT (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH3_DATCLR (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH3_DATSET (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH3_DATINV (PIC32MX_DMACH3_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) +#endif + +#if CHIP_NDMACH > 4 +# define PIC32MX_DMACH4_CON (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH4_CONCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH4_CONSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH4_CONINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH4_ECON (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH4_ECONCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH4_ECONSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH4_ECONINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH4_INT (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH4_INTCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH4_INTSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH4_INTINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH4_SSA (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH4_SSACLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH4_SSASET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH4_SSAINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH4_DSA (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH4_DSACLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH4_DSASET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH4_DSAINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH4_SSIZ (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH4_SSIZCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH4_SSIZSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH4_SSIZINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH4_DSIZ (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH4_DSIZCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH4_DSIZSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH4_DSIZINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH4_SPTR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH4_DPTR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH4_CSIZ (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH4_CSIZCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH4_CSIZSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH4_CSIZINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH4_CPTR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH4_DAT (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH4_DATCLR (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH4_DATSET (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH4_DATINV (PIC32MX_DMACH4_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) +#endif + +#if CHIP_NDMACH > 5 +# define PIC32MX_DMACH5_CON (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH5_CONCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH5_CONSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH5_CONINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH5_ECON (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH5_ECONCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH5_ECONSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH5_ECONINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH5_INT (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH5_INTCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH5_INTSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH5_INTINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH5_SSA (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH5_SSACLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH5_SSASET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH5_SSAINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH5_DSA (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH5_DSACLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH5_DSASET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH5_DSAINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH5_SSIZ (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH5_SSIZCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH5_SSIZSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH5_SSIZINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH5_DSIZ (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH5_DSIZCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH5_DSIZSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH5_DSIZINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH5_SPTR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH5_DPTR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH5_CSIZ (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH5_CSIZCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH5_CSIZSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH5_CSIZINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH5_CPTR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH5_DAT (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH5_DATCLR (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH5_DATSET (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH5_DATINV (PIC32MX_DMACH5_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) +#endif + +#if CHIP_NDMACH > 6 +# define PIC32MX_DMACH6_CON (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH6_CONCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH6_CONSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH6_CONINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH6_ECON (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH6_ECONCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH6_ECONSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH6_ECONINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH6_INT (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH6_INTCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH6_INTSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH6_INTINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH6_SSA (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH6_SSACLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH6_SSASET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH6_SSAINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH6_DSA (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH6_DSACLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH6_DSASET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH6_DSAINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH6_SSIZ (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH6_SSIZCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH6_SSIZSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH6_SSIZINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH6_DSIZ (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH6_DSIZCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH6_DSIZSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH6_DSIZINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH6_SPTR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH6_DPTR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH6_CSIZ (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH6_CSIZCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH6_CSIZSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH6_CSIZINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH6_CPTR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH6_DAT (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH6_DATCLR (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH6_DATSET (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH6_DATINV (PIC32MX_DMACH6_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) +#endif + +#if CHIP_NDMACH > 7 +# define PIC32MX_DMACH7_CON (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CON_OFFSET) +# define PIC32MX_DMACH7_CONCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONCLR_OFFSET) +# define PIC32MX_DMACH7_CONSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONSET_OFFSET) +# define PIC32MX_DMACH7_CONINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CONINV_OFFSET) +# define PIC32MX_DMACH7_ECON (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECON_OFFSET) +# define PIC32MX_DMACH7_ECONCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONCLR_OFFSET) +# define PIC32MX_DMACH7_ECONSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONSET_OFFSET) +# define PIC32MX_DMACH7_ECONINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_ECONINV_OFFSET) +# define PIC32MX_DMACH7_INT (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INT_OFFSET) +# define PIC32MX_DMACH7_INTCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTCLR_OFFSET) +# define PIC32MX_DMACH7_INTSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTSET_OFFSET) +# define PIC32MX_DMACH7_INTINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_INTINV_OFFSET) +# define PIC32MX_DMACH7_SSA (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSA_OFFSET) +# define PIC32MX_DMACH7_SSACLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSACLR_OFFSET) +# define PIC32MX_DMACH7_SSASET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSASET_OFFSET) +# define PIC32MX_DMACH7_SSAINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSAINV_OFFSET) +# define PIC32MX_DMACH7_DSA (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSA_OFFSET) +# define PIC32MX_DMACH7_DSACLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSACLR_OFFSET) +# define PIC32MX_DMACH7_DSASET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSASET_OFFSET) +# define PIC32MX_DMACH7_DSAINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSAINV_OFFSET) +# define PIC32MX_DMACH7_SSIZ (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZ_OFFSET) +# define PIC32MX_DMACH7_SSIZCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZCLR_OFFSET) +# define PIC32MX_DMACH7_SSIZSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZSET_OFFSET) +# define PIC32MX_DMACH7_SSIZINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SSIZINV_OFFSET) +# define PIC32MX_DMACH7_DSIZ (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZ_OFFSET) +# define PIC32MX_DMACH7_DSIZCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZCLR_OFFSET) +# define PIC32MX_DMACH7_DSIZSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZSET_OFFSET) +# define PIC32MX_DMACH7_DSIZINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DSIZINV_OFFSET) +# define PIC32MX_DMACH7_SPTR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_SPTR_OFFSET) +# define PIC32MX_DMACH7_DPTR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DPTR_OFFSET) +# define PIC32MX_DMACH7_CSIZ (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZ_OFFSET) +# define PIC32MX_DMACH7_CSIZCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZCLR_OFFSET) +# define PIC32MX_DMACH7_CSIZSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZSET_OFFSET) +# define PIC32MX_DMACH7_CSIZINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CSIZINV_OFFSET) +# define PIC32MX_DMACH7_CPTR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_CPTR_OFFSET) +# define PIC32MX_DMACH7_DAT (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DAT_OFFSET) +# define PIC32MX_DMACH7_DATCLR (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATCLR_OFFSET) +# define PIC32MX_DMACH7_DATSET (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATSET_OFFSET) +# define PIC32MX_DMACH7_DATINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATINV_OFFSET) +#endif + +/* Register Bit-Field Definitions ***********************************************************/ +/* Global DMA Registers */ +/* DMA Controller Control Register */ + +#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +# define DMA_CON_DMABUSY (1 << 11) /* Bit 15: DMA module busy */ +# define DMA_CON_SUSPEND (1 << 12) /* Bit 12: DMA suspend */ +# define DMA_CON_ON (1 << 15) /* Bit 15: DMA on */ + +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +# define DMA_CON_SUSPEND (1 << 12) /* Bit 12: DMA suspend */ +# define DMA_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +# define DMA_CON_FRZ (1 << 14) /* Bit 14: DMA freeze */ +# define DMA_CON_ON (1 << 15) /* Bit 15: DMA on */ + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define DMA_CON_DMABUSY (1 << 11) /* Bit 15: DMA module busy */ +# define DMA_CON_SUSPEND (1 << 12) /* Bit 12: DMA suspend */ +# define DMA_CON_FRZ (1 << 14) /* Bit 14: DMA freeze */ +# define DMA_CON_ON (1 << 15) /* Bit 15: DMA on */ + +#endif + +/* DMA Status Register */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX3) || \ + defined(CHIP_PIC32MX4) + +# define DMA_STAT_DMACH_SHIFT (0) /* Bits 0-1: DMA channel */ +# define DMA_STAT_DMACH_MASK (3 << DMA_STAT_DMACH_SHIFT) +# define DMA_STAT_RDWR (1 << 3) /* Bit 3: Read/write status */ + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define DMA_STAT_DMACH_SHIFT (0) /* Bits 0-2: DMA channel */ +# define DMA_STAT_DMACH_MASK (7 << DMA_STAT_DMACH_SHIFT) +# define DMA_STAT_RDWR (1 << 3) /* Bit 3: Read/write status */ + +#endif + +/* DMA Address Register -- This register contains a 32-bit address value */ + +/* DMA CRC Control Register */ + +#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +# define DMA_CRCCON_CRCCH_SHIFT (0) /* Bits 0-1: CRC channel select */ +# define DMA_CRCCON_CRCCH_MASK (3 << DMA_CRCCON_CRCCH_SHIFT) +# define DMA_CRCCON_CRCAPP (1 << 6) /* Bit 6: CRC append mode */ +# define DMA_CRCCON_CRCEN (1 << 7) /* Bit 7: CRC enable */ +# define DMA_CRCCON_PLEN_SHIFT (8) /* Bits 8-11: Polynomial length */ +# define DMA_CRCCON_PLEN_MASK (15 << DMA_CRCCON_PLEN_SHIFT) + +#elif defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define DMA_CRCCON_CRCCH_SHIFT (0) /* Bits 0-2: CRC channel select */ +# define DMA_CRCCON_CRCCH_MASK (7 << DMA_CRCCON_CRCCH_SHIFT) +# define DMA_CRCCON_CRCTYP (1 << 5) /* Bit 5: CRC type selection */ +# define DMA_CRCCON_CRCAPP (1 << 6) /* Bit 6: CRC append mode */ +# define DMA_CRCCON_CRCEN (1 << 7) /* Bit 7: CRC enable */ +# define DMA_CRCCON_PLEN_SHIFT (8) /* Bits 8-12: Polynomial length */ +# define DMA_CRCCON_PLEN_MASK (31 << DMA_CRCCON_PLEN_SHIFT) +# define DMA_CRCCON_BITO (1 << 24) /* Bit 24: CRC bit order selection */ +# define DMA_CRCCON_WBO (1 << 27) /* Bit 27: CRC write byte order selection */ +# define DMA_CRCCON_BYTO_SHIFT (28) /* Bits 28-29: CRC byte order selection */ +# define DMA_CRCCON_BYTO_MASK (3 << DMA_CRCCON_BYTO_SHIFT) +# define DMA_CRCCON_BYTO_SRCORDER (0 << DMA_CRCCON_BYTO_SHIFT) /* No swapping (i.e., source byte order) */ +# define DMA_CRCCON_BYTO_SWAP32 (1 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on word boundaries */ +# define DMA_CRCCON_BYTO_SWAP32H (2 << DMA_CRCCON_BYTO_SHIFT) /* Swap half-words on word boundaries */ +# define DMA_CRCCON_BYTO_SWAP16 (3 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on half-word boundaries */ + +#endif + +/* DMA CRC Data Register -- 16 or 32-bits of data */ + +/* DMA CRCXOR Enable Register -- 16 or 32-bits of data */ + +/* Per-Channel DMA Registers */ +/* DMA Channel Control Register */ + +#define DMACH_CON_CHPRI_SHIFT (0) /* Bits 0-1: Channel priority */ +#define DMACH_CON_CHPRI_MASK (3 << DMACH_CON_CHPRI_SHIFT) +# define DMACH_CON_CHPRI(n) ((n) << DMACH_CON_CHPRI_SHIFT) +#define DMACH_CON_CHEDET (1 << 2) /* Bit 2: Channel event detected */ +#define DMACH_CON_CHAEN (1 << 4) /* Bit 4: Channel automatic enable */ +#define DMACH_CON_CHCHN (1 << 5) /* Bit 5: Channel chain enable */ +#define DMACH_CON_CHAED (1 << 6) /* Bit 6: Channel allow events if disabled */ +#define DMACH_CON_CHEN (1 << 7) /* Bit 7: Channel enable */ +#define DMACH_CON_CHCHNS (1 << 8) /* Bit 8: Chain channel selection */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define DMACH_CON_CHBUSY (1 << 15) /* Bit 15: Channel busy */ +#endif + +/* DMA Channel Event Control Register */ + +#define DMACH_ECON_AIRQEN (1 << 3) /* Bit 3: Channel abort IRQ enable */ +#define DMACH_ECON_SIRQEN (1 << 4) /* Bit 4: Channel start IRQ enable */ +#define DMACH_ECON_PATEN (1 << 5) /* Bit 5: Channel pattern match abort enable */ +#define DMACH_ECON_CABORT (1 << 6) /* Bit 6: DMA abort transfer */ +#define DMACH_ECON_CFORCE (1 << 7) /* Bit 7: DMA forced transfer */ +#define DMACH_ECON_CHSIRQ_SHIFT (8) /* Bits 8-15: Channel Transfer Start IRQ */ +#define DMACH_ECON_CHSIRQ_MASK (0xff << DMACH_ECON_CHSIRQ_SHIFT) +# define DMACH_ECON_CHSIRQ(n) ((n) << DMACH_ECON_CHSIRQ_SHIFT) /* Interrupt n will initiate a DMA transfer */ +#define DMACH_ECON_CHAIRQ_SHIFT (16) /* Bits 16-23: Channel transfer abort irq */ +#define DMACH_ECON_CHAIRQ_MASK (0xff << DMACH_ECON_CHAIRQ_SHIFT) +# define DMACH_ECON_CHAIRQ(n) ((n) << DMACH_ECON_CHAIRQ_SHIFT) /* Interrupt n will abort any transfers in progress and set CHAIF */ + +/* DMA Channel Interrupt Control Register */ + +#define DMACH_INT_CHERIF (1 << 0) /* Bit 0: Channel address error interrupt flag */ +#define DMACH_INT_CHTAIF (1 << 1) /* Bit 1: Channel transfer abort interrupt flag */ +#define DMACH_INT_CHCCIF (1 << 2) /* Bit 2: Channel cell transfer complete interrupt flag */ +#define DMACH_INT_CHBCIF (1 << 3) /* Bit 3: Channel block transfer complete interrupt flag */ +#define DMACH_INT_CHDHIF (1 << 4) /* Bit 4: Channel destination half full interrupt flag */ +#define DMACH_INT_CHDDIF (1 << 5) /* Bit 5: Channel destination done interrupt flag */ +#define DMACH_INT_CHSHIF (1 << 6) /* Bit 6: Channel source half empty interrupt flag */ +#define DMACH_INT_CHSDIF (1 << 7) /* Bit 7: Channel source done interrupt flag */ +#define DMACH_INT_CHERIE (1 << 16) /* Bit 16: Channel address error interrupt enable */ +#define DMACH_INT_CHTAIE (1 << 17) /* Bit 17: Channel transfer abort interrupt enable */ +#define DMACH_INT_CHCCIE (1 << 18) /* Bit 18: Channel cell transfer complete interrupt enable */ +#define DMACH_INT_CHBCIE (1 << 19) /* Bit 19: Channel block transfer complete interrupt enable */ +#define DMACH_INT_CHDHIE (1 << 20) /* Bit 20: Channel destination half full interrupt enable */ +#define DMACH_INT_CHDDIE (1 << 21) /* Bit 21: Channel destination done interrupt enable */ +#define DMACH_INT_CHSHIE (1 << 22) /* Bit 22: Channel source half empty interrupt enable */ +#define DMACH_INT_CHSDIE (1 << 23) /* Bit 23: Channel source done interrupt enable */ + +/* DMA Channel Source Start Address Register -- This register contains a 32-bit address value */ + +/* DMA Channel Destination Start Address Register -- This register contains a 32-bit address value */ + +/* DMA Channel Source Size Register -- 8 or 16 bits of byte size data */ + +/* DMA Channel Destination Size Register -- 8 or 16 bits of byte size data */ + +/* DMA Channel Source Pointer Register -- 8 or 16 bits of byte index data */ + +/* DMA Channel Destination Pointer Register -- 8 or 16 bits of byte index data */ + +/* DMA Channel Cell-Size Register -- 8 or 16 bits of byte transferred data */ + +/* DMA Channel Cell Pointer Register -- 8 or 16 bits of byte transferred data */ + +/* DMA Channel Pattern Data Register -- 8-bits of pattern data */ + +#define DMACH_DAT_MASK 0xff + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CHIP_NDMACH > 0 */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-int.h b/nuttx/arch/mips/src/pic32mx/pic32mx-int.h index c774cd621..ba017bb04 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-int.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-int.h @@ -1,873 +1,1084 @@ -/****************************************************************************
- * arch/mips/src/pic32mx/pic32mx-int.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_INT_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_INT_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "pic32mx-memorymap.h"
-
-/****************************************************************************
- * Pre-Processor Definitions
- ****************************************************************************/
-/* Register Offsets *********************************************************/
-
-#define PIC32MX_INT_INTCON_OFFSET 0x0000 /* Interrupt control register */
-#define PIC32MX_INT_INTCONCLR_OFFSET 0x0004 /* Interrupt control clear register */
-#define PIC32MX_INT_INTCONSET_OFFSET 0x0008 /* Interrupt control set register */
-#define PIC32MX_INT_INTCONINV_OFFSET 0x000c /* Interrupt control invert register */
-#define PIC32MX_INT_INTSTAT_OFFSET 0x0010 /* Interrupt status register */
-#define PIC32MX_INT_INTSTATCLR_OFFSET 0x0014 /* Interrupt status clear register */
-#define PIC32MX_INT_INTSTATSET_OFFSET 0x0018 /* Interrupt status set register */
-#define PIC32MX_INT_INTSTATINV_OFFSET 0x001c /* Interrupt status invert register */
-#define PIC32MX_INT_TPTMR_OFFSET 0x0020 /* Temporal proximity timer register */
-#define PIC32MX_INT_TPTMRCLR_OFFSET 0x0024 /* Temporal proximity timer clear register */
-#define PIC32MX_INT_TPTMRSET_OFFSET 0x0028 /* Temporal proximity timer set register */
-#define PIC32MX_INT_TPTMRINV_OFFSET 0x002c /* Temporal proximity timer invert register */
-#define PIC32MX_INT_IFS_OFFSET(n) (0x0030 + ((n) << 4))
-#define PIC32MX_INT_IFSCLR_OFFSET(n) (0x0034 + ((n) << 4))
-#define PIC32MX_INT_IFSSET_OFFSET(n) (0x0038 + ((n) << 4))
-#define PIC32MX_INT_IFSINV_OFFSET(n) (0x003c + ((n) << 4))
-#define PIC32MX_INT_IFS0_OFFSET 0x0030 /* Interrupt flag status register 0 */
-#define PIC32MX_INT_IFS0CLR_OFFSET 0x0034 /* Interrupt flag status clear register 0 */
-#define PIC32MX_INT_IFS0SET_OFFSET 0x0038 /* Interrupt flag status set register 0 */
-#define PIC32MX_INT_IFS0INV_OFFSET 0x003c /* Interrupt flag status invert register 0 */
-#define PIC32MX_INT_IFS1_OFFSET 0x0040 /* Interrupt flag status register 1 */
-#define PIC32MX_INT_IFS1CLR_OFFSET 0x0044 /* Interrupt flag status clear register 1 */
-#define PIC32MX_INT_IFS1SET_OFFSET 0x0048 /* Interrupt flag status set register 1 */
-#define PIC32MX_INT_IFS1INV_OFFSET 0x004c /* Interrupt flag status invert register 1 */
-#define PIC32MX_INT_IFS2_OFFSET 0x0050 /* Interrupt flag status register 2 */
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IFS2CLR_OFFSET 0x0054 /* Interrupt flag status clear register 2 */
-# define PIC32MX_INT_IFS2SET_OFFSET 0x0058 /* Interrupt flag status set register 2 */
-# define PIC32MX_INT_IFS2INV_OFFSET 0x005c /* Interrupt flag status invert register 2 */
-#endif
-#define PIC32MX_INT_IEC_OFFSET(n) (0x0060 + ((n) << 4))
-#define PIC32MX_INT_IECCLR_OFFSET(n) (0x0064 + ((n) << 4))
-#define PIC32MX_INT_IECSET_OFFSET(n) (0x0068 + ((n) << 4))
-#define PIC32MX_INT_IECINV_OFFSET(n) (0x006c + ((n) << 4))
-#define PIC32MX_INT_IEC0_OFFSET 0x0060 /* Interrupt enable control register 0 */
-#define PIC32MX_INT_IEC0CLR_OFFSET 0x0064 /* Interrupt enable control clear register 0 */
-#define PIC32MX_INT_IEC0SET_OFFSET 0x0068 /* Interrupt enable control set register 0 */
-#define PIC32MX_INT_IEC0INV_OFFSET 0x006c /* Interrupt enable control invert register 0 */
-#define PIC32MX_INT_IEC1_OFFSET 0x0070 /* Interrupt enable control register 1 */
-#define PIC32MX_INT_IEC1CLR_OFFSET 0x0074 /* Interrupt enable control clear register 1 */
-#define PIC32MX_INT_IEC1SET_OFFSET 0x0078 /* Interrupt enable control set register 1 */
-#define PIC32MX_INT_IEC1INV_OFFSET 0x007c /* Interrupt enable control invert register 1 */
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IEC2_OFFSET 0x0080 /* Interrupt enable control register 2 */
-# define PIC32MX_INT_IEC2CLR_OFFSET 0x0084 /* Interrupt enable control clear register 2 */
-# define PIC32MX_INT_IEC2SET_OFFSET 0x0088 /* Interrupt enable control set register 2 */
-# define PIC32MX_INT_IEC2INV_OFFSET 0x008c /* Interrupt enable control invert register 2 */
-#endif
-#define PIC32MX_INT_IPC_OFFSET(n) (0x0090 + ((n) << 4))
-#define PIC32MX_INT_IPCCLR_OFFSET(n) (0x0094 + ((n) << 4))
-#define PIC32MX_INT_IPCSET_OFFSET(n) (0x0098 + ((n) << 4))
-#define PIC32MX_INT_IPCINV_OFFSET(n) (0x009c + ((n) << 4))
-#define PIC32MX_INT_IPC0_OFFSET 0x0090 /* Interrupt priority control register 0 */
-#define PIC32MX_INT_IPC0CLR_OFFSET 0x0094 /* Interrupt priority control clear register 0 */
-#define PIC32MX_INT_IPC0SET_OFFSET 0x0098 /* Interrupt priority control set register 0 */
-#define PIC32MX_INT_IPC0INV_OFFSET 0x009c /* Interrupt priority control invert register 0 */
-#define PIC32MX_INT_IPC1_OFFSET 0x00a0 /* Interrupt priority control register 1 */
-#define PIC32MX_INT_IPC1CLR_OFFSET 0x00a4 /* Interrupt priority control clear register 1 */
-#define PIC32MX_INT_IPC1SET_OFFSET 0x00a8 /* Interrupt priority control set register 1 */
-#define PIC32MX_INT_IPC1INV_OFFSET 0x00ac /* Interrupt priority control invert register 1 */
-#define PIC32MX_INT_IPC2_OFFSET 0x00b0 /* Interrupt priority control register 2 */
-#define PIC32MX_INT_IPC2CLR_OFFSET 0x00b4 /* Interrupt priority control clear register 2 */
-#define PIC32MX_INT_IPC2SET_OFFSET 0x00b8 /* Interrupt priority control set register 2 */
-#define PIC32MX_INT_IPC2INV_OFFSET 0x00bc /* Interrupt priority control invert register 2 */
-#define PIC32MX_INT_IPC3_OFFSET 0x00c0 /* Interrupt priority control register 3 */
-#define PIC32MX_INT_IPC3CLR_OFFSET 0x00c4 /* Interrupt priority control clear register 3 */
-#define PIC32MX_INT_IPC3SET_OFFSET 0x00c8 /* Interrupt priority control set register 3 */
-#define PIC32MX_INT_IPC3INV_OFFSET 0x00cc /* Interrupt priority control invert register 3 */
-#define PIC32MX_INT_IPC4_OFFSET 0x00d0 /* Interrupt priority control register 4 */
-#define PIC32MX_INT_IPC4CLR_OFFSET 0x00d4 /* Interrupt priority control clear register 4 */
-#define PIC32MX_INT_IPC4SET_OFFSET 0x00d8 /* Interrupt priority control set register 4 */
-#define PIC32MX_INT_IPC4INV_OFFSET 0x00dc /* Interrupt priority control invert register 4 */
-#define PIC32MX_INT_IPC5_OFFSET 0x00e0 /* Interrupt priority control register 5 */
-#define PIC32MX_INT_IPC5CLR_OFFSET 0x00e4 /* Interrupt priority control clear register 5 */
-#define PIC32MX_INT_IPC5SET_OFFSET 0x00e8 /* Interrupt priority control set register 5 */
-#define PIC32MX_INT_IPC5INV_OFFSET 0x00ec /* Interrupt priority control invert register 5 */
-#define PIC32MX_INT_IPC6_OFFSET 0x00f0 /* Interrupt priority control register 6 */
-#define PIC32MX_INT_IPC6CLR_OFFSET 0x00f4 /* Interrupt priority control clear register 6 */
-#define PIC32MX_INT_IPC6SET_OFFSET 0x00f8 /* Interrupt priority control set register 6 */
-#define PIC32MX_INT_IPC6INV_OFFSET 0x00fc /* Interrupt priority control invert register 6 */
-#define PIC32MX_INT_IPC7_OFFSET 0x0100 /* Interrupt priority control register 7 */
-#define PIC32MX_INT_IPC7CLR_OFFSET 0x0104 /* Interrupt priority control clear register 7 */
-#define PIC32MX_INT_IPC7SET_OFFSET 0x0108 /* Interrupt priority control set register 7 */
-#define PIC32MX_INT_IPC7INV_OFFSET 0x010c /* Interrupt priority control invert register 7 */
-#define PIC32MX_INT_IPC8_OFFSET 0x0110 /* Interrupt priority control register 8 */
-#define PIC32MX_INT_IPC8CLR_OFFSET 0x0114 /* Interrupt priority control clear register 8 */
-#define PIC32MX_INT_IPC8SET_OFFSET 0x0118 /* Interrupt priority control set register 8 */
-#define PIC32MX_INT_IPC8INV_OFFSET 0x011c /* Interrupt priority control invert register 8 */
-#define PIC32MX_INT_IPC9_OFFSET 0x0120 /* Interrupt priority control register 9 */
-#define PIC32MX_INT_IPC9CLR_OFFSET 0x0124 /* Interrupt priority control clear register 9 */
-#define PIC32MX_INT_IPC9SET_OFFSET 0x0128 /* Interrupt priority control set register 9 */
-#define PIC32MX_INT_IPC9INV_OFFSET 0x012c /* Interrupt priority control invert register 9 */
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IPC10_OFFSET 0x0130 /* Interrupt priority control register 10 */
-# define PIC32MX_INT_IPC10CLR_OFFSET 0x0134 /* Interrupt priority control clear register 10 */
-# define PIC32MX_INT_IPC10SET_OFFSET 0x0138 /* Interrupt priority control set register 10 */
-# define PIC32MX_INT_IPC10INV_OFFSET 0x013c /* Interrupt priority control invert register 10 */
-#endif
-#define PIC32MX_INT_IPC11_OFFSET 0x0140 /* Interrupt priority control register 11 */
-#define PIC32MX_INT_IPC11CLR_OFFSET 0x0144 /* Interrupt priority control clear register 11 */
-#define PIC32MX_INT_IPC11SET_OFFSET 0x0148 /* Interrupt priority control set register 11 */
-#define PIC32MX_INT_IPC11INV_OFFSET 0x014c /* Interrupt priority control invert register 11 */
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IPC12_OFFSET 0x0150 /* Interrupt priority control register 12 */
-# define PIC32MX_INT_IPC12CLR_OFFSET 0x0154 /* Interrupt priority control clear register 12 */
-# define PIC32MX_INT_IPC12SET_OFFSET 0x0158 /* Interrupt priority control set register 12 */
-# define PIC32MX_INT_IPC12INV_OFFSET 0x015c /* Interrupt priority control invert register 12 */
-#endif
-
-/* Register Addresses *******************************************************/
-
-#define PIC32MX_INT_INTCON (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCON_OFFSET)
-#define PIC32MX_INT_INTCONCLR (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCONCLR_OFFSET)
-#define PIC32MX_INT_INTCONSET (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCONSET_OFFSET)
-#define PIC32MX_INT_INTCONINV (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCONINV_OFFSET)
-#define PIC32MX_INT_INTSTAT (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTAT_OFFSET)
-#define PIC32MX_INT_INTSTATCLR (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTATCLR_OFFSET)
-#define PIC32MX_INT_INTSTATSET (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTATSET_OFFSET)
-#define PIC32MX_INT_INTSTATINV (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTATINV_OFFSET)
-#define PIC32MX_INT_TPTMR (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMR_OFFSET)
-#define PIC32MX_INT_TPTMRCLR (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMRCLR_OFFSET)
-#define PIC32MX_INT_TPTMRSET (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMRSET_OFFSET)
-#define PIC32MX_INT_TPTMRINV (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMRINV_OFFSET)
-#define PIC32MX_INT_IFS(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS_OFFSET(n))
-#define PIC32MX_INT_IFSCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFSCLR_OFFSET(n))
-#define PIC32MX_INT_IFSSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFSSET_OFFSET(n))
-#define PIC32MX_INT_IFSINV(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFSINV_OFFSET(n))
-#define PIC32MX_INT_IFS0 (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0_OFFSET)
-#define PIC32MX_INT_IFS0CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0CLR_OFFSET)
-#define PIC32MX_INT_IFS0SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0SET_OFFSET)
-#define PIC32MX_INT_IFS0INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0INV_OFFSET)
-#define PIC32MX_INT_IFS1 (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1_OFFSET)
-#define PIC32MX_INT_IFS1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1CLR_OFFSET)
-#define PIC32MX_INT_IFS1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1SET_OFFSET)
-#define PIC32MX_INT_IFS1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1INV_OFFSET)
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IFS2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2_OFFSET)
-# define PIC32MX_INT_IFS2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2CLR_OFFSET)
-# define PIC32MX_INT_IFS2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2SET_OFFSET)
-# define PIC32MX_INT_IFS2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2INV_OFFSET)
-#endif
-#define PIC32MX_INT_IEC(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC_OFFSET(n))
-#define PIC32MX_INT_IECCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECCLR_OFFSET(n))
-#define PIC32MX_INT_IECSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECSET_OFFSET(n))
-#define PIC32MX_INT_IECINV(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECINV_OFFSET(n))
-#define PIC32MX_INT_IEC0 (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0_OFFSET)
-#define PIC32MX_INT_IEC0CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0CLR_OFFSET)
-#define PIC32MX_INT_IEC0SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0SET_OFFSET)
-#define PIC32MX_INT_IEC0INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0_OFFSET)
-#define PIC32MX_INT_IEC1 (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1_OFFSET)
-#define PIC32MX_INT_IEC1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1CLR_OFFSET)
-#define PIC32MX_INT_IEC1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1SET_OFFSET)
-#define PIC32MX_INT_IEC1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1INV_OFFSET)
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IEC2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2_OFFSET)
-# define PIC32MX_INT_IEC2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2CLR_OFFSET)
-# define PIC32MX_INT_IEC2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2SET_OFFSET)
-# define PIC32MX_INT_IEC2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2INV_OFFSET)
-#endif
-#define PIC32MX_INT_IPC(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC_OFFSET(n))
-#define PIC32MX_INT_IPCCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCCLR_OFFSET(n))
-#define PIC32MX_INT_IPCSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCSET_OFFSET(n))
-#define PIC32MX_INT_IPCINV(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCINV_OFFSET(n))
-#define PIC32MX_INT_IPC0 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0_OFFSET)
-#define PIC32MX_INT_IPC0CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0CLR_OFFSET)
-#define PIC32MX_INT_IPC0SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0SET_OFFSET)
-#define PIC32MX_INT_IPC0INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0INV_OFFSET)
-#define PIC32MX_INT_IPC1 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1_OFFSET)
-#define PIC32MX_INT_IPC1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1CLR_OFFSET)
-#define PIC32MX_INT_IPC1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1SET_OFFSET)
-#define PIC32MX_INT_IPC1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1INV_OFFSET)
-#define PIC32MX_INT_IPC2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2_OFFSET)
-#define PIC32MX_INT_IPC2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2CLR_OFFSET)
-#define PIC32MX_INT_IPC2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2SET_OFFSET)
-#define PIC32MX_INT_IPC2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2INV_OFFSET)
-#define PIC32MX_INT_IPC3 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3_OFFSET)
-#define PIC32MX_INT_IPC3CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3CLR_OFFSET)
-#define PIC32MX_INT_IPC3SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3SET_OFFSET)
-#define PIC32MX_INT_IPC3INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3INV_OFFSET)
-#define PIC32MX_INT_IPC4 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4_OFFSET)
-#define PIC32MX_INT_IPC4CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4CLR_OFFSET)
-#define PIC32MX_INT_IPC4SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4SET_OFFSET)
-#define PIC32MX_INT_IPC4INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4INV_OFFSET)
-#define PIC32MX_INT_IPC5 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5_OFFSET)
-#define PIC32MX_INT_IPC5CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5CLR_OFFSET)
-#define PIC32MX_INT_IPC5SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5SET_OFFSET)
-#define PIC32MX_INT_IPC5INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5INV_OFFSET)
-#define PIC32MX_INT_IPC6 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6_OFFSET)
-#define PIC32MX_INT_IPC6CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6CLR_OFFSET)
-#define PIC32MX_INT_IPC6SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6SET_OFFSET)
-#define PIC32MX_INT_IPC6INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6INV_OFFSET)
-#define PIC32MX_INT_IPC7 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7_OFFSET)
-#define PIC32MX_INT_IPC7CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7CLR_OFFSET)
-#define PIC32MX_INT_IPC7SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7SET_OFFSET)
-#define PIC32MX_INT_IPC7INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7INV_OFFSET)
-#define PIC32MX_INT_IPC8 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8_OFFSET)
-#define PIC32MX_INT_IPC8CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8CLR_OFFSET)
-#define PIC32MX_INT_IPC8SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8SET_OFFSET)
-#define PIC32MX_INT_IPC8INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8INV_OFFSET)
-#define PIC32MX_INT_IPC9 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9_OFFSET)
-#define PIC32MX_INT_IPC9CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9CLR_OFFSET)
-#define PIC32MX_INT_IPC9SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9SET_OFFSET)
-#define PIC32MX_INT_IPC9INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9INV_OFFSET)
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IPC10 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10_OFFSET)
-# define PIC32MX_INT_IPC10CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10CLR_OFFSET)
-# define PIC32MX_INT_IPC10SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10SET_OFFSET)
-# define PIC32MX_INT_IPC10INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10INV_OFFSET)
-#endif
-#define PIC32MX_INT_IPC11 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11_OFFSET)
-#define PIC32MX_INT_IPC11CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11CLR_OFFSET)
-#define PIC32MX_INT_IPC11SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11SET_OFFSET)
-#define PIC32MX_INT_IPC11INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11INV_OFFSET)
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-# define PIC32MX_INT_IPC12 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12_OFFSET)
-# define PIC32MX_INT_IPC12CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12CLR_OFFSET)
-# define PIC32MX_INT_IPC12SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12SET_OFFSET)
-# define PIC32MX_INT_IPC12INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12INV_OFFSET)
-#endif
-
-/* Register Bit-Field Definitions *******************************************/
-
-/* Interrupt control register */
-
-#define INT_INTCON_INT0EP (1 << 0) /* Bit 0: External interrupt 0 edge polarity control */
-#define INT_INTCON_INT1EP (1 << 1) /* Bit 1: External interrupt 1 edge polarity control */
-#define INT_INTCON_INT2EP (1 << 2) /* Bit 2: External interrupt 2 edge polarity control */
-#define INT_INTCON_INT3EP (1 << 3) /* Bit 3: External interrupt 3 edge polarity control */
-#define INT_INTCON_INT4EP (1 << 4) /* Bit 4: External interrupt 4 edge polarity control */
-#define INT_INTCON_TPC_SHIFT (8) /* Bits 8-10: Temporal proximity control */
-#define INT_INTCON_TPC_MASK (7 << INT_INTCON_TPC_SHIFT)
-# define INT_INTCON_TPC_DIS (0 << INT_INTCON_TPC_SHIFT) /* Disables proximity timer */
-# define INT_INTCON_TPC_PRIO1 (1 << INT_INTCON_TPC_SHIFT) /* Int group priority 1 start IP timer */
-# define INT_INTCON_TPC_PRIO2 (2 << INT_INTCON_TPC_SHIFT) /* Int group priority <=2 start TP timer */
-# define INT_INTCON_TPC_PRIO3 (3 << INT_INTCON_TPC_SHIFT) /* Int group priority <=3 start TP timer */
-# define INT_INTCON_TPC_PRIO4 (4 << INT_INTCON_TPC_SHIFT) /* Int group priority <=4 start TP timer */
-# define INT_INTCON_TPC_PRIO5 (5 << INT_INTCON_TPC_SHIFT) /* Int group priority <=5 start TP timer */
-# define INT_INTCON_TPC_PRIO6 (6 << INT_INTCON_TPC_SHIFT) /* Int group priority <=6 start TP timer */
-# define INT_INTCON_TPC_PRIO7 (7 << INT_INTCON_TPC_SHIFT) /* Int group priority <=7 start TP timer */
-#define INT_INTCON_MVEC (1 << 12) /* Bit 12: Multi vector configuration */
-#define INT_INTCON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
-#define INT_INTCON_SS0 (1 << 16) /* Bit 16: Single vector shadow register set */
-
-/* Interrupt status register */
-
-#define INT_INTSTAT_VEC_SHIFT (0) /* Bits 0-5: Interrupt vector */
-#define INT_INTSTAT_VEC_MASK (0x3f << INT_INTSTAT_VEC_SHIFT)
-#define INT_INTSTAT_RIPL_SHIFT (8) /* Bits 8-10: Requested priority level */
-#define INT_INTSTAT_RIPL_MASK (7 << INT_INTSTAT_RIPL_SHIFT)
-
-/* Temporal proximity timer register -- This register contains a 32-bit value
- * with no field definitions.
- */
-
-/* Interrupt flag status register 0 and Interrupt enable control register 0 */
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-# define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */
-# define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */
-# define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */
-# define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */
-# define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */
-# define INT_IC1 (1 << 5) /* Vector: 5, Input Capture 1 */
-# define INT_OC1 (1 << 6) /* Vector: 6, Output Compare 1 */
-# define INT_INT1 (1 << 7) /* Vector: 7, External Interrupt 1 */
-# define INT_T2 (1 << 8) /* Vector: 8, Timer 2 */
-# define INT_IC2 (1 << 9) /* Vector: 9, Input Capture 2 */
-# define INT_OC2 (1 << 10) /* Vector: 10, Output Compare 2 */
-# define INT_INT2 (1 << 11) /* Vector: 11, External Interrupt 2 */
-# define INT_T3 (1 << 12) /* Vector: 12, Timer 3 */
-# define INT_IC3 (1 << 13) /* Vector: 13, Input Capture 3 */
-# define INT_OC3 (1 << 14) /* Vector: 14, Output Compare 3 */
-# define INT_INT3 (1 << 15) /* Vector: 15, External Interrupt 3 */
-# define INT_T4 (1 << 16) /* Vector: 16, Timer 4 */
-# define INT_IC4 (1 << 17) /* Vector: 17, Input Capture 4 */
-# define INT_OC4 (1 << 18) /* Vector: 18, Output Compare 4 */
-# define INT_INT4 (1 << 19) /* Vector: 19, External Interrupt 4 */
-# define INT_T5 (1 << 20) /* Vector: 20, Timer 5 */
-# define INT_IC5 (1 << 21) /* Vector: 21, Input Capture 5 */
-# define INT_OC5 (1 << 22) /* Vector: 22, Output Compare 5 */
-# define INT_SPI1E (1 << 23) /* Vector: 23, SPI1 Error */
-# define INT_SPI1TX (1 << 24) /* Vector: 23, " " Transfer done */
-# define INT_SPI1RX (1 << 25) /* Vector: 23, " " Receive done */
-# define INT_U1E (1 << 26) /* Vector: 24, UART1 Error */
-# define INT_U1RX (1 << 27) /* Vector: 24, " " Receiver */
-# define INT_U1TX (1 << 28) /* Vector: 24, " " Transmitter */
-# define INT_I2C1B (1 << 29) /* Vector: 25, I2C1 Bus collision event */
-# define INT_I2C1S (1 << 30) /* Vector: 25, " " Slave event */
-# define INT_I2C1M (1 << 31) /* Vector: 25, " " Master event */
-
-#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */
-# define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */
-# define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */
-# define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */
-# define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */
-# define INT_IC1 (1 << 5) /* Vector: 5, Input Capture 1 */
-# define INT_OC1 (1 << 6) /* Vector: 6, Output Compare 1 */
-# define INT_INT1 (1 << 7) /* Vector: 7, External Interrupt 1 */
-# define INT_T2 (1 << 8) /* Vector: 8, Timer 2 */
-# define INT_IC2 (1 << 9) /* Vector: 9, Input Capture 2 */
-# define INT_OC2 (1 << 10) /* Vector: 10, Output Compare 2 */
-# define INT_INT2 (1 << 11) /* Vector: 11, External Interrupt 2 */
-# define INT_T3 (1 << 12) /* Vector: 12, Timer 3 */
-# define INT_IC3 (1 << 13) /* Vector: 13, Input Capture 3 */
-# define INT_OC3 (1 << 14) /* Vector: 14, Output Compare 3 */
-# define INT_INT3 (1 << 15) /* Vector: 15, External Interrupt 3 */
-# define INT_T4 (1 << 16) /* Vector: 16, Timer 4 */
-# define INT_IC4 (1 << 17) /* Vector: 17, Input Capture 4 */
-# define INT_OC4 (1 << 18) /* Vector: 18, Output Compare 4 */
-# define INT_INT4 (1 << 19) /* Vector: 19, External Interrupt 4 */
-# define INT_T5 (1 << 20) /* Vector: 20, Timer 5 */
-# define INT_IC5 (1 << 21) /* Vector: 21, Input Capture 5 */
-# define INT_OC5 (1 << 22) /* Vector: 22, Output Compare 5 */
-# define INT_SPI1E (1 << 23) /* Vector: 23, SPI1 Error */
-# define INT_SPI1TX (1 << 24) /* Vector: 23, " " Transfer done */
-# define INT_SPI1RX (1 << 25) /* Vector: 23, " " Receive done */
-# define INT_26 (1 << 26) /* Vector: 24, UART1, SPI3, I2C3 */
-# define INT_U1E (1 << 26) /* Vector: 24, UART1 Error */
-# define INT_SPI3E (1 << 26) /* Vector: 24, SPI3 Fault */
-# define INT_I2C3B (1 << 26) /* Vector: 24, I2C3 Bus collision event */
-# define INT_27 (1 << 27) /* Vector: 24, UART1, SPI3, I2C3 */
-# define INT_U1RX (1 << 27) /* Vector: 24, UART1 Receiver */
-# define INT_SPI3RX (1 << 27) /* Vector: 24, SPI3 Receive done */
-# define INT_I2C3S (1 << 27) /* Vector: 24, I2C3 Slave event */
-# define INT_28 (1 << 28) /* Vector: 24, UART1, SPI3, I2C3 */
-# define INT_U1TX (1 << 28) /* Vector: 24, UART1 Transmitter */
-# define INT_SPI3TX (1 << 28) /* Vector: 24, SPI3 Transfer done */
-# define INT_I2C3M (1 << 28) /* Vector: 24, I2C3 Master event */
-# define INT_I2C1B (1 << 29) /* Vector: 25, I2C1 Bus collision event */
-# define INT_I2C1S (1 << 30) /* Vector: 25, " " Slave event */
-# define INT_I2C1M (1 << 31) /* Vector: 25, " " Master event */
-
-#else
-# error "Unknown PIC32MX family
-#endif
-
-/* Interrupt flag status register 1 and Interrupt enable control register 1 */
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-# define INT_CN (1 << 0) /* Vector: 26, Input Change Interrupt */
-# define INT_AD1 (1 << 1) /* Vector: 27, ADC1 Convert Done */
-# define INT_PMP (1 << 2) /* Vector: 28, Parallel Master Port */
-# define INT_CMP1 (1 << 3) /* Vector: 29, Comparator Interrupt */
-# define INT_CMP2 (1 << 4) /* Vector: 30, Comparator Interrupt */
-# define INT_SPI2E (1 << 5) /* Vector: 31, SPI2 Error */
-# define INT_SPI2TX (1 << 6) /* Vector: 31, " " Transfer done */
-# define INT_SPI2RX (1 << 7) /* Vector: 31, " " Receive done*/
-# define INT_U2E (1 << 8) /* Vector: 32, UART2 Error */
-# define INT_U2RX (1 << 9) /* Vector: 32, " " Receiver */
-# define INT_U2TX (1 << 10) /* Vector: 32, " " Transmitter */
-# define INT_I2C2B (1 << 11) /* Vector: 33, I2C2 Bus collision event */
-# define INT_I2C2S (1 << 12) /* Vector: 33, " " Master event */
-# define INT_I2C2M (1 << 13) /* Vector: 33, " " Slave event */
-# define INT_FSCM (1 << 14) /* Vector: 34, Fail-Safe Clock Monitor */
-# define INT_RTCC (1 << 15) /* Vector: 35, Real-Time Clock and Calendar */
-# define INT_DMA0 (1 << 16) /* Vector: 36, DMA Channel 0 */
-# define INT_DMA1 (1 << 17) /* Vector: 37, DMA Channel 1 */
-# define INT_DMA2 (1 << 18) /* Vector: 38, DMA Channel 2 */
-# define INT_DMA3 (1 << 19) /* Vector: 39, DMA Channel 3 */
-# define INT_FCE (1 << 24) /* Vector: 44, Flash Control Event */
-# define INT_USB (1 << 25) /* Vector: 45, USB Interrupt */
-
-#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define INT_CN (1 << 0) /* Vector: 26, Input Change Interrupt */
-# define INT_AD1 (1 << 1) /* Vector: 27, ADC1 Convert Done */
-# define INT_PMP (1 << 2) /* Vector: 28, Parallel Master Port */
-# define INT_CMP1 (1 << 3) /* Vector: 29, Comparator Interrupt */
-# define INT_CMP2 (1 << 4) /* Vector: 30, Comparator Interrupt */
-# define INT_37 (1 << 5) /* Vector: 31, UART3, SPI2, I2C4 */
-# define INT_U3E (1 << 5) /* Vector: 31, UART3 Error */
-# define INT_SPI2E (1 << 5) /* Vector: 31, SPI2 Fault */
-# define INT_I2C4B (1 << 5) /* Vector: 31, I2C4 Bus collision event */
-# define INT_38 (1 << 6) /* Vector: 31, UART3, SPI2, I2C4 */
-# define INT_U3RX (1 << 6) /* Vector: 31, UART3 Receiver */
-# define INT_SPI2RX (1 << 6) /* Vector: 31, SPI2 Receive done */
-# define INT_I2C4S (1 << 6) /* Vector: 31, I2C4 Slave event */
-# define INT_39 (1 << 7) /* Vector: 31, UART3, SPI2, I2C4 */
-# define INT_U3TX (1 << 7) /* Vector: 31, UART3 Transmitter */
-# define INT_SPI2TX (1 << 7) /* Vector: 31, SPI2 Transfer done */
-# define INT_I2C4M (1 << 7) /* Vector: 31, I2C4 Master event */
-# define INT_40 (1 << 8) /* Vector: 32, UART2, SPI4, I2C5 */
-# define INT_U2E (1 << 8) /* Vector: 32, UART2 Error */
-# define INT_SPI4E (1 << 8) /* Vector: 32, SPI4 Fault */
-# define INT_I2C5B (1 << 8) /* Vector: 32, I2C5 Bus collision event */
-# define INT_41 (1 << 9) /* Vector: 32, UART2, SPI4, I2C5 */
-# define INT_U2RX (1 << 9) /* Vector: 32, UART2 Receiver */
-# define INT_SPI4RX (1 << 9) /* Vector: 32, SPI4 Receive done */
-# define INT_I2C5S (1 << 9) /* Vector: 32, I2C5 Slave event */
-# define INT_42 (1 << 10) /* Vector: 32, UART2, SPI4, I2C5 */
-# define INT_U2TX (1 << 10) /* Vector: 32, UART2 Transmitter */
-# define INT_SPI4TX (1 << 10) /* Vector: 32, SPI4 Transfer done */
-# define INT_I2C5M (1 << 10) /* Vector: 32, I2C5 Master event */
-# define INT_I2C2B (1 << 11) /* Vector: 33, I2C2 Bus collision event */
-# define INT_I2C2S (1 << 12) /* Vector: 33, " " Master event */
-# define INT_I2C2M (1 << 13) /* Vector: 33, " " Slave event */
-# define INT_FSCM (1 << 14) /* Vector: 34, Fail-Safe Clock Monitor */
-# define INT_RTCC (1 << 15) /* Vector: 35, Real-Time Clock and Calendar */
-# define INT_DMA0 (1 << 16) /* Vector: 36, DMA Channel 0 */
-# define INT_DMA1 (1 << 17) /* Vector: 37, DMA Channel 1 */
-# define INT_DMA2 (1 << 18) /* Vector: 38, DMA Channel 2 */
-# define INT_DMA3 (1 << 19) /* Vector: 39, DMA Channel 3 */
-# define INT_DMA4 (1 << 20) /* Vector: 40, DMA Channel 3 */
-# define INT_DMA5 (1 << 21) /* Vector: 41, DMA Channel 3 */
-# define INT_DMA6 (1 << 22) /* Vector: 42, DMA Channel 3 */
-# define INT_DMA7 (1 << 23) /* Vector: 43, DMA Channel 3 */
-# define INT_FCE (1 << 24) /* Vector: 44, Flash Control Event */
-# define INT_USB (1 << 25) /* Vector: 45, USB Interrupt */
-# define INT_CAN1 (1 << 26) /* Vector: 46, Control Area Network 1 */
-# define INT_CAN2 (1 << 27) /* Vector: 47, Control Area Network 2 */
-# define INT_ETH (1 << 28) /* Vector: 48, Ethernet interrupt */
-# define INT_IC1E (1 << 29) /* Vector: 5, Input capture 1 error */
-# define INT_IC2E (1 << 30) /* Vector: 9, Input capture 1 error */
-# define INT_IC3E (1 << 31) /* Vector: 13, Input capture 1 error */
-
-#else
-# error "Unknown PIC32MX family
-#endif
-
-/* Interrupt flag status register 2 and Interrupt enable control register 2 */
-
-#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define INT_IC4E (1 << 0) /* Vector: 17, Input capture 1 error */
-# define INT_IC5E (1 << 1) /* Vector: 21, Input capture 1 error */
-# define INT_PMPE (1 << 2) /* Vector: 28, Parallel master port error */
-# define INT_U4E (1 << 3) /* Vector: 49, UART4 Error */
-# define INT_U4RX (1 << 4) /* Vector: 49, UART4 Receiver */
-# define INT_U4TX (1 << 5) /* Vector: 49, UART4 Transmitter */
-# define INT_U6E (1 << 6) /* Vector: 50, UART6 Error */
-# define INT_U6RX (1 << 7) /* Vector: 50, UART6 Receiver */
-# define INT_U6TX (1 << 8) /* Vector: 50, UART6 Transmitter */
-# define INT_U5E (1 << 9) /* Vector: 51, UART5 Error */
-# define INT_U5RX (1 << 10) /* Vector: 51, UART5 Receiver */
-# define INT_U5TX (1 << 11) /* Vector: 51, UART5 Transmitter */
-
-#endif
-
-/* Interrupt priority control register 0-11 */
-
-#define INT_ICP_DISABLED 0 /* Disabled! */
-#define INT_ICP_MIN_PRIORITY 1 /* Minimum (enabled) priority */
-#define INT_ICP_MID_PRIORITY 4 /* Can be used as the default */
-#define INT_ICP_MAX_PRIORITY 7 /* Maximum priority */
-#define INT_ICP_MIN_SUBPRIORITY 0 /* Minimum sub-priority */
-#define INT_ICP_MAX_SUBPRIORITY 0 /* Maximum sub-priority */
-
-#define INT_IPC0_CTIS_SHIFT (0) /* Bits 0-1, Vector: 0, Core Timer Interrupt */
-#define INT_IPC0_CTIS_MASK (3 << INT_IPC0_CTIS_SHIFT)
-#define INT_IPC0_CTIP_SHIFT (2) /* Bits 2-4, Vector: 0, Core Timer Interrupt */
-#define INT_IPC0_CTIP_MASK (7 << INT_IPC0_CTIP_SHIFT)
-#define INT_IPC0_CS0IS_SHIFT (8) /* Bits 8-9, Vector: 1, Core Software Interrupt 0 */
-#define INT_IPC0_CS0IS_MASK (3 << INT_IPC0_CS0IS_SHIFT)
-#define INT_IPC0_CS0IP_SHIFT (10) /* Bits 10-12, Vector: 1, Core Software Interrupt 0 */
-#define INT_IPC0_CS0IP_MASK (7 << INT_IPC0_CS0IP_SHIFT)
-#define INT_IPC0_CS1IS_SHIFT (16) /* Bits 16-17, Vector: 2, Core Software Interrupt 1 */
-#define INT_IPC0_CS1IS_MASK (3 << INT_IPC0_CS1IS_SHIFT)
-#define INT_IPC0_CS1IP_SHIFT (18) /* Bits 18-20, Vector: 2, Core Software Interrupt 1 */
-#define INT_IPC0_CS1IP_MASK (7 << INT_IPC0_CS1IP_SHIFT)
-#define INT_IPC0_INT0IS_SHIFT (24) /* Bits 24-25, Vector: 3, External Interrupt 0 */
-#define INT_IPC0_INT0IS_MASK (3 << INT_IPC0_INT0IS_SHIFT)
-#define INT_IPC0_INT0IP_SHIFT (26) /* Bits 26-28, Vector: 3, External Interrupt 0 */
-#define INT_IPC0_INT0IP_MASK (7 << INT_IPC0_INT0IP_SHIFT)
-
-#define INT_IPC1_T1IS_SHIFT (0) /* Bits 0-1, Vector: 4, Timer 1 */
-#define INT_IPC1_T1IS_MASK (3 << INT_IPC1_T1IS_SHIFT)
-#define INT_IPC1_T1IP_SHIFT (2) /* Bits 2-4, Vector: 4, Timer 1 */
-#define INT_IPC1_T1IP_MASK (7 << INT_IPC1_T1IP_SHIFT)
-#define INT_IPC1_IC1IS_SHIFT (8) /* Bits 8-9, Vector: 5, Input Capture 1 */
-#define INT_IPC1_IC1IS_MASK (3 << INT_IPC1_IC1IS_SHIFT)
-#define INT_IPC1_IC1IP_SHIFT (10) /* Bits 10-12, Vector: 5, Input Capture 1 */
-#define INT_IPC1_IC1IP_MASK (7 << INT_IPC1_IC1IP_SHIFT)
-#define INT_IPC1_OC1IS_SHIFT (16) /* Bits 16-17, Vector: 6, Output Compare 1 */
-#define INT_IPC1_OC1IS_MASK (3 << INT_IPC1_OC1IS_SHIFT)
-#define INT_IPC1_OC1IP_SHIFT (18) /* Bits 18-20, Vector: 6, Output Compare 1 */
-#define INT_IPC1_OC1IP_MASK (7 << INT_IPC1_OC1IP_SHIFT)
-#define INT_IPC1_INT1IS_SHIFT (24) /* Bits 24-25, Vector: 7, External Interrupt 1 */
-#define INT_IPC1_INT1IS_MASK (3 << INT_IPC1_INT1IS_SHIFT)
-#define INT_IPC1_INT1IP_SHIFT (26) /* Bits 26-28, Vector: 7, External Interrupt 1 */
-#define INT_IPC1_INT1IP_MASK (7 << INT_IPC1_INT1IP_SHIFT)
-
-#define INT_IPC2_T2IS_SHIFT (0) /* Bits 0-1, Vector: 8, Timer 2 */
-#define INT_IPC2_T2IS_MASK (3 << INT_IPC2_T2IS_SHIFT)
-#define INT_IPC2_T2IP_SHIFT (2) /* Bits 2-4, Vector: 8, Timer 2 */
-#define INT_IPC2_T2IP_MASK (7 << INT_IPC2_T2IP_SHIFT)
-#define INT_IPC2_IC2IS_SHIFT (8) /* Bits 8-9, Vector: 9, Input Capture 2 */
-#define INT_IPC2_IC2IS_MASK (3 << INT_IPC2_IC2IS_SHIFT)
-#define INT_IPC2_IC2IP_SHIFT (10) /* Bits 10-12, Vector: 9, Input Capture 2 */
-#define INT_IPC2_IC2IP_MASK (7 << INT_IPC2_IC2IP_SHIFT)
-#define INT_IPC2_OC2IS_SHIFT (16) /* Bits 16-17, Vector: 10, Output Compare 2 */
-#define INT_IPC2_OC2IS_MASK (3 << INT_IPC2_OC2IS_SHIFT)
-#define INT_IPC2_OC2IP_SHIFT (18) /* Bits 18-20, Vector: 10, Output Compare 2 */
-#define INT_IPC2_OC2IP_MASK (7 << INT_IPC2_OC2IP_SHIFT)
-#define INT_IPC2_INT2IS_SHIFT (24) /* Bits 24-25, Vector: 11, External Interrupt 2 */
-#define INT_IPC2_INT2IS_MASK (3 << INT_IPC2_INT2IS_SHIFT)
-#define INT_IPC2_INT2IP_SHIFT (26) /* Bits 26-28, Vector: 11, External Interrupt 2 */
-#define INT_IPC2_INT2IP_MASK (7 << INT_IPC2_INT2IP_SHIFT)
-
-#define INT_IPC3_T3IS_SHIFT (0) /* Bits 0-1, Vector: 12, Timer 3 */
-#define INT_IPC3_T3IS_MASK (3 << INT_IPC3_T3IS_SHIFT)
-#define INT_IPC3_T3IP_SHIFT (2) /* Bits 2-4, Vector: 12, Timer 3 */
-#define INT_IPC3_T3IP_MASK (7 << INT_IPC3_T3IP_SHIFT)
-#define INT_IPC3_IC3IS_SHIFT (8) /* Bits 8-9, Vector: 13, Input Capture 3 */
-#define INT_IPC3_IC3IS_MASK (3 << INT_IPC3_IC3IS_SHIFT)
-#define INT_IPC3_IC3IP_SHIFT (10) /* Bits 10-12, Vector: 13, Input Capture 3 */
-#define INT_IPC3_IC3IP_MASK (7 << INT_IPC3_IC3IP_SHIFT)
-#define INT_IPC3_OC3IS_SHIFT (16) /* Bits 16-17, Vector: 14, Output Compare 3 */
-#define INT_IPC3_OC3IS_MASK (3 << INT_IPC3_OC3IS_SHIFT)
-#define INT_IPC3_OC3IP_SHIFT (18) /* Bits 18-20, Vector: 14, Output Compare 3 */
-#define INT_IPC3_OC3IP_MASK (7 << INT_IPC3_OC3IP_SHIFT)
-#define INT_IPC3_INT3IS_SHIFT (24) /* Bits 24-25, Vector: 15, External Interrupt 3 */
-#define INT_IPC3_INT3IS_MASK (3 << INT_IPC3_INT3IS_SHIFT)
-#define INT_IPC3_INT3IP_SHIFT (26) /* Bits 26-28, Vector: 15, External Interrupt 3 */
-#define INT_IPC3_INT3IP_MASK (7 << INT_IPC3_INT3IP_SHIFT)
-
-#define INT_IPC4_T4IS_SHIFT (0) /* Bits 0-1, Vector: 16, Timer 4 */
-#define INT_IPC4_T4IS_MASK (3 << INT_IPC4_T4IS_SHIFT)
-#define INT_IPC4_T4IP_SHIFT (2) /* Bits 2-4, Vector: 16, Timer 4 */
-#define INT_IPC4_T4IP_MASK (7 << INT_IPC4_T4IP_SHIFT)
-#define INT_IPC4_IC4IS_SHIFT (8) /* Bits 8-9, Vector: 17, Input Capture 4 */
-#define INT_IPC4_IC4IS_MASK (3 << INT_IPC4_IC4IS_SHIFT)
-#define INT_IPC4_IC4IP_SHIFT (10) /* Bits 10-12, Vector: 17, Input Capture 4 */
-#define INT_IPC4_IC4IP_MASK (7 << INT_IPC4_IC4IP_SHIFT)
-#define INT_IPC4_OC4IS_SHIFT (16) /* Bits 16-17, Vector: 18, Output Compare 4 */
-#define INT_IPC4_OC4IS_MASK (3 << INT_IPC4_OC4IS_SHIFT)
-#define INT_IPC4_OC4IP_SHIFT (18) /* Bits 18-20, Vector: 18, Output Compare 4 */
-#define INT_IPC4_OC4IP_MASK (7 << INT_IPC4_OC4IP_SHIFT)
-#define INT_IPC4_INT4IS_SHIFT (24) /* Bits 24-25, Vector: 19, External Interrupt 4 */
-#define INT_IPC4_INT4IS_MASK (3 << INT_IPC4_INT4IS_SHIFT)
-#define INT_IPC4_INT4IP_SHIFT (26) /* Bits 26-28, Vector: 19, External Interrupt 4 */
-#define INT_IPC4_INT4IP_MASK (7 << INT_IPC4_INT4IP_SHIFT)
-
-#define INT_IPC5_T5IS_SHIFT (0) /* Bits 0-1, Vector: 20, Timer 5 */
-#define INT_IPC5_T5IS_MASK (3 << INT_IPC5_T5IS_SHIFT)
-#define INT_IPC5_T5IP_SHIFT (2) /* Bits 2-4, Vector: 20, Timer 5 */
-#define INT_IPC5_T5IP_MASK (7 << INT_IPC5_T5IP_SHIFT)
-#define INT_IPC5_IC5IS_SHIFT (8) /* Bits 8-9, Vector: 21, Input Capture 5 */
-#define INT_IPC5_IC5IS_MASK (3 << INT_IPC5_IC5IS_SHIFT)
-#define INT_IPC5_IC5IP_SHIFT (10) /* Bits 10-12, Vector: 21, Input Capture 5 */
-#define INT_IPC5_IC5IP_MASK (7 << INT_IPC5_IC5IP_SHIFT)
-#define INT_IPC5_OC5IS_SHIFT (16) /* Bits 16-17, Vector: 22, Output Compare 5 */
-#define INT_IPC5_OC5IS_MASK (3 << INT_IPC5_OC5IS_SHIFT)
-#define INT_IPC5_OC5IP_SHIFT (18) /* Bits 18-20, Vector: 22, Output Compare 5 */
-#define INT_IPC5_OC5IP_MASK (7 << INT_IPC5_OC5IP_SHIFT)
-#define INT_IPC5_SPI1IS_SHIFT (24) /* Bits 24-25, Vector: 23, SPI1 */
-#define INT_IPC5_SPI1IS_MASK (3 << INT_IPC5_SPI1IS_SHIFT)
-#define INT_IPC5_SPI1IP_SHIFT (26) /* Bits 26-28, Vector: 23, SPI1 */
-#define INT_IPC5_SPI1IP_MASK (7 << INT_IPC5_SPI1IP_SHIFT)
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-# define INT_IPC6_U1IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1 */
-# define INT_IPC6_U1IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
-# define INT_IPC6_U1IP_SHIFT (2) /* Bits 2-4, Vector: 24, UART1 */
-# define INT_IPC6_U1IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
-# define INT_IPC6_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 25, I2C1 */
-# define INT_IPC6_I2C1IS_MASK (3 << INT_IPC6_I2C1IS_SHIFT)
-# define INT_IPC6_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 25, I2C1 */
-# define INT_IPC6_I2C1IP_MASK (7 << INT_IPC6_I2C1IP_SHIFT)
-# define INT_IPC6_CNIS_SHIFT (16) /* Bits 16-17, Vector: 26, Input Change Interrupt */
-# define INT_IPC6_CNIS_MASK (3 << INT_IPC6_CNIS_SHIFT)
-# define INT_IPC6_CNIP_SHIFT (18) /* Bits 18-20, Vector: 26, Input Change Interrupt */
-# define INT_IPC6_CNIP_MASK (7 << INT_IPC6_CNIP_SHIFT)
-# define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 27, ADC1 Convert Done */
-# define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT)
-# define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 27, ADC1 Convert Done */
-# define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT)
-
-# define INT_IPC7_PMPIS_SHIFT (0) /* Bits 0-1, Vector: 28, Parallel Master Port */
-# define INT_IPC7_PMPIS_MASK (3 << INT_IPC7_PMPIS_SHIFT)
-# define INT_IPC7_PMPIP_SHIFT (2) /* Bits 2-4, Vector: 28, Parallel Master Port */
-# define INT_IPC7_PMPIP_MASK (7 << INT_IPC7_PMPIP_SHIFT)
-# define INT_IPC7_CMP1IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */
-# define INT_IPC7_CMP1IS_MASK (3 << INT_IPC7_CMP1IS_SHIFT)
-# define INT_IPC7_CMP1IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */
-# define INT_IPC7_CMP1IP_MASK (7 << INT_IPC7_CMP1IP_SHIFT)
-# define INT_IPC7_CMP2IS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */
-# define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT)
-# define INT_IPC7_CMP2IP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */
-# define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT)
-# define INT_IPC7_SPI2IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI2 */
-# define INT_IPC7_SPI2IS_MASK (3 << INT_IPC7_SPI2IS_SHIFT)
-# define INT_IPC7_SPI2IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI2 */
-# define INT_IPC7_SPI2IP_MASK (7 << INT_IPC7_SPI2IP_SHIFT)
-
-# define INT_IPC8_U2IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2 */
-# define INT_IPC8_U2IS_MASK (3 << INT_IPC8_U2IS_SHIFT)
-# define INT_IPC8_U2IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART2 */
-# define INT_IPC8_U2IP_MASK (7 << INT_IPC8_U2IP_SHIFT)
-# define INT_IPC8_I2C2IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C2 */
-# define INT_IPC8_I2C2IS_MASK (3 << INT_IPC8_I2C2IS_SHIFT)
-# define INT_IPC8_I2C2IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C2 */
-# define INT_IPC8_I2C2IP_MASK (7 << INT_IPC8_I2C2IP_SHIFT)
-# define INT_IPC8_FSCMIS_SHIFT (16) /* Bits 16-17, Vector: 34, Fail-Safe Clock Monitor */
-# define INT_IPC8_FSCMIS_MASK (3 << INT_IPC8_FSCMIS_SHIFT)
-# define INT_IPC8_FSCMIP_SHIFT (18) /* Bits 18-20, Vector: 34, Fail-Safe Clock Monitor */
-# define INT_IPC8_FSCMIP_MASK (7 << INT_IPC8_FSCMIP_SHIFT)
-# define INT_IPC8_RTCCIS_SHIFT (24) /* Bits 24-25, Vector: 35, Real-Time Clock and Calendar */
-# define INT_IPC8_RTCCIS_MASK (3 << INT_IPC8_RTCCIS_SHIFT)
-# define INT_IPC8_RTCCIP_SHIFT (26) /* Bits 26-28, Vector: 35, Real-Time Clock and Calendar */
-# define INT_IPC8_RTCCIP_MASK (7 << INT_IPC8_RTCCIP_SHIFT)
-
-# define INT_IPC9_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 0 */
-# define INT_IPC9_DMA0IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT)
-# define INT_IPC9_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 0 */
-# define INT_IPC9_DMA0IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT)
-# define INT_IPC9_DMA1IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 1 */
-# define INT_IPC9_DMA1IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT)
-# define INT_IPC9_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 1 */
-# define INT_IPC9_DMA1IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT)
-# define INT_IPC9_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 2 */
-# define INT_IPC9_DMA2IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
-# define INT_IPC9_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 2 */
-# define INT_IPC9_DMA2IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
-# define INT_IPC9_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 3 */
-# define INT_IPC9_DMA3IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
-# define INT_IPC9_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 3 */
-# define INT_IPC9_DMA3IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
-
-# define INT_IPC11_FCEIS_SHIFT (0) /* Bits 0-1, Vector: 44, Flash Control Event */
-# define INT_IPC11_FCEIS_MASK (3 << INT_IPC11_FCEIS_SHIFT)
-# define INT_IPC11_FCEIP_SHIFT (2) /* Bits 2-4, Vector: 44, Flash Control Event */
-# define INT_IPC11_FCEIP_MASK (7 << INT_IPC11_FCEIP_SHIFT)
-# define INT_IPC11_USBIS_SHIFT (8) /* Bits 8-9, Vector: 45, USB */
-# define INT_IPC11_USBIS_MASK (3 << INT_IPC11_USBIS_SHIFT)
-# define INT_IPC11_USBIP_SHIFT (10) /* Bits 10-12, Vector: 45, USB */
-# define INT_IPC11_USBIP_MASK (7 << INT_IPC11_USBIP_SHIFT)
-
-#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
-
-# define INT_IPC6_VEC24IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1, SPI3, I2C3 */
-# define INT_IPC6_VEC24IS_MASK (3 << INT_IPC6_INT26IS_SHIFT)
-# define INT_IPC6_U1IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1 */
-# define INT_IPC6_U1IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
-# define INT_IPC6_SPI3IS_SHIFT (0) /* Bits 0-1, Vector: 24, SPI3 */
-# define INT_IPC6_SPI3IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT)
-# define INT_IPC6_I2C3IS_SHIFT (0) /* Bits 0-1, Vector: 24, I2C3 */
-# define INT_IPC6_I2C3IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT)
-# define INT_IPC6_VEC24IP_SHIFT (0) /* Bits 2-4, Vector: 24, UART1, SPI3, I2C3 */
-# define INT_IPC6_VEC24IP_MASK (7 << INT_IPC6_INT26IP_SHIFT)
-# define INT_IPC6_U1IP_SHIFT (2) /* Bits 2-4, Vector: 24, UART1 */
-# define INT_IPC6_U1IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
-# define INT_IPC6_SPI3IP_SHIFT (2) /* Bits 2-4, Vector: 24, SPI3 */
-# define INT_IPC6_SPI3IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT)
-# define INT_IPC6_I2C3IP_SHIFT (2) /* Bits 2-4, Vector: 24, I2C3 */
-# define INT_IPC6_I2C3IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT)
-# define INT_IPC6_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 25, I2C1 */
-# define INT_IPC6_I2C1IS_MASK (3 << INT_IPC6_I2C1IS_SHIFT)
-# define INT_IPC6_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 25, I2C1 */
-# define INT_IPC6_I2C1IP_MASK (7 << INT_IPC6_I2C1IP_SHIFT)
-# define INT_IPC6_CNIS_SHIFT (16) /* Bits 16-17, Vector: 26, Input Change Interrupt */
-# define INT_IPC6_CNIS_MASK (3 << INT_IPC6_CNIS_SHIFT)
-# define INT_IPC6_CNIP_SHIFT (18) /* Bits 18-20, Vector: 26, Input Change Interrupt */
-# define INT_IPC6_CNIP_MASK (7 << INT_IPC6_CNIP_SHIFT)
-# define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 27, ADC1 Convert Done */
-# define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT)
-# define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 27, ADC1 Convert Done */
-# define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT)
-
-# define INT_IPC7_PMPIS_SHIFT (0) /* Bits 0-1, Vector: 28, Parallel Master Port */
-# define INT_IPC7_PMPIS_MASK (3 << INT_IPC7_PMPIS_SHIFT)
-# define INT_IPC7_PMPIP_SHIFT (2) /* Bits 2-4, Vector: 28, Parallel Master Port */
-# define INT_IPC7_PMPIP_MASK (7 << INT_IPC7_PMPIP_SHIFT)
-# define INT_IPC7_CMP1IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */
-# define INT_IPC7_CMP1IS_MASK (3 << INT_IPC7_CMP1IS_SHIFT)
-# define INT_IPC7_CMP1IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */
-# define INT_IPC7_CMP1IP_MASK (7 << INT_IPC7_CMP1IP_SHIFT)
-# define INT_IPC7_CMP2IS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */
-# define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT)
-# define INT_IPC7_CMP2IP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */
-# define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT)
-# define INT_IPC6_VEC31IS_SHIFT (24) /* Bits 24-25, Vector: 31, UART3, SPI2, I2C4 */
-# define INT_IPC6_VEC31IS_MASK (3 << INT_IPC6_INT26IS_SHIFT)
-# define INT_IPC6_U3IS_SHIFT (24) /* Bits 24-25, Vector: 31, UART3 */
-# define INT_IPC6_U3IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
-# define INT_IPC6_SPI2IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI2 */
-# define INT_IPC6_SPI2IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT)
-# define INT_IPC6_I2C4IS_SHIFT (24) /* Bits 24-25, Vector: 31, I2C4 */
-# define INT_IPC6_I2C4IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT)
-# define INT_IPC6_VEC31IP_SHIFT (26) /* Bits 26-28, Vector: 31, UART3, SPI2, I2C4 */
-# define INT_IPC6_VEC31IP_MASK (7 << INT_IPC6_INT26IP_SHIFT)
-# define INT_IPC6_U3IP_SHIFT (26) /* Bits 26-28, Vector: 31, UART3 */
-# define INT_IPC6_U3IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
-# define INT_IPC6_SPI2IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI2 */
-# define INT_IPC6_SPI2IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT)
-# define INT_IPC6_I2C4IP_SHIFT (26) /* Bits 26-28, Vector: 31, I2C4 */
-# define INT_IPC6_I2C4IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT)
-
-# define INT_IPC6_VEC32IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2, SPI4, I2C5 */
-# define INT_IPC6_VEC32IS_MASK (3 << INT_IPC6_INT26IS_SHIFT)
-# define INT_IPC6_U2IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2 */
-# define INT_IPC6_U2IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
-# define INT_IPC6_SPI4IS_SHIFT (0) /* Bits 0-1, Vector: 32, SPI4 */
-# define INT_IPC6_SPI4IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT)
-# define INT_IPC6_I2C5IS_SHIFT (0) /* Bits 0-1, Vector: 32, I2C5 */
-# define INT_IPC6_I2C5IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT)
-# define INT_IPC6_VEC32IP_SHIFT (0) /* Bits 2-4, Vector: 32, UART2, SPI4, I2C5 */
-# define INT_IPC6_VEC32IP_MASK (7 << INT_IPC6_INT26IP_SHIFT)
-# define INT_IPC6_U2IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART2 */
-# define INT_IPC6_U2IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
-# define INT_IPC6_SPI4IP_SHIFT (2) /* Bits 2-4, Vector: 32, SPI4 */
-# define INT_IPC6_SPI4IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT)
-# define INT_IPC6_I2C5IP_SHIFT (2) /* Bits 2-4, Vector: 32, I2C5 */
-# define INT_IPC6_I2C5IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT)
-# define INT_IPC8_I2C2IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C2 */
-# define INT_IPC8_I2C2IS_MASK (3 << INT_IPC8_I2C2IS_SHIFT)
-# define INT_IPC8_I2C2IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C2 */
-# define INT_IPC8_I2C2IP_MASK (7 << INT_IPC8_I2C2IP_SHIFT)
-# define INT_IPC8_FSCMIS_SHIFT (16) /* Bits 16-17, Vector: 34, Fail-Safe Clock Monitor */
-# define INT_IPC8_FSCMIS_MASK (3 << INT_IPC8_FSCMIS_SHIFT)
-# define INT_IPC8_FSCMIP_SHIFT (18) /* Bits 18-20, Vector: 34, Fail-Safe Clock Monitor */
-# define INT_IPC8_FSCMIP_MASK (7 << INT_IPC8_FSCMIP_SHIFT)
-# define INT_IPC8_RTCCIS_SHIFT (24) /* Bits 24-25, Vector: 35, Real-Time Clock and Calendar */
-# define INT_IPC8_RTCCIS_MASK (3 << INT_IPC8_RTCCIS_SHIFT)
-# define INT_IPC8_RTCCIP_SHIFT (26) /* Bits 26-28, Vector: 35, Real-Time Clock and Calendar */
-# define INT_IPC8_RTCCIP_MASK (7 << INT_IPC8_RTCCIP_SHIFT)
-
-# define INT_IPC9_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 0 */
-# define INT_IPC9_DMA0IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT)
-# define INT_IPC9_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 0 */
-# define INT_IPC9_DMA0IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT)
-# define INT_IPC9_DMA1IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 1 */
-# define INT_IPC9_DMA1IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT)
-# define INT_IPC9_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 1 */
-# define INT_IPC9_DMA1IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT)
-# define INT_IPC9_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 2 */
-# define INT_IPC9_DMA2IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
-# define INT_IPC9_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 2 */
-# define INT_IPC9_DMA2IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
-# define INT_IPC9_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 3 */
-# define INT_IPC9_DMA3IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
-# define INT_IPC9_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 3 */
-# define INT_IPC9_DMA3IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
-
-# define INT_IPC10_DMA4IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 4 */
-# define INT_IPC10_DMA4IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT)
-# define INT_IPC10_DMA4IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 4 */
-# define INT_IPC10_DMA4IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT)
-# define INT_IPC10_DMA5IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 5 */
-# define INT_IPC10_DMA5IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT)
-# define INT_IPC10_DMA5IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 5 */
-# define INT_IPC10_DMA5IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT)
-# define INT_IPC10_DMA6IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 6 */
-# define INT_IPC10_DMA6IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
-# define INT_IPC10_DMA6IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 6 */
-# define INT_IPC10_DMA6IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
-# define INT_IPC10_DMA7IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 7 */
-# define INT_IPC10_DMA7IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
-# define INT_IPC10_DMA7IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 7 */
-# define INT_IPC10_DMA7IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
-
-# define INT_IPC11_FCEIS_SHIFT (0) /* Bits 0-1, Vector: 44, Flash Control Event */
-# define INT_IPC11_FCEIS_MASK (3 << INT_IPC11_FCEIS_SHIFT)
-# define INT_IPC11_FCEIP_SHIFT (2) /* Bits 2-4, Vector: 44, Flash Control Event */
-# define INT_IPC11_FCEIP_MASK (7 << INT_IPC11_FCEIP_SHIFT)
-# define INT_IPC11_USBIS_SHIFT (8) /* Bits 8-9, Vector: 45, USB */
-# define INT_IPC11_USBIS_MASK (3 << INT_IPC11_USBIS_SHIFT)
-# define INT_IPC11_USBIP_SHIFT (10) /* Bits 10-12, Vector: 45, USB */
-# define INT_IPC11_USBIP_MASK (7 << INT_IPC11_USBIP_SHIFT)
-# define INT_IPC11_CAN1IS_SHIFT (16) /* Bits 16-17, Vector: 46, Controller area network 1 */
-# define INT_IPC11_CAN1IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
-# define INT_IPC11_CAN1IP_SHIFT (18) /* Bits 18-20, Vector: 46, Controller area network 1 */
-# define INT_IPC11_CAN1IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
-# define INT_IPC11_CAN2IS_SHIFT (24) /* Bits 24-25, Vector: 47, Controller area network 2 */
-# define INT_IPC11_CAN2IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
-# define INT_IPC11_CAN2IP_SHIFT (26) /* Bits 26-28, Vector: 47, Controller area network 2 */
-# define INT_IPC11_CAN2IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
-
-# define INT_IPC12_ETHIS_SHIFT (0) /* Bits 0-1, Vector: 48, Ethernet interrupt */
-# define INT_IPC12_ETHIS_MASK (3 << INT_IPC11_FCEIS_SHIFT)
-# define INT_IPC12_ETHIP_SHIFT (2) /* Bits 2-4, Vector: 48, Ethernet interrupt */
-# define INT_IPC12_ETHIP_MASK (7 << INT_IPC11_FCEIP_SHIFT)
-# define INT_IPC12_U4IS_SHIFT (8) /* Bits 8-9, Vector: 49, UART4 */
-# define INT_IPC12_U4IS_MASK (3 << INT_IPC11_USBIS_SHIFT)
-# define INT_IPC12_U4IP_SHIFT (10) /* Bits 10-12, Vector: 49, UART4 */
-# define INT_IPC12_U4IP_MASK (7 << INT_IPC11_USBIP_SHIFT)
-# define INT_IPC12_U6IS_SHIFT (16) /* Bits 16-17, Vector: 50, UART6 */
-# define INT_IPC12_U6IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
-# define INT_IPC12_U6IP_SHIFT (18) /* Bits 18-20, Vector: 50, UART6 */
-# define INT_IPC12_U6IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
-# define INT_IPC12_U5IS_SHIFT (24) /* Bits 24-25, Vector: 51, UART5 */
-# define INT_IPC12_U5IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
-# define INT_IPC12_U5IP_SHIFT (26) /* Bits 26-28, Vector: 51, UART5 */
-# define INT_IPC12_U5IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
-
-#else
-# error "Unknown PIC32MX family
-#endif
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_INT_H */
+/**************************************************************************** + * arch/mips/src/pic32mx/pic32mx-int.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_INT_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_INT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "pic32mx-memorymap.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Register Offsets *********************************************************/ + +#define PIC32MX_INT_INTCON_OFFSET 0x0000 /* Interrupt control register */ +#define PIC32MX_INT_INTCONCLR_OFFSET 0x0004 /* Interrupt control clear register */ +#define PIC32MX_INT_INTCONSET_OFFSET 0x0008 /* Interrupt control set register */ +#define PIC32MX_INT_INTCONINV_OFFSET 0x000c /* Interrupt control invert register */ +#define PIC32MX_INT_INTSTAT_OFFSET 0x0010 /* Interrupt status register */ +#define PIC32MX_INT_INTSTATCLR_OFFSET 0x0014 /* Interrupt status clear register */ +#define PIC32MX_INT_INTSTATSET_OFFSET 0x0018 /* Interrupt status set register */ +#define PIC32MX_INT_INTSTATINV_OFFSET 0x001c /* Interrupt status invert register */ +#define PIC32MX_INT_TPTMR_OFFSET 0x0020 /* Temporal proximity timer register */ +#define PIC32MX_INT_TPTMRCLR_OFFSET 0x0024 /* Temporal proximity timer clear register */ +#define PIC32MX_INT_TPTMRSET_OFFSET 0x0028 /* Temporal proximity timer set register */ +#define PIC32MX_INT_TPTMRINV_OFFSET 0x002c /* Temporal proximity timer invert register */ +#define PIC32MX_INT_IFS_OFFSET(n) (0x0030 + ((n) << 4)) +#define PIC32MX_INT_IFSCLR_OFFSET(n) (0x0034 + ((n) << 4)) +#define PIC32MX_INT_IFSSET_OFFSET(n) (0x0038 + ((n) << 4)) +#define PIC32MX_INT_IFSINV_OFFSET(n) (0x003c + ((n) << 4)) +#define PIC32MX_INT_IFS0_OFFSET 0x0030 /* Interrupt flag status register 0 */ +#define PIC32MX_INT_IFS0CLR_OFFSET 0x0034 /* Interrupt flag status clear register 0 */ +#define PIC32MX_INT_IFS0SET_OFFSET 0x0038 /* Interrupt flag status set register 0 */ +#define PIC32MX_INT_IFS0INV_OFFSET 0x003c /* Interrupt flag status invert register 0 */ +#define PIC32MX_INT_IFS1_OFFSET 0x0040 /* Interrupt flag status register 1 */ +#define PIC32MX_INT_IFS1CLR_OFFSET 0x0044 /* Interrupt flag status clear register 1 */ +#define PIC32MX_INT_IFS1SET_OFFSET 0x0048 /* Interrupt flag status set register 1 */ +#define PIC32MX_INT_IFS1INV_OFFSET 0x004c /* Interrupt flag status invert register 1 */ +#define PIC32MX_INT_IFS2_OFFSET 0x0050 /* Interrupt flag status register 2 */ + +#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IFS2CLR_OFFSET 0x0054 /* Interrupt flag status clear register 2 */ +# define PIC32MX_INT_IFS2SET_OFFSET 0x0058 /* Interrupt flag status set register 2 */ +# define PIC32MX_INT_IFS2INV_OFFSET 0x005c /* Interrupt flag status invert register 2 */ +#endif + +#define PIC32MX_INT_IEC_OFFSET(n) (0x0060 + ((n) << 4)) +#define PIC32MX_INT_IECCLR_OFFSET(n) (0x0064 + ((n) << 4)) +#define PIC32MX_INT_IECSET_OFFSET(n) (0x0068 + ((n) << 4)) +#define PIC32MX_INT_IECINV_OFFSET(n) (0x006c + ((n) << 4)) +#define PIC32MX_INT_IEC0_OFFSET 0x0060 /* Interrupt enable control register 0 */ +#define PIC32MX_INT_IEC0CLR_OFFSET 0x0064 /* Interrupt enable control clear register 0 */ +#define PIC32MX_INT_IEC0SET_OFFSET 0x0068 /* Interrupt enable control set register 0 */ +#define PIC32MX_INT_IEC0INV_OFFSET 0x006c /* Interrupt enable control invert register 0 */ +#define PIC32MX_INT_IEC1_OFFSET 0x0070 /* Interrupt enable control register 1 */ +#define PIC32MX_INT_IEC1CLR_OFFSET 0x0074 /* Interrupt enable control clear register 1 */ +#define PIC32MX_INT_IEC1SET_OFFSET 0x0078 /* Interrupt enable control set register 1 */ +#define PIC32MX_INT_IEC1INV_OFFSET 0x007c /* Interrupt enable control invert register 1 */ + +#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IEC2_OFFSET 0x0080 /* Interrupt enable control register 2 */ +# define PIC32MX_INT_IEC2CLR_OFFSET 0x0084 /* Interrupt enable control clear register 2 */ +# define PIC32MX_INT_IEC2SET_OFFSET 0x0088 /* Interrupt enable control set register 2 */ +# define PIC32MX_INT_IEC2INV_OFFSET 0x008c /* Interrupt enable control invert register 2 */ +#endif + +#define PIC32MX_INT_IPC_OFFSET(n) (0x0090 + ((n) << 4)) +#define PIC32MX_INT_IPCCLR_OFFSET(n) (0x0094 + ((n) << 4)) +#define PIC32MX_INT_IPCSET_OFFSET(n) (0x0098 + ((n) << 4)) +#define PIC32MX_INT_IPCINV_OFFSET(n) (0x009c + ((n) << 4)) +#define PIC32MX_INT_IPC0_OFFSET 0x0090 /* Interrupt priority control register 0 */ +#define PIC32MX_INT_IPC0CLR_OFFSET 0x0094 /* Interrupt priority control clear register 0 */ +#define PIC32MX_INT_IPC0SET_OFFSET 0x0098 /* Interrupt priority control set register 0 */ +#define PIC32MX_INT_IPC0INV_OFFSET 0x009c /* Interrupt priority control invert register 0 */ +#define PIC32MX_INT_IPC1_OFFSET 0x00a0 /* Interrupt priority control register 1 */ +#define PIC32MX_INT_IPC1CLR_OFFSET 0x00a4 /* Interrupt priority control clear register 1 */ +#define PIC32MX_INT_IPC1SET_OFFSET 0x00a8 /* Interrupt priority control set register 1 */ +#define PIC32MX_INT_IPC1INV_OFFSET 0x00ac /* Interrupt priority control invert register 1 */ +#define PIC32MX_INT_IPC2_OFFSET 0x00b0 /* Interrupt priority control register 2 */ +#define PIC32MX_INT_IPC2CLR_OFFSET 0x00b4 /* Interrupt priority control clear register 2 */ +#define PIC32MX_INT_IPC2SET_OFFSET 0x00b8 /* Interrupt priority control set register 2 */ +#define PIC32MX_INT_IPC2INV_OFFSET 0x00bc /* Interrupt priority control invert register 2 */ +#define PIC32MX_INT_IPC3_OFFSET 0x00c0 /* Interrupt priority control register 3 */ +#define PIC32MX_INT_IPC3CLR_OFFSET 0x00c4 /* Interrupt priority control clear register 3 */ +#define PIC32MX_INT_IPC3SET_OFFSET 0x00c8 /* Interrupt priority control set register 3 */ +#define PIC32MX_INT_IPC3INV_OFFSET 0x00cc /* Interrupt priority control invert register 3 */ +#define PIC32MX_INT_IPC4_OFFSET 0x00d0 /* Interrupt priority control register 4 */ +#define PIC32MX_INT_IPC4CLR_OFFSET 0x00d4 /* Interrupt priority control clear register 4 */ +#define PIC32MX_INT_IPC4SET_OFFSET 0x00d8 /* Interrupt priority control set register 4 */ +#define PIC32MX_INT_IPC4INV_OFFSET 0x00dc /* Interrupt priority control invert register 4 */ +#define PIC32MX_INT_IPC5_OFFSET 0x00e0 /* Interrupt priority control register 5 */ +#define PIC32MX_INT_IPC5CLR_OFFSET 0x00e4 /* Interrupt priority control clear register 5 */ +#define PIC32MX_INT_IPC5SET_OFFSET 0x00e8 /* Interrupt priority control set register 5 */ +#define PIC32MX_INT_IPC5INV_OFFSET 0x00ec /* Interrupt priority control invert register 5 */ +#define PIC32MX_INT_IPC6_OFFSET 0x00f0 /* Interrupt priority control register 6 */ +#define PIC32MX_INT_IPC6CLR_OFFSET 0x00f4 /* Interrupt priority control clear register 6 */ +#define PIC32MX_INT_IPC6SET_OFFSET 0x00f8 /* Interrupt priority control set register 6 */ +#define PIC32MX_INT_IPC6INV_OFFSET 0x00fc /* Interrupt priority control invert register 6 */ +#define PIC32MX_INT_IPC7_OFFSET 0x0100 /* Interrupt priority control register 7 */ +#define PIC32MX_INT_IPC7CLR_OFFSET 0x0104 /* Interrupt priority control clear register 7 */ +#define PIC32MX_INT_IPC7SET_OFFSET 0x0108 /* Interrupt priority control set register 7 */ +#define PIC32MX_INT_IPC7INV_OFFSET 0x010c /* Interrupt priority control invert register 7 */ +#define PIC32MX_INT_IPC8_OFFSET 0x0110 /* Interrupt priority control register 8 */ +#define PIC32MX_INT_IPC8CLR_OFFSET 0x0114 /* Interrupt priority control clear register 8 */ +#define PIC32MX_INT_IPC8SET_OFFSET 0x0118 /* Interrupt priority control set register 8 */ +#define PIC32MX_INT_IPC8INV_OFFSET 0x011c /* Interrupt priority control invert register 8 */ +#define PIC32MX_INT_IPC9_OFFSET 0x0120 /* Interrupt priority control register 9 */ +#define PIC32MX_INT_IPC9CLR_OFFSET 0x0124 /* Interrupt priority control clear register 9 */ +#define PIC32MX_INT_IPC9SET_OFFSET 0x0128 /* Interrupt priority control set register 9 */ +#define PIC32MX_INT_IPC9INV_OFFSET 0x012c /* Interrupt priority control invert register 9 */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IPC10_OFFSET 0x0130 /* Interrupt priority control register 10 */ +# define PIC32MX_INT_IPC10CLR_OFFSET 0x0134 /* Interrupt priority control clear register 10 */ +# define PIC32MX_INT_IPC10SET_OFFSET 0x0138 /* Interrupt priority control set register 10 */ +# define PIC32MX_INT_IPC10INV_OFFSET 0x013c /* Interrupt priority control invert register 10 */ +#endif + +#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IPC11_OFFSET 0x0140 /* Interrupt priority control register 11 */ +# define PIC32MX_INT_IPC11CLR_OFFSET 0x0144 /* Interrupt priority control clear register 11 */ +# define PIC32MX_INT_IPC11SET_OFFSET 0x0148 /* Interrupt priority control set register 11 */ +# define PIC32MX_INT_IPC11INV_OFFSET 0x014c /* Interrupt priority control invert register 11 */ +#endif + +#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IPC12_OFFSET 0x0150 /* Interrupt priority control register 12 */ +# define PIC32MX_INT_IPC12CLR_OFFSET 0x0154 /* Interrupt priority control clear register 12 */ +# define PIC32MX_INT_IPC12SET_OFFSET 0x0158 /* Interrupt priority control set register 12 */ +# define PIC32MX_INT_IPC12INV_OFFSET 0x015c /* Interrupt priority control invert register 12 */ +#endif + +/* Register Addresses *******************************************************/ + +#define PIC32MX_INT_INTCON (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCON_OFFSET) +#define PIC32MX_INT_INTCONCLR (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCONCLR_OFFSET) +#define PIC32MX_INT_INTCONSET (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCONSET_OFFSET) +#define PIC32MX_INT_INTCONINV (PIC32MX_INT_K1BASE+PIC32MX_INT_INTCONINV_OFFSET) +#define PIC32MX_INT_INTSTAT (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTAT_OFFSET) +#define PIC32MX_INT_INTSTATCLR (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTATCLR_OFFSET) +#define PIC32MX_INT_INTSTATSET (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTATSET_OFFSET) +#define PIC32MX_INT_INTSTATINV (PIC32MX_INT_K1BASE+PIC32MX_INT_INTSTATINV_OFFSET) +#define PIC32MX_INT_TPTMR (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMR_OFFSET) +#define PIC32MX_INT_TPTMRCLR (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMRCLR_OFFSET) +#define PIC32MX_INT_TPTMRSET (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMRSET_OFFSET) +#define PIC32MX_INT_TPTMRINV (PIC32MX_INT_K1BASE+PIC32MX_INT_TPTMRINV_OFFSET) +#define PIC32MX_INT_IFS(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS_OFFSET(n)) +#define PIC32MX_INT_IFSCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFSCLR_OFFSET(n)) +#define PIC32MX_INT_IFSSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFSSET_OFFSET(n)) +#define PIC32MX_INT_IFSINV(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IFSINV_OFFSET(n)) +#define PIC32MX_INT_IFS0 (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0_OFFSET) +#define PIC32MX_INT_IFS0CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0CLR_OFFSET) +#define PIC32MX_INT_IFS0SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0SET_OFFSET) +#define PIC32MX_INT_IFS0INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS0INV_OFFSET) +#define PIC32MX_INT_IFS1 (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1_OFFSET) +#define PIC32MX_INT_IFS1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1CLR_OFFSET) +#define PIC32MX_INT_IFS1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1SET_OFFSET) +#define PIC32MX_INT_IFS1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1INV_OFFSET) + +#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IFS2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2_OFFSET) +# define PIC32MX_INT_IFS2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2CLR_OFFSET) +# define PIC32MX_INT_IFS2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2SET_OFFSET) +# define PIC32MX_INT_IFS2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2INV_OFFSET) +#endif + +#define PIC32MX_INT_IEC(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC_OFFSET(n)) +#define PIC32MX_INT_IECCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECCLR_OFFSET(n)) +#define PIC32MX_INT_IECSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECSET_OFFSET(n)) +#define PIC32MX_INT_IECINV(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECINV_OFFSET(n)) +#define PIC32MX_INT_IEC0 (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0_OFFSET) +#define PIC32MX_INT_IEC0CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0CLR_OFFSET) +#define PIC32MX_INT_IEC0SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0SET_OFFSET) +#define PIC32MX_INT_IEC0INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC0_OFFSET) +#define PIC32MX_INT_IEC1 (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1_OFFSET) +#define PIC32MX_INT_IEC1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1CLR_OFFSET) +#define PIC32MX_INT_IEC1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1SET_OFFSET) +#define PIC32MX_INT_IEC1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1INV_OFFSET) + +#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IEC2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2_OFFSET) +# define PIC32MX_INT_IEC2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2CLR_OFFSET) +# define PIC32MX_INT_IEC2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2SET_OFFSET) +# define PIC32MX_INT_IEC2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2INV_OFFSET) +#endif + +#define PIC32MX_INT_IPC(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC_OFFSET(n)) +#define PIC32MX_INT_IPCCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCCLR_OFFSET(n)) +#define PIC32MX_INT_IPCSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCSET_OFFSET(n)) +#define PIC32MX_INT_IPCINV(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCINV_OFFSET(n)) +#define PIC32MX_INT_IPC0 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0_OFFSET) +#define PIC32MX_INT_IPC0CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0CLR_OFFSET) +#define PIC32MX_INT_IPC0SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0SET_OFFSET) +#define PIC32MX_INT_IPC0INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC0INV_OFFSET) +#define PIC32MX_INT_IPC1 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1_OFFSET) +#define PIC32MX_INT_IPC1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1CLR_OFFSET) +#define PIC32MX_INT_IPC1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1SET_OFFSET) +#define PIC32MX_INT_IPC1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC1INV_OFFSET) +#define PIC32MX_INT_IPC2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2_OFFSET) +#define PIC32MX_INT_IPC2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2CLR_OFFSET) +#define PIC32MX_INT_IPC2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2SET_OFFSET) +#define PIC32MX_INT_IPC2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC2INV_OFFSET) +#define PIC32MX_INT_IPC3 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3_OFFSET) +#define PIC32MX_INT_IPC3CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3CLR_OFFSET) +#define PIC32MX_INT_IPC3SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3SET_OFFSET) +#define PIC32MX_INT_IPC3INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC3INV_OFFSET) +#define PIC32MX_INT_IPC4 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4_OFFSET) +#define PIC32MX_INT_IPC4CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4CLR_OFFSET) +#define PIC32MX_INT_IPC4SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4SET_OFFSET) +#define PIC32MX_INT_IPC4INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC4INV_OFFSET) +#define PIC32MX_INT_IPC5 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5_OFFSET) +#define PIC32MX_INT_IPC5CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5CLR_OFFSET) +#define PIC32MX_INT_IPC5SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5SET_OFFSET) +#define PIC32MX_INT_IPC5INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC5INV_OFFSET) +#define PIC32MX_INT_IPC6 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6_OFFSET) +#define PIC32MX_INT_IPC6CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6CLR_OFFSET) +#define PIC32MX_INT_IPC6SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6SET_OFFSET) +#define PIC32MX_INT_IPC6INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC6INV_OFFSET) +#define PIC32MX_INT_IPC7 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7_OFFSET) +#define PIC32MX_INT_IPC7CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7CLR_OFFSET) +#define PIC32MX_INT_IPC7SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7SET_OFFSET) +#define PIC32MX_INT_IPC7INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC7INV_OFFSET) +#define PIC32MX_INT_IPC8 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8_OFFSET) +#define PIC32MX_INT_IPC8CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8CLR_OFFSET) +#define PIC32MX_INT_IPC8SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8SET_OFFSET) +#define PIC32MX_INT_IPC8INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC8INV_OFFSET) +#define PIC32MX_INT_IPC9 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9_OFFSET) +#define PIC32MX_INT_IPC9CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9CLR_OFFSET) +#define PIC32MX_INT_IPC9SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9SET_OFFSET) +#define PIC32MX_INT_IPC9INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9INV_OFFSET) + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IPC10 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10_OFFSET) +# define PIC32MX_INT_IPC10CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10CLR_OFFSET) +# define PIC32MX_INT_IPC10SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10SET_OFFSET) +# define PIC32MX_INT_IPC10INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10INV_OFFSET) +#endif + +#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IPC11 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11_OFFSET) +# define PIC32MX_INT_IPC11CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11CLR_OFFSET) +# define PIC32MX_INT_IPC11SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11SET_OFFSET) +# define PIC32MX_INT_IPC11INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11INV_OFFSET) +#endif + +#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define PIC32MX_INT_IPC12 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12_OFFSET) +# define PIC32MX_INT_IPC12CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12CLR_OFFSET) +# define PIC32MX_INT_IPC12SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12SET_OFFSET) +# define PIC32MX_INT_IPC12INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12INV_OFFSET) +#endif + +/* Register Bit-Field Definitions *******************************************/ + +/* Interrupt control register */ + +#define INT_INTCON_INT0EP (1 << 0) /* Bit 0: External interrupt 0 edge polarity control */ +#define INT_INTCON_INT1EP (1 << 1) /* Bit 1: External interrupt 1 edge polarity control */ +#define INT_INTCON_INT2EP (1 << 2) /* Bit 2: External interrupt 2 edge polarity control */ +#define INT_INTCON_INT3EP (1 << 3) /* Bit 3: External interrupt 3 edge polarity control */ +#define INT_INTCON_INT4EP (1 << 4) /* Bit 4: External interrupt 4 edge polarity control */ +#define INT_INTCON_TPC_SHIFT (8) /* Bits 8-10: Temporal proximity control */ +#define INT_INTCON_TPC_MASK (7 << INT_INTCON_TPC_SHIFT) +# define INT_INTCON_TPC_DIS (0 << INT_INTCON_TPC_SHIFT) /* Disables proximity timer */ +# define INT_INTCON_TPC_PRIO1 (1 << INT_INTCON_TPC_SHIFT) /* Int group priority 1 start IP timer */ +# define INT_INTCON_TPC_PRIO2 (2 << INT_INTCON_TPC_SHIFT) /* Int group priority <=2 start TP timer */ +# define INT_INTCON_TPC_PRIO3 (3 << INT_INTCON_TPC_SHIFT) /* Int group priority <=3 start TP timer */ +# define INT_INTCON_TPC_PRIO4 (4 << INT_INTCON_TPC_SHIFT) /* Int group priority <=4 start TP timer */ +# define INT_INTCON_TPC_PRIO5 (5 << INT_INTCON_TPC_SHIFT) /* Int group priority <=5 start TP timer */ +# define INT_INTCON_TPC_PRIO6 (6 << INT_INTCON_TPC_SHIFT) /* Int group priority <=6 start TP timer */ +# define INT_INTCON_TPC_PRIO7 (7 << INT_INTCON_TPC_SHIFT) /* Int group priority <=7 start TP timer */ +#define INT_INTCON_MVEC (1 << 12) /* Bit 12: Multi vector configuration */ + +#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define INT_INTCON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */ +#endif + +#define INT_INTCON_SS0 (1 << 16) /* Bit 16: Single vector shadow register set */ + +/* Interrupt status register */ + +#define INT_INTSTAT_VEC_SHIFT (0) /* Bits 0-5: Interrupt vector */ +#define INT_INTSTAT_VEC_MASK (0x3f << INT_INTSTAT_VEC_SHIFT) +#define INT_INTSTAT_RIPL_SHIFT (8) /* Bits 8-10: Requested priority level */ +#define INT_INTSTAT_RIPL_MASK (7 << INT_INTSTAT_RIPL_SHIFT) + +/* Temporal proximity timer register -- This register contains a 32-bit value + * with no field definitions. + */ + +/* Interrupt flag status register 0 and Interrupt enable control register 0 */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +#define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */ +#define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */ +#define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */ +#define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */ +#define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */ +#define INT_IC1E (1 << 5) /* Vector: 5, Input Capture 1 Error */ +#define INT_IC1 (1 << 6) /* Vector: 5, Input Capture 1 */ +#define INT_OC1 (1 << 7) /* Vector: 6, Output Compare 1 */ +#define INT_INT1 (1 << 8) /* Vector: 7, External Interrupt 1 */ +#define INT_T2 (1 << 9) /* Vector: 8, Timer 2 */ +#define INT_IC2E (1 << 10) /* Vector: 9, Input Capture 2 Error */ +#define INT_IC2 (1 << 11) /* Vector: 9, Input Capture 2 */ +#define INT_OC2 (1 << 12) /* Vector: 10, Output Compare 2 */ +#define INT_INT2 (1 << 13) /* Vector: 11, External Interrupt 2 */ +#define INT_T3 (1 << 14) /* Vector: 12, Timer 3 */ +#define INT_IC3E (1 << 15) /* Vector: 13, Input Capture 3 Error */ +#define INT_IC3 (1 << 16) /* Vector: 13, Input Capture 3 */ +#define INT_OC3 (1 << 17) /* Vector: 14, Output Compare 3 */ +#define INT_INT3 (1 << 18) /* Vector: 15, External Interrupt 3 */ +#define INT_T4 (1 << 19) /* Vector: 16, Timer 4 */ +#define INT_IC4E (1 << 20) /* Vector: 17, Input Capture 4 Error */ +#define INT_IC4 (1 << 21) /* Vector: 17, Input Capture 4 */ +#define INT_OC4 (1 << 22) /* Vector: 18, Output Compare 4 */ +#define INT_INT4 (1 << 23) /* Vector: 19, External Interrupt 4 */ +#define INT_T5 (1 << 24) /* Vector: 20, Timer 5 */ +#define INT_IC5E (1 << 25) /* Vector: 21, Input Capture 5 Error */ +#define INT_IC5 (1 << 26) /* Vector: 21, Input Capture 5 */ +#define INT_OC5 (1 << 27) /* Vector: 22, Output Compare 5 */ +#define INT_AD1 (1 << 28) /* Vector: 23, ADC1 Convert Done */ +#define INT_FSCM (1 << 29) /* Vector: 24, Fail-Safe Clock Monitor */ +#define INT_RTCC (1 << 30) /* Vector: 25, Real-Time Clock and Calendar */ +#define INT_FCE (1 << 31) /* Vector: 26, Flash Control Event */ + +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +# define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */ +# define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */ +# define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */ +# define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */ +# define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */ +# define INT_IC1 (1 << 5) /* Vector: 5, Input Capture 1 */ +# define INT_OC1 (1 << 6) /* Vector: 6, Output Compare 1 */ +# define INT_INT1 (1 << 7) /* Vector: 7, External Interrupt 1 */ +# define INT_T2 (1 << 8) /* Vector: 8, Timer 2 */ +# define INT_IC2 (1 << 9) /* Vector: 9, Input Capture 2 */ +# define INT_OC2 (1 << 10) /* Vector: 10, Output Compare 2 */ +# define INT_INT2 (1 << 11) /* Vector: 11, External Interrupt 2 */ +# define INT_T3 (1 << 12) /* Vector: 12, Timer 3 */ +# define INT_IC3 (1 << 13) /* Vector: 13, Input Capture 3 */ +# define INT_OC3 (1 << 14) /* Vector: 14, Output Compare 3 */ +# define INT_INT3 (1 << 15) /* Vector: 15, External Interrupt 3 */ +# define INT_T4 (1 << 16) /* Vector: 16, Timer 4 */ +# define INT_IC4 (1 << 17) /* Vector: 17, Input Capture 4 */ +# define INT_OC4 (1 << 18) /* Vector: 18, Output Compare 4 */ +# define INT_INT4 (1 << 19) /* Vector: 19, External Interrupt 4 */ +# define INT_T5 (1 << 20) /* Vector: 20, Timer 5 */ +# define INT_IC5 (1 << 21) /* Vector: 21, Input Capture 5 */ +# define INT_OC5 (1 << 22) /* Vector: 22, Output Compare 5 */ +# define INT_SPI1E (1 << 23) /* Vector: 23, SPI1 Error */ +# define INT_SPI1TX (1 << 24) /* Vector: 23, " " Transfer done */ +# define INT_SPI1RX (1 << 25) /* Vector: 23, " " Receive done */ +# define INT_U1E (1 << 26) /* Vector: 24, UART1 Error */ +# define INT_U1RX (1 << 27) /* Vector: 24, " " Receiver */ +# define INT_U1TX (1 << 28) /* Vector: 24, " " Transmitter */ +# define INT_I2C1B (1 << 29) /* Vector: 25, I2C1 Bus collision event */ +# define INT_I2C1S (1 << 30) /* Vector: 25, " " Slave event */ +# define INT_I2C1M (1 << 31) /* Vector: 25, " " Master event */ + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */ +# define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */ +# define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */ +# define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */ +# define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */ +# define INT_IC1 (1 << 5) /* Vector: 5, Input Capture 1 */ +# define INT_OC1 (1 << 6) /* Vector: 6, Output Compare 1 */ +# define INT_INT1 (1 << 7) /* Vector: 7, External Interrupt 1 */ +# define INT_T2 (1 << 8) /* Vector: 8, Timer 2 */ +# define INT_IC2 (1 << 9) /* Vector: 9, Input Capture 2 */ +# define INT_OC2 (1 << 10) /* Vector: 10, Output Compare 2 */ +# define INT_INT2 (1 << 11) /* Vector: 11, External Interrupt 2 */ +# define INT_T3 (1 << 12) /* Vector: 12, Timer 3 */ +# define INT_IC3 (1 << 13) /* Vector: 13, Input Capture 3 */ +# define INT_OC3 (1 << 14) /* Vector: 14, Output Compare 3 */ +# define INT_INT3 (1 << 15) /* Vector: 15, External Interrupt 3 */ +# define INT_T4 (1 << 16) /* Vector: 16, Timer 4 */ +# define INT_IC4 (1 << 17) /* Vector: 17, Input Capture 4 */ +# define INT_OC4 (1 << 18) /* Vector: 18, Output Compare 4 */ +# define INT_INT4 (1 << 19) /* Vector: 19, External Interrupt 4 */ +# define INT_T5 (1 << 20) /* Vector: 20, Timer 5 */ +# define INT_IC5 (1 << 21) /* Vector: 21, Input Capture 5 */ +# define INT_OC5 (1 << 22) /* Vector: 22, Output Compare 5 */ +# define INT_SPI1E (1 << 23) /* Vector: 23, SPI1 Error */ +# define INT_SPI1TX (1 << 24) /* Vector: 23, " " Transfer done */ +# define INT_SPI1RX (1 << 25) /* Vector: 23, " " Receive done */ +# define INT_26 (1 << 26) /* Vector: 24, UART1, SPI3, I2C3 */ +# define INT_U1E (1 << 26) /* Vector: 24, UART1 Error */ +# define INT_SPI3E (1 << 26) /* Vector: 24, SPI3 Fault */ +# define INT_I2C3B (1 << 26) /* Vector: 24, I2C3 Bus collision event */ +# define INT_27 (1 << 27) /* Vector: 24, UART1, SPI3, I2C3 */ +# define INT_U1RX (1 << 27) /* Vector: 24, UART1 Receiver */ +# define INT_SPI3RX (1 << 27) /* Vector: 24, SPI3 Receive done */ +# define INT_I2C3S (1 << 27) /* Vector: 24, I2C3 Slave event */ +# define INT_28 (1 << 28) /* Vector: 24, UART1, SPI3, I2C3 */ +# define INT_U1TX (1 << 28) /* Vector: 24, UART1 Transmitter */ +# define INT_SPI3TX (1 << 28) /* Vector: 24, SPI3 Transfer done */ +# define INT_I2C3M (1 << 28) /* Vector: 24, I2C3 Master event */ +# define INT_I2C1B (1 << 29) /* Vector: 25, I2C1 Bus collision event */ +# define INT_I2C1S (1 << 30) /* Vector: 25, " " Slave event */ +# define INT_I2C1M (1 << 31) /* Vector: 25, " " Master event */ + +#else +# error "Unknown PIC32MX family +#endif + +/* Interrupt flag status register 1 and Interrupt enable control register 1 */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +# define INT_CMP1 (1 << 0) /* Vector: 27, Comparator 1 Interrupt */ +# define INT_CMP2 (1 << 1) /* Vector: 28, Comparator 2 Interrupt */ +# define INT_CMP2 (1 << 2) /* Vector: 29, Comparator 3 Interrupt */ +# define INT_USB (1 << 3) /* Vector: 30, USB */ +# define INT_SPI1E (1 << 4) /* Vector: 31, SPI1 */ +# define INT_SPI1TX (1 << 5) /* Vector: 31, " " */ +# define INT_SPI1RX (1 << 6) /* Vector: 31, " " */ +# define INT_U1E (1 << 7) /* Vector: 32, UART1 */ +# define INT_U1RX (1 << 8) /* Vector: 32, " " */ +# define INT_U1TX (1 << 9) /* Vector: 32, " " */ +# define INT_I2C1B (1 << 10) /* Vector: 33, I2C1 */ +# define INT_I2C1S (1 << 11) /* Vector: 33, " " */ +# define INT_I2C1M (1 << 12) /* Vector: 33, " " */ +# define INT_CNA (1 << 13) /* Vector: 34, Input Change Interrupt */ +# define INT_CNB (1 << 14) /* Vector: 34, Input Change Interrupt */ +# define INT_CNC (1 << 15) /* Vector: 34, Input Change Interrupt */ +# define INT_PMP (1 << 16) /* Vector: 35, Parallel Master Port */ +# define INT_PMPE (1 << 17) /* Vector: 35, Parallel Master Port */ +# define INT_SPI2E (1 << 18) /* Vector: 36, SPI2 */ +# define INT_SPI2TX (1 << 19) /* Vector: 36, " " */ +# define INT_SPI2RX (1 << 20) /* Vector: 36, " " */ +# define INT_U2E (1 << 21) /* Vector: 37, UART2 */ +# define INT_U2RX (1 << 22) /* Vector: 37, " " */ +# define INT_U2TX (1 << 23) /* Vector: 37, " " */ +# define INT_I2C2B (1 << 24) /* Vector: 38, I2C2 */ +# define INT_I2C2S (1 << 25) /* Vector: 38, " " */ +# define INT_I2C2M (1 << 26) /* Vector: 38, " " */ +# define INT_CTMU (1 << 27) /* Vector: 39, CTMU */ +# define INT_DMA0 (1 << 28) /* Vector: 40, DMA Channel 0 */ +# define INT_DMA1 (1 << 29) /* Vector: 41, DMA Channel 1 */ +# define INT_DMA2 (1 << 30) /* Vector: 42, DMA Channel 2 */ +# define INT_DMA3 (1 << 31) /* Vector: 43, DMA Channel 3 */ + +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +# define INT_CN (1 << 0) /* Vector: 26, Input Change Interrupt */ +# define INT_AD1 (1 << 1) /* Vector: 27, ADC1 Convert Done */ +# define INT_PMP (1 << 2) /* Vector: 28, Parallel Master Port */ +# define INT_CMP1 (1 << 3) /* Vector: 29, Comparator Interrupt */ +# define INT_CMP2 (1 << 4) /* Vector: 30, Comparator Interrupt */ +# define INT_SPI2E (1 << 5) /* Vector: 31, SPI2 Error */ +# define INT_SPI2TX (1 << 6) /* Vector: 31, " " Transfer done */ +# define INT_SPI2RX (1 << 7) /* Vector: 31, " " Receive done*/ +# define INT_U2E (1 << 8) /* Vector: 32, UART2 Error */ +# define INT_U2RX (1 << 9) /* Vector: 32, " " Receiver */ +# define INT_U2TX (1 << 10) /* Vector: 32, " " Transmitter */ +# define INT_I2C2B (1 << 11) /* Vector: 33, I2C2 Bus collision event */ +# define INT_I2C2S (1 << 12) /* Vector: 33, " " Master event */ +# define INT_I2C2M (1 << 13) /* Vector: 33, " " Slave event */ +# define INT_FSCM (1 << 14) /* Vector: 34, Fail-Safe Clock Monitor */ +# define INT_RTCC (1 << 15) /* Vector: 35, Real-Time Clock and Calendar */ +# define INT_DMA0 (1 << 16) /* Vector: 36, DMA Channel 0 */ +# define INT_DMA1 (1 << 17) /* Vector: 37, DMA Channel 1 */ +# define INT_DMA2 (1 << 18) /* Vector: 38, DMA Channel 2 */ +# define INT_DMA3 (1 << 19) /* Vector: 39, DMA Channel 3 */ +# define INT_FCE (1 << 24) /* Vector: 44, Flash Control Event */ +# define INT_USB (1 << 25) /* Vector: 45, USB Interrupt */ + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define INT_CN (1 << 0) /* Vector: 26, Input Change Interrupt */ +# define INT_AD1 (1 << 1) /* Vector: 27, ADC1 Convert Done */ +# define INT_PMP (1 << 2) /* Vector: 28, Parallel Master Port */ +# define INT_CMP1 (1 << 3) /* Vector: 29, Comparator Interrupt */ +# define INT_CMP2 (1 << 4) /* Vector: 30, Comparator Interrupt */ +# define INT_37 (1 << 5) /* Vector: 31, UART3, SPI2, I2C4 */ +# define INT_U3E (1 << 5) /* Vector: 31, UART3 Error */ +# define INT_SPI2E (1 << 5) /* Vector: 31, SPI2 Fault */ +# define INT_I2C4B (1 << 5) /* Vector: 31, I2C4 Bus collision event */ +# define INT_38 (1 << 6) /* Vector: 31, UART3, SPI2, I2C4 */ +# define INT_U3RX (1 << 6) /* Vector: 31, UART3 Receiver */ +# define INT_SPI2RX (1 << 6) /* Vector: 31, SPI2 Receive done */ +# define INT_I2C4S (1 << 6) /* Vector: 31, I2C4 Slave event */ +# define INT_39 (1 << 7) /* Vector: 31, UART3, SPI2, I2C4 */ +# define INT_U3TX (1 << 7) /* Vector: 31, UART3 Transmitter */ +# define INT_SPI2TX (1 << 7) /* Vector: 31, SPI2 Transfer done */ +# define INT_I2C4M (1 << 7) /* Vector: 31, I2C4 Master event */ +# define INT_40 (1 << 8) /* Vector: 32, UART2, SPI4, I2C5 */ +# define INT_U2E (1 << 8) /* Vector: 32, UART2 Error */ +# define INT_SPI4E (1 << 8) /* Vector: 32, SPI4 Fault */ +# define INT_I2C5B (1 << 8) /* Vector: 32, I2C5 Bus collision event */ +# define INT_41 (1 << 9) /* Vector: 32, UART2, SPI4, I2C5 */ +# define INT_U2RX (1 << 9) /* Vector: 32, UART2 Receiver */ +# define INT_SPI4RX (1 << 9) /* Vector: 32, SPI4 Receive done */ +# define INT_I2C5S (1 << 9) /* Vector: 32, I2C5 Slave event */ +# define INT_42 (1 << 10) /* Vector: 32, UART2, SPI4, I2C5 */ +# define INT_U2TX (1 << 10) /* Vector: 32, UART2 Transmitter */ +# define INT_SPI4TX (1 << 10) /* Vector: 32, SPI4 Transfer done */ +# define INT_I2C5M (1 << 10) /* Vector: 32, I2C5 Master event */ +# define INT_I2C2B (1 << 11) /* Vector: 33, I2C2 Bus collision event */ +# define INT_I2C2S (1 << 12) /* Vector: 33, " " Master event */ +# define INT_I2C2M (1 << 13) /* Vector: 33, " " Slave event */ +# define INT_FSCM (1 << 14) /* Vector: 34, Fail-Safe Clock Monitor */ +# define INT_RTCC (1 << 15) /* Vector: 35, Real-Time Clock and Calendar */ +# define INT_DMA0 (1 << 16) /* Vector: 36, DMA Channel 0 */ +# define INT_DMA1 (1 << 17) /* Vector: 37, DMA Channel 1 */ +# define INT_DMA2 (1 << 18) /* Vector: 38, DMA Channel 2 */ +# define INT_DMA3 (1 << 19) /* Vector: 39, DMA Channel 3 */ +# define INT_DMA4 (1 << 20) /* Vector: 40, DMA Channel 3 */ +# define INT_DMA5 (1 << 21) /* Vector: 41, DMA Channel 3 */ +# define INT_DMA6 (1 << 22) /* Vector: 42, DMA Channel 3 */ +# define INT_DMA7 (1 << 23) /* Vector: 43, DMA Channel 3 */ +# define INT_FCE (1 << 24) /* Vector: 44, Flash Control Event */ +# define INT_USB (1 << 25) /* Vector: 45, USB Interrupt */ +# define INT_CAN1 (1 << 26) /* Vector: 46, Control Area Network 1 */ +# define INT_CAN2 (1 << 27) /* Vector: 47, Control Area Network 2 */ +# define INT_ETH (1 << 28) /* Vector: 48, Ethernet interrupt */ +# define INT_IC1E (1 << 29) /* Vector: 5, Input capture 1 error */ +# define INT_IC2E (1 << 30) /* Vector: 9, Input capture 1 error */ +# define INT_IC3E (1 << 31) /* Vector: 13, Input capture 1 error */ + +#else +# error "Unknown PIC32MX family +#endif + +/* Interrupt flag status register 2 and Interrupt enable control register 2 */ + +#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define INT_IC4E (1 << 0) /* Vector: 17, Input capture 1 error */ +# define INT_IC5E (1 << 1) /* Vector: 21, Input capture 1 error */ +# define INT_PMPE (1 << 2) /* Vector: 28, Parallel master port error */ +# define INT_U4E (1 << 3) /* Vector: 49, UART4 Error */ +# define INT_U4RX (1 << 4) /* Vector: 49, UART4 Receiver */ +# define INT_U4TX (1 << 5) /* Vector: 49, UART4 Transmitter */ +# define INT_U6E (1 << 6) /* Vector: 50, UART6 Error */ +# define INT_U6RX (1 << 7) /* Vector: 50, UART6 Receiver */ +# define INT_U6TX (1 << 8) /* Vector: 50, UART6 Transmitter */ +# define INT_U5E (1 << 9) /* Vector: 51, UART5 Error */ +# define INT_U5RX (1 << 10) /* Vector: 51, UART5 Receiver */ +# define INT_U5TX (1 << 11) /* Vector: 51, UART5 Transmitter */ + +#endif + +/* Interrupt priority control register 0-11 */ + +#define INT_IPC_DISABLED 0 /* Disabled! */ +#define INT_IPC_MIN_PRIORITY 1 /* Minimum (enabled) priority */ +#define INT_IPC_MID_PRIORITY 4 /* Can be used as the default */ +#define INT_IPC_MAX_PRIORITY 7 /* Maximum priority */ +#define INT_IPC_MIN_SUBPRIORITY 0 /* Minimum sub-priority */ +#define INT_IPC_MAX_SUBPRIORITY 0 /* Maximum sub-priority */ + +#define INT_IPC0_CTIS_SHIFT (0) /* Bits 0-1, Vector: 0, Core Timer Interrupt */ +#define INT_IPC0_CTIS_MASK (3 << INT_IPC0_CTIS_SHIFT) +#define INT_IPC0_CTIP_SHIFT (2) /* Bits 2-4, Vector: 0, Core Timer Interrupt */ +#define INT_IPC0_CTIP_MASK (7 << INT_IPC0_CTIP_SHIFT) +#define INT_IPC0_CS0IS_SHIFT (8) /* Bits 8-9, Vector: 1, Core Software Interrupt 0 */ +#define INT_IPC0_CS0IS_MASK (3 << INT_IPC0_CS0IS_SHIFT) +#define INT_IPC0_CS0IP_SHIFT (10) /* Bits 10-12, Vector: 1, Core Software Interrupt 0 */ +#define INT_IPC0_CS0IP_MASK (7 << INT_IPC0_CS0IP_SHIFT) +#define INT_IPC0_CS1IS_SHIFT (16) /* Bits 16-17, Vector: 2, Core Software Interrupt 1 */ +#define INT_IPC0_CS1IS_MASK (3 << INT_IPC0_CS1IS_SHIFT) +#define INT_IPC0_CS1IP_SHIFT (18) /* Bits 18-20, Vector: 2, Core Software Interrupt 1 */ +#define INT_IPC0_CS1IP_MASK (7 << INT_IPC0_CS1IP_SHIFT) +#define INT_IPC0_INT0IS_SHIFT (24) /* Bits 24-25, Vector: 3, External Interrupt 0 */ +#define INT_IPC0_INT0IS_MASK (3 << INT_IPC0_INT0IS_SHIFT) +#define INT_IPC0_INT0IP_SHIFT (26) /* Bits 26-28, Vector: 3, External Interrupt 0 */ +#define INT_IPC0_INT0IP_MASK (7 << INT_IPC0_INT0IP_SHIFT) + +#define INT_IPC1_T1IS_SHIFT (0) /* Bits 0-1, Vector: 4, Timer 1 */ +#define INT_IPC1_T1IS_MASK (3 << INT_IPC1_T1IS_SHIFT) +#define INT_IPC1_T1IP_SHIFT (2) /* Bits 2-4, Vector: 4, Timer 1 */ +#define INT_IPC1_T1IP_MASK (7 << INT_IPC1_T1IP_SHIFT) +#define INT_IPC1_IC1IS_SHIFT (8) /* Bits 8-9, Vector: 5, Input Capture 1 */ +#define INT_IPC1_IC1IS_MASK (3 << INT_IPC1_IC1IS_SHIFT) +#define INT_IPC1_IC1IP_SHIFT (10) /* Bits 10-12, Vector: 5, Input Capture 1 */ +#define INT_IPC1_IC1IP_MASK (7 << INT_IPC1_IC1IP_SHIFT) +#define INT_IPC1_OC1IS_SHIFT (16) /* Bits 16-17, Vector: 6, Output Compare 1 */ +#define INT_IPC1_OC1IS_MASK (3 << INT_IPC1_OC1IS_SHIFT) +#define INT_IPC1_OC1IP_SHIFT (18) /* Bits 18-20, Vector: 6, Output Compare 1 */ +#define INT_IPC1_OC1IP_MASK (7 << INT_IPC1_OC1IP_SHIFT) +#define INT_IPC1_INT1IS_SHIFT (24) /* Bits 24-25, Vector: 7, External Interrupt 1 */ +#define INT_IPC1_INT1IS_MASK (3 << INT_IPC1_INT1IS_SHIFT) +#define INT_IPC1_INT1IP_SHIFT (26) /* Bits 26-28, Vector: 7, External Interrupt 1 */ +#define INT_IPC1_INT1IP_MASK (7 << INT_IPC1_INT1IP_SHIFT) + +#define INT_IPC2_T2IS_SHIFT (0) /* Bits 0-1, Vector: 8, Timer 2 */ +#define INT_IPC2_T2IS_MASK (3 << INT_IPC2_T2IS_SHIFT) +#define INT_IPC2_T2IP_SHIFT (2) /* Bits 2-4, Vector: 8, Timer 2 */ +#define INT_IPC2_T2IP_MASK (7 << INT_IPC2_T2IP_SHIFT) +#define INT_IPC2_IC2IS_SHIFT (8) /* Bits 8-9, Vector: 9, Input Capture 2 */ +#define INT_IPC2_IC2IS_MASK (3 << INT_IPC2_IC2IS_SHIFT) +#define INT_IPC2_IC2IP_SHIFT (10) /* Bits 10-12, Vector: 9, Input Capture 2 */ +#define INT_IPC2_IC2IP_MASK (7 << INT_IPC2_IC2IP_SHIFT) +#define INT_IPC2_OC2IS_SHIFT (16) /* Bits 16-17, Vector: 10, Output Compare 2 */ +#define INT_IPC2_OC2IS_MASK (3 << INT_IPC2_OC2IS_SHIFT) +#define INT_IPC2_OC2IP_SHIFT (18) /* Bits 18-20, Vector: 10, Output Compare 2 */ +#define INT_IPC2_OC2IP_MASK (7 << INT_IPC2_OC2IP_SHIFT) +#define INT_IPC2_INT2IS_SHIFT (24) /* Bits 24-25, Vector: 11, External Interrupt 2 */ +#define INT_IPC2_INT2IS_MASK (3 << INT_IPC2_INT2IS_SHIFT) +#define INT_IPC2_INT2IP_SHIFT (26) /* Bits 26-28, Vector: 11, External Interrupt 2 */ +#define INT_IPC2_INT2IP_MASK (7 << INT_IPC2_INT2IP_SHIFT) + +#define INT_IPC3_T3IS_SHIFT (0) /* Bits 0-1, Vector: 12, Timer 3 */ +#define INT_IPC3_T3IS_MASK (3 << INT_IPC3_T3IS_SHIFT) +#define INT_IPC3_T3IP_SHIFT (2) /* Bits 2-4, Vector: 12, Timer 3 */ +#define INT_IPC3_T3IP_MASK (7 << INT_IPC3_T3IP_SHIFT) +#define INT_IPC3_IC3IS_SHIFT (8) /* Bits 8-9, Vector: 13, Input Capture 3 */ +#define INT_IPC3_IC3IS_MASK (3 << INT_IPC3_IC3IS_SHIFT) +#define INT_IPC3_IC3IP_SHIFT (10) /* Bits 10-12, Vector: 13, Input Capture 3 */ +#define INT_IPC3_IC3IP_MASK (7 << INT_IPC3_IC3IP_SHIFT) +#define INT_IPC3_OC3IS_SHIFT (16) /* Bits 16-17, Vector: 14, Output Compare 3 */ +#define INT_IPC3_OC3IS_MASK (3 << INT_IPC3_OC3IS_SHIFT) +#define INT_IPC3_OC3IP_SHIFT (18) /* Bits 18-20, Vector: 14, Output Compare 3 */ +#define INT_IPC3_OC3IP_MASK (7 << INT_IPC3_OC3IP_SHIFT) +#define INT_IPC3_INT3IS_SHIFT (24) /* Bits 24-25, Vector: 15, External Interrupt 3 */ +#define INT_IPC3_INT3IS_MASK (3 << INT_IPC3_INT3IS_SHIFT) +#define INT_IPC3_INT3IP_SHIFT (26) /* Bits 26-28, Vector: 15, External Interrupt 3 */ +#define INT_IPC3_INT3IP_MASK (7 << INT_IPC3_INT3IP_SHIFT) + +#define INT_IPC4_T4IS_SHIFT (0) /* Bits 0-1, Vector: 16, Timer 4 */ +#define INT_IPC4_T4IS_MASK (3 << INT_IPC4_T4IS_SHIFT) +#define INT_IPC4_T4IP_SHIFT (2) /* Bits 2-4, Vector: 16, Timer 4 */ +#define INT_IPC4_T4IP_MASK (7 << INT_IPC4_T4IP_SHIFT) +#define INT_IPC4_IC4IS_SHIFT (8) /* Bits 8-9, Vector: 17, Input Capture 4 */ +#define INT_IPC4_IC4IS_MASK (3 << INT_IPC4_IC4IS_SHIFT) +#define INT_IPC4_IC4IP_SHIFT (10) /* Bits 10-12, Vector: 17, Input Capture 4 */ +#define INT_IPC4_IC4IP_MASK (7 << INT_IPC4_IC4IP_SHIFT) +#define INT_IPC4_OC4IS_SHIFT (16) /* Bits 16-17, Vector: 18, Output Compare 4 */ +#define INT_IPC4_OC4IS_MASK (3 << INT_IPC4_OC4IS_SHIFT) +#define INT_IPC4_OC4IP_SHIFT (18) /* Bits 18-20, Vector: 18, Output Compare 4 */ +#define INT_IPC4_OC4IP_MASK (7 << INT_IPC4_OC4IP_SHIFT) +#define INT_IPC4_INT4IS_SHIFT (24) /* Bits 24-25, Vector: 19, External Interrupt 4 */ +#define INT_IPC4_INT4IS_MASK (3 << INT_IPC4_INT4IS_SHIFT) +#define INT_IPC4_INT4IP_SHIFT (26) /* Bits 26-28, Vector: 19, External Interrupt 4 */ +#define INT_IPC4_INT4IP_MASK (7 << INT_IPC4_INT4IP_SHIFT) + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +# define INT_IPC5_T5IS_SHIFT (0) /* Bits 0-1, Vector: 20, Timer 5 */ +# define INT_IPC5_T5IS_MASK (3 << INT_IPC5_T5IS_SHIFT) +# define INT_IPC5_T5IP_SHIFT (2) /* Bits 2-4, Vector: 20, Timer 5 */ +# define INT_IPC5_T5IP_MASK (7 << INT_IPC5_T5IP_SHIFT) +# define INT_IPC5_IC5IS_SHIFT (8) /* Bits 8-9, Vector: 21, Input Capture 5 */ +# define INT_IPC5_IC5IS_MASK (3 << INT_IPC5_IC5IS_SHIFT) +# define INT_IPC5_IC5IP_SHIFT (10) /* Bits 10-12, Vector: 21, Input Capture 5 */ +# define INT_IPC5_IC5IP_MASK (7 << INT_IPC5_IC5IP_SHIFT) +# define INT_IPC5_OC5IS_SHIFT (16) /* Bits 16-17, Vector: 22, Output Compare 5 */ +# define INT_IPC5_OC5IS_MASK (3 << INT_IPC5_OC5IS_SHIFT) +# define INT_IPC5_OC5IP_SHIFT (18) /* Bits 18-20, Vector: 22, Output Compare 5 */ +# define INT_IPC5_OC5IP_MASK (7 << INT_IPC5_OC5IP_SHIFT) +# define INT_IPC5_SPI1IS_SHIFT (24) /* Bits 24-25, Vector: 23, SPI1 */ +# define INT_IPC5_SPI1IS_MASK (3 << INT_IPC5_SPI1IS_SHIFT) +# define INT_IPC5_SPI1IP_SHIFT (26) /* Bits 26-28, Vector: 23, SPI1 */ +# define INT_IPC5_SPI1IP_MASK (7 << INT_IPC5_SPI1IP_SHIFT) +# define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 23, ADC1 Convert Done */ +# define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT) +# define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 23, ADC1 Convert Done */ +# define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT) + +#else + +# define INT_IPC5_T5IS_SHIFT (0) /* Bits 0-1, Vector: 20, Timer 5 */ +# define INT_IPC5_T5IS_MASK (3 << INT_IPC5_T5IS_SHIFT) +# define INT_IPC5_T5IP_SHIFT (2) /* Bits 2-4, Vector: 20, Timer 5 */ +# define INT_IPC5_T5IP_MASK (7 << INT_IPC5_T5IP_SHIFT) +# define INT_IPC5_IC5IS_SHIFT (8) /* Bits 8-9, Vector: 21, Input Capture 5 */ +# define INT_IPC5_IC5IS_MASK (3 << INT_IPC5_IC5IS_SHIFT) +# define INT_IPC5_IC5IP_SHIFT (10) /* Bits 10-12, Vector: 21, Input Capture 5 */ +# define INT_IPC5_IC5IP_MASK (7 << INT_IPC5_IC5IP_SHIFT) +# define INT_IPC5_OC5IS_SHIFT (16) /* Bits 16-17, Vector: 22, Output Compare 5 */ +# define INT_IPC5_OC5IS_MASK (3 << INT_IPC5_OC5IS_SHIFT) +# define INT_IPC5_OC5IP_SHIFT (18) /* Bits 18-20, Vector: 22, Output Compare 5 */ +# define INT_IPC5_OC5IP_MASK (7 << INT_IPC5_OC5IP_SHIFT) +# define INT_IPC5_SPI1IS_SHIFT (24) /* Bits 24-25, Vector: 23, SPI1 */ +# define INT_IPC5_SPI1IS_MASK (3 << INT_IPC5_SPI1IS_SHIFT) +# define INT_IPC5_SPI1IP_SHIFT (26) /* Bits 26-28, Vector: 23, SPI1 */ +# define INT_IPC5_SPI1IP_MASK (7 << INT_IPC5_SPI1IP_SHIFT) + +#endif + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +# define INT_IPC6_FSCMIS_SHIFT (0) /* Bits 0-1, Vector: 24, Fail-Safe Clock Monitor */ +# define INT_IPC6_FSCMIS_MASK (3 << INT_IPC6_FSCMIS_SHIFT) +# define INT_IPC6_FSCMIP_SHIFT (2) /* Bits 2-4, Vector: 24, Fail-Safe Clock Monitor */ +# define INT_IPC6_FSCMIP_MASK (7 << INT_IPC6_FSCMIP_SHIFT) +# define INT_IPC6_RTCCIS_SHIFT (8) /* Bits 8-9, Vector: 25, Real-Time Clock and Calendar */ +# define INT_IPC6_RTCCIS_MASK (3 << INT_IPC6_RTCCIS_SHIFT) +# define INT_IPC6_RTCCIP_SHIFT (10) /* Bits 10-12, Vector: 25, Real-Time Clock and Calendar */ +# define INT_IPC6_RTCCIP_MASK (7 << INT_IPC6_RTCCIP_SHIFT) +# define INT_IPC6_FCEIS_SHIFT (16) /* Bits 16-17, Vector: 26, Flash Control Event */ +# define INT_IPC6_FCEIS_MASK (3 << INT_IPC6_FCEIS_SHIFT) +# define INT_IPC6_FCEIP_SHIFT (18) /* Bits 18-20, Vector: 26, Flash Control Event */ +# define INT_IPC6_FCEIP_MASK (7 << INT_IPC6_FCEIP_SHIFT) +# define INT_IPC6_CMP1IS_SHIFT (24) /* Bits 24-25, Vector: 27, Comparator 1 */ +# define INT_IPC6_CMP1IS_MASK (3 << INT_IPC6_CMP1IS_SHIFT) +# define INT_IPC6_CMP1IP_SHIFT (26) /* Bits 26-28, Vector: 27, Comparator 1 */ +# define INT_IPC6_CMP1IP_MASK (7 << INT_IPC6_CMP1IP_SHIFT) + +# define INT_IPC7_CMP2IS_SHIFT (0) /* Bits 0-1, Vector: 28, Comparator 2 */ +# define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT) +# define INT_IPC7_CMP2IP_SHIFT (2) /* Bits 2-4, Vector: 28, Comparator 2 */ +# define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT) +# define INT_IPC7_CMP3IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */ +# define INT_IPC7_CMP3IS_MASK (3 << INT_IPC7_CMP3IS_SHIFT) +# define INT_IPC7_CMP3IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */ +# define INT_IPC7_CMP3IP_MASK (7 << INT_IPC7_CMP3IP_SHIFT) +# define INT_IPC7_USBIS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */ +# define INT_IPC7_USBIS_MASK (3 << INT_IPC7_USBIS_SHIFT) +# define INT_IPC7_USBIP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */ +# define INT_IPC7_USBIP_MASK (7 << INT_IPC7_USBIP_SHIFT) +# define INT_IPC7_SPI1IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI1 */ +# define INT_IPC7_SPI1IS_MASK (3 << INT_IPC7_SPI1IS_SHIFT) +# define INT_IPC7_SPI1IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI1 */ +# define INT_IPC7_SPI1IP_MASK (7 << INT_IPC7_SPI1IP_SHIFT) + +# define INT_IPC8_U1IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART1 */ +# define INT_IPC8_U1IS_MASK (3 << INT_IPC8_U1IS_SHIFT) +# define INT_IPC8_U1IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART1 */ +# define INT_IPC8_U1IP_MASK (7 << INT_IPC8_U1IP_SHIFT) +# define INT_IPC8_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C1 */ +# define INT_IPC8_I2C1IS_MASK (3 << INT_IPC8_I2C1IS_SHIFT) +# define INT_IPC8_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C1 */ +# define INT_IPC8_I2C1IP_MASK (7 << INT_IPC8_I2C1IP_SHIFT) +# define INT_IPC8_CNIS_SHIFT (16) /* Bits 16-17, Vector: 34, Input Change */ +# define INT_IPC8_CNIS_MASK (3 << INT_IPC8_CNIS_SHIFT) +# define INT_IPC8_CNIP_SHIFT (18) /* Bits 18-20, Vector: 34, Input Change */ +# define INT_IPC8_CNIP_MASK (7 << INT_IPC8_CNIP_SHIFT) +# define INT_IPC8_PMPIS_SHIFT (24) /* Bits 24-25, Vector: 35, Parallel Master Port */ +# define INT_IPC8_PMPIS_MASK (3 << INT_IPC8_PMPIS_SHIFT) +# define INT_IPC8_PMPIP_SHIFT (26) /* Bits 26-28, Vector: 35, RParallel Master Port */ +# define INT_IPC8_PMPIP_MASK (7 << INT_IPC8_PMPIP_SHIFT) + +# define INT_IPC9_SPI2IS_SHIFT (0) /* Bits 0-1, Vector: 36, SPI2 */ +# define INT_IPC9_SPI2IS_MASK (3 << INT_IPC9_SPI2IS_SHIFT) +# define INT_IPC9_SPI2IP_SHIFT (2) /* Bits 2-4, Vector: 36, SPI2 */ +# define INT_IPC9_SPI2IP_MASK (7 << INT_IPC9_SPI2IP_SHIFT) +# define INT_IPC9_U2IS_SHIFT (8) /* Bits 8-9, Vector: 37, UART2 */ +# define INT_IPC9_U2IS_MASK (3 << INT_IPC9_U2IS_SHIFT) +# define INT_IPC9_U2IP_SHIFT (10) /* Bits 10-12, Vector: 37, UART2 */ +# define INT_IPC9_U2IP_MASK (7 << INT_IPC9_U2IP_SHIFT) +# define INT_IPC9_I2C2IS_SHIFT (16) /* Bits 16-17, Vector: 38, I2C2 */ +# define INT_IPC9_I2C2IS_MASK (3 << INT_IPC9_I2C2IS_SHIFT) +# define INT_IPC9_I2C2IP_SHIFT (18) /* Bits 18-20, Vector: 38, I2C2 */ +# define INT_IPC9_I2C2IP_MASK (7 << INT_IPC9_I2C2IP_SHIFT) +# define INT_IPC9_CTMUIS_SHIFT (24) /* Bits 24-25, Vector: 39, CTMU */ +# define INT_IPC9_CTMUIS_MASK (3 << INT_IPC9_CTMUIS_SHIFT) +# define INT_IPC9_CTMUIP_SHIFT (26) /* Bits 26-28, Vector: 39, CTMU */ +# define INT_IPC9_CTMUIP_MASK (7 << INT_IPC9_CTMUIP_SHIFT) + +# define INT_IPC10_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 40, DMA Channel 0 */ +# define INT_IPC10_DMA0IS_MASK (3 << INT_IPC10_DMA0IS_SHIFT) +# define INT_IPC10_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 40, DMA Channel 0 */ +# define INT_IPC10_DMA0IP_MASK (7 << INT_IPC10_DMA0IP_SHIFT) +# define INT_IPC10_DMA1IS_SHIFT (8) /* Bits 8-10, Vector: 41, DMA Channel 1 */ +# define INT_IPC10_DMA1IS_MASK (3 << INT_IPC10_DMA1IS_SHIFT) +# define INT_IPC10_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 41, DMA Channel 1 */ +# define INT_IPC10_DMA1IP_MASK (7 << INT_IPC10_DMA1IP_SHIFT) +# define INT_IPC10_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 42, DMA Channel 2 */ +# define INT_IPC10_DMA2IS_MASK (3 << INT_IPC10_DMA2IS_SHIFT) +# define INT_IPC10_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 42, DMA Channel 2 */ +# define INT_IPC10_DMA2IP_MASK (7 << INT_IPC10_DMA2IP_SHIFT) +# define INT_IPC10_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 43, DMA Channel 3 */ +# define INT_IPC10_DMA3IS_MASK (3 << INT_IPC10_DMA3IS_SHIFT) +# define INT_IPC10_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 43, DMA Channel 3 */ +# define INT_IPC10_DMA3IP_MASK (7 << INT_IPC10_DMA3IP_SHIFT) + +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +# define INT_IPC6_U1IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1 */ +# define INT_IPC6_U1IS_MASK (3 << INT_IPC6_U1IS_SHIFT) +# define INT_IPC6_U1IP_SHIFT (2) /* Bits 2-4, Vector: 24, UART1 */ +# define INT_IPC6_U1IP_MASK (7 << INT_IPC6_U1IP_SHIFT) +# define INT_IPC6_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 25, I2C1 */ +# define INT_IPC6_I2C1IS_MASK (3 << INT_IPC6_I2C1IS_SHIFT) +# define INT_IPC6_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 25, I2C1 */ +# define INT_IPC6_I2C1IP_MASK (7 << INT_IPC6_I2C1IP_SHIFT) +# define INT_IPC6_CNIS_SHIFT (16) /* Bits 16-17, Vector: 26, Input Change Interrupt */ +# define INT_IPC6_CNIS_MASK (3 << INT_IPC6_CNIS_SHIFT) +# define INT_IPC6_CNIP_SHIFT (18) /* Bits 18-20, Vector: 26, Input Change Interrupt */ +# define INT_IPC6_CNIP_MASK (7 << INT_IPC6_CNIP_SHIFT) +# define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 27, ADC1 Convert Done */ +# define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT) +# define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 27, ADC1 Convert Done */ +# define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT) + +# define INT_IPC7_PMPIS_SHIFT (0) /* Bits 0-1, Vector: 28, Parallel Master Port */ +# define INT_IPC7_PMPIS_MASK (3 << INT_IPC7_PMPIS_SHIFT) +# define INT_IPC7_PMPIP_SHIFT (2) /* Bits 2-4, Vector: 28, Parallel Master Port */ +# define INT_IPC7_PMPIP_MASK (7 << INT_IPC7_PMPIP_SHIFT) +# define INT_IPC7_CMP1IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */ +# define INT_IPC7_CMP1IS_MASK (3 << INT_IPC7_CMP1IS_SHIFT) +# define INT_IPC7_CMP1IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */ +# define INT_IPC7_CMP1IP_MASK (7 << INT_IPC7_CMP1IP_SHIFT) +# define INT_IPC7_CMP2IS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */ +# define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT) +# define INT_IPC7_CMP2IP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */ +# define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT) +# define INT_IPC7_SPI2IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI2 */ +# define INT_IPC7_SPI2IS_MASK (3 << INT_IPC7_SPI2IS_SHIFT) +# define INT_IPC7_SPI2IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI2 */ +# define INT_IPC7_SPI2IP_MASK (7 << INT_IPC7_SPI2IP_SHIFT) + +# define INT_IPC8_U2IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2 */ +# define INT_IPC8_U2IS_MASK (3 << INT_IPC8_U2IS_SHIFT) +# define INT_IPC8_U2IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART2 */ +# define INT_IPC8_U2IP_MASK (7 << INT_IPC8_U2IP_SHIFT) +# define INT_IPC8_I2C2IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C2 */ +# define INT_IPC8_I2C2IS_MASK (3 << INT_IPC8_I2C2IS_SHIFT) +# define INT_IPC8_I2C2IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C2 */ +# define INT_IPC8_I2C2IP_MASK (7 << INT_IPC8_I2C2IP_SHIFT) +# define INT_IPC8_FSCMIS_SHIFT (16) /* Bits 16-17, Vector: 34, Fail-Safe Clock Monitor */ +# define INT_IPC8_FSCMIS_MASK (3 << INT_IPC8_FSCMIS_SHIFT) +# define INT_IPC8_FSCMIP_SHIFT (18) /* Bits 18-20, Vector: 34, Fail-Safe Clock Monitor */ +# define INT_IPC8_FSCMIP_MASK (7 << INT_IPC8_FSCMIP_SHIFT) +# define INT_IPC8_RTCCIS_SHIFT (24) /* Bits 24-25, Vector: 35, Real-Time Clock and Calendar */ +# define INT_IPC8_RTCCIS_MASK (3 << INT_IPC8_RTCCIS_SHIFT) +# define INT_IPC8_RTCCIP_SHIFT (26) /* Bits 26-28, Vector: 35, Real-Time Clock and Calendar */ +# define INT_IPC8_RTCCIP_MASK (7 << INT_IPC8_RTCCIP_SHIFT) + +# define INT_IPC9_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 0 */ +# define INT_IPC9_DMA0IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT) +# define INT_IPC9_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 0 */ +# define INT_IPC9_DMA0IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT) +# define INT_IPC9_DMA1IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 1 */ +# define INT_IPC9_DMA1IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT) +# define INT_IPC9_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 1 */ +# define INT_IPC9_DMA1IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT) +# define INT_IPC9_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 2 */ +# define INT_IPC9_DMA2IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT) +# define INT_IPC9_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 2 */ +# define INT_IPC9_DMA2IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT) +# define INT_IPC9_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 3 */ +# define INT_IPC9_DMA3IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT) +# define INT_IPC9_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 3 */ +# define INT_IPC9_DMA3IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT) + +# define INT_IPC11_FCEIS_SHIFT (0) /* Bits 0-1, Vector: 44, Flash Control Event */ +# define INT_IPC11_FCEIS_MASK (3 << INT_IPC11_FCEIS_SHIFT) +# define INT_IPC11_FCEIP_SHIFT (2) /* Bits 2-4, Vector: 44, Flash Control Event */ +# define INT_IPC11_FCEIP_MASK (7 << INT_IPC11_FCEIP_SHIFT) +# define INT_IPC11_USBIS_SHIFT (8) /* Bits 8-9, Vector: 45, USB */ +# define INT_IPC11_USBIS_MASK (3 << INT_IPC11_USBIS_SHIFT) +# define INT_IPC11_USBIP_SHIFT (10) /* Bits 10-12, Vector: 45, USB */ +# define INT_IPC11_USBIP_MASK (7 << INT_IPC11_USBIP_SHIFT) + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +# define INT_IPC6_VEC24IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1, SPI3, I2C3 */ +# define INT_IPC6_VEC24IS_MASK (3 << INT_IPC6_INT26IS_SHIFT) +# define INT_IPC6_U1IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1 */ +# define INT_IPC6_U1IS_MASK (3 << INT_IPC6_U1IS_SHIFT) +# define INT_IPC6_SPI3IS_SHIFT (0) /* Bits 0-1, Vector: 24, SPI3 */ +# define INT_IPC6_SPI3IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT) +# define INT_IPC6_I2C3IS_SHIFT (0) /* Bits 0-1, Vector: 24, I2C3 */ +# define INT_IPC6_I2C3IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT) +# define INT_IPC6_VEC24IP_SHIFT (0) /* Bits 2-4, Vector: 24, UART1, SPI3, I2C3 */ +# define INT_IPC6_VEC24IP_MASK (7 << INT_IPC6_INT26IP_SHIFT) +# define INT_IPC6_U1IP_SHIFT (2) /* Bits 2-4, Vector: 24, UART1 */ +# define INT_IPC6_U1IP_MASK (7 << INT_IPC6_U1IP_SHIFT) +# define INT_IPC6_SPI3IP_SHIFT (2) /* Bits 2-4, Vector: 24, SPI3 */ +# define INT_IPC6_SPI3IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT) +# define INT_IPC6_I2C3IP_SHIFT (2) /* Bits 2-4, Vector: 24, I2C3 */ +# define INT_IPC6_I2C3IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT) +# define INT_IPC6_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 25, I2C1 */ +# define INT_IPC6_I2C1IS_MASK (3 << INT_IPC6_I2C1IS_SHIFT) +# define INT_IPC6_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 25, I2C1 */ +# define INT_IPC6_I2C1IP_MASK (7 << INT_IPC6_I2C1IP_SHIFT) +# define INT_IPC6_CNIS_SHIFT (16) /* Bits 16-17, Vector: 26, Input Change Interrupt */ +# define INT_IPC6_CNIS_MASK (3 << INT_IPC6_CNIS_SHIFT) +# define INT_IPC6_CNIP_SHIFT (18) /* Bits 18-20, Vector: 26, Input Change Interrupt */ +# define INT_IPC6_CNIP_MASK (7 << INT_IPC6_CNIP_SHIFT) +# define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 27, ADC1 Convert Done */ +# define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT) +# define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 27, ADC1 Convert Done */ +# define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT) + +# define INT_IPC7_PMPIS_SHIFT (0) /* Bits 0-1, Vector: 28, Parallel Master Port */ +# define INT_IPC7_PMPIS_MASK (3 << INT_IPC7_PMPIS_SHIFT) +# define INT_IPC7_PMPIP_SHIFT (2) /* Bits 2-4, Vector: 28, Parallel Master Port */ +# define INT_IPC7_PMPIP_MASK (7 << INT_IPC7_PMPIP_SHIFT) +# define INT_IPC7_CMP1IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */ +# define INT_IPC7_CMP1IS_MASK (3 << INT_IPC7_CMP1IS_SHIFT) +# define INT_IPC7_CMP1IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */ +# define INT_IPC7_CMP1IP_MASK (7 << INT_IPC7_CMP1IP_SHIFT) +# define INT_IPC7_CMP2IS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */ +# define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT) +# define INT_IPC7_CMP2IP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */ +# define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT) +# define INT_IPC6_VEC31IS_SHIFT (24) /* Bits 24-25, Vector: 31, UART3, SPI2, I2C4 */ +# define INT_IPC6_VEC31IS_MASK (3 << INT_IPC6_INT26IS_SHIFT) +# define INT_IPC6_U3IS_SHIFT (24) /* Bits 24-25, Vector: 31, UART3 */ +# define INT_IPC6_U3IS_MASK (3 << INT_IPC6_U1IS_SHIFT) +# define INT_IPC6_SPI2IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI2 */ +# define INT_IPC6_SPI2IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT) +# define INT_IPC6_I2C4IS_SHIFT (24) /* Bits 24-25, Vector: 31, I2C4 */ +# define INT_IPC6_I2C4IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT) +# define INT_IPC6_VEC31IP_SHIFT (26) /* Bits 26-28, Vector: 31, UART3, SPI2, I2C4 */ +# define INT_IPC6_VEC31IP_MASK (7 << INT_IPC6_INT26IP_SHIFT) +# define INT_IPC6_U3IP_SHIFT (26) /* Bits 26-28, Vector: 31, UART3 */ +# define INT_IPC6_U3IP_MASK (7 << INT_IPC6_U1IP_SHIFT) +# define INT_IPC6_SPI2IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI2 */ +# define INT_IPC6_SPI2IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT) +# define INT_IPC6_I2C4IP_SHIFT (26) /* Bits 26-28, Vector: 31, I2C4 */ +# define INT_IPC6_I2C4IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT) + +# define INT_IPC6_VEC32IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2, SPI4, I2C5 */ +# define INT_IPC6_VEC32IS_MASK (3 << INT_IPC6_INT26IS_SHIFT) +# define INT_IPC6_U2IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2 */ +# define INT_IPC6_U2IS_MASK (3 << INT_IPC6_U1IS_SHIFT) +# define INT_IPC6_SPI4IS_SHIFT (0) /* Bits 0-1, Vector: 32, SPI4 */ +# define INT_IPC6_SPI4IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT) +# define INT_IPC6_I2C5IS_SHIFT (0) /* Bits 0-1, Vector: 32, I2C5 */ +# define INT_IPC6_I2C5IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT) +# define INT_IPC6_VEC32IP_SHIFT (0) /* Bits 2-4, Vector: 32, UART2, SPI4, I2C5 */ +# define INT_IPC6_VEC32IP_MASK (7 << INT_IPC6_INT26IP_SHIFT) +# define INT_IPC6_U2IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART2 */ +# define INT_IPC6_U2IP_MASK (7 << INT_IPC6_U1IP_SHIFT) +# define INT_IPC6_SPI4IP_SHIFT (2) /* Bits 2-4, Vector: 32, SPI4 */ +# define INT_IPC6_SPI4IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT) +# define INT_IPC6_I2C5IP_SHIFT (2) /* Bits 2-4, Vector: 32, I2C5 */ +# define INT_IPC6_I2C5IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT) +# define INT_IPC8_I2C2IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C2 */ +# define INT_IPC8_I2C2IS_MASK (3 << INT_IPC8_I2C2IS_SHIFT) +# define INT_IPC8_I2C2IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C2 */ +# define INT_IPC8_I2C2IP_MASK (7 << INT_IPC8_I2C2IP_SHIFT) +# define INT_IPC8_FSCMIS_SHIFT (16) /* Bits 16-17, Vector: 34, Fail-Safe Clock Monitor */ +# define INT_IPC8_FSCMIS_MASK (3 << INT_IPC8_FSCMIS_SHIFT) +# define INT_IPC8_FSCMIP_SHIFT (18) /* Bits 18-20, Vector: 34, Fail-Safe Clock Monitor */ +# define INT_IPC8_FSCMIP_MASK (7 << INT_IPC8_FSCMIP_SHIFT) +# define INT_IPC8_RTCCIS_SHIFT (24) /* Bits 24-25, Vector: 35, Real-Time Clock and Calendar */ +# define INT_IPC8_RTCCIS_MASK (3 << INT_IPC8_RTCCIS_SHIFT) +# define INT_IPC8_RTCCIP_SHIFT (26) /* Bits 26-28, Vector: 35, Real-Time Clock and Calendar */ +# define INT_IPC8_RTCCIP_MASK (7 << INT_IPC8_RTCCIP_SHIFT) + +# define INT_IPC9_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 0 */ +# define INT_IPC9_DMA0IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT) +# define INT_IPC9_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 0 */ +# define INT_IPC9_DMA0IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT) +# define INT_IPC9_DMA1IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 1 */ +# define INT_IPC9_DMA1IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT) +# define INT_IPC9_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 1 */ +# define INT_IPC9_DMA1IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT) +# define INT_IPC9_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 2 */ +# define INT_IPC9_DMA2IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT) +# define INT_IPC9_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 2 */ +# define INT_IPC9_DMA2IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT) +# define INT_IPC9_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 3 */ +# define INT_IPC9_DMA3IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT) +# define INT_IPC9_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 3 */ +# define INT_IPC9_DMA3IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT) + +# define INT_IPC10_DMA4IS_SHIFT (0) /* Bits 0-1, Vector: 40, DMA Channel 4 */ +# define INT_IPC10_DMA4IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT) +# define INT_IPC10_DMA4IP_SHIFT (2) /* Bits 2-4, Vector: 40, DMA Channel 4 */ +# define INT_IPC10_DMA4IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT) +# define INT_IPC10_DMA5IS_SHIFT (8) /* Bits 8-9, Vector: 41, DMA Channel 5 */ +# define INT_IPC10_DMA5IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT) +# define INT_IPC10_DMA5IP_SHIFT (10) /* Bits 10-12, Vector: 41, DMA Channel 5 */ +# define INT_IPC10_DMA5IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT) +# define INT_IPC10_DMA6IS_SHIFT (16) /* Bits 16-17, Vector: 42, DMA Channel 6 */ +# define INT_IPC10_DMA6IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT) +# define INT_IPC10_DMA6IP_SHIFT (18) /* Bits 18-20, Vector: 42, DMA Channel 6 */ +# define INT_IPC10_DMA6IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT) +# define INT_IPC10_DMA7IS_SHIFT (24) /* Bits 24-25, Vector: 43, DMA Channel 7 */ +# define INT_IPC10_DMA7IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT) +# define INT_IPC10_DMA7IP_SHIFT (26) /* Bits 26-28, Vector: 43, DMA Channel 7 */ +# define INT_IPC10_DMA7IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT) + +# define INT_IPC11_FCEIS_SHIFT (0) /* Bits 0-1, Vector: 44, Flash Control Event */ +# define INT_IPC11_FCEIS_MASK (3 << INT_IPC11_FCEIS_SHIFT) +# define INT_IPC11_FCEIP_SHIFT (2) /* Bits 2-4, Vector: 44, Flash Control Event */ +# define INT_IPC11_FCEIP_MASK (7 << INT_IPC11_FCEIP_SHIFT) +# define INT_IPC11_USBIS_SHIFT (8) /* Bits 8-9, Vector: 45, USB */ +# define INT_IPC11_USBIS_MASK (3 << INT_IPC11_USBIS_SHIFT) +# define INT_IPC11_USBIP_SHIFT (10) /* Bits 10-12, Vector: 45, USB */ +# define INT_IPC11_USBIP_MASK (7 << INT_IPC11_USBIP_SHIFT) +# define INT_IPC11_CAN1IS_SHIFT (16) /* Bits 16-17, Vector: 46, Controller area network 1 */ +# define INT_IPC11_CAN1IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT) +# define INT_IPC11_CAN1IP_SHIFT (18) /* Bits 18-20, Vector: 46, Controller area network 1 */ +# define INT_IPC11_CAN1IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT) +# define INT_IPC11_CAN2IS_SHIFT (24) /* Bits 24-25, Vector: 47, Controller area network 2 */ +# define INT_IPC11_CAN2IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT) +# define INT_IPC11_CAN2IP_SHIFT (26) /* Bits 26-28, Vector: 47, Controller area network 2 */ +# define INT_IPC11_CAN2IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT) + +# define INT_IPC12_ETHIS_SHIFT (0) /* Bits 0-1, Vector: 48, Ethernet interrupt */ +# define INT_IPC12_ETHIS_MASK (3 << INT_IPC11_FCEIS_SHIFT) +# define INT_IPC12_ETHIP_SHIFT (2) /* Bits 2-4, Vector: 48, Ethernet interrupt */ +# define INT_IPC12_ETHIP_MASK (7 << INT_IPC11_FCEIP_SHIFT) +# define INT_IPC12_U4IS_SHIFT (8) /* Bits 8-9, Vector: 49, UART4 */ +# define INT_IPC12_U4IS_MASK (3 << INT_IPC11_USBIS_SHIFT) +# define INT_IPC12_U4IP_SHIFT (10) /* Bits 10-12, Vector: 49, UART4 */ +# define INT_IPC12_U4IP_MASK (7 << INT_IPC11_USBIP_SHIFT) +# define INT_IPC12_U6IS_SHIFT (16) /* Bits 16-17, Vector: 50, UART6 */ +# define INT_IPC12_U6IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT) +# define INT_IPC12_U6IP_SHIFT (18) /* Bits 18-20, Vector: 50, UART6 */ +# define INT_IPC12_U6IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT) +# define INT_IPC12_U5IS_SHIFT (24) /* Bits 24-25, Vector: 51, UART5 */ +# define INT_IPC12_U5IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT) +# define INT_IPC12_U5IP_SHIFT (26) /* Bits 26-28, Vector: 51, UART5 */ +# define INT_IPC12_U5IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT) + +#else +# error "Unknown PIC32MX family +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_INT_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h b/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h index 6d9373df8..7ba2d239f 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-internal.h @@ -59,7 +59,7 @@ /* GPIO settings used in the configport, readport, writeport, etc. * * General encoding: - * MMxV IIxx RRRx PPPP + * MMxV IIDx RRRx PPPP */ #define GPIO_MODE_SHIFT (14) /* Bits 14-15: I/O mode */ @@ -72,12 +72,20 @@ # define GPIO_VALUE_ONE (1 << 12) # define GPIO_VALUE_ZERO (0) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define GPIO_PULLUP (1 << 11) /* Bit 11: Change notification pull-up */ +#endif + #define GPIO_INT_SHIFT (10) /* Bits 10-11: Interrupt mode */ #define GPIO_INT_MASK (3 << GPIO_INT_SHIFT) # define GPIO_INT_NONE (0 << GPIO_INT_SHIFT) /* Bit 00: No interrupt */ # define GPIO_INT (1 << GPIO_INT_SHIFT) /* Bit 01: Change notification enable */ # define GPIO_PUINT (3 << GPIO_INT_SHIFT) /* Bit 11: Pulled-up interrupt input */ +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define GPIO_PULLDOWN (1 << 9) /* Bit 11: Change notification pull-down */ +#endif + #define GPIO_PORT_SHIFT (5) /* Bits 5-7: Port number */ #define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h b/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h index a84d05cb9..578ce055b 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ioport.h @@ -49,42 +49,92 @@ * Pre-Processor Definitions ********************************************************************************************/ /* Register Offsets *************************************************************************/ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +/* Offsets relative to PIC32MX_IOPORTn_K1BASE */ + +# define PIC32MX_IOPORT_ANSEL_OFFSET 0x0000 /* Analog select register */ +# define PIC32MX_IOPORT_ANSELCLR_OFFSET 0x0004 /* Analog select clear register */ +# define PIC32MX_IOPORT_ANSELSET_OFFSET 0x0008 /* Analog select set register */ +# define PIC32MX_IOPORT_ANSELINV_OFFSET 0x000c /* Analog select invert register */ +# define PIC32MX_IOPORT_TRIS_OFFSET 0x0010 /* Tri-state register */ +# define PIC32MX_IOPORT_TRISCLR_OFFSET 0x0014 /* Tri-state clear register */ +# define PIC32MX_IOPORT_TRISSET_OFFSET 0x0018 /* Tri-state set register */ +# define PIC32MX_IOPORT_TRISINV_OFFSET 0x001c /* Tri-state invert register */ +# define PIC32MX_IOPORT_PORT_OFFSET 0x0020 /* Port register */ +# define PIC32MX_IOPORT_PORTCLR_OFFSET 0x0024 /* Port clear register */ +# define PIC32MX_IOPORT_PORTSET_OFFSET 0x0028 /* Port set register */ +# define PIC32MX_IOPORT_PORTINV_OFFSET 0x002c /* Port invert register */ +# define PIC32MX_IOPORT_LAT_OFFSET 0x0030 /* Port data latch register */ +# define PIC32MX_IOPORT_LATCLR_OFFSET 0x0034 /* Port data latch clear register */ +# define PIC32MX_IOPORT_LATSET_OFFSET 0x0038 /* Port data latch set register */ +# define PIC32MX_IOPORT_LATINV_OFFSET 0x003c /* Port data latch invert register */ +# define PIC32MX_IOPORT_ODC_OFFSET 0x0040 /* Open drain control register */ +# define PIC32MX_IOPORT_ODCCLR_OFFSET 0x0044 /* Open drain control clear register */ +# define PIC32MX_IOPORT_ODCSET_OFFSET 0x0048 /* Open drain control set register */ +# define PIC32MX_IOPORT_ODCINV_OFFSET 0x004c /* Open drain control invert register */ +# define PIC32MX_IOPORT_CNPU_OFFSET 0x0050 /* Change Notification Pull-up register */ +# define PIC32MX_IOPORT_CNPUCLR_OFFSET 0x0054 /* Change Notification Pull-up clear register */ +# define PIC32MX_IOPORT_CNPUSET_OFFSET 0x0058 /* Change Notification Pull-up set register */ +# define PIC32MX_IOPORT_CNPUINV_OFFSET 0x005c /* Change Notification Pull-up invert register */ +# define PIC32MX_IOPORT_CNPD_OFFSET 0x0060 /* Change Notification Pull-down register */ +# define PIC32MX_IOPORT_CNPDCLR_OFFSET 0x0064 /* Change Notification Pull-down clear register */ +# define PIC32MX_IOPORT_CNPDSET_OFFSET 0x0068 /* Change Notification Pull-down set register */ +# define PIC32MX_IOPORT_CNPDINV_OFFSET 0x006c /* Change Notification Pull-down invert register */ +# define PIC32MX_IOPORT_CNCON_OFFSET 0x0070 /* Change Notification Control register */ +# define PIC32MX_IOPORT_CNCONCLR_OFFSET 0x0074 /* Change Notification Control clear register */ +# define PIC32MX_IOPORT_CNCONSET_OFFSET 0x0078 /* Change Notification Control set register */ +# define PIC32MX_IOPORT_CNCONINV_OFFSET 0x007c /* Change Notification Control invert register */ +# define PIC32MX_IOPORT_CNEN_OFFSET 0x0080 /* Change Notification Interrupt Enable register */ +# define PIC32MX_IOPORT_CNENCLR_OFFSET 0x0084 /* Change Notification Interrupt Enable clear register */ +# define PIC32MX_IOPORT_CNENSET_OFFSET 0x0088 /* Change Notification Interrupt Enable set register */ +# define PIC32MX_IOPORT_CNENINV_OFFSET 0x008c /* Change Notification Interrupt Enable *invert register */ + +#else /* Offsets relative to PIC32MX_IOPORTn_K1BASE */ -#define PIC32MX_IOPORT_TRIS_OFFSET 0x0000 /* Tri-state register */ -#define PIC32MX_IOPORT_TRISCLR_OFFSET 0x0004 /* Tri-state clear register */ -#define PIC32MX_IOPORT_TRISSET_OFFSET 0x0008 /* Tri-state set register */ -#define PIC32MX_IOPORT_TRISINV_OFFSET 0x000c /* Tri-state invert register */ -#define PIC32MX_IOPORT_PORT_OFFSET 0x0010 /* Port register */ -#define PIC32MX_IOPORT_PORTCLR_OFFSET 0x0014 /* Port clear register */ -#define PIC32MX_IOPORT_PORTSET_OFFSET 0x0018 /* Port set register */ -#define PIC32MX_IOPORT_PORTINV_OFFSET 0x001c /* Port invert register */ -#define PIC32MX_IOPORT_LAT_OFFSET 0x0020 /* Port data latch register */ -#define PIC32MX_IOPORT_LATCLR_OFFSET 0x0024 /* Port data latch clear register */ -#define PIC32MX_IOPORT_LATSET_OFFSET 0x0028 /* Port data latch set register */ -#define PIC32MX_IOPORT_LATINV_OFFSET 0x002c /* Port data latch invert register */ -#define PIC32MX_IOPORT_ODC_OFFSET 0x0030 /* Open drain control register */ -#define PIC32MX_IOPORT_ODCCLR_OFFSET 0x0034 /* Open drain control clear register */ -#define PIC32MX_IOPORT_ODCSET_OFFSET 0x0038 /* Open drain control set register */ -#define PIC32MX_IOPORT_ODCINV_OFFSET 0x003c /* Open drain control invert register */ +# define PIC32MX_IOPORT_TRIS_OFFSET 0x0000 /* Tri-state register */ +# define PIC32MX_IOPORT_TRISCLR_OFFSET 0x0004 /* Tri-state clear register */ +# define PIC32MX_IOPORT_TRISSET_OFFSET 0x0008 /* Tri-state set register */ +# define PIC32MX_IOPORT_TRISINV_OFFSET 0x000c /* Tri-state invert register */ +# define PIC32MX_IOPORT_PORT_OFFSET 0x0010 /* Port register */ +# define PIC32MX_IOPORT_PORTCLR_OFFSET 0x0014 /* Port clear register */ +# define PIC32MX_IOPORT_PORTSET_OFFSET 0x0018 /* Port set register */ +# define PIC32MX_IOPORT_PORTINV_OFFSET 0x001c /* Port invert register */ +# define PIC32MX_IOPORT_LAT_OFFSET 0x0020 /* Port data latch register */ +# define PIC32MX_IOPORT_LATCLR_OFFSET 0x0024 /* Port data latch clear register */ +# define PIC32MX_IOPORT_LATSET_OFFSET 0x0028 /* Port data latch set register */ +# define PIC32MX_IOPORT_LATINV_OFFSET 0x002c /* Port data latch invert register */ +# define PIC32MX_IOPORT_ODC_OFFSET 0x0030 /* Open drain control register */ +# define PIC32MX_IOPORT_ODCCLR_OFFSET 0x0034 /* Open drain control clear register */ +# define PIC32MX_IOPORT_ODCSET_OFFSET 0x0038 /* Open drain control set register */ +# define PIC32MX_IOPORT_ODCINV_OFFSET 0x003c /* Open drain control invert register */ /* Offsets relative to PIC32MX_IOPORTCN_K1BASE */ -#define PIC32MX_IOPORT_CNCON_OFFSET 0x0000 /* Interrupt-on-change control register */ -#define PIC32MX_IOPORT_CNCONCLR_OFFSET 0x0004 /* Interrupt-on-change control clear register */ -#define PIC32MX_IOPORT_CNCONSET_OFFSET 0x0008 /* Interrupt-on-change control set register */ -#define PIC32MX_IOPORT_CNCONINV_OFFSET 0x000c /* Interrupt-on-change control invert register */ -#define PIC32MX_IOPORT_CNEN_OFFSET 0x0010 /* Input change notification interrupt enable */ -#define PIC32MX_IOPORT_CNENCLR_OFFSET 0x0014 /* Input change notification interrupt enable clear */ -#define PIC32MX_IOPORT_CNENSET_OFFSET 0x0018 /* Input change notification interrupt enable set */ -#define PIC32MX_IOPORT_CNENINV_OFFSET 0x001c /* Input change notification interrupt enable invert */ -#define PIC32MX_IOPORT_CNPUE_OFFSET 0x0020 /* Input change notification pull-up enable */ -#define PIC32MX_IOPORT_CNPUECLR_OFFSET 0x0024 /* Input change notification pull-up enable clear */ -#define PIC32MX_IOPORT_CNPUESET_OFFSET 0x0028 /* Input change notification pull-up enable set */ -#define PIC32MX_IOPORT_CNPUEINV_OFFSET 0x002c /* Input change notification pull-up enable invert */ +# define PIC32MX_IOPORT_CNCON_OFFSET 0x0000 /* Interrupt-on-change control register */ +# define PIC32MX_IOPORT_CNCONCLR_OFFSET 0x0004 /* Interrupt-on-change control clear register */ +# define PIC32MX_IOPORT_CNCONSET_OFFSET 0x0008 /* Interrupt-on-change control set register */ +# define PIC32MX_IOPORT_CNCONINV_OFFSET 0x000c /* Interrupt-on-change control invert register */ +# define PIC32MX_IOPORT_CNEN_OFFSET 0x0010 /* Input change notification interrupt enable */ +# define PIC32MX_IOPORT_CNENCLR_OFFSET 0x0014 /* Input change notification interrupt enable clear */ +# define PIC32MX_IOPORT_CNENSET_OFFSET 0x0018 /* Input change notification interrupt enable set */ +# define PIC32MX_IOPORT_CNENINV_OFFSET 0x001c /* Input change notification interrupt enable invert */ +# define PIC32MX_IOPORT_CNPUE_OFFSET 0x0020 /* Input change notification pull-up enable */ +# define PIC32MX_IOPORT_CNPUECLR_OFFSET 0x0024 /* Input change notification pull-up enable clear */ +# define PIC32MX_IOPORT_CNPUESET_OFFSET 0x0028 /* Input change notification pull-up enable set */ +# define PIC32MX_IOPORT_CNPUEINV_OFFSET 0x002c /* Input change notification pull-up enable invert */ +#endif /* Register Addresses ***********************************************************************/ +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORT_ANSEL(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ANSEL_OFFSET) +# define PIC32MX_IOPORT_ANSELCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ANSELCLR_OFFSET) +# define PIC32MX_IOPORT_ANSELSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ANSELSET_OFFSET) +# define PIC32MX_IOPORT_ANSELINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ANSELINV_OFFSET) +#endif + #define PIC32MX_IOPORT_TRIS(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRIS_OFFSET) #define PIC32MX_IOPORT_TRISCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISCLR_OFFSET) #define PIC32MX_IOPORT_TRISSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISSET_OFFSET) @@ -102,6 +152,32 @@ #define PIC32MX_IOPORT_ODCSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCSET_OFFSET) #define PIC32MX_IOPORT_ODCINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCINV_OFFSET) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORT_CNPU(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPU_OFFSET) +# define PIC32MX_IOPORT_CNPUCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPUCLR_OFFSET) +# define PIC32MX_IOPORT_CNPUSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPUSET_OFFSET) +# define PIC32MX_IOPORT_CNPUINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPUINV_OFFSET) +# define PIC32MX_IOPORT_CNPD(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPD_OFFSET) +# define PIC32MX_IOPORT_CNPDCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPDCLR_OFFSET) +# define PIC32MX_IOPORT_CNPDSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPDSET_OFFSET) +# define PIC32MX_IOPORT_CNPDINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNPDINV_OFFSET) +# define PIC32MX_IOPORT_CNCON(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNCON_OFFSET) +# define PIC32MX_IOPORT_CNCONCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNCONCLR_OFFSET) +# define PIC32MX_IOPORT_CNCONSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNCONSET_OFFSET) +# define PIC32MX_IOPORT_CNCONINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNCONINV_OFFSET) +# define PIC32MX_IOPORT_CNEN(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNEN_OFFSET) +# define PIC32MX_IOPORT_CNENCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNENCLR_OFFSET) +# define PIC32MX_IOPORT_CNENSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNENSET_OFFSET) +# define PIC32MX_IOPORT_CNENINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_CNENINV_OFFSET) +#endif + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORTA_ANSEL (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ANSEL_OFFSET) +# define PIC32MX_IOPORTA_ANSELCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ANSELCLR_OFFSET) +# define PIC32MX_IOPORTA_ANSELSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ANSELSET_OFFSET) +# define PIC32MX_IOPORTA_ANSELINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ANSELINV_OFFSET) +#endif + #define PIC32MX_IOPORTA_TRIS (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) #define PIC32MX_IOPORTA_TRISCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) #define PIC32MX_IOPORTA_TRISSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) @@ -119,6 +195,32 @@ #define PIC32MX_IOPORTA_ODCSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) #define PIC32MX_IOPORTA_ODCINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORTA_CNPU (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPU_OFFSET) +# define PIC32MX_IOPORTA_CNPUCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPUCLR_OFFSET) +# define PIC32MX_IOPORTA_CNPUSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPUSET_OFFSET) +# define PIC32MX_IOPORTA_CNPUINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPUINV_OFFSET) +# define PIC32MX_IOPORTA_CNPD (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPD_OFFSET) +# define PIC32MX_IOPORTA_CNPDCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPDCLR_OFFSET) +# define PIC32MX_IOPORTA_CNPDSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPDSET_OFFSET) +# define PIC32MX_IOPORTA_CNPDINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNPDINV_OFFSET) +# define PIC32MX_IOPORTA_CNCON (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET) +# define PIC32MX_IOPORTA_CNCONCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET) +# define PIC32MX_IOPORTA_CNCONSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET) +# define PIC32MX_IOPORTA_CNCONINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET) +# define PIC32MX_IOPORTA_CNEN (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET) +# define PIC32MX_IOPORTA_CNENCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET) +# define PIC32MX_IOPORTA_CNENSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET) +# define PIC32MX_IOPORTA_CNENINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET) +#endif + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORTB_ANSEL (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ANSEL_OFFSET) +# define PIC32MX_IOPORTB_ANSELCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ANSELCLR_OFFSET) +# define PIC32MX_IOPORTB_ANSELSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ANSELSET_OFFSET) +# define PIC32MX_IOPORTB_ANSELINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ANSELINV_OFFSET) +#endif + #define PIC32MX_IOPORTB_TRIS (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) #define PIC32MX_IOPORTB_TRISCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) #define PIC32MX_IOPORTB_TRISSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) @@ -136,6 +238,32 @@ #define PIC32MX_IOPORTB_ODCSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) #define PIC32MX_IOPORTB_ODCINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORTB_CNPU (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPU_OFFSET) +# define PIC32MX_IOPORTB_CNPUCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPUCLR_OFFSET) +# define PIC32MX_IOPORTB_CNPUSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPUSET_OFFSET) +# define PIC32MX_IOPORTB_CNPUINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPUINV_OFFSET) +# define PIC32MX_IOPORTB_CNPD (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPD_OFFSET) +# define PIC32MX_IOPORTB_CNPDCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPDCLR_OFFSET) +# define PIC32MX_IOPORTB_CNPDSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPDSET_OFFSET) +# define PIC32MX_IOPORTB_CNPDINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNPDINV_OFFSET) +# define PIC32MX_IOPORTB_CNCON (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET) +# define PIC32MX_IOPORTB_CNCONCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET) +# define PIC32MX_IOPORTB_CNCONSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET) +# define PIC32MX_IOPORTB_CNCONINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET) +# define PIC32MX_IOPORTB_CNEN (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET) +# define PIC32MX_IOPORTB_CNENCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET) +# define PIC32MX_IOPORTB_CNENSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET) +# define PIC32MX_IOPORTB_CNENINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET) +#endif + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORTC_ANSEL (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ANSEL_OFFSET) +# define PIC32MX_IOPORTC_ANSELCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ANSELCLR_OFFSET) +# define PIC32MX_IOPORTC_ANSELSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ANSELSET_OFFSET) +# define PIC32MX_IOPORTC_ANSELINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ANSELINV_OFFSET) +#endif + #define PIC32MX_IOPORTC_TRIS (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) #define PIC32MX_IOPORTC_TRISCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) #define PIC32MX_IOPORTC_TRISSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) @@ -153,6 +281,25 @@ #define PIC32MX_IOPORTC_ODCSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) #define PIC32MX_IOPORTC_ODCINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORTC_CNPU (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPU_OFFSET) +# define PIC32MX_IOPORTC_CNPUCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPUCLR_OFFSET) +# define PIC32MX_IOPORTC_CNPUSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPUSET_OFFSET) +# define PIC32MX_IOPORTC_CNPUINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPUINV_OFFSET) +# define PIC32MX_IOPORTC_CNPD (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPD_OFFSET) +# define PIC32MX_IOPORTC_CNPDCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPDCLR_OFFSET) +# define PIC32MX_IOPORTC_CNPDSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPDSET_OFFSET) +# define PIC32MX_IOPORTC_CNPDINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNPDINV_OFFSET) +# define PIC32MX_IOPORTC_CNCON (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET) +# define PIC32MX_IOPORTC_CNCONCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET) +# define PIC32MX_IOPORTC_CNCONSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET) +# define PIC32MX_IOPORTC_CNCONINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET) +# define PIC32MX_IOPORTC_CNEN (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET) +# define PIC32MX_IOPORTC_CNENCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET) +# define PIC32MX_IOPORTC_CNENSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET) +# define PIC32MX_IOPORTC_CNENINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET) +#endif + #define PIC32MX_IOPORTD_TRIS (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) #define PIC32MX_IOPORTD_TRISCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) #define PIC32MX_IOPORTD_TRISSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) @@ -221,21 +368,29 @@ #define PIC32MX_IOPORTG_ODCSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) #define PIC32MX_IOPORTG_ODCINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) -#define PIC32MX_IOPORT_CNCON (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET) -#define PIC32MX_IOPORT_CNCONCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET) -#define PIC32MX_IOPORT_CNCONSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET) -#define PIC32MX_IOPORT_CNCONINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET) -#define PIC32MX_IOPORT_CNEN (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET) -#define PIC32MX_IOPORT_CNENCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET) -#define PIC32MX_IOPORT_CNENSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET) -#define PIC32MX_IOPORT_CNENINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET) -#define PIC32MX_IOPORT_CNPUE (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUE_OFFSET) -#define PIC32MX_IOPORT_CNPUECLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUECLR_OFFSET) -#define PIC32MX_IOPORT_CNPUESET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUESET_OFFSET) -#define PIC32MX_IOPORT_CNPUEINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUEINV_OFFSET) +#if !defined(CHIP_PIC32MX1) && !defined(CHIP_PIC32MX2) +# define PIC32MX_IOPORT_CNCON (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET) +# define PIC32MX_IOPORT_CNCONCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET) +# define PIC32MX_IOPORT_CNCONSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET) +# define PIC32MX_IOPORT_CNCONINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET) +# define PIC32MX_IOPORT_CNEN (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET) +# define PIC32MX_IOPORT_CNENCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET) +# define PIC32MX_IOPORT_CNENSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET) +# define PIC32MX_IOPORT_CNENINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET) +# define PIC32MX_IOPORT_CNPUE (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUE_OFFSET) +# define PIC32MX_IOPORT_CNPUECLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUECLR_OFFSET) +# define PIC32MX_IOPORT_CNPUESET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUESET_OFFSET) +# define PIC32MX_IOPORT_CNPUEINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUEINV_OFFSET) +#endif /* Register Bit-Field Definitions ***********************************************************/ +/* Analog select register */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define IOPORT_ANSEL(n) (1 << (n)) /* Bits 0-15: Analog select */ +#endif + /* Tri-state register */ #define IOPORT_TRIS(n) (1 << (n)) /* Bits 0-15: 1: Input 0: Output */ @@ -252,26 +407,46 @@ #define IOPORT_ODC(n) (1 << (n)) /* Bits 0-15: 1: OD output enabled, 0: Disabled */ -/* Interrupt-on-change control register */ +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +/* Change Notification Pull-up register */ + +# define IOPORT_CNPU(n) (1 << (n)) /* Bits 0:15: 1=Pull-up enabled */ + +/* Change Notification Pull-down register */ + +# define IOPORT_CNPD(n) (1 << (n)) /* Bits 0:15: 1=Pull-down enabled */ + +/* Change Notification Control register */ + +# define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +# define IOPORT_CNCON_ON (1 << 15) /* Bit 15: Change notice module enable */ + +/* Change Notification Interrupt Enable register */ + +# define IOPORT_CNEN(n) (1 << (n)) /* Bits 0:15: 1=Interrupt enabled */ + +#else + /* Interrupt-on-change control register */ -#define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ -#define IOPORT_CNCON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */ -#define IOPORT_CNCON_ON (1 << 15) /* Bit 15: Change notice module enable */ +# define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +# define IOPORT_CNCON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */ +# define IOPORT_CNCON_ON (1 << 15) /* Bit 15: Change notice module enable */ -/* Input change notification interrupt enable */ + /* Input change notification interrupt enable */ -#define IOPORT_CNEN(n) (1 << (n)) /* Bits 0-18/21: Port pin input change notice enabled */ +# define IOPORT_CNEN(n) (1 << (n)) /* Bits 0-18/21: Port pin input change notice enabled */ -/* Input change notification pull-up enable */ + /* Input change notification pull-up enable */ -#define IOPORT_CNPUE(n) (1 << (n)) /* Bits 0-18/21: Port pin pull-up enabled */ +# define IOPORT_CNPUE(n) (1 << (n)) /* Bits 0-18/21: Port pin pull-up enabled */ -#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) -# define IOPORT_CN_ALL 0x0007ffff /* Bits 0-18 */ -# define IOPORT_NUMCN 19 -#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) -# define IOPORT_CN_ALL 0x003fffff /* Bits 0-21 */ -# define IOPORT_NUMCN 22 +# if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) +# define IOPORT_CN_ALL 0x0007ffff /* Bits 0-18 */ +# define IOPORT_NUMCN 19 +# elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define IOPORT_CN_ALL 0x003fffff /* Bits 0-21 */ +# define IOPORT_NUMCN 22 +# endif #endif /******************************************************************************************** diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c index a50f3204d..601eeb071 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-irq.c @@ -105,7 +105,7 @@ void up_irqinitialize(void) for (irq = 0; irq < NR_IRQS; irq++) { - (void)up_prioritize_irq(irq, (INT_ICP_MID_PRIORITY << 2)); + (void)up_prioritize_irq(irq, (INT_IPC_MID_PRIORITY << 2)); } /* Set the BEV bit in the STATUS register */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h index a3fe2791c..7126fa09a 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h @@ -48,41 +48,177 @@ /************************************************************************************ * Pre-Processor Definitions ************************************************************************************/ +/* Physical Memory Map **************************************************************/ + +/* This top-level memory map is valid for the PIC32MX1xx/2xx families. */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +# define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */ +# define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */ +# define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */ +# define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */ +# define PIC32MX_DEVCFG_PBASE 0x1fc00bf0 /* Device configuration registers */ + /* This top-level memory map is valid for the PIC32MX3xx/4xx as well as the * PIC32MX5xx/6xx/7xx families. */ -#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || \ +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || \ defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) -/* Physical Memory Map **************************************************************/ - # define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */ # define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */ # define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */ # define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */ # define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */ -/* Virtual Memory Map ***************************************************************/ - -# define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE) -# define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE) -# define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE) -# define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE) - -# define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE) -# define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE) -# define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE) -# define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE) -# define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE) - #else # error "Memory map unknown for this PIC32 chip" #endif +/* Virtual Memory Map ***************************************************************/ + +#define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE) +#define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE) +#define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE) +#define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE) + +#define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE) +#define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE) +#define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE) +#define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE) +#define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE) + /* Register Base Addresses **********************************************************/ -#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +/* Watchdog Register Base Address */ + +# define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000) + +/* RTCC Register Base Address */ + +# define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200) + +/* Timer 1-5 Register Base Addresses */ + +# define PIC32MX_TIMER_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00000600 + 0x200*(n-1)) +# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600) +# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800) +# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00) +# define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00) +# define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00) + +/* Input Capture 1-5 Register Base Addresses */ + +# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1)) +# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000) +# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200) +# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400) +# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600) +# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800) + +/* Output Compare 1-5 Register Base Addresses */ + +# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1)) +# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000) +# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200) +# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400) +# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600) +# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800) + +/* I2C 1-2 Register Base Addresses */ + +# define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000) +# define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005100) + +/* SPI 1-2 Register Base Addresses */ + +# define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800) +# define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00) + +/* UART 1-2 Register Base Addresses */ + +# define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000) +# define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200) + +/* Parallel Master Register Base Address */ + +# define PIC32MX_PMP_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000) + +/* ADC Register Base Addresses */ + +# define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000) + +/* Comparator Voltage Reference Register Base Addresses */ + +# define PIC32MX_CVR_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800) + +/* Comparator Register Base Addresses */ + +# define PIC32MX_CM_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000) + +/* CTMU Register Base Addresses */ + +# define PIC32MX_CTMU_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a200) + +/* Oscillator Control Register Base Addresses */ + +# define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000) + +/* Configuration Control Register Base Addresses */ + +# define PIC32MX_CFG_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200) + +/* FLASH Controller Register Base Addresses */ + +# define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400) + +/* Reset Control Register Base Address */ + +# define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600) + +/* Peripheral Pin Select Input/Ouput Register Base Address */ + +# define PIC32MX_INSEL_K1BASE (PIC32MX_SFR_K1BASE + 0x0000fa00) +# define PIC32MX_OUTSEL_K1BASE (PIC32MX_SFR_K1BASE + 0x0000fb00) + +/* Interrupt Register Base Address */ + +# define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000) + +/* Bus Matrix Register Base Address */ + +# define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000) + +/* DMA Register Base Address */ + +# define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000) +# define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n)) +# define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060) +# define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120) +# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0) +# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0) + +/* USBOTG Register Base Addresses */ + +# define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000) + +/* Port Register Base Addresses */ + +# define PIC32MX_IOPORTA 0 +# define PIC32MX_IOPORTB 1 +# define PIC32MX_IOPORTC 2 + +# define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x100*(n)) + +# define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000) +# define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100) +# define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086200) + +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) /* Watchdog Register Base Address */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-spi.h b/nuttx/arch/mips/src/pic32mx/pic32mx-spi.h index fd01091e5..308a8b7f6 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-spi.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-spi.h @@ -62,6 +62,10 @@ #define PIC32MX_SPI_BRGSET_OFFSET 0x0038 /* SPI baud rate set register */ #define PIC32MX_SPI_BRGINV_OFFSET 0x003c /* SPI baud rate invert register */ +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +#define PIC32MX_SPI_CON2_OFFSET 0x0020 /* SPI control register 2*/ +#endif + /* Register Addresses *******************************************************/ #ifdef PIC32MX_SPI1_K1BASE @@ -76,6 +80,9 @@ # define PIC32MX_SPI1_BRGCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET) # define PIC32MX_SPI1_BRGSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGSET_OFFSET) # define PIC32MX_SPI1_BRGINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGINV_OFFSET) +# if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_SPI1_CON2 (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CON2_OFFSET) +# endif #endif #ifdef PIC32MX_SPI2_K1BASE @@ -90,6 +97,9 @@ # define PIC32MX_SPI2_BRGCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET) # define PIC32MX_SPI2_BRGSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGSET_OFFSET) # define PIC32MX_SPI2_BRGINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGINV_OFFSET) +# if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define PIC32MX_SPI2_CON2 (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CON2_OFFSET) +# endif #endif #ifdef PIC32MX_SPI3_K1BASE @@ -124,11 +134,12 @@ /* SPI control register */ -#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) # define SPI_CON_RTXISEL_SHIFT (0) /* Bits 0-1: SPI Receive Buffer Full Interrupt Mode */ # define SPI_CON_RTXISEL_MASK (3 << SPI_CON_RTXISEL_SHIFT) -# define SPI_CON_RTXISEL_EMPTY (0 << SPI_CON_RTXISEL_SHIFT) /* Buffer empty*/ -# define SPI_CON_RTXISEL_NEMPTY (1 << SPI_CON_RTXISEL_SHIFT) /* Buffer not empty*/ +# define SPI_CON_RTXISEL_EMPTY (0 << SPI_CON_RTXISEL_SHIFT) /* Buffer empty */ +# define SPI_CON_RTXISEL_NEMPTY (1 << SPI_CON_RTXISEL_SHIFT) /* Buffer not empty */ # define SPI_CON_RTXISEL_HALF (2 << SPI_CON_RTXISEL_SHIFT) /* Buffer half full or more */ # define SPI_CON_RTXISEL_FULL (3 << SPI_CON_RTXISEL_SHIFT) /* Buffer full */ # define SPI_CON_STXISEL_SHIFT (2) /* Bits 2-3: SPI Transmit Buffer Empty Interrupt Mode */ @@ -138,7 +149,13 @@ # define SPI_CON_STXISEL_HALF (2 << SPI_CON_STXISEL_SHIFT) /* Buffer half empty or more */ # define SPI_CON_STXISEL_NFULL (3 << SPI_CON_STXISEL_SHIFT) /* Buffer not full */ #endif + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define SPI_CON_DISSDI (1 << 4) /* Bit 4: Disable SDI */ +#else /* Bit 4: Reserved */ +#endif + #define SPI_CON_MSTEN (1 << 5) /* Bits 5: Master mode enable */ #define SPI_CON_CKP (1 << 6) /* Bits 6: Clock polarity select */ #define SPI_CON_SSEN (1 << 7) /* Bits 7: Slave select enable (slave mode) */ @@ -148,15 +165,30 @@ #define SPI_CON_MODE_MASK (3 << SPI_CON_MODE_SHIFT) # define SPI_CON_MODE_8BIT (0 << SPI_CON_MODE_SHIFT) /* 8-bit data width */ # define SPI_CON_MODE_16BIT (1 << SPI_CON_MODE_SHIFT) /* 16-bit data width */ -# define SPI_CON_MODE_32BIT (2 << SPI_CON_MODE_SHIFT) /* 2-bit data width */ +# define SPI_CON_MODE_32BIT (2 << SPI_CON_MODE_SHIFT) /* 32-bit data width */ +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + /* With AUDEN=1: */ +# define SPI_CON_MODE_243232 (0 << SPI_CON_MODE_SHIFT) /* 24-bit data, 32-bit FIFO, 32-bit channel */ +# define SPI_CON_MODE_323232 (0 << SPI_CON_MODE_SHIFT) /* 32-bit data, 32-bit FIFO, 32-bit channel */ +# define SPI_CON_MODE_161632 (0 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 32-bit channel */ +# define SPI_CON_MODE_161616 (0 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 16-bit channel */ +#endif #define SPI_CON_DISSDO (1 << 12) /* Bits 12: Disable SDOx pin */ #define SPI_CON_SIDL (1 << 13) /* Bits 13: Stop in idle mode */ -#define SPI_CON_FRZ (1 << 14) /* Bits 14: Freeze in debug exception */ +#if !defined(CHIP_PIC32MX1) && !defined(CHIP_PIC32MX2) +# define SPI_CON_FRZ (1 << 14) /* Bits 14: Freeze in debug exception */ +#endif #define SPI_CON_ON (1 << 15) /* Bits 15: SPI peripheral on */ #define SPI_CON_ENHBUF (1 << 16) /* Bits 16: Enhanced buffer enable */ #define SPI_CON_SPIFE (1 << 17) /* Bits 17: Frame sync pulse edge select */ +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + /* Bits 18-22: Reserved */ +# define SPI_CON_MCLKSEL (1 << 18) /* Master clock enable */ +#else /* Bits 18-23: Reserved */ -#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +#endif +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) # define SPI_CON_FRMCNT_SHIFT (24) /* Bits 24-26: Frame Sync Pulse Counter bits */ # define SPI_CON_FRMCNT_MASK (7 << SPI_CON_FRMCNT_SHIFT) # define SPI_CON_FRMCNT_CHAR1 (0 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse each char */ @@ -172,22 +204,50 @@ #define SPI_CON_FRMSYNC (1 << 30) /* Bits 30: Frame sync pulse direction control on SSx pin */ #define SPI_CON_FRMEN (1 << 31) /* Bits 31: Framed SPI support */ +/* SPI control register 2 */ + +#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + +# define SPI2_CON2_AUDMOD_SHIFT (0) /* Bits 0-1: Audio Protocol Mode */ +# define SPI2_CON2_AUDMOD_MASK (3 << SPI2_CON2_AUDMOD_SHIFT) +# define SPI2_CON2_AUDMOD_I2S (0 << SPI2_CON2_AUDMOD_SHIFT) /* I2S mode */ +# define SPI2_CON2_AUDMOD_LJ (1 << SPI2_CON2_AUDMOD_SHIFT) /* Left Justified mode */ +# define SPI2_CON2_AUDMOD_RJ (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */ +# define SPI2_CON2_AUDMOD_PCM (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */ + /* Bit 2: Reserved */ +# define SPI2_CON2_AUDMONO (1 << 6) /* Bit 3: Transmit Audio Data Format */ + /* Bits 5-6: Reserved */ +# define SPI2_CON2_AUDEN (1 << 7) /* Bit 7: Enable Audio CODEC Support */ +# define SPI2_CON2_IGNTUR (1 << 8) /* Bit 8: Ignore Transmit Underrun bit */ +# define SPI2_CON2_IGNROV (1 << 9) /* Bit 9: Ignore Receive Overflow */ +# define SPI2_CON2_SPITUREN (1 << 10) /* Bit 10: Enable Interrupt Events via SPITUR */ +# define SPI2_CON2_SPIROVEN (1 << 11) /* Bit 11: Enable Interrupt Events via SPIROV */ +# define SPI2_CON2_FRMERREN (1 << 12) /* Bit 12: Enable Interrupt Events via FRMERR */ + /* Bits 13-14: Reserved */ +# define SPI2_CON2_SPISGNEXT (1 << 15) /* Bit 15 : Sign Extend Read Data from the RX FIFO */ + /* Bits 16-31: Reserved */ +#endif + /* SPI status register */ #if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) -# define SPI_STAT_SPIRBF (1 << 0) /* Bits 0: SPI receive buffer full status */ -# define SPI_STAT_SPITBE (1 << 3) /* Bits 3: SPI transmit buffer empty status */ -# define SPI_STAT_SPIROV (1 << 6) /* Bits 6: Receive overflow flag */ -# define SPI_STAT_SPIBUSY (1 << 11) /* Bits 11: SPI activity status */ -#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) -# define SPI_STAT_SPIRBF (1 << 0) /* Bits 0: SPI receive buffer full status */ -# define SPI_STAT_SPITBF (1 << 1) /* Bits 1: SPI transmit buffer full status */ -# define SPI_STAT_SPITBE (1 << 3) /* Bits 3: SPI transmit buffer empty status */ -# define SPI_STAT_SPIRBE (1 << 5) /* Bits 5: RX FIFO Empty */ -# define SPI_STAT_SPIROV (1 << 6) /* Bits 6: Receive overflow flag */ -# define SPI_STAT_SRMT (1 << 7) /* Bits 6: Shift Register Empty */ -# define SPI_STAT_SPITUR (1 << 6) /* Bits 8: Transmit under run */ -# define SPI_STAT_SPIBUSY (1 << 11) /* Bits 11: SPI activity status */ +# define SPI_STAT_SPIRBF (1 << 0) /* Bit 0: SPI receive buffer full status */ +# define SPI_STAT_SPITBE (1 << 3) /* Bit 3: SPI transmit buffer empty status */ +# define SPI_STAT_SPIROV (1 << 6) /* Bit 6: Receive overflow flag */ +# define SPI_STAT_SPIBUSY (1 << 11) /* Bit 11: SPI activity status */ +#elif defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) || defined(CHIP_PIC32MX5) || \ + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# define SPI_STAT_SPIRBF (1 << 0) /* Bit 0: SPI receive buffer full status */ +# define SPI_STAT_SPITBF (1 << 1) /* Bit 1: SPI transmit buffer full status */ +# define SPI_STAT_SPITBE (1 << 3) /* Bit 3: SPI transmit buffer empty status */ +# define SPI_STAT_SPIRBE (1 << 5) /* Bit 5: RX FIFO Empty */ +# define SPI_STAT_SPIROV (1 << 6) /* Bit 6: Receive overflow flag */ +# define SPI_STAT_SRMT (1 << 7) /* Bit 6: Shift Register Empty */ +# define SPI_STAT_SPITUR (1 << 8) /* Bit 8: Transmit under run */ +# define SPI_STAT_SPIBUSY (1 << 11) /* Bit 11: SPI activity status */ +# if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) +# define SPI_STAT_FRMERR (1 << 12) /* Bit 12: SPI Frame Error status */ +# endif # define SPI_STAT_TXBUFELM_SHIFT (16) /* Bits 16-20: Transmit Buffer Element Count bits */ # define SPI_STAT_TXBUFELM_MASK (31 << SPI_STAT_TXBUFELM_SHIFT) # define SPI_STAT_RXBUFELM_SHIFT (24) /* Bits 24-28: Receive Buffer Element Count bits */ |