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author | Gregory Nutt <gnutt@nuttx.org> | 2013-04-16 18:00:59 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-04-16 18:00:59 -0600 |
commit | 9255670a9d9fab07e941008aa9e9edbf5b460c0b (patch) | |
tree | f31c4ec2141db41f31b1de70af701d45b695e3a7 /nuttx/ChangeLog | |
parent | 82b1ed85155de4cac47551adb2363cc36b8806d0 (diff) | |
download | px4-nuttx-9255670a9d9fab07e941008aa9e9edbf5b460c0b.tar.gz px4-nuttx-9255670a9d9fab07e941008aa9e9edbf5b460c0b.tar.bz2 px4-nuttx-9255670a9d9fab07e941008aa9e9edbf5b460c0b.zip |
Fix major misthink in Cortex-M0 port: The Cortex-M0 has no BASEPRI register. We have to revert to using the nasty PRIMASK register
Diffstat (limited to 'nuttx/ChangeLog')
-rw-r--r-- | nuttx/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 4fc39c64b..8e180e574 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4556,3 +4556,8 @@ contributed by Alan Carvalho de Assis. NOTE: This is still very much a work inprogress as of this initial commit (2013-04-16). + * arm/arm/src/armv6-m and arch/arm/include/armv6-m: Ooops. Fix + a major screw-up: The Cortex-M0 has no BASEPRI register but + the current logic was using it to manage interrupts. Switch + to using the PRIMASK. This means that hardfaults will (again) + occur when SVC instructions are executed (2013-4-16). |