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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2013-01-22 01:25:40 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2013-01-22 01:25:40 +0000
commitfefa8ee3353d5ac7ef0e925ba8dcbbb89f2c96ae (patch)
treea1914fb5c45a61232078c98064198ac8818f07b4 /nuttx/arch/arm/include/lpc17xx
parentc86261aac88dcc280ca37e532ba96435c1c54699 (diff)
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Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/include/lpc17xx')
-rw-r--r--nuttx/arch/arm/include/lpc17xx/chip.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/nuttx/arch/arm/include/lpc17xx/chip.h b/nuttx/arch/arm/include/lpc17xx/chip.h
index d2c436d35..c22c6aa60 100644
--- a/nuttx/arch/arm/include/lpc17xx/chip.h
+++ b/nuttx/arch/arm/include/lpc17xx/chip.h
@@ -362,6 +362,20 @@
# error "Unsupported LPC17xx chip"
#endif
+/* NVIC priority levels *************************************************************/
+/* Each priority field holds a priority value, 0-31. The lower the value, the greater
+ * the priority of the corresponding interrupt. The processor implements only
+ * bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
+
+#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
+
/************************************************************************************
* Public Types
************************************************************************************/