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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-03-19 01:28:50 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-03-19 01:28:50 +0000 |
| commit | ed784e97c354a92faafe8760beb933688b3e9a30 (patch) | |
| tree | 5a0634af068bfc19b3a5bdd7ab4e6c09bf9537a5 /nuttx/arch/arm/src/armv7-m/nvic.h | |
| parent | da460d18fab3e9e8c864aae340ef4867d90483d6 (diff) | |
| download | px4-nuttx-ed784e97c354a92faafe8760beb933688b3e9a30.tar.gz px4-nuttx-ed784e97c354a92faafe8760beb933688b3e9a30.tar.bz2 px4-nuttx-ed784e97c354a92faafe8760beb933688b3e9a30.zip | |
Fields of vector offset table appear to vary with MCU
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5758 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/armv7-m/nvic.h')
| -rw-r--r-- | nuttx/arch/arm/src/armv7-m/nvic.h | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/nuttx/arch/arm/src/armv7-m/nvic.h b/nuttx/arch/arm/src/armv7-m/nvic.h index 6bd842a76..46837ab99 100644 --- a/nuttx/arch/arm/src/armv7-m/nvic.h +++ b/nuttx/arch/arm/src/armv7-m/nvic.h @@ -483,6 +483,26 @@ #define NVIC_SYSH_PRIORITY_PR15_SHIFT 24 #define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT) +/* Vector Table Offset Register (VECTAB) */ + +#define NVIC_VECTAB_TBLOFF_MASK (0xffffffc0) +#define NVIC_VECTAB_TBLBASE (0) +#define NVIC_VECTAB_ALIGN_MASK (0x0000003f) + +/* Application Interrupt and Reset Control Register (AIRCR) */ + +#define NVIC_AIRCR_VECTRESET (1 << 0) /* Bit 0: VECTRESET */ +#define NVIC_AIRCR_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */ +#define NVIC_AIRCR_SYSRESETREQ (1 << 2) /* Bit 2: System reset */ + /* Bits 2-7: Reserved */ +#define NVIC_AIRCR_PRIGROUP_SHIFT (8) /* Bits 8-14: PRIGROUP */ +#define NVIC_AIRCR_PRIGROUP_MASK (7 << NVIC_AIRCR_PRIGROUP_SHIFT) +#define NVIC_AIRCR_ENDIANNESS (1 << 15) /* Bit 15: 1=Big endian */ +#define NVIC_AIRCR_VECTKEY_SHIFT (16) /* Bits 16-31: VECTKEY */ +#define NVIC_AIRCR_VECTKEY_MASK (0xffff << NVIC_AIRCR_VECTKEY_SHIFT) +#define NVIC_AIRCR_VECTKEYSTAT_SHIFT (16) /* Bits 16-31: VECTKEYSTAT */ +#define NVIC_AIRCR_VECTKEYSTAT_MASK (0xffff << NVIC_AIRCR_VECTKEYSTAT_SHIFT) + /* System handler control and state register (SYSHCON) */ #define NVIC_SYSHCON_MEMFAULTACT (1 << 0) /* Bit 0: MemManage is active */ @@ -500,20 +520,6 @@ #define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */ #define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */ -/* Application Interrupt and Reset Control Register (AIRCR) */ - -#define NVIC_AIRCR_VECTRESET (1 << 0) /* Bit 0: VECTRESET */ -#define NVIC_AIRCR_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */ -#define NVIC_AIRCR_SYSRESETREQ (1 << 2) /* Bit 2: System reset */ - /* Bits 2-7: Reserved */ -#define NVIC_AIRCR_PRIGROUP_SHIFT (8) /* Bits 8-14: PRIGROUP */ -#define NVIC_AIRCR_PRIGROUP_MASK (7 << NVIC_AIRCR_PRIGROUP_SHIFT) -#define NVIC_AIRCR_ENDIANNESS (1 << 15) /* Bit 15: 1=Big endian */ -#define NVIC_AIRCR_VECTKEY_SHIFT (16) /* Bits 16-31: VECTKEY */ -#define NVIC_AIRCR_VECTKEY_MASK (0xffff << NVIC_AIRCR_VECTKEY_SHIFT) -#define NVIC_AIRCR_VECTKEYSTAT_SHIFT (16) /* Bits 16-31: VECTKEYSTAT */ -#define NVIC_AIRCR_VECTKEYSTAT_MASK (0xffff << NVIC_AIRCR_VECTKEYSTAT_SHIFT) - /* Debug Exception and Monitor Control Register (DEMCR) */ #define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */ |