diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-05-14 00:22:31 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-05-14 00:22:31 +0000 |
| commit | 3b8a6dddff146b60cd09d1f3dd3b95cd8042ccd5 (patch) | |
| tree | 66a5ff991fbd784101e2e833d83981c50aca837a /nuttx/arch/arm/src/calypso/calypso_heap.c | |
| parent | c39c92fb6b3803270215d5552acf6ac6d23a31f8 (diff) | |
| download | px4-nuttx-3b8a6dddff146b60cd09d1f3dd3b95cd8042ccd5.tar.gz px4-nuttx-3b8a6dddff146b60cd09d1f3dd3b95cd8042ccd5.tar.bz2 px4-nuttx-3b8a6dddff146b60cd09d1f3dd3b95cd8042ccd5.zip | |
Calypso update from Denis Carkiki. Adds UWire driver and support for external memory in NuttX heap
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4733 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/calypso/calypso_heap.c')
| -rw-r--r-- | nuttx/arch/arm/src/calypso/calypso_heap.c | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/nuttx/arch/arm/src/calypso/calypso_heap.c b/nuttx/arch/arm/src/calypso/calypso_heap.c index a6b5e55c9..b51596f90 100644 --- a/nuttx/arch/arm/src/calypso/calypso_heap.c +++ b/nuttx/arch/arm/src/calypso/calypso_heap.c @@ -38,6 +38,7 @@ ****************************************************************************/ #include <nuttx/config.h> +#include <nuttx/mm.h> #include <sys/types.h> #include <debug.h> @@ -60,25 +61,30 @@ * ****************************************************************************/ +#if CONFIG_MM_REGIONS > 1 void up_addregion(void) { #ifdef CONFIG_ARCH_BOARD_COMPALE99 - /* Disable watchdog in first non-common function */ - wdog_enable(0); + /* Disable watchdog in first non-common function */ + wdog_enable(0); #endif - // XXX: change to initialization of extern memory with save defaults - /* Configure memory interface */ - calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1); - calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1); - calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0); + // XXX: change to initialization of extern memory with save defaults + /* Configure memory interface */ + calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1); + calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1); + calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0); - /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */ - calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2); + /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */ + calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2); + + /* Configure the RHEA bridge with some sane default values */ + calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0); + + mm_addregion((FAR void*)CONFIG_HEAP2_START, CONFIG_HEAP2_END-CONFIG_HEAP2_START); - /* Configure the RHEA bridge with some sane default values */ - calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0); } +#endif |