spi update

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1739 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 91 insertions, 24 deletions

diff --git a/nuttx/arch/arm/src/imx/imx_cspi.h b/nuttx/arch/arm/src/imx/imx_cspi.h
index ffe02c659..a42ca296a 100755
--- a/nuttx/arch/arm/src/imx/imx_cspi.h
+++ b/nuttx/arch/arm/src/imx/imx_cspi.h
@@ -50,41 +50,108 @@
 
 /* CSPI Register Offsets ************************************************************/
 
-#define CSPI_SPIRXD_OFFSET         0x0000
-#define CSPI_SPITXD_OFFSET         0x0004
-#define CSPI_SPICONT1_OFFSET       0x0008
-#define CSPI_INTCS_OFFSET          0x000c
-#define CSPI_SPITEST_OFFSET        0x0010
-#define CSPI_SPISPCR_OFFSET        0x0014
-#define CSPI_SPIDMA_OFFSET         0x0018
-#define CSPI_SPIRESET_OFFSET       0x001c
+#define CSPI_RXD_OFFSET          0x0000 /* Receive Data Register */
+#define CSPI_TXD_OFFSET          0x0004 /* Transmit Data Register */
+#define CSPI_CTRL_OFFSET         0x0008 /* Control Register */
+#define CSPI_INTCS_OFFSET        0x000c /* Interrupt Control/Status Register */
+#define CSPI_TEST_OFFSET         0x0010 /* Test Register */
+#define CSPI_SPCR_OFFSET         0x0014 /* Sample Period Control Register */
+#define CSPI_DMA_OFFSET          0x0018 /* DMA Control Register */
+#define CSPI_RESET_OFFSET        0x001c /* Soft Reset Register */
 
 /* CSPI Register Addresses **********************************************************/
 
 /* CSPI1 */
 
-#define IMX_CSPI1_SPIRXD           (IMX_CSPI1_VBASE + CSPI_SPIRXD_OFFSET)
-#define IMX_CSPI1_SPITXD           (IMX_CSPI1_VBASE + CSPI_SPITXD_OFFSET)
-#define IMX_CSPI1_SPICONT1         (IMX_CSPI1_VBASE + CSPI_SPICONT1_OFFSET)
-#define IMX_CSPI1_INTCS            (IMX_CSPI1_VBASE + CSPI_INTCS_OFFSET)
-#define IMX_CSPI1_SPITEST          (IMX_CSPI1_VBASE + CSPI_SPITEST_OFFSET)
-#define IMX_CSPI1_SPISPCR          (IMX_CSPI1_VBASE + CSPI_SPISPCR_OFFSET)
-#define IMX_CSPI1_SPIDMA           (IMX_CSPI1_VBASE + CSPI_SPIDMA_OFFSET)
-#define IMX_CSPI1_SPIRESET         (IMX_CSPI1_VBASE + CSPI_SPIRESET_OFFSET)
+#define IMX_CSPI1_RXD            (IMX_CSPI1_VBASE + CSPI_RXD_OFFSET)
+#define IMX_CSPI1_TXD            (IMX_CSPI1_VBASE + CSPI_TXD_OFFSET)
+#define IMX_CSPI1_CTRL           (IMX_CSPI1_VBASE + CSPI_CTRL_OFFSET)
+#define IMX_CSPI1_INTCS          (IMX_CSPI1_VBASE + CSPI_INTCS_OFFSET)
+#define IMX_CSPI1_SPITEST        (IMX_CSPI1_VBASE + CSPI_TEST_OFFSET)
+#define IMX_CSPI1_SPISPCR        (IMX_CSPI1_VBASE + CSPI_SPCR_OFFSET)
+#define IMX_CSPI1_SPIDMA         (IMX_CSPI1_VBASE + CSPI_DMA_OFFSET)
+#define IMX_CSPI1_SPIRESET       (IMX_CSPI1_VBASE + CSPI_RESET_OFFSET)
 
 /* CSPI1 */
 
-#define IMX_CSPI2_SPIRXD           (IMX_CSPI2_VBASE + CSPI_SPIRXD_OFFSET)
-#define IMX_CSPI2_SPITXD           (IMX_CSPI2_VBASE + CSPI_SPITXD_OFFSET)
-#define IMX_CSPI2_SPICONT1         (IMX_CSPI2_VBASE + CSPI_SPICONT1_OFFSET)
-#define IMX_CSPI2_INTCS            (IMX_CSPI2_VBASE + CSPI_INTCS_OFFSET)
-#define IMX_CSPI2_SPITEST          (IMX_CSPI2_VBASE + CSPI_SPITEST_OFFSET)
-#define IMX_CSPI2_SPISPCR          (IMX_CSPI2_VBASE + CSPI_SPISPCR_OFFSET)
-#define IMX_CSPI2_SPIDMA           (IMX_CSPI2_VBASE + CSPI_SPIDMA_OFFSET)
-#define IMX_CSPI2_SPIRESET         (IMX_CSPI2_VBASE + CSPI_SPIRESET_OFFSET)
+#define IMX_CSPI2_RXD            (IMX_CSPI2_VBASE + CSPI_RXD_OFFSET)
+#define IMX_CSPI2_TXD            (IMX_CSPI2_VBASE + CSPI_TXD_OFFSET)
+#define IMX_CSPI2_CTRL           (IMX_CSPI2_VBASE + CSPI_CTRL_OFFSET)
+#define IMX_CSPI2_INTCS          (IMX_CSPI2_VBASE + CSPI_INTCS_OFFSET)
+#define IMX_CSPI2_SPITEST        (IMX_CSPI2_VBASE + CSPI_TEST_OFFSET)
+#define IMX_CSPI2_SPISPCR        (IMX_CSPI2_VBASE + CSPI_SPCR_OFFSET)
+#define IMX_CSPI2_SPIDMA         (IMX_CSPI2_VBASE + CSPI_DMA_OFFSET)
+#define IMX_CSPI2_SPIRESET       (IMX_CSPI2_VBASE + CSPI_RESET_OFFSET)
 
 /* CSPI Register Bit Definitions ****************************************************/
 
+/* CSPI Control Register */
+
+#define CSPI_CTRL_DATARATE_SHIFT 13
+#define CSPI_CTRL_DATARATE_MASK    (7 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV4             (0 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV8             (1 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV16            (2 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV32            (3 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV64            (4 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV128           (5 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV256           (6 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DIV512           (7 << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_CTRL_DRCTL_SHIFT      11
+#define CSPI_CTRL_DRCTL_MASK       (3 << CSPI_CTRL_DRCTL_SHIFT)
+#define CSPI_CTRL_DRCTL_IGNRDY     (0 << CSPI_CTRL_DRCTL_SHIFT)
+#define CSPI_CTRL_DRCTL_FALLING    (1 << CSPI_CTRL_DRCTL_SHIFT)
+#define CSPI_CTRL_DRCTL_ACTVLOW    (2 << CSPI_CTRL_DRCTL_SHIFT)
+#define CSPI_CTRL_MODE             (1 << 10)
+#define CSPI_CTRL_SPIEN            (1 << 9)
+#define CSPI_CTRL_XCH              (1 << 8)
+#define CSPI_CTRL_SSPOL            (1 << 7)
+#define CSPI_CTRL_SSCTL            (1 << 6)
+#define CSPI_CTRL_PHA              (1 << 5)
+#define CSPI_CTRL_POL              (1 << 4)
+#define CSPI_CTRL_BITCOUNT_SHIFT   0
+#define CSPI_CTRL_BITCOUNT_MASK    (15 << CSPI_CTRL_BITCOUNT_SHIFT)
+
+/* CSPI Interrrupt Control/Status Register */
+
+#define CSPI_INTCS_TE              (1 << 0)  /* Bit  0: TXFIFO Empty Status */
+#define CSPI_INTCS_TH              (1 << 1)  /* Bit  1: TXFIFO Half Status */
+#define CSPI_INTCS_TF              (1 << 2)  /* Bit  2: TXFIFO Full Status */
+#define CSPI_INTCS_RR              (1 << 3)  /* Bit  3: RXFIFO Data Ready Status */
+#define CSPI_INTCS_RH              (1 << 4)  /* Bit  4: RXFIFO Half Status */
+#define CSPI_INTCS_RF              (1 << 5)  /* Bit  5: RXFIFO Full Status */
+#define CSPI_INTCS_RO              (1 << 6)  /* Bit  6: RXFIFO Overflow */
+#define CSPI_INTCS_BO              (1 << 7)  /* Bit  7: Bit Count Overflow */
+#define CSPI_INTCS_TEEN            (1 << 8)  /* Bit  8: TXFIFO Empty Interrupt Enable */
+#define CSPI_INTCS_THEN            (1 << 9)  /* Bit  9: TXFIFO Half Interrupt Enable */
+#define CSPI_INTCS_TFEN            (1 << 10) /* Bit 10: TXFIFO Full Interrupt Enable */
+#define CSPI_INTCS_RREN            (1 << 11) /* Bit 11: RXFIFO Data Ready Interrupt Enable */
+#define CSPI_INTCS_RHEN            (1 << 12) /* Bit 12: RXFIFO Half Interrupt Enable */
+#define CSPI_INTCS_RFEN            (1 << 13) /* Bit 13: RXFIFO Full Interrupt Enable */
+#define CSPI_INTCS_ROEN            (1 << 14) /* BIT 14: RXFIFO Overflow Interrupt Enable */
+#define CSPI_INTCS_BOEN            (1 << 15) /* Bit 15: Bit Count Overflow Interrupt Enable */
+
+/* CSPI Sample Period Control Register */
+
+#define CSPI_SPCR_WAIT_SHIFT       0
+#define CSPI_SPCR_WAIT_MASK        (0x7ff << CSPI_CTRL_DATARATE_SHIFT)
+#define CSPI_SPCR_CSRC             (1 << 15) /* Bit 15: 1:32768 or 32 kHz clock source */
+
+/* CSPI DMA Control Register */
+
+#define CSPI_DMA_RHDMA             (1 <<  4) /* Bit  4: RXFIFO Half Status */
+#define CSPI_DMA_RFDMA             (1 <<  5) /* Bit  5: RXFIFO Full Status */
+#define CSPI_DMA_TEDMA             (1 <<  6) /* Bit  6: TXFIFO Empty Status */
+#define CSPI_DMA_THDMA             (1 <<  7) /* Bit  7: TXFIFO Half Status */
+#define CSPI_DMA_RHDEN             (1 << 12) /* Bit 12: Enable RXFIFO Half DMA Request */
+#define CSPI_DMA_RFDEN             (1 << 13) /* Bit 13: Enables RXFIFO Full DMA Request */
+#define CSPI_DMA_TEDEN             (1 << 14) /* Bit 14: Enable TXFIFO Empty DMA Request */
+#define CSPI_DMA_THDEN             (1 << 15) /* Bit 15: Enable TXFIFO Half DMA Request */
+
+/* Soft Reset Register */
+
+#define CSPI_RESET_START           (1 << 0)  /* Bit  0: Execute soft reset */
+
 /************************************************************************************
  * Inline Functions
  ************************************************************************************/