Fix Freedom KL25Z SysTick rate

4 files changed, 15 insertions, 380 deletions

diff --git a/nuttx/arch/arm/src/kl/Kconfig b/nuttx/arch/arm/src/kl/Kconfig
index 7f1910963..3da807cf0 100644
--- a/nuttx/arch/arm/src/kl/Kconfig
+++ b/nuttx/arch/arm/src/kl/Kconfig
@@ -296,6 +296,9 @@ choice
 config KL_SYSTICK_CORECLK
 	bool "Cortex-M0 core clock"
 
+config KL_SYSTICK_CORECLK_DIV16
+	bool "Cortex-M0 core clock divided by 16"
+
 endchoice
 
 comment "Kinetis GPIO Interrupt Configuration"
diff --git a/nuttx/arch/arm/src/kl/chip/kl_clk.h b/nuttx/arch/arm/src/kl/chip/kl_clk.h
deleted file mode 100644
index 2125d4dea..000000000
--- a/nuttx/arch/arm/src/kl/chip/kl_clk.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_clk.h
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_CLK_H
-#define __ARCH_ARM_SRC_KL_CHIP_KL_CLK_H
-
-/********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-
-/********************************************************************************************
- * Pre-processor Definitions
- ********************************************************************************************/
-/* Well-known clock frequencies *************************************************************/
-
-#define KL_INTHI_FREQUENCY          22118400
-#define KL_INTLO_FREQUENCY          10000
-
-/* Register offsets *************************************************************************/
-
-#define KL_CLK_PWRCON_OFFSET        0x0000 /* System power down control register */
-#define KL_CLK_AHBCLK_OFFSET        0x0004 /* AHB devices clock enable control register */
-#define KL_CLK_APBCLK_OFFSET        0x0008 /* APB devices clock enable control register */
-#define KL_CLK_CLKSTATUS_OFFSET     0x000c /* Clock status monitor register */
-#define KL_CLK_CLKSEL0_OFFSET       0x0010 /* Clock source select control register 0 */
-#define KL_CLK_CLKSEL1_OFFSET       0x0014 /* Clock source select control register 1 */
-#define KL_CLK_CLKSEL2_OFFSET       0x001c /* Clock source select control register 2 */
-#define KL_CLK_CLKDIV_OFFSET        0x0018 /* Clock divider number register */
-#define KL_CLK_PLLCON_OFFSET        0x0020 /* PLL control register */
-#define KL_CLK_FRQDIV_OFFSET        0x0024 /* Frequency divider control register */
-
-/* Register addresses ***********************************************************************/
-
-#define KL_CLK_PWRCON               (KL_CLK_BASE+KL_CLK_PWRCON_OFFSET)
-#define KL_CLK_AHBCLK               (KL_CLK_BASE+KL_CLK_AHBCLK_OFFSET)
-#define KL_CLK_APBCLK               (KL_CLK_BASE+KL_CLK_APBCLK_OFFSET)
-#define KL_CLK_CLKSTATUS            (KL_CLK_BASE+KL_CLK_CLKSTATUS_OFFSET)
-#define KL_CLK_CLKSEL0              (KL_CLK_BASE+KL_CLK_CLKSEL0_OFFSET)
-#define KL_CLK_CLKSEL1              (KL_CLK_BASE+KL_CLK_CLKSEL1_OFFSET)
-#define KL_CLK_CLKSEL2              (KL_CLK_BASE+KL_CLK_CLKSEL2_OFFSET)
-#define KL_CLK_CLKDIV               (KL_CLK_BASE+KL_CLK_CLKDIV_OFFSET)
-#define KL_CLK_PLLCON               (KL_CLK_BASE+KL_CLK_PLLCON_OFFSET)
-#define KL_CLK_FRQDIV               (KL_CLK_BASE+KL_CLK_FRQDIV_OFFSET)
-
-/* Register bit-field definitions ***********************************************************/
-
-/* System power down control register */
-
-#define CLK_PWRCON_XTL12M_EN        (1 << 0)  /* Bit 0:  External 4~24 mhz high speed crystal enable */
-#define CLK_PWRCON_XTL32K_EN        (1 << 1)  /* Bit 1:  External 32.768 khz low speed crystal enable */
-#define CLK_PWRCON_OSC22M_EN        (1 << 2)  /* Bit 2:  Internal 22.1184 MHz high speed oscillator enable */
-#define CLK_PWRCON_OSC10K_EN        (1 << 3)  /* Bit 3:  Internal 10KHz low speed oscillator enable */
-#define CLK_PWRCON_PD_WU_DLY        (1 << 4)  /* Bit 4:  Enable the wake-up delay counter */
-#define CLK_PWRCON_PD_WU_INT_EN     (1 << 5)  /* Bit 5:  Power down mode wake-up interrupt status */
-#define CLK_PWRCON_PD_WU_STS        (1 << 6)  /* Bit 6:  Power down mode wake-up interupt status */
-#define CLK_PWRCON_PWR_DOWN_EN      (1 << 7)  /* Bit 7:  System power down enable bit */
-#define CLK_PWRCON_PD_WAIT_CPU      (1 << 8)  /* Bit 8:  Power down entry condition */
-
-/* AHB devices clock enable control register */
-
-#define CLK_AHBCLK_PDMA_EN          (1 << 1)  /* Bit 1:  PDMA acontroller clock enable control */
-#define CLK_AHBCLK_ISP_EN           (1 << 2)  /* Bit 2:  FLASH ISPO controller clock enable control */
-#define CLK_AHBCLK_EBI_EN           (1 << 3)  /* Bit 3:  EBI controller clock enable control */
-
-/* APB devices clock enable control register */
-
-#define CLK_APBCLK_WDT_EN           (1 << 0)  /* Bit 0:  Watchdog time clock enable */
-#define CLK_APBCLK_RTC_EN           (1 << 1)  /* Bit 1:  Real time clock clock enable */
-#define CLK_APBCLK_TMR0_EN          (1 << 2)  /* Bit 2:  Timer0 clock enable */
-#define CLK_APBCLK_TMR1_EN          (1 << 3)  /* Bit 3:  Timer1 clock enable */
-#define CLK_APBCLK_TMR2_EN          (1 << 4)  /* Bit 4:  Timer2 clock enable */
-#define CLK_APBCLK_TMR3_EN          (1 << 5)  /* Bit 5:  Timer3 clock enable */
-#define CLK_APBCLK_FDIV_EN          (1 << 6)  /* Bit 6:  Frequency divider output clock enable */
-#define CLK_APBCLK_I2C0_EN          (1 << 8)  /* Bit 8:  I2C0 clock enable */
-#define CLK_APBCLK_I2C1_EN          (1 << 9)  /* Bit 9:  I2C1 clock enable */
-#define CLK_APBCLK_SPI0_EN          (1 << 12) /* Bit 12: SPI0 clock enable */
-#define CLK_APBCLK_SPI1_EN          (1 << 13) /* Bit 13: SPI1 clock enable */
-#define CLK_APBCLK_SPI2_EN          (1 << 14) /* Bit 14: SPI2 clock enable */
-#define CLK_APBCLK_SPI3_EN          (1 << 15) /* Bit 15: SPI3 clock enable */
-#define CLK_APBCLK_UART0_EN         (1 << 16) /* Bit 16: UART0 clock enable */
-#define CLK_APBCLK_UART1_EN         (1 << 17) /* Bit 17: UART1 clock enable */
-#define CLK_APBCLK_UART2_EN         (1 << 18) /* Bit 18: UART2 clock enable */
-#define CLK_APBCLK_PWM01_EN         (1 << 20) /* Bit 20: PWM_01 clock enable */
-#define CLK_APBCLK_PWM23_EN         (1 << 21) /* Bit 21: PWM_23 clock enable */
-#define CLK_APBCLK_PWM45_EN         (1 << 22) /* Bit 22: PWM_45 clock enable */
-#define CLK_APBCLK_PWM67_EN         (1 << 23) /* Bit 23: PWM_67 clock enable */
-#define CLK_APBCLK_USBD_EN          (1 << 27) /* Bit 27: USB 2.0 FS device controller clock enable */
-#define CLK_APBCLK_ADC_EN           (1 << 28) /* Bit 28: Analog-digital-converter clock enable */
-#define CLK_APBCLK_I2S_EN           (1 << 29) /* Bit 29: I2S clock enable */
-#define CLK_APBCLK_ACMP_EN          (1 << 30) /* Bit 30: Analog comparator clock enable */
-#define CLK_APBCLK_PS2_EN           (1 << 31) /* Bit 31: PS/2 clock enable */
-
-/* Clock status monitor register */
-
-#define CLK_CLKSTATUS_XTL12M_STB    (1 << 0)  /* Bit 0:  External 4~24 mhz high speed crystal
-                                               *         clock source stable flag */
-#define CLK_CLKSTATUS_STL32K_STB    (1 << 1)  /* Bit 1:  External 32.768 kHz low speed crystal
-                                               *         clock source stable flag */
-#define CLK_CLKSTATUS_PLL_STB       (1 << 2)  /* Bit 2:  Internal PLL clock source stable flag */
-#define CLK_CLKSTATUS_OSC10K_STB    (1 << 3)  /* Bit 3:  Internal 10kHz low speed clock source
-                                               *         stable flag */
-#define CLK_CLKSTATUS_OSC22M_STB    (1 << 4)  /* Bit 4:  Internal 22.1184MHz high speed
-                                               *         osciallator clock source stable flag */
-#define CLK_CLKSTATUS_CLK_SW_FAIL   (1 << 7)  /* Bit 7:  Clock switching fail flag */
-
-/* Clock source select control register 0 */
-
-#define CLK_CLKSEL0_HCLK_S_SHIFT    (0)       /* Bits 0-2: HCLK clock source select */
-#define CLK_CLKSEL0_HCLK_S_MASK     (7 << CLK_CLKSEL0_HCLK_S_SHIFT)
-#  define CLK_CLKSEL0_HCLK_S_XTALHI (0 << CLK_CLKSEL0_HCLK_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL0_HCLK_S_XTALLO (1 << CLK_CLKSEL0_HCLK_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL0_HCLK_S_PLL    (2 << CLK_CLKSEL0_HCLK_S_SHIFT) /* PLL clock */
-#  define CLK_CLKSEL0_HCLK_S_INTLO  (3 << CLK_CLKSEL0_HCLK_S_SHIFT) /* Internal low speed clock */
-#  define CLK_CLKSEL0_HCLK_S_INTHI  (7 << CLK_CLKSEL0_HCLK_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL0_STCLK_S_SHIFT   (3)       /* Bits 3-5: Cortex M0 Systick clock source select */
-#define CLK_CLKSEL0_STCLK_S_MASK    (7 << CLK_CLKSEL0_STCLK_S_SHIFT)
-#  define CLK_CLKSEL0_STCLK_S_XTALHI   (0 << CLK_CLKSEL0_STCLK_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL0_STCLK_S_XTALLO   (1 << CLK_CLKSEL0_STCLK_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL0_STCLK_S_XTALDIV2 (2 << CLK_CLKSEL0_STCLK_S_SHIFT) /* High speed XTAL clock/2 */
-#  define CLK_CLKSEL0_STCLK_S_HCLKDIV2 (3 << CLK_CLKSEL0_STCLK_S_SHIFT) /* HCLK/2 */
-#  define CLK_CLKSEL0_STCLK_S_INTDIV2  (7 << CLK_CLKSEL0_STCLK_S_SHIFT) /* Internal high speed clock/2 */
-
-/* Clock source select control register 1 */
-
-#define CLK_CLKSEL1_WDT_S_SHIFT     (0)       /* Bits 0-1: Watchdog timer clock source select */
-#define CLK_CLKSEL1_WDT_S_MASK      (3 << CLK_CLKSEL1_WDT_S_SHIFT)
-#  define CLK_CLKSEL1_ADC_S_HCLKDIV (2 << CLK_CLKSEL1_WDT_S_SHIFT) /* HCLK / 2048 */
-#  define CLK_CLKSEL1_ADC_S_INTLO   (3 << CLK_CLKSEL1_WDT_S_SHIFT) /* Internal low speed clock */
-#define CLK_CLKSEL1_ADC_S_SHIFT     (2)       /* Bits 2-3: ADC clock source select */
-#define CLK_CLKSEL1_ADC_S_MASK      (3 << CLK_CLKSEL1_ADC_S_SHIFT)
-#  define CLK_CLKSEL1_ADC_S_XTALHI  (0 << CLK_CLKSEL1_ADC_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_ADC_S_PLL     (1 << CLK_CLKSEL1_ADC_S_SHIFT) /* PLL */
-#  define CLK_CLKSEL1_ADC_S_INTHI   (3 << CLK_CLKSEL1_ADC_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL1_TMR0_S_SHIFT    (8)       /* Bits 8-10: Timer0 clock source select */
-#define CLK_CLKSEL1_TMR0_S_MASK     (7 << CLK_CLKSEL1_TMR0_S_SHIFT)
-#  define CLK_CLKSEL1_TMR0_S_XTALHI (0 << CLK_CLKSEL1_TMR0_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_TMR0_S_XTALLO (1 << CLK_CLKSEL1_TMR0_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_TMR0_S_HCLK   (2 << CLK_CLKSEL1_TMR0_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_TMR0_S_INTHI  (7 << CLK_CLKSEL1_TMR0_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL1_TMR1_S_SHIFT    (12)      /* Bits 12-14: Timer1 clock source select */
-#define CLK_CLKSEL1_TMR1_S_MASK     (7 << CLK_CLKSEL1_TMR1_S_SHIFT)
-#  define CLK_CLKSEL1_TMR1_S_XTALHI (0 << CLK_CLKSEL1_TMR1_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_TMR1_S_XTALLO (1 << CLK_CLKSEL1_TMR1_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_TMR1_S_HCLK   (2 << CLK_CLKSEL1_TMR1_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_TMR1_S_INTHI  (7 << CLK_CLKSEL1_TMR1_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL1_TMR2_S_SHIFT    (16)      /* Bits 16-18: Timer2 clock source select */
-#define CLK_CLKSEL1_TMR2_S_MASK     (7 << CLK_CLKSEL1_TMR2_S_SHIFT)
-#  define CLK_CLKSEL1_TMR2_S_XTALHI (0 << CLK_CLKSEL1_TMR2_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_TMR2_S_XTALLO (1 << CLK_CLKSEL1_TMR2_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_TMR2_S_HCLK   (2 << CLK_CLKSEL1_TMR2_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_TMR2_S_INTHI  (7 << CLK_CLKSEL1_TMR2_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL1_TMR3_S_SHIFT    (20)      /* Bits 20-22: Timer3 clock source select */
-#define CLK_CLKSEL1_TMR3_S_MASK     (7 << CLK_CLKSEL1_TMR3_S_SHIFT)
-#  define CLK_CLKSEL1_TMR3_S_XTALHI (0 << CLK_CLKSEL1_TMR3_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_TMR3_S_XTALLO (1 << CLK_CLKSEL1_TMR3_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_TMR3_S_HCLK   (2 << CLK_CLKSEL1_TMR3_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_TMR3_S_INTHI  (7 << CLK_CLKSEL1_TMR3_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL1_UART_S_SHIFT    (24)      /* Bits 24-25: UART clock source select */
-#define CLK_CLKSEL1_UART_S_MASK     (3 << CLK_CLKSEL1_UART_S_SHIFT)
-#  define CLK_CLKSEL1_UART_S_XTALHI (0 << CLK_CLKSEL1_UART_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_UART_S_PLL    (1 << CLK_CLKSEL1_UART_S_SHIFT) /* PLL */
-#  define CLK_CLKSEL1_UART_S_INTHI  (3 << CLK_CLKSEL1_UART_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL1_PWM01_S_SHIFT   (28)      /* Bits 28-29: PWM0 and PWM1 clock source select */
-#define CLK_CLKSEL1_PWM01_S_MASK    (3 << CLK_CLKSEL1_PWM01_S_SHIFT)
-#  define CLK_CLKSEL1_PWM01_S_XTALHI  (0 << CLK_CLKSEL1_PWM01_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_PWM01_S_XTALLO  (1 << CLK_CLKSEL1_PWM01_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_PWM01_S_HCLK    (2 << CLK_CLKSEL1_PWM01_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_PWM01_S_INTHI   (3 << CLK_CLKSEL1_PWM01_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL1_PWM23_S_SHIFT   (30)      /* Bits 30-31: PWM2 and PWM3 clock source select */
-#define CLK_CLKSEL1_PWM23_S_MASK    (3 << CLK_CLKSEL1_PWM23_S_SHIFT)
-#  define CLK_CLKSEL1_PWM23_S_XTALHI  (0 << CLK_CLKSEL1_PWM23_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_PWM23_S_XTALLO  (1 << CLK_CLKSEL1_PWM23_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_PWM23_S_HCLK    (2 << CLK_CLKSEL1_PWM23_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_PWM23_S_INTHI   (3 << CLK_CLKSEL1_PWM23_S_SHIFT) /* Internal high speed clock */
-
-/* Clock source select control register 2 */
-
-#define CLK_CLKSEL2_I2S_S_SHIFT     (0)       /* Bits 0-1: I2S clock source select */
-#define CLK_CLKSEL2_I2S_S_MASK      (3 << CLK_CLKSEL2_I2S_S_SHIFT)
-#  define CLK_CLKSEL1_I2S_S_XTALHI  (0 << CLK_CLKSEL2_I2S_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_I2S_S_XTALLO  (1 << CLK_CLKSEL2_I2S_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_I2S_S_HCLK    (2 << CLK_CLKSEL2_I2S_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_I2S_S_INTHI   (3 << CLK_CLKSEL2_I2S_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL2_FRQDIV_S_SHIFT  (2)       /* Bits 2-3: Frequency divider clock source select */
-#define CLK_CLKSEL2_FRQDIV_S_MASK   (3 << CLK_CLKSEL2_FRQDIV_S_SHIFT)
-#  define CLK_CLKSEL1_FRQDIV_S_XTALHI (0 << CLK_CLKSEL2_FRQDIV_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_FRQDIV_S_XTALLO (1 << CLK_CLKSEL2_FRQDIV_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_FRQDIV_S_HCLK   (2 << CLK_CLKSEL2_FRQDIV_S_SHIFT) /* HCLK */
-#define CLK_CLKSEL2_PWM45_S_SHIFT   (4)       /* Bits 4-5: PWM4 and PWM5 clock source select */
-#define CLK_CLKSEL2_PWM45_S_MASK    (3 << CLK_CLKSEL2_PWM45_S_SHIFT)
-#  define CLK_CLKSEL1_PWM45_S_XTALHI  (0 << CLK_CLKSEL2_PWM45_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_PWM45_S_XTALLO  (1 << CLK_CLKSEL2_PWM45_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_PWM45_S_HCLK    (2 << CLK_CLKSEL2_PWM45_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_PWM45_S_INTHI   (3 << CLK_CLKSEL2_PWM45_S_SHIFT) /* Internal high speed clock */
-#define CLK_CLKSEL2_PWM67_S_SHIFT   (6)       /* Bits 6-7: PWM6 and PWM7 clock source select */
-#define CLK_CLKSEL2_PWM67_S_MASK    (3 << CLK_CLKSEL2_PWM67_S_SHIFT)
-#  define CLK_CLKSEL1_PWM67_S_XTALHI  (0 << CLK_CLKSEL2_PWM67_S_SHIFT) /* High speed XTAL clock */
-#  define CLK_CLKSEL1_PWM67_S_XTALLO  (1 << CLK_CLKSEL2_PWM67_S_SHIFT) /* Low speed XTAL clock */
-#  define CLK_CLKSEL1_PWM67_S_HCLK    (2 << CLK_CLKSEL2_PWM67_S_SHIFT) /* HCLK */
-#  define CLK_CLKSEL1_PWM67_S_INTHI   (3 << CLK_CLKSEL2_PWM67_S_SHIFT) /* Internal high speed clock */
-
-/* Clock divider number register */
-
-#define CLK_CLKDIV_HCLK_N_SHIFT     (0) /* Bits 0-3: HCLCK divide from clock source */
-#define CLK_CLKDIV_HCLK_N_MASK      (15 << CLK_CLKDIV_HCLK_N_SHIFT)
-#  define CLK_CLKDIV_HCLK_N(n)      (((n)-1) << CLK_CLKDIV_HCLK_N_SHIFT) /* n=1..16 */
-#define CLK_CLKDIV_USB_N_SHIFT      (4) /* Bits 4-7: USBD divide from clock source */
-#define CLK_CLKDIV_USB_N_MASK       (15 << CLK_CLKDIV_USB_N_SHIFT)
-#  define CLK_CLKDIV_USB_N(n)       (((n)-1) << CLK_CLKDIV_USB_N_SHIFT) /* n=1..16 */
-#define CLK_CLKDIV_UART_N_SHIFT     (8) /* Bits 8-11 UART divide from clock source */
-#define CLK_CLKDIV_UART_N_MASK      (15 << CLK_CLKDIV_UART_N_SHIFT)
-#  define CLK_CLKDIV_UART_N(n)      (((n)-1) << CLK_CLKDIV_UART_N_SHIFT) /* n=1..16 */
-#define CLK_CLKDIV_ADC_N_SHIFT      (16) /* Bits 16-23: ADC divide from clock source */
-#define CLK_CLKDIV_ADC_N_MASK       (255 << CLK_CLKDIV_ADC_N_SHIFT)
-#  define CLK_CLKDIV_ADC_N(n)       (((n)-1) << CLK_CLKDIV_UART_N_SHIFT) /* n=1..256 */
-
-/* PLL control register */
-
-#define CLK_PLLCON_FB_DV_SHIFT      (0)       /* Bits 0-8: PLL feedback divider control pins */
-#define CLK_PLLCON_FB_DV_MASK       (0x1ff << CLK_PLLCON_FB_DV_SHIFT)
-#  define CLK_PLLCON_FB_DV(n)       ((n) << CLK_PLLCON_FB_DV_SHIFT)
-#define CLK_PLLCON_IN_DV_SHIFT      (9)       /* bits 9-13: PLL input divider control pins */
-#define CLK_PLLCON_IN_DV_MASK       (0x1f << CLK_PLLCON_IN_DV_SHIFT)
-#  define CLK_PLLCON_IN_DV(n)       ((n) << CLK_PLLCON_IN_DV_SHIFT)
-#define CLK_PLLCON_OUT_DV_SHIFT     (14)      /* Bits 14-15: PLL output divider control pins */
-#define CLK_PLLCON_OUT_DV_MASK      (3 << CLK_PLLCON_OUT_DV_SHIFT)
-#  define CLK_PLLCON_OUT_DV(n)      ((n) << CLK_PLLCON_OUT_DV_SHIFT)
-#define CLK_PLLCON_PD               (1 << 16) /* Bit 16: Power down mode  */
-#define CLK_PLLCON_BP               (1 << 17) /* Bit 17: PLL bypass control */
-#define CLK_PLLCON_OE               (1 << 18) /* Bit 18: PLL OE (FOUT enable) pin control */
-#define CLK_PLLCON_PLL_SRC          (1 << 19) /* Bit 19: PLL source clock select */
-
-/* Frequency divider control register */
-
-#define CLK_FRQDIV_FSEL_SHIFT       (0)       /* Bits 0-3: Divider output frequency selection bits */
-#define CLK_FRQDIV_FSEL_MASK        (15 << CLK_FRQDIV_FSEL_SHIFT)
-#  define CLK_FRQDIV_FSEL(n)        ((n) << CLK_FRQDIV_FSEL_SHIFT) /* fout = fin / (2^(n+1)) */
-#define CLK_FRQDIV_DIVIDER_EN       (1 << 4)  /* Bit 4: Frequency divider enable bit */
-
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Data
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Functions
- ********************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_CLK_H */
diff --git a/nuttx/arch/arm/src/kl/kl_start.c b/nuttx/arch/arm/src/kl/kl_start.c
index 9a55a1750..decd934a0 100644
--- a/nuttx/arch/arm/src/kl/kl_start.c
+++ b/nuttx/arch/arm/src/kl/kl_start.c
@@ -72,13 +72,13 @@
  */
 
 #define IDLE_STACK ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
-#define HEAP_BASE  ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
+#define HEAP_BASE  ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
 
 /****************************************************************************
  * Public Data
  ****************************************************************************/
 
-const uint32_t g_idle_topstack = HEAP_BASE;
+const uint32_t g_idle_topstack = IDLE_STACK;
 
 /****************************************************************************
  * Private Functions
diff --git a/nuttx/arch/arm/src/kl/kl_timerisr.c b/nuttx/arch/arm/src/kl/kl_timerisr.c
index 7ee8cba5f..0df667016 100644
--- a/nuttx/arch/arm/src/kl/kl_timerisr.c
+++ b/nuttx/arch/arm/src/kl/kl_timerisr.c
@@ -51,26 +51,20 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/kl_clk.h"
 #include "chip/kl_gcr.h"
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
-/* Get the frequency of the selected clock source */
+/* "The CLKSOURCE bit in SysTick Control and Status register selects either
+ * the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock
+ * (when CLKSOURCE = 0). ..."
+ */
 
 #if defined(CONFIG_KL_SYSTICK_CORECLK)
-#  define SYSTICK_CLOCK BOARD_HCLK_FREQUENCY       /* Core clock */
-#elif defined(CONFIG_KL_SYSTICK_XTALHI)
-#  define SYSTICK_CLOCK BOARD_XTALHI_FREQUENCY     /* High speed XTAL clock */
-#elif defined(CONFIG_KL_SYSTICK_XTALLO)
-#  define SYSTICK_CLOCK BOARD_XTALLO_FREQUENCY     /* Low speed XTAL clock */
-#elif defined(CONFIG_KL_SYSTICK_XTALHId2)
-#  define SYSTICK_CLOCK (BOARD_XTALHI_FREQUENCY/2) /* High speed XTAL clock/2 */
-#elif defined(CONFIG_KL_SYSTICK_HCLKd2)
-#  define SYSTICK_CLOCK (BOARD_HCLK_FREQUENCY/2)   /* HCLK/2 */
-#elif defined(CONFIG_KL_SYSTICK_INTHId2)
-#  define SYSTICK_CLOCK (KL_INTHI_FREQUENCY/2)     /* Internal high speed clock/2 */
+#  define SYSTICK_CLOCK BOARD_CORECLK_FREQ        /* Core clock */
+#elif defined(CONFIG_KL_SYSTICK_CORECLK_DIV16)
+#  define (SYSTICK_CLOCK BOARD_CORECLK_FREQ / 16) /* Core clock divided by 16 */
 #endif
 
 /* The desired timer interrupt frequency is provided by the definition
@@ -108,50 +102,6 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: kl_unlock
- *
- * Description:
- *   Unlock registers
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifdef CONFIG_KL_SYSTICK_CORECLK
-static inline void kl_unlock(void)
-{
-  putreg32(0x59, KL_GCR_REGWRPROT);
-  putreg32(0x16, KL_GCR_REGWRPROT);
-  putreg32(0x88, KL_GCR_REGWRPROT);
-}
-#endif
-
-/****************************************************************************
- * Name: kl_clock
- *
- * Description:
- *   Lok registers
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifdef CONFIG_KL_SYSTICK_CORECLK
-static inline void kl_lock(void)
-{
-  putreg32(0, KL_GCR_REGWRPROT);
-}
-#endif
-
-/****************************************************************************
  * Global Functions
  ****************************************************************************/
 
@@ -185,37 +135,6 @@ void up_timerinit(void)
 {
   uint32_t regval;
 
-  /* Configure the SysTick clock source. This is only necessary if we are not
-   * using the Cortex-M0 core clock as the frequency source.
-   */
-
-#ifndef CONFIG_KL_SYSTICK_CORECLK
-  /* This field is write protected and must be unlocked */
-
-  kl_unlock();
-
-  /* Read the CLKSEL0 register and set the STCLK_S field appropriately */
-
-  regval  = getreg32(KL_CLK_CLKSEL0);
-  regval &= ~CLK_CLKSEL0_STCLK_S_MASK;
-#if defined(CONFIG_KL_SYSTICK_XTALHI)
-  regval |= CLK_CLKSEL0_STCLK_S_XTALHI;   /* High speed XTAL clock */
-#elif defined(CONFIG_KL_SYSTICK_XTALLO)
-  regval |= CLK_CLKSEL0_STCLK_S_XTALLO;   /* Low speed XTAL clock */
-#elif defined(CONFIG_KL_SYSTICK_XTALHId2)
-  regval |= CLK_CLKSEL0_STCLK_S_XTALDIV2; /* High speed XTAL clock/2 */
-#elif defined(CONFIG_KL_SYSTICK_HCLKd2)
-  regval |= CLK_CLKSEL0_STCLK_S_HCLKDIV2; /* HCLK/2 */
-#elif defined(CONFIG_KL_SYSTICK_INTHId2)
-  regval |= CLK_CLKSEL0_STCLK_S_INTDIV2;  /* Internal high speed clock/2 */
-#endif
-  putreg32(regval, KL_CLK_CLKSEL0);
-
-  /* Re-lock the register */
-
-  kl_lock();
-#endif
-
   /* Set the SysTick interrupt to the default priority */
 
   regval = getreg32(ARMV6M_SYSCON_SHPR3);
@@ -231,8 +150,9 @@ void up_timerinit(void)
 
   (void)irq_attach(KL_IRQ_SYSTICK, (xcpt_t)up_timerisr);
 
-  /* Enable SysTick interrupts.  We need to select the core clock here if
-   * we are not using one of the alternative clock sources above.
+  /* Enable SysTick interrupts.  "The CLKSOURCE bit in SysTick Control and
+   * Status register selects either the core clock (when CLKSOURCE = 1) or
+   * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..."
    */
 
 #ifdef CONFIG_KL_SYSTICK_CORECLK