diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-09 18:15:02 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-09 18:15:02 +0000 |
commit | 4a6b5ec135f4a952fbe23640c01b9b0f3f90bf2b (patch) | |
tree | 1b4d1241dd040eb89cb7451ba59448a0ca600797 /nuttx/arch/arm/src/lm/lm_ssi.c | |
parent | 25f65f6524fe5c6508de38300796e1183051ab3b (diff) | |
download | px4-nuttx-4a6b5ec135f4a952fbe23640c01b9b0f3f90bf2b.tar.gz px4-nuttx-4a6b5ec135f4a952fbe23640c01b9b0f3f90bf2b.tar.bz2 px4-nuttx-4a6b5ec135f4a952fbe23640c01b9b0f3f90bf2b.zip |
Change naming of all Stellaris pre-processor symbols from LM3S_ to LM_ to make room in the namespace for LM4F
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5498 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lm/lm_ssi.c')
-rw-r--r-- | nuttx/arch/arm/src/lm/lm_ssi.c | 112 |
1 files changed, 56 insertions, 56 deletions
diff --git a/nuttx/arch/arm/src/lm/lm_ssi.c b/nuttx/arch/arm/src/lm/lm_ssi.c index c6f8dcdb1..dae08e092 100644 --- a/nuttx/arch/arm/src/lm/lm_ssi.c +++ b/nuttx/arch/arm/src/lm/lm_ssi.c @@ -83,12 +83,12 @@ * such case, the following must be expanded). */ -#if LM3S_NSSI == 0 +#if LM_NSSI == 0 # undef CONFIG_SSI0_DISABLE # define CONFIG_SSI0_DISABLE 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 +#elif LM_NSSI == 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 #endif @@ -102,15 +102,15 @@ # define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */ # else # define NSSI_ENABLED 1 /* One SSI interface: SSI0 */ -# define SSI_BASE LM3S_SSI0_BASE -# define SSI_IRQ LM3S_IRQ_SSI0 +# define SSI_BASE LM_SSI0_BASE +# define SSI_IRQ LM_IRQ_SSI0 # endif #else # ifndef CONFIG_SSI1_DISABLE # define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */ # define NSSI_ENABLED 1 /* One SSI interface: SSI1 */ -# define SSI_BASE LM3S_SSI1_BASE -# define SSI_IRQ LM3S_IRQ_SSI1 +# define SSI_BASE LM_SSI1_BASE +# define SSI_IRQ LM_IRQ_SSI1 # else # define NSSI_ENABLED 0 /* No SSI interfaces */ # endif @@ -124,19 +124,19 @@ /* The number of (16-bit) words that will fit in the Tx FIFO */ -#define LM3S_TXFIFO_WORDS 8 +#define LM_TXFIFO_WORDS 8 /* Configuration settings */ #ifndef CONFIG_SSI_TXLIMIT -# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2) +# define CONFIG_SSI_TXLIMIT (LM_TXFIFO_WORDS/2) #endif -#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS +#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM_TXFIFO_WORDS # error "Invalid range for CONFIG_SSI_TXLIMIT" #endif -#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2) +#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM_TXFIFO_WORDS/2) # error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size" #endif @@ -304,10 +304,10 @@ static struct lm_ssidev_s g_ssidev[] = { .ops = &g_spiops, #if NSSI_ENABLED > 1 - .base = LM3S_SSI0_BASE, + .base = LM_SSI0_BASE, #endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI0, + .irq = LM_IRQ_SSI0, #endif }, #endif @@ -315,10 +315,10 @@ static struct lm_ssidev_s g_ssidev[] = { .ops = &g_spiops, #if NSSI_ENABLED > 1 - .base = LM3S_SSI1_BASE, + .base = LM_SSI1_BASE, #endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI1, + .irq = LM_IRQ_SSI1, #endif }, #endif @@ -404,9 +404,9 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv) uint32_t retval; uint32_t regval; - retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + retval = ssi_getreg(priv, LM_SSI_CR1_OFFSET); regval = (retval & ~SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval); ssivdbg("CR1: %08x\n", regval); return retval; } @@ -430,10 +430,10 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv) static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable) { - uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + uint32_t regval = ssi_getreg(priv, LM_SSI_CR1_OFFSET); regval &= ~SSI_CR1_SSE; regval |= (enable & SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval); ssivdbg("CR1: %08x\n", regval); } @@ -484,14 +484,14 @@ static void ssi_semtake(sem_t *sem) static void ssi_txnull(struct lm_ssidev_s *priv) { ssivdbg("TX: ->0xffff\n"); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff); + ssi_putreg(priv, LM_SSI_DR_OFFSET, 0xffff); } static void ssi_txuint16(struct lm_ssidev_s *priv) { uint16_t *ptr = (uint16_t*)priv->txbuffer; ssivdbg("TX: %p->%04x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++)); priv->txbuffer = (void*)ptr; } @@ -499,7 +499,7 @@ static void ssi_txuint8(struct lm_ssidev_s *priv) { uint8_t *ptr = (uint8_t*)priv->txbuffer; ssivdbg("TX: %p->%02x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++)); priv->txbuffer = (void*)ptr; } @@ -523,17 +523,17 @@ static void ssi_txuint8(struct lm_ssidev_s *priv) static void ssi_rxnull(struct lm_ssidev_s *priv) { #if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE) - uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + uint32_t regval = ssi_getreg(priv, LM_SSI_DR_OFFSET); ssivdbg("RX: discard %04x\n", regval); #else - (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + (void)ssi_getreg(priv, LM_SSI_DR_OFFSET); #endif } static void ssi_rxuint16(struct lm_ssidev_s *priv) { uint16_t *ptr = (uint16_t*)priv->rxbuffer; - *ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + *ptr = (uint16_t)ssi_getreg(priv, LM_SSI_DR_OFFSET); ssivdbg("RX: %p<-%04x\n", ptr, *ptr); priv->rxbuffer = (void*)(++ptr); } @@ -541,7 +541,7 @@ static void ssi_rxuint16(struct lm_ssidev_s *priv) static void ssi_rxuint8(struct lm_ssidev_s *priv) { uint8_t *ptr = (uint8_t*)priv->rxbuffer; - *ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + *ptr = (uint8_t)ssi_getreg(priv, LM_SSI_DR_OFFSET); ssivdbg("RX: %p<-%02x\n", ptr, *ptr); priv->rxbuffer = (void*)(++ptr); } @@ -562,7 +562,7 @@ static void ssi_rxuint8(struct lm_ssidev_s *priv) static inline bool ssi_txfifofull(struct lm_ssidev_s *priv) { - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; + return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; } /**************************************************************************** @@ -581,7 +581,7 @@ static inline bool ssi_txfifofull(struct lm_ssidev_s *priv) static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv) { - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; + return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; } /**************************************************************************** @@ -657,7 +657,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv) /* Check again... Now have all of the Tx words been sent? */ #ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + regval = ssi_getreg(priv, LM_SSI_IM_OFFSET); if (priv->ntxwords > 0) { /* No.. Enable the Tx FIFO interrupt. This interrupt occurs @@ -678,7 +678,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv) regval &= ~(SSI_IM_TX|SSI_RIS_ROR); } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); + ssi_putreg(priv, LM_SSI_IM_OFFSET, regval); #endif /* CONFIG_SSI_POLLWAIT */ } return ntxd; @@ -728,7 +728,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv) */ #ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + regval = ssi_getreg(priv, LM_SSI_IM_OFFSET); if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords) { /* There are no more outgoing words to send, but there are @@ -751,7 +751,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv) regval &= ~(SSI_IM_RX|SSI_IM_RT); } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); + ssi_putreg(priv, LM_SSI_IM_OFFSET, regval); #endif /* CONFIG_SSI_POLLWAIT */ } @@ -829,7 +829,7 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer, flags = irqsave(); ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET)); ntxd = ssi_performtx(priv); @@ -842,8 +842,8 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer, ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET), + ssi_getreg(priv, LM_SSI_IM_OFFSET)); /* Wait for the transfer to complete. Since there is no handshake * with SPI, the following should complete even if there are problems @@ -908,11 +908,11 @@ static inline struct lm_ssidev_s *ssi_mapirq(int irq) switch (irq) { #ifndef CONFIG_SSI0_DISABLE - case LM3S_IRQ_SSI0: + case LM_IRQ_SSI0: return &g_ssidev[SSI0_NDX]; #endif #ifndef CONFIG_SSI1_DISABLE - case LM3S_IRQ_SSI1: + case LM_IRQ_SSI1: return &g_ssidev[SSI1_NDX]; #endif default: @@ -952,8 +952,8 @@ static int ssi_interrupt(int irq, void *context) /* Clear pending interrupts */ - regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET); - ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval); + regval = ssi_getreg(priv, LM_SSI_RIS_OFFSET); + ssi_putreg(priv, LM_SSI_ICR_OFFSET, regval); /* Check for Rx FIFO overruns */ @@ -966,7 +966,7 @@ static int ssi_interrupt(int irq, void *context) ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET)); /* Handle outgoing Tx FIFO transfers */ @@ -978,8 +978,8 @@ static int ssi_interrupt(int irq, void *context) ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET), + ssi_getreg(priv, LM_SSI_IM_OFFSET)); /* Check if the transfer is complete */ @@ -987,7 +987,7 @@ static int ssi_interrupt(int irq, void *context) { /* Yes.. Disable all SSI interrupt sources */ - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + ssi_putreg(priv, LM_SSI_IM_OFFSET, 0); /* Wake up the waiting thread */ @@ -1135,14 +1135,14 @@ static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, uint32_t freq /* Set CPDVSR */ DEBUGASSERT(cpsdvsr < 255); - ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr); + ssi_putreg(priv, LM_SSI_CPSR_OFFSET, cpsdvsr); /* Set SCR */ - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET); regval &= ~SSI_CR0_SCR_MASK; regval |= (scr << SSI_CR0_SCR_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval); ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr); /* Calcluate the actual frequency */ @@ -1235,10 +1235,10 @@ static void ssi_setmodeinternal(struct lm_ssidev_s *priv, enum spi_mode_e mode) /* Then set the selected mode: Freescale SPI format, mode0-3 */ - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET); regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO); regval |= modebits; - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval); ssivdbg("CR0: %08x\n", regval); /* Save the mode so that subsequent re-configuratins will be faster */ @@ -1287,10 +1287,10 @@ static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits) DEBUGASSERT(priv); if (nbits != priv->nbits && nbits >=4 && nbits <= 16) { - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET); regval &= ~SSI_CR0_DSS_MASK; regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval); ssivdbg("CR0: %08x\n", regval); priv->nbits = nbits; @@ -1464,9 +1464,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Enable the SSI0 peripheral */ - regval = getreg32(LM3S_SYSCON_RCGC1); + regval = getreg32(LM_SYSCON_RCGC1); regval |= SYSCON_RCGC1_SSI0; - putreg32(regval, LM3S_SYSCON_RCGC1); + putreg32(regval, LM_SYSCON_RCGC1); ssivdbg("RCGC1: %08x\n", regval); /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the @@ -1488,9 +1488,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Enable the SSI1 peripheral */ - regval = getreg32(LM3S_SYSCON_RCGC1); + regval = getreg32(LM_SYSCON_RCGC1); regval |= SYSCON_RCGC1_SSI1; - putreg32(regval, LM3S_SYSCON_RCGC1); + putreg32(regval, LM_SYSCON_RCGC1); ssivdbg("RCGC1: %08x\n", regval); /* Configure SSI1 GPIOs */ @@ -1518,11 +1518,11 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Set all CR1 fields to reset state. This will be master mode. */ - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0); + ssi_putreg(priv, LM_SSI_CR1_OFFSET, 0); /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */ - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, 0); /* Set the initial mode to mode 0. The application may override * this initial setting using the setmode() method. @@ -1547,7 +1547,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) * while there is an SSI transfer in progress. */ - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + ssi_putreg(priv, LM_SSI_IM_OFFSET, 0); /* Attach the interrupt */ |