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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-22 14:37:17 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-22 14:37:17 +0000 |
| commit | f538392b3b9cb194d8b33b14b9a8e17636cf7f81 (patch) | |
| tree | 3dd51c0f8e6e1c0a5804b84e7018e7044c484a06 /nuttx/arch/arm/src/lm | |
| parent | fefa8ee3353d5ac7ef0e925ba8dcbbb89f2c96ae (diff) | |
| download | px4-nuttx-f538392b3b9cb194d8b33b14b9a8e17636cf7f81.tar.gz px4-nuttx-f538392b3b9cb194d8b33b14b9a8e17636cf7f81.tar.bz2 px4-nuttx-f538392b3b9cb194d8b33b14b9a8e17636cf7f81.zip | |
More logic to use BASEPRI to control interrupts -- still doesn't work
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5547 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lm')
| -rw-r--r-- | nuttx/arch/arm/src/lm/lm_irq.c | 3 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lm/lm_vectors.S | 9 |
2 files changed, 10 insertions, 2 deletions
diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index dc9997afa..7d8d2135a 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -379,8 +379,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S index d3798fbb7..1d3553b4e 100644 --- a/nuttx/arch/arm/src/lm/lm_vectors.S +++ b/nuttx/arch/arm/src/lm/lm_vectors.S @@ -203,7 +203,11 @@ lm_irqcommon: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_NUTTX_KERNEL stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ #else @@ -289,7 +293,12 @@ lm_irqcommon: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP |