More lpc17xx port files

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2735 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 22 insertions, 0 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h
index 90e3c422f..52c6b45f2 100755
--- a/nuttx/arch/arm/src/lpc17xx/chip.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip.h
@@ -51,6 +51,8 @@
 #if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -61,6 +63,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1767)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
 #  define LPC17_NUSBHOST        0  /* No USB host controller */
 #  define LPC17_NUSBOTG         0  /* No USB OTG controller */
@@ -71,6 +75,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1766)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -81,6 +87,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1765)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -91,6 +99,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1764)
 #  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
 #  define LPC17_NUSBHOST        0  /* No USB host controller */
 #  define LPC17_NUSBOTG         0  /* No USB OTG controller */
@@ -101,6 +111,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1759)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -111,6 +123,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1758)
 #  define LPC17_FLASH_SIZE      (512*1024) /* 512Kb */
 #  define LPC17_SRAM_SIZE       (64*1024)  /*  64Kb */
+#  define LPC17_HAVE_BANK0      1  /* Have AHB SRAM bank 0 */
+#  define LPC17_HAVE_BANK1      1  /* Have AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 1  /* One Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -121,6 +135,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1756)
 #  define LPC17_FLASH_SIZE      (256*1024) /* 256Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -131,6 +147,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1754)
 #  define LPC17_FLASH_SIZE      (128*1024) /* 128Kb */
 #  define LPC17_SRAM_SIZE       (32*1024)  /*  32Kb */
+#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        1  /* One USB host controller */
 #  define LPC17_NUSBOTG         1  /* One USB OTG controller */
@@ -141,6 +159,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1752)
 #  define LPC17_FLASH_SIZE      (64*1024) /* 65Kb */
 #  define LPC17_SRAM_SIZE       (16*1024) /* 16Kb */
+#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        0  /* No USB host controller */
 #  define LPC17_NUSBOTG         0  /* No USB OTG controller */
@@ -151,6 +171,8 @@
 #elif defined(CONFIG_ARCH_CHIP_LPC1751)
 #  define LPC17_FLASH_SIZE      (32*1024) /* 32Kb */
 #  define LPC17_SRAM_SIZE       (8*1024)  /*  8Kb */
+#  undef  LPC17_HAVE_BANK0      1  /* No AHB SRAM bank 0 */
+#  undef  LPC17_HAVE_BANK1      1  /* No AHB SRAM bank 1 */
 #  define LPC17_NETHCONTROLLERS 0  /* No Ethernet controller */
 #  define LPC17_NUSBHOST        0  /* No USB host controller */
 #  define LPC17_NUSBOTG         0  /* No USB OTG controller */