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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-17 23:53:44 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-17 23:53:44 +0000 |
| commit | 31a5581021afca8240e6aa7eebed28ef7a55e561 (patch) | |
| tree | 2fd44a81e2d57d07e5947847899188bfe4129249 /nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h | |
| parent | 0377c66608387053b0fb62db0236294f0b70f959 (diff) | |
| download | px4-nuttx-31a5581021afca8240e6aa7eebed28ef7a55e561.tar.gz px4-nuttx-31a5581021afca8240e6aa7eebed28ef7a55e561.tar.bz2 px4-nuttx-31a5581021afca8240e6aa7eebed28ef7a55e561.zip | |
LPC1788 updates from Rommel Marcelo; NUC120 updates
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5658 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h')
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h index ca4ab6b1d..11a94240c 100755 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h @@ -88,13 +88,13 @@ /* Register addresses ***************************************************************/ -#define LPC17_IOCON_P_BASE(b) (LPC17_IOCON_BASE + (unsigned int(b) << 7)) +#define LPC17_IOCON_P_BASE(b) (LPC17_IOCON_BASE + ((unsigned int)(b) << 7)) #define LPC17_IOCON_P0_BASE (LPC17_IOCON_BASE + 0x0000) #define LPC17_IOCON_P1_BASE (LPC17_IOCON_BASE + 0x0080) #define LPC17_IOCON_P2_BASE (LPC17_IOCON_BASE + 0x0100) #define LPC17_IOCON_P3_BASE (LPC17_IOCON_BASE + 0x0180) #define LPC17_IOCON_P4_BASE (LPC17_IOCON_BASE + 0x0200) -#define LPC17_IOCON_P4_BASE (LPC17_IOCON_BASE + 0x0280) +#define LPC17_IOCON_P5_BASE (LPC17_IOCON_BASE + 0x0280) #define LPC17_IOCON_P(b,p) (LPC17_IOCON_P_BASE(b) + LPC17_IOCON_PP_OFFSET(p)) @@ -308,9 +308,9 @@ #define IOCON_FUNC_ALT6 (6) #define IOCON_FUNC_ALT7 (7) -#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */ +#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */ #define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT) -#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */ +#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */ #define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT ) #define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */ #define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT) |