Files needed to make LPC17xx EMAC RAM more configurable

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3141 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 1 insertions, 120 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
index fe0ac2e43..2f2e53fc7 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -60,6 +60,7 @@
 #include "up_arch.h"
 #include "lpc17_syscon.h"
 #include "lpc17_ethernet.h"
+#include "lpc17_emacram.h"
 #include "lpc17_internal.h"
 
 #include <arch/board/board.h>
@@ -199,126 +200,6 @@
 #  endif
 #endif
 
-/* Descriptors **************************************************************/
-/* EMAC DMA RAM and descriptor definitions.  The configured number of
- * descriptors will determine the organization and the size of the
- * descriptor and status tables.  There is a complex interaction between
- * the maximum packet size (CONFIG_NET_BUFSIZE) and the number of 
- * Rx and Tx descriptors that can be suppored (CONFIG_NET_NRXDESC and
- * CONFIG_NET_NTXDESC): Small buffers -> more packets.  This is
- * something that needs to be tuned for you system.
- *
- * For a 16Kb SRAM region, here is the relationship:
- *
- *  16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8)
- *
- * If ntx == nrx and pktsize == 424, then you could have
- * ntx = nrx = 18.
- *
- * An example with all of the details:
- *
- * NTXDESC=18 NRXDESC=18 CONFIG_NET_BUFSIZE=420:
- *   LPC17_TXDESCTAB_SIZE = 18*8 = 144
- *   LPC17_TXSTATTAB_SIZE = 18*4 =  72
- *   LPC17_TXTAB_SIZE     = 216
- *
- *   LPC17_RXDESCTAB_SIZE = 16*8 = 144
- *   LPC17_RXSTATTAB_SIZE = 16*8 = 144
- *   LPC17_TXTAB_SIZE     = 288
- *
- *   LPC17_DESCTAB_SIZE   = 504
- *   LPC17_DESC_BASE      = LPC17_SRAM_BANK0 + 0x00004000 - 504
- *                        = LPC17_SRAM_BANK0 + 0x00003e08
- *   LPC17_TXDESC_BASE    = LPC17_SRAM_BANK0 + 0x00003e08
- *   LPC17_TXSTAT_BASE    = LPC17_SRAM_BANK0 + 0x00003e98
- *   LPC17_RXDESC_BASE    = LPC17_SRAM_BANK0 + 0x00003ee0
- *   LPC17_RXSTAT_BASE    = LPC17_SRAM_BANK0 + 0x00003f70
- *
- *   LPC17_PKTMEM_BASE    = LPC17_SRAM_BANK0
- *   LPC17_PKTMEM_SIZE    = 0x00004000-504 = 0x00003e40
- *   LPC17_PKTMEM_END     = LPC17_SRAM_BANK0 + 0x00003e08
-
- *   LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424
- *   LPC17_NTXPKTS        = 18
- *   LPC17_NRXPKTS        = 18
-
- *   LPC17_TXBUFFER_SIZE  = 18 * 424 = 0x00001dd0
- *   LPC17_RXBUFFER_SIZE  = 18 * 424 = 0x00001dd0
- *   LPC17_BUFFER_SIZE    = 0x00003ba0
-
- *   LPC17_BUFFER_BASE    = LPC17_SRAM_BANK0
- *   LPC17_TXBUFFER_BASE  = LPC17_SRAM_BANK0
- *   LPC17_RXBUFFER_BASE  = LPC17_SRAM_BANK0 + 0x00001dd0
- *   LPC17_BUFFER_END     = LPC17_SRAM_BANK0 + 0x00003ba0
- *
- *   Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The
- *   amount of unused memory is small: 0x00003e08-0x00003ba0 or about
- *   616 bytes -- not enough for two more packets.
- *
- * [It is also possible, with some effort, to reclaim any unused
- *  SRAM for the use in the heap.  But that has not yet been pursued.]
- */
-
-#ifndef CONFIG_NET_NTXDESC
-#  define CONFIG_NET_NTXDESC 18
-#endif
-#define LPC17_TXDESCTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXDESC_SIZE)
-#define LPC17_TXSTATTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXSTAT_SIZE)
-#define LPC17_TXTAB_SIZE     (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE)
-
-#ifndef CONFIG_NET_NRXDESC
-#  define CONFIG_NET_NRXDESC 18
-#endif
-#define LPC17_RXDESCTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXDESC_SIZE)
-#define LPC17_RXSTATTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXSTAT_SIZE)
-#define LPC17_RXTAB_SIZE     (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE)
-
-#define LPC17_DESCTAB_SIZE   (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE)
-
-/* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors. */
-
-#define LPC17_BANK0_SIZE     0x00004000
-
-#define LPC17_EMACRAM_BASE   LPC17_SRAM_BANK0
-#define LPC17_EMACRAM_SIZE   LPC17_BANK0_SIZE
-
-/* Descriptor table memory organization.  Descriptor tables are packed at
- * the end of AHB SRAM, Bank 0.  The beginning of bank 0 is reserved for
- * packet memory.
- */
-
-#define LPC17_DESC_BASE      (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
-#define LPC17_TXDESC_BASE    LPC17_DESC_BASE
-#define LPC17_TXSTAT_BASE    (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE)
-#define LPC17_RXDESC_BASE    (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE)
-#define LPC17_RXSTAT_BASE    (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE)
-
-/* Now carve up the beginning of SRAM for packet memory.  The size of a
- * packet buffer is related to the size of the MTU.  We'll round sizes up
- * to multiples of 256 bytes.
- */
-
-#define LPC17_PKTMEM_BASE     LPC17_EMACRAM_BASE
-#define LPC17_PKTMEM_SIZE     (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
-#define LPC17_PKTMEM_END      (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE)
-
-#define LPC17_MAXPACKET_SIZE  ((CONFIG_NET_BUFSIZE + 3 + 2) & ~3)
-#define LPC17_NTXPKTS         CONFIG_NET_NTXDESC
-#define LPC17_NRXPKTS         CONFIG_NET_NRXDESC
-
-#define LPC17_TXBUFFER_SIZE   (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE)
-#define LPC17_RXBUFFER_SIZE   (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE)
-#define LPC17_BUFFER_SIZE     (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE)
-
-#define LPC17_BUFFER_BASE     LPC17_PKTMEM_BASE
-#define LPC17_TXBUFFER_BASE   LPC17_BUFFER_BASE
-#define LPC17_RXBUFFER_BASE   (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE)
-#define LPC17_BUFFER_END      (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE)
-
-#if LPC17_BUFFER_END > LPC17_PKTMEM_END
-#  error "Packet memory overlaps descriptor tables"
-#endif
-
 /****************************************************************************
  * Private Types
  ****************************************************************************/