Refactor all lpc17xx header files (more like STM32 header file structure now)

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5534 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 170 insertions, 357 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h
index c0e70efa5..41e60877d 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/lpc17xx/lpc17_gpdma.h
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -41,377 +41,190 @@
  ************************************************************************************/
 
 #include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
+#include "chip/lpc17_gpdma.h"
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* Register offsets *****************************************************************/
-
-/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */
-
-#define LPC17_DMA_INTST_OFFSET        0x0000 /* DMA Interrupt Status Register */
-#define LPC17_DMA_INTTCST_OFFSET      0x0004 /* DMA Interrupt Terminal Count Request Status Register */
-#define LPC17_DMA_INTTCCLR_OFFSET     0x0008 /* DMA Interrupt Terminal Count Request Clear Register */
-#define LPC17_DMA_INTERRST_OFFSET     0x000c /* DMA Interrupt Error Status Register */
-#define LPC17_DMA_INTERRCLR_OFFSET    0x0010 /* DMA Interrupt Error Clear Register */
-#define LPC17_DMA_RAWINTTCST_OFFSET   0x0014 /* DMA Raw Interrupt Terminal Count Status Register */
-#define LPC17_DMA_RAWINTERRST_OFFSET  0x0018 /* DMA Raw Error Interrupt Status Register */
-#define LPC17_DMA_ENBLDCHNS_OFFSET    0x001c /* DMA Enabled Channel Register */
-#define LPC17_DMA_SOFTBREQ_OFFSET     0x0020 /* DMA Software Burst Request Register */
-#define LPC17_DMA_SOFTSREQ_OFFSET     0x0024 /* DMA Software Single Request Register */
-#define LPC17_DMA_SOFTLBREQ_OFFSET    0x0028 /* DMA Software Last Burst Request Register */
-#define LPC17_DMA_SOFTLSREQ_OFFSET    0x002c /* DMA Software Last Single Request Register */
-#define LPC17_DMA_CONFIG_OFFSET       0x0030 /* DMA Configuration Register */
-#define LPC17_DMA_SYNC_OFFSET         0x0034 /* DMA Synchronization Register */
-
-/* Channel Registers */
-
-#define LPC17_DMA_CHAN_OFFSET(n)      (0x0100 + ((n) << 5)) /* n=0,1,...7 */
-
-#define LPC17_DMACH_SRCADDR_OFFSET    0x0000 /* DMA Channel Source Address Register */
-#define LPC17_DMACH_DESTADDR_OFFSET   0x0004 /* DMA Channel Destination Address Register */
-#define LPC17_DMACH_LLI_OFFSET        0x0008 /* DMA Channel Linked List Item Register */
-#define LPC17_DMACH_CONTROL_OFFSET    0x000c /* DMA Channel Control Register */
-#define LPC17_DMACH_CONFIG_OFFSET     0x0010 /* DMA Channel Configuration Register */
-
-#define LPC17_DMACH0_SRCADDR_OFFSET   (0x100+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH0_DESTADDR_OFFSET  (0x100+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH0_LLI_OFFSET       (0x100+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH0_CONTROL_OFFSET   (0x100+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH0_CONFIG_OFFSET    (0x100+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH1_SRCADDR_OFFSET   (0x120+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH1_DESTADDR_OFFSET  (0x120+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH1_LLI_OFFSET       (0x120+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH1_CONTROL_OFFSET   (0x120+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH1_CONFIG_OFFSET    (0x120+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH2_SRCADDR_OFFSET   (0x140+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH2_DESTADDR_OFFSET  (0x140+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH2_LLI_OFFSET       (0x140+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH2_CONTROL_OFFSET   (0x140+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH2_CONFIG_OFFSET    (0x140+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH3_SRCADDR_OFFSET   (0x160+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH3_DESTADDR_OFFSET  (0x160+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH3_LLI_OFFSET       (0x160+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH3_CONTROL_OFFSET   (0x160+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH3_CONFIG_OFFSET    (0x160+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH4_SRCADDR_OFFSET   (0x180+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH4_DESTADDR_OFFSET  (0x180+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH4_LLI_OFFSET       (0x180+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH4_CONTROL_OFFSET   (0x180+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH4_CONFIG_OFFSET    (0x180+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH5_SRCADDR_OFFSET   (0x1a0+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH5_DESTADDR_OFFSET  (0x1a0+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH5_LLI_OFFSET       (0x1a0+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH5_CONTROL_OFFSET   (0x1a0+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH5_CONFIG_OFFSET    (0x1a0+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH6_SRCADDR_OFFSET   (0x1c0+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH6_DESTADDR_OFFSET  (0x1c0+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH6_LLI_OFFSET       (0x1c0+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH6_CONTROL_OFFSET   (0x1c0+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH6_CONFIG_OFFSET    (0x1c0+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH7_SRCADDR_OFFSET   (0x1e0+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH7_DESTADDR_OFFSET  (0x1e0+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH7_LLI_OFFSET       (0x1e0+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH7_CONTROL_OFFSET   (0x1e0+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH7_CONFIG_OFFSET    (0x1e0+LPC17_DMACH_CONFIG_OFFSET)
-
-/* Register addresses ***************************************************************/
-/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */
-
-#define LPC17_DMA_INTST               (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET)
-#define LPC17_DMA_INTTCST             (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET)
-#define LPC17_DMA_INTTCCLR            (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET)
-#define LPC17_DMA_INTERRST            (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET)
-#define LPC17_DMA_INTERRCLR           (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET)
-#define LPC17_DMA_RAWINTTCST          (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET)
-#define LPC17_DMA_RAWINTERRST         (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET)
-#define LPC17_DMA_ENBLDCHNS           (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET)
-#define LPC17_DMA_SOFTBREQ            (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET)
-#define LPC17_DMA_SOFTSREQ            (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET)
-#define LPC17_DMA_SOFTLBREQ           (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET)
-#define LPC17_DMA_SOFTLSREQ           (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET)
-#define LPC17_DMA_CONFIG              (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET)
-#define LPC17_DMA_SYNC                (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET)
-
-/* Channel Registers */
-
-#define LPC17_DMACH_BASE(n)           (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n))
-
-#define LPC17_DMACH_SRCADDR(n)        (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH_DESTADDR(n)       (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH_LLI(n)            (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH_CONTROL(n)        (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH_CONFIG(n)         (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH0_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET)
-#define LPC17_DMACH0_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET)
-#define LPC17_DMACH0_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET)
-#define LPC17_DMACH0_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET)
-#define LPC17_DMACH0_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET)
-
-#define LPC17_DMACH1_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET)
-#define LPC17_DMACH1_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET)
-#define LPC17_DMACH1_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET)
-#define LPC17_DMACH1_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET)
-#define LPC17_DMACH1_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET)
-
-#define LPC17_DMACH2_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET)
-#define LPC17_DMACH2_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET)
-#define LPC17_DMACH2_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET)
-#define LPC17_DMACH2_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET)
-#define LPC17_DMACH2_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET)
-
-#define LPC17_DMACH3_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET)
-#define LPC17_DMACH3_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET)
-#define LPC17_DMACH3_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET)
-#define LPC17_DMACH3_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET)
-#define LPC17_DMACH3_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET)
-
-#define LPC17_DMACH4_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET)
-#define LPC17_DMACH4_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET)
-#define LPC17_DMACH4_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET)
-#define LPC17_DMACH4_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET)
-#define LPC17_DMACH4_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET)
-
-#define LPC17_DMACH5_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET)
-#define LPC17_DMACH5_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET)
-#define LPC17_DMACH5_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET)
-#define LPC17_DMACH5_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET)
-#define LPC17_DMACH5_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET)
-
-#define LPC17_DMACH6_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET)
-#define LPC17_DMACH6_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET)
-#define LPC17_DMACH6_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET)
-#define LPC17_DMACH6_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET)
-#define LPC17_DMACH6_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET)
-
-#define LPC17_DMACH7_SRCADDR          (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET)
-#define LPC17_DMACH7_DESTADDR         (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET)
-#define LPC17_DMACH7_LLI              (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET)
-#define LPC17_DMACH7_CONTROL          (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET)
-#define LPC17_DMACH7_CONFIG           (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* DMA request connections */
-
-#define DMA_REQ_SSP0TX                (0)
-#define DMA_REQ_SSP0RX                (1)
-#define DMA_REQ_SSP1TX                (2)
-#define DMA_REQ_SSP1RX                (3)
-#define DMA_REQ_ADC                   (4)
-#define DMA_REQ_I2SCH0                (5)
-#define DMA_REQ_I2SCH1                (6)
-#define DMA_REQ_DAC                   (7)
-
-#define DMA_REQ_UART0TX               (8)
-#define DMA_REQ_UART0RX               (9)
-#define DMA_REQ_UART1TX               (10)
-#define DMA_REQ_UART1RX               (11)
-#define DMA_REQ_UART2TX               (12)
-#define DMA_REQ_UART2RX               (13)
-#define DMA_REQ_UART3TX               (14)
-#define DMA_REQ_UART3RX               (15)
-
-#define DMA_REQ_MAT0p0                (8)
-#define DMA_REQ_MAT0p1                (9)
-#define DMA_REQ_MAT1p0                (10)
-#define DMA_REQ_MAT1p1                (11)
-#define DMA_REQ_MAT2p0                (12)
-#define DMA_REQ_MAT2p1                (13)
-#define DMA_REQ_MAT3p0                (14)
-#define DMA_REQ_MAT3p1                (15)
-
-/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */
-/* Fach of the following registers, bits 0-7 controls DMA channels 9-7,
- * respectively.  Bits 8-31 are reserved.
- *
- *   DMA Interrupt Status Register
- *   DMA Interrupt Terminal Count Request Status Register
- *   DMA Interrupt Terminal Count Request Clear Register
- *   DMA Interrupt Error Status Register
- *   DMA Interrupt Error Clear Register
- *   DMA Raw Interrupt Terminal Count Status Register
- *   DMA Raw Error Interrupt Status Register
- *   DMA Enabled Channel Register
- */
-
-#define DMACH(n)                      (1 << (n)) /* n=0,1,...7 */
-
-/* For each of the following registers, bits 0-15 represent a set of encoded
- * DMA sources. Bits 16-31 are reserved in each case.
- *
- *   DMA Software Burst Request Register
- *   DMA Software Single Request Register
- *   DMA Software Last Burst Request Register
- *   DMA Software Last Single Request Register
- *   DMA Synchronization Register
- */
-
-#define DMA_REQ_SSP0TX_BIT            (1 << DMA_REQ_SSP0TX)
-#define DMA_REQ_SSP0RX_BIT            (1 << DMA_REQ_SSP0RX)
-#define DMA_REQ_SSP1TX_BIT            (1 << DMA_REQ_SSP1TX)
-#define DMA_REQ_SSP1RX_BIT            (1 << DMA_REQ_SSP0RX)
-#define DMA_REQ_ADC_BIT               (1 << DMA_REQ_ADC)
-#define DMA_REQ_I2SCH0_BIT            (1 << DMA_REQ_I2SCH0)
-#define DMA_REQ_I2SCH1_BIT            (1 << DMA_REQ_I2SCH1)
-#define DMA_REQ_DAC_BIT               (1 << DMA_REQ_DAC)
-
-#define DMA_REQ_UART0TX_BIT           (1 << DMA_REQ_UART0TX)
-#define DMA_REQ_UART0RX_BIT           (1 << DMA_REQ_UART0RX)
-#define DMA_REQ_UART1TX_BIT           (1 << DMA_REQ_UART1TX)
-#define DMA_REQ_UART1RX_BIT           (1 << DMA_REQ_UART1RX)
-#define DMA_REQ_UART2TX_BIT           (1 << DMA_REQ_UART2TX)
-#define DMA_REQ_UART2RX_BIT           (1 << DMA_REQ_UART2RX)
-#define DMA_REQ_UART3TX_BIT           (1 << DMA_REQ_UART3TX)
-#define DMA_REQ_UART3RX_BIT           (1 << DMA_REQ_UART3RX)
-
-#define DMA_REQ_MAT0p0_BIT            (1 << DMA_REQ_MAT0p0)
-#define DMA_REQ_MAT0p1_BIT            (1 << DMA_REQ_MAT0p1)
-#define DMA_REQ_MAT1p0_BIT            (1 << DMA_REQ_MAT1p0)
-#define DMA_REQ_MAT1p1_BIT            (1 << DMA_REQ_MAT1p1)
-#define DMA_REQ_MAT2p0_BIT            (1 << DMA_REQ_MAT2p0)
-#define DMA_REQ_MAT2p1_BIT            (1 << DMA_REQ_MAT2p1)
-#define DMA_REQ_MAT3p0_BIT            (1 << DMA_REQ_MAT3p0)
-#define DMA_REQ_MAT3p1_BIT            (1 << DMA_REQ_MAT3p1)
-
-/* DMA Configuration Register */
-
-#define DMA_CONFIG_E                  (1 << 0)  /* Bit 0:  DMA Controller enable */
-#define DMA_CONFIG_M                  (1 << 1)  /* Bit 1:  AHB Master endianness configuration */
-                                                /* Bits 2-31: Reserved */
-/* Channel Registers */
-
-/* DMA Channel Source Address Register (Bits 0-31: Source Address) */
-/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */
-/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list
- * item.  Bits 0-1 must be zero.
- */
-
-/* DMA Channel Control Register */
-
-#define DMACH_CONTROL_XFRSIZE_SHIFT   (0)       /* Bits 0-11: Transfer size */
-#define DMACH_CONTROL_XFRSIZE_MASK    (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT)
-#define DMACH_CONTROL_SBSIZE_SHIFT    (12)      /* Bits 12-14: Source burst size */
-#define DMACH_CONTROL_SBSIZE_MASK     (7 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_1      (0 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_4      (1 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_8      (2 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_16     (3 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_32     (4 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_64     (5 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_128    (6 << DMACH_CONTROL_SBSIZE_SHIFT)
-#  define DMACH_CONTROL_SBSIZE_256    (7 << DMACH_CONTROL_SBSIZE_SHIFT)
-#define DMACH_CONTROL_DBSIZE_SHIFT    (15)      /* Bits 15-17: Destination burst size */
-#define DMACH_CONTROL_DBSIZE_MASK     (7 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_1      (0 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_4      (1 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_8      (2 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_16     (3 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_32     (4 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_64     (5 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_128    (6 << DMACH_CONTROL_DBSIZE_SHIFT)
-#  define DMACH_CONTROL_DBSIZE_256    (7 << DMACH_CONTROL_DBSIZE_SHIFT)
-#define DMACH_CONTROL_SWIDTH_SHIFT    (18)      /* Bits 18-20: Source transfer width */
-#define DMACH_CONTROL_SWIDTH_MASK     (7 << DMACH_CONTROL_SWIDTH_SHIFT)
-#define DMACH_CONTROL_DWIDTH_SHIFT    (21)      /* Bits 21-23: Destination transfer width */
-#define DMACH_CONTROL_DWIDTH_MASK     (7 << DMACH_CONTROL_DWIDTH_SHIFT)
-#define DMACH_CONTROL_SI              (1 << 26) /* Bit 26: Source increment */
-#define DMACH_CONTROL_DI              (1 << 27) /* Bit 27: Destination increment */
-#define DMACH_CONTROL_PROT1           (1 << 28) /* Bit 28: User/priviledged mode */
-#define DMACH_CONTROL_PROT2           (1 << 29) /* Bit 29: Bufferable */
-#define DMACH_CONTROL_PROT3           (1 << 30) /* Bit 30: Cacheable */
-#define DMACH_CONTROL_I               (1 << 31) /* Bit 31: Terminal count interrupt enable */
-
-/* DMA Channel Configuration Register */
-
-
-#define DMACH_CONFIG_E                (1 << 0) /* Bit 0: Channel enable */
-#define DMACH_CONFIG_SRCPER_SHIFT     (1)      /* Bits 1-5: Source peripheral */
-#define DMACH_CONFIG_SRCPER_MASK      (31 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_SSP0TX  (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_SSP0RX  (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_SSP1TX  (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_SSP1RX  (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_ADC     (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_I2SCH0  (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_I2SCH1  (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_DAC     (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT0p0  (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT0p1  (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT1p0  (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT1p1  (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT2p0  (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT2p1  (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT3p0  (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT)
-#  define DMACH_CONFIG_SRCPER_MAT3p1  (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT)
-#define DMACH_CONFIG_DSTPER_SHIFT     (6)      /* Bits 6-10: Source peripheral */
-#define DMACH_CONFIG_DSTPER_MASK      (31 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_SSP0TX  (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_SSP0RX  (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_SSP1TX  (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_SSP1RX  (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_ADC     (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_I2SCH0  (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_I2SCH1  (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_DAC     (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT0p0  (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT0p1  (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT1p0  (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT1p1  (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT2p0  (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT2p1  (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT3p0  (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT)
-#  define DMACH_CONFIG_DSTPER_MAT3p1  (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT)
-#define DMACH_CONFIG_XFRTYPE_SHIFT    (11)      /* Bits 11-13: Type of transfer */
-#define DMACH_CONFIG_XFRTYPE_MASK     (7 << DMACH_CONFIG_XFRTYPE_SHIFT)
-#  define DMACH_CONFIG_XFRTYPE_M2M    (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory DMA */
-#  define DMACH_CONFIG_XFRTYPE_M2P    (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral DMA */
-#  define DMACH_CONFIG_XFRTYPE_P2M    (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory DMA */
-#  define DMACH_CONFIG_XFRTYPE_P2P    (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral DMA */
-#define DMACH_CONFIG_IE               (1 << 14) /* Bit 14: Interrupt error mask */
-#define DMACH_CONFIG_ ITC             (1 << 15) /* Bit 15: Terminal count interrupt mask */
-#define DMACH_CONFIG_L                (1 << 16) /* Bit 16: Lock */
-#define DMACH_CONFIG_A                (1 << 17) /* Bit 17: Active */
-#define DMACH_CONFIG_H                (1 << 18) /* Bit 18: Halt */
-                                                /* Bits 19-31: Reserved */
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/
 
+#ifdef CONFIG_LPC17_GPDMA
+
+typedef FAR void *DMA_HANDLE;
+typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
+
+/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
+
+#ifdef CONFIG_DEBUG_DMA
+struct lpc17_dmaglobalregs_s
+{
+  /* Global Registers */
+
+  uint32_t intst;       /* DMA Interrupt Status Register */
+  uint32_t inttcst;     /* DMA Interrupt Terminal Count Request Status Register */
+  uint32_t interrst;    /* DMA Interrupt Error Status Register */
+  uint32_t rawinttcst;  /* DMA Raw Interrupt Terminal Count Status Register */
+  uint32_t rawinterrst; /* DMA Raw Error Interrupt Status Register */
+  uint32_t enbldchns;   /* DMA Enabled Channel Register */
+  uint32_t softbreq;    /* DMA Software Burst Request Register */
+  uint32_t softsreq;    /* DMA Software Single Request Register */
+  uint32_t softlbreq;   /* DMA Software Last Burst Request Register */
+  uint32_t softlsreq;   /* DMA Software Last Single Request Register */
+  uint32_t config;      /* DMA Configuration Register */
+  uint32_t sync;        /* DMA Synchronization Register */
+};
+
+struct lpc17_dmachanregs_s
+{
+  /* Channel Registers */
+
+  uint32_t srcaddr;  /* DMA Channel Source Address Register */
+  uint32_t destaddr; /* DMA Channel Destination Address Register */
+  uint32_t lli;      /* DMA Channel Linked List Item Register */
+  uint32_t control;  /* DMA Channel Control Register */
+  uint32_t config;   /* DMA Channel Configuration Register */
+};
+
+struct lpc17_dmaregs_s
+{
+  /* Global Registers */
+
+  struct lpc17_dmaglobalregs_s gbl;
+
+  /* Channel Registers */
+
+  struct lpc17_dmachanregs_s   ch;
+};
+
+#endif /* CONFIG_DEBUG_DMA */
+
 /************************************************************************************
  * Public Data
  ************************************************************************************/
 
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
 
+/****************************************************************************
+ * Name: lpc17_dmainitialize
+ *
+ * Description:
+ *   Initialize the GPDMA subsystem.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void lpc17_dmainitilaize(void);
+
+/****************************************************************************
+ * Name: lpc17_dmachannel
+ *
+ * Description:
+ *   Allocate a DMA channel.  This function sets aside a DMA channel and
+ *   gives the caller exclusive access to the DMA channel.
+ *
+ * Returned Value:
+ *   One success, this function returns a non-NULL, void* DMA channel
+ *   handle.  NULL is returned on any failure.  This function can fail only
+ *   if no DMA channel is available.
+ *
+ ****************************************************************************/
+
+DMA_HANDLE lpc17_dmachannel(void);
+
+/****************************************************************************
+ * Name: lpc17_dmafree
+ *
+ * Description:
+ *   Release a DMA channel.  NOTE:  The 'handle' used in this argument must
+ *   NEVER be used again until lpc17_dmachannel() is called again to re-gain
+ *   a valid handle.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void lpc17_dmafree(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: lpc17_dmasetup
+ *
+ * Description:
+ *   Configure DMA for one transfer.
+ *
+ ****************************************************************************/
+
+int lpc17_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
+                     uint32_t srcaddr, uint32_t destaddr, size_t nbytes);
+
+/****************************************************************************
+ * Name: lpc17_dmastart
+ *
+ * Description:
+ *   Start the DMA transfer
+ *
+ ****************************************************************************/
+
+int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
+
+/****************************************************************************
+ * Name: lpc17_dmastop
+ *
+ * Description:
+ *   Cancel the DMA.  After lpc17_dmastop() is called, the DMA channel is
+ *   reset and lpc17_dmasetup() must be called before lpc17_dmastart() can be
+ *   called again
+ *
+ ****************************************************************************/
+
+void lpc17_dmastop(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: lpc17_dmasample
+ *
+ * Description:
+ *   Sample DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+EXTERN void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs);
+#else
+#  define lpc17_dmasample(handle,regs)
+#endif
+
+/****************************************************************************
+ * Name: lpc17_dmadump
+ *
+ * Description:
+ *   Dump previously sampled DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+EXTERN void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs,
+                          const char *msg);
+#else
+#  define lpc17_dmadump(handle,regs,msg)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_LPC17_GPDMA */
 #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H */