Refactor all lpc17xx header files (more like STM32 header file structure now)

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5534 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 2 insertions, 48 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h
index bd7790a6e..b9ef49fc3 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/lpc17xx/lpc17_wdt.h
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -41,58 +41,12 @@
  ************************************************************************************/
 
 #include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
+#include "chip/lpc17_wdt.h"
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* Register offsets *****************************************************************/
-
-#define LPC17_WDT_WDMOD_OFFSET     0x0000  /* Watchdog mode register */
-#define LPC17_WDT_WDTC_OFFSET      0x0004  /* Watchdog timer constant register */
-#define LPC17_WDT_WDFEED_OFFSET    0x0008  /* Watchdog feed sequence register */
-#define LPC17_WDT_WDTV_OFFSET      0x000c  /* Watchdog timer value register */
-#define LPC17_WDT_WDCLKSEL_OFFSET  0x0010  /* Watchdog clock source selection register */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_WDT_WDMOD            (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET)
-#define LPC17_WDT_WDTC             (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET)
-#define LPC17_WDT_WDFEED           (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET)
-#define LPC17_WDT_WDTV             (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET)
-#define LPC17_WDT_WDCLKSEL         (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET)
-
-/* Register bit definitions *********************************************************/
-
-/* Watchdog mode register */
-
-#define WDT_WDMOD_WDEN             (1 << 0)  /* Bit 0: Watchdog enable */
-#define WDT_WDMOD_WDRESET          (1 << 1)  /* Bit 1: Watchdog reset enable */
-#define WDT_WDMOD_WDTOF            (1 << 2)  /* Bit 2: Watchdog time-out */
-#define WDT_WDMOD_WDINT            (1 << 3)  /* Bit 3: Watchdog interrupt */
-                                             /* Bits 14-31: Reserved */
-
-/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */
-
-/* Watchdog feed sequence register  */
-
-#define WDT_WDFEED_MASK            (0xff)    /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */
-                                             /* Bits 14-31: Reserved */
-/* Watchdog timer value register (Bits 0-31: Counter timer value) */
-
-/* Watchdog clock source selection register */
-
-#define WDT_WDCLKSEL_WDSEL_SHIFT   (0)       /* Bits 0-1: Clock source for the Watchdog timer */
-#define WDT_WDCLKSEL_WDSEL_MASK    (3 << WDT_WDCLKSEL_WDSEL_SHIFT)
-#  define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */
-#  define WDT_WDCLKSEL_WDSEL_APB   (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */
-#  define WDT_WDCLKSEL_WDSEL_RTC   (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */
-                                             /* Bits 2-30: Reserved */
-#define WDT_WDCLKSEL_WDLOCK        (1 << 31) /* Bit 31: Lock WDT register bits if set */
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/