LPC1788 updated from Rommel Marcelo

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5583 42af7a65-404d-4744-a932-0658087f49c3

3 files changed, 389 insertions, 34 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
index b8c9ee480..a3c247caf 100755
--- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
+++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
@@ -52,13 +52,7 @@
 
 /* Register offsets *****************************************************************/
 
-#define LPC17_IOCON_P0_OFFSET       (LPC17_IOCON_BASE+0x0000)
-#define LPC17_IOCON_P1_OFFSET       (LPC17_IOCON_BASE+0x0080)
-#define LPC17_IOCON_P2_OFFSET       (LPC17_IOCON_BASE+0x0100)
-#define LPC17_IOCON_P3_OFFSET       (LPC17_IOCON_BASE+0x0180)
-#define LPC17_IOCON_P4_OFFSET       (LPC17_IOCON_BASE+0x0200)
-#define LPC17_IOCON_P5_OFFSET       (LPC17_IOCON_BASE+0x0280)
-
+#define LPC17_IOCON_PP_OFFSET(p)    ((p) << 2)
 #define LPC17_IOCON_PP0_OFFSET      (0x0000) /* IOCON Port(n) register 0  */
 #define LPC17_IOCON_PP1_OFFSET      (0x0004) /* IOCON Port(n) register 1  */
 #define LPC17_IOCON_PP2_OFFSET      (0x0008) /* IOCON Port(n) register 2  */
@@ -94,10 +88,215 @@
 
 /* Register addresses ***************************************************************/
 
-//~ #define LPC17_IOCON_PP1(portoffset)        (portoffset+LPC17_IOCON_P0_OFFSET)
+#define LPC17_IOCON_P_BASE(b)       (LPC17_IOCON_BASE + ((b) << 7))
+#define LPC17_IOCON_P0_BASE         (LPC17_IOCON_BASE + 0x0000)
+#define LPC17_IOCON_P1_BASE         (LPC17_IOCON_BASE + 0x0080)
+#define LPC17_IOCON_P2_BASE         (LPC17_IOCON_BASE + 0x0100)
+#define LPC17_IOCON_P3_BASE         (LPC17_IOCON_BASE + 0x0180)
+#define LPC17_IOCON_P4_BASE         (LPC17_IOCON_BASE + 0x0200)
+#define LPC17_IOCON_P4_BASE         (LPC17_IOCON_BASE + 0x0280)
+
+#define LPC17_IOCON_P(b,p)          (LPC17_IOCON_P_BASE(b) + LPC17_IOCON_PP_OFFSET(p))
+
+#define LPC17_IOCON_P0_0            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP0_OFFSET)
+#define LPC17_IOCON_P0_1            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP1_OFFSET)
+#define LPC17_IOCON_P0_2            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP2_OFFSET)
+#define LPC17_IOCON_P0_3            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP3_OFFSET)
+#define LPC17_IOCON_P0_4            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP4_OFFSET)
+#define LPC17_IOCON_P0_5            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP5_OFFSET)
+#define LPC17_IOCON_P0_6            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP6_OFFSET)
+#define LPC17_IOCON_P0_7            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP7_OFFSET)
+#define LPC17_IOCON_P0_8            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP8_OFFSET)
+#define LPC17_IOCON_P0_9            (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP9_OFFSET)
+#define LPC17_IOCON_P0_10           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP10_OFFSET)
+#define LPC17_IOCON_P0_11           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP11_OFFSET)
+#define LPC17_IOCON_P0_12           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP12_OFFSET)
+#define LPC17_IOCON_P0_13           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP13_OFFSET)
+#define LPC17_IOCON_P0_14           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP14_OFFSET)
+#define LPC17_IOCON_P0_15           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP15_OFFSET)
+#define LPC17_IOCON_P0_16           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP16_OFFSET)
+#define LPC17_IOCON_P0_17           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP17_OFFSET)
+#define LPC17_IOCON_P0_18           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP18_OFFSET)
+#define LPC17_IOCON_P0_19           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP19_OFFSET)
+#define LPC17_IOCON_P0_20           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP20_OFFSET)
+#define LPC17_IOCON_P0_21           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP21_OFFSET)
+#define LPC17_IOCON_P0_22           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP22_OFFSET)
+#define LPC17_IOCON_P0_23           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP23_OFFSET)
+#define LPC17_IOCON_P0_24           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP24_OFFSET)
+#define LPC17_IOCON_P0_25           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP25_OFFSET)
+#define LPC17_IOCON_P0_26           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP26_OFFSET)
+#define LPC17_IOCON_P0_27           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP27_OFFSET)
+#define LPC17_IOCON_P0_28           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP28_OFFSET)
+#define LPC17_IOCON_P0_29           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP29_OFFSET)
+#define LPC17_IOCON_P0_30           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP30_OFFSET)
+#define LPC17_IOCON_P0_31           (LPC17_IOCON_P0_BASE + LPC17_IOCON_PP31_OFFSET)
+
+#define LPC17_IOCON_P1_0            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP0_OFFSET)
+#define LPC17_IOCON_P1_1            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP1_OFFSET)
+#define LPC17_IOCON_P1_2            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP2_OFFSET)
+#define LPC17_IOCON_P1_3            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP3_OFFSET)
+#define LPC17_IOCON_P1_4            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP4_OFFSET)
+#define LPC17_IOCON_P1_5            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP5_OFFSET)
+#define LPC17_IOCON_P1_6            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP6_OFFSET)
+#define LPC17_IOCON_P1_7            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP7_OFFSET)
+#define LPC17_IOCON_P1_8            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP8_OFFSET)
+#define LPC17_IOCON_P1_9            (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP9_OFFSET)
+#define LPC17_IOCON_P1_10           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP10_OFFSET)
+#define LPC17_IOCON_P1_11           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP11_OFFSET)
+#define LPC17_IOCON_P1_12           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP12_OFFSET)
+#define LPC17_IOCON_P1_13           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP13_OFFSET)
+#define LPC17_IOCON_P1_14           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP14_OFFSET)
+#define LPC17_IOCON_P1_15           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP15_OFFSET)
+#define LPC17_IOCON_P1_16           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP16_OFFSET)
+#define LPC17_IOCON_P1_17           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP17_OFFSET)
+#define LPC17_IOCON_P1_18           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP18_OFFSET)
+#define LPC17_IOCON_P1_19           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP19_OFFSET)
+#define LPC17_IOCON_P1_20           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP20_OFFSET)
+#define LPC17_IOCON_P1_21           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP21_OFFSET)
+#define LPC17_IOCON_P1_22           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP22_OFFSET)
+#define LPC17_IOCON_P1_23           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP23_OFFSET)
+#define LPC17_IOCON_P1_24           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP24_OFFSET)
+#define LPC17_IOCON_P1_25           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP25_OFFSET)
+#define LPC17_IOCON_P1_26           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP26_OFFSET)
+#define LPC17_IOCON_P1_27           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP27_OFFSET)
+#define LPC17_IOCON_P1_28           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP28_OFFSET)
+#define LPC17_IOCON_P1_29           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP29_OFFSET)
+#define LPC17_IOCON_P1_30           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP30_OFFSET)
+#define LPC17_IOCON_P1_31           (LPC17_IOCON_P1_BASE + LPC17_IOCON_PP31_OFFSET)
+
+#define LPC17_IOCON_P2_0            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP0_OFFSET)
+#define LPC17_IOCON_P2_1            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP1_OFFSET)
+#define LPC17_IOCON_P2_2            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP2_OFFSET)
+#define LPC17_IOCON_P2_3            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP3_OFFSET)
+#define LPC17_IOCON_P2_4            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP4_OFFSET)
+#define LPC17_IOCON_P2_5            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP5_OFFSET)
+#define LPC17_IOCON_P2_6            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP6_OFFSET)
+#define LPC17_IOCON_P2_7            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP7_OFFSET)
+#define LPC17_IOCON_P2_8            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP8_OFFSET)
+#define LPC17_IOCON_P2_9            (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP9_OFFSET)
+#define LPC17_IOCON_P2_10           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP10_OFFSET)
+#define LPC17_IOCON_P2_11           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP11_OFFSET)
+#define LPC17_IOCON_P2_12           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP12_OFFSET)
+#define LPC17_IOCON_P2_13           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP13_OFFSET)
+#define LPC17_IOCON_P2_14           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP14_OFFSET)
+#define LPC17_IOCON_P2_15           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP15_OFFSET)
+#define LPC17_IOCON_P2_16           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP16_OFFSET)
+#define LPC17_IOCON_P2_17           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP17_OFFSET)
+#define LPC17_IOCON_P2_18           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP18_OFFSET)
+#define LPC17_IOCON_P2_19           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP19_OFFSET)
+#define LPC17_IOCON_P2_20           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP20_OFFSET)
+#define LPC17_IOCON_P2_21           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP21_OFFSET)
+#define LPC17_IOCON_P2_22           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP22_OFFSET)
+#define LPC17_IOCON_P2_23           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP23_OFFSET)
+#define LPC17_IOCON_P2_24           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP24_OFFSET)
+#define LPC17_IOCON_P2_25           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP25_OFFSET)
+#define LPC17_IOCON_P2_26           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP26_OFFSET)
+#define LPC17_IOCON_P2_27           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP27_OFFSET)
+#define LPC17_IOCON_P2_28           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP28_OFFSET)
+#define LPC17_IOCON_P2_29           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP29_OFFSET)
+#define LPC17_IOCON_P2_30           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP30_OFFSET)
+#define LPC17_IOCON_P2_31           (LPC17_IOCON_P2_BASE + LPC17_IOCON_PP31_OFFSET)
+
+#define LPC17_IOCON_P3_0            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP0_OFFSET)
+#define LPC17_IOCON_P3_1            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP1_OFFSET)
+#define LPC17_IOCON_P3_2            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP2_OFFSET)
+#define LPC17_IOCON_P3_3            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP3_OFFSET)
+#define LPC17_IOCON_P3_4            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP4_OFFSET)
+#define LPC17_IOCON_P3_5            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP5_OFFSET)
+#define LPC17_IOCON_P3_6            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP6_OFFSET)
+#define LPC17_IOCON_P3_7            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP7_OFFSET)
+#define LPC17_IOCON_P3_8            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP8_OFFSET)
+#define LPC17_IOCON_P3_9            (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP9_OFFSET)
+#define LPC17_IOCON_P3_10           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP10_OFFSET)
+#define LPC17_IOCON_P3_11           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP11_OFFSET)
+#define LPC17_IOCON_P3_12           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP12_OFFSET)
+#define LPC17_IOCON_P3_13           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP13_OFFSET)
+#define LPC17_IOCON_P3_14           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP14_OFFSET)
+#define LPC17_IOCON_P3_15           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP15_OFFSET)
+#define LPC17_IOCON_P3_16           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP16_OFFSET)
+#define LPC17_IOCON_P3_17           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP17_OFFSET)
+#define LPC17_IOCON_P3_18           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP18_OFFSET)
+#define LPC17_IOCON_P3_19           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP19_OFFSET)
+#define LPC17_IOCON_P3_20           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP20_OFFSET)
+#define LPC17_IOCON_P3_21           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP21_OFFSET)
+#define LPC17_IOCON_P3_22           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP22_OFFSET)
+#define LPC17_IOCON_P3_23           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP23_OFFSET)
+#define LPC17_IOCON_P3_24           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP24_OFFSET)
+#define LPC17_IOCON_P3_25           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP25_OFFSET)
+#define LPC17_IOCON_P3_26           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP26_OFFSET)
+#define LPC17_IOCON_P3_27           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP27_OFFSET)
+#define LPC17_IOCON_P3_28           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP28_OFFSET)
+#define LPC17_IOCON_P3_29           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP29_OFFSET)
+#define LPC17_IOCON_P3_30           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP30_OFFSET)
+#define LPC17_IOCON_P3_31           (LPC17_IOCON_P3_BASE + LPC17_IOCON_PP31_OFFSET)
+
+#define LPC17_IOCON_P4_0            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP0_OFFSET)
+#define LPC17_IOCON_P4_1            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP1_OFFSET)
+#define LPC17_IOCON_P4_2            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP2_OFFSET)
+#define LPC17_IOCON_P4_3            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP3_OFFSET)
+#define LPC17_IOCON_P4_4            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP4_OFFSET)
+#define LPC17_IOCON_P4_5            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP5_OFFSET)
+#define LPC17_IOCON_P4_6            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP6_OFFSET)
+#define LPC17_IOCON_P4_7            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP7_OFFSET)
+#define LPC17_IOCON_P4_8            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP8_OFFSET)
+#define LPC17_IOCON_P4_9            (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP9_OFFSET)
+#define LPC17_IOCON_P4_10           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP10_OFFSET)
+#define LPC17_IOCON_P4_11           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP11_OFFSET)
+#define LPC17_IOCON_P4_12           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP12_OFFSET)
+#define LPC17_IOCON_P4_13           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP13_OFFSET)
+#define LPC17_IOCON_P4_14           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP14_OFFSET)
+#define LPC17_IOCON_P4_15           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP15_OFFSET)
+#define LPC17_IOCON_P4_16           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP16_OFFSET)
+#define LPC17_IOCON_P4_17           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP17_OFFSET)
+#define LPC17_IOCON_P4_18           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP18_OFFSET)
+#define LPC17_IOCON_P4_19           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP19_OFFSET)
+#define LPC17_IOCON_P4_20           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP20_OFFSET)
+#define LPC17_IOCON_P4_21           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP21_OFFSET)
+#define LPC17_IOCON_P4_22           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP22_OFFSET)
+#define LPC17_IOCON_P4_23           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP23_OFFSET)
+#define LPC17_IOCON_P4_24           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP24_OFFSET)
+#define LPC17_IOCON_P4_25           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP25_OFFSET)
+#define LPC17_IOCON_P4_26           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP26_OFFSET)
+#define LPC17_IOCON_P4_27           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP27_OFFSET)
+#define LPC17_IOCON_P4_28           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP28_OFFSET)
+#define LPC17_IOCON_P4_29           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP29_OFFSET)
+#define LPC17_IOCON_P4_30           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP30_OFFSET)
+#define LPC17_IOCON_P4_31           (LPC17_IOCON_P4_BASE + LPC17_IOCON_PP31_OFFSET)
+
+#define LPC17_IOCON_P5_0            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP0_OFFSET)
+#define LPC17_IOCON_P5_1            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP1_OFFSET)
+#define LPC17_IOCON_P5_2            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP2_OFFSET)
+#define LPC17_IOCON_P5_3            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP3_OFFSET)
+#define LPC17_IOCON_P5_4            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP4_OFFSET)
+#define LPC17_IOCON_P5_5            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP5_OFFSET)
+#define LPC17_IOCON_P5_6            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP6_OFFSET)
+#define LPC17_IOCON_P5_7            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP7_OFFSET)
+#define LPC17_IOCON_P5_8            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP8_OFFSET)
+#define LPC17_IOCON_P5_9            (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP9_OFFSET)
+#define LPC17_IOCON_P5_10           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP10_OFFSET)
+#define LPC17_IOCON_P5_11           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP11_OFFSET)
+#define LPC17_IOCON_P5_12           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP12_OFFSET)
+#define LPC17_IOCON_P5_13           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP13_OFFSET)
+#define LPC17_IOCON_P5_14           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP14_OFFSET)
+#define LPC17_IOCON_P5_15           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP15_OFFSET)
+#define LPC17_IOCON_P5_16           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP16_OFFSET)
+#define LPC17_IOCON_P5_17           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP17_OFFSET)
+#define LPC17_IOCON_P5_18           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP18_OFFSET)
+#define LPC17_IOCON_P5_19           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP19_OFFSET)
+#define LPC17_IOCON_P5_20           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP20_OFFSET)
+#define LPC17_IOCON_P5_21           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP21_OFFSET)
+#define LPC17_IOCON_P5_22           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP22_OFFSET)
+#define LPC17_IOCON_P5_23           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP23_OFFSET)
+#define LPC17_IOCON_P5_24           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP24_OFFSET)
+#define LPC17_IOCON_P5_25           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP25_OFFSET)
+#define LPC17_IOCON_P5_26           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP26_OFFSET)
+#define LPC17_IOCON_P5_27           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP27_OFFSET)
+#define LPC17_IOCON_P5_28           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP28_OFFSET)
+#define LPC17_IOCON_P5_29           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP29_OFFSET)
+#define LPC17_IOCON_P5_30           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP30_OFFSET)
+#define LPC17_IOCON_P5_31           (LPC17_IOCON_P5_BASE + LPC17_IOCON_PP31_OFFSET)
 
 /* Register bit definitions *********************************************************/
-/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */
 /* IOCON pin function select */
 
 #define IOCON_FUNC_GPIO             (0)
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
index 73939a389..ece6adc5f 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
@@ -93,37 +93,101 @@ const uint32_t g_fiobase[GPIO_NPORTS] =
   LPC17_FIO2_BASE,
   LPC17_FIO3_BASE,
   LPC17_FIO4_BASE
+#if GPIO_NPORTS > 5
+  , LPC17_FIO5_BASE
+#endif
+};
+
+#ifdef LPC178X
+/* IOCON register base addresses */
+
+const uint32_t g_ioconport[GPIO_NPORTS] =
+{
+  LPC17_IOCON_P0,
+  LPC17_IOCON_P1,
+  LPC17_IOCON_P2,
+  LPC17_IOCON_P3,
+  LPC17_IOCON_P4,
+  LPC17_IOCON_P5
+}
+
+/* Register offsets */
+
+const uint32_t g_ioconpin[32] =
+{
+  LPC17_IOCON_PP0_OFFSET,
+  LPC17_IOCON_PP1_OFFSET,
+  LPC17_IOCON_PP2_OFFSET,
+  LPC17_IOCON_PP3_OFFSET,
+  LPC17_IOCON_PP4_OFFSET,
+  LPC17_IOCON_PP5_OFFSET,
+  LPC17_IOCON_PP6_OFFSET,
+  LPC17_IOCON_PP7_OFFSET,
+  LPC17_IOCON_PP8_OFFSET,
+  LPC17_IOCON_PP9_OFFSET,
+  LPC17_IOCON_PP10_OFFSET,
+  LPC17_IOCON_PP11_OFFSET,
+  LPC17_IOCON_PP12_OFFSET,
+  LPC17_IOCON_PP13_OFFSET,
+  LPC17_IOCON_PP14_OFFSET,
+  LPC17_IOCON_PP15_OFFSET,
+  LPC17_IOCON_PP16_OFFSET,
+  LPC17_IOCON_PP17_OFFSET,
+  LPC17_IOCON_PP18_OFFSET,
+  LPC17_IOCON_PP19_OFFSET,
+  LPC17_IOCON_PP20_OFFSET,
+  LPC17_IOCON_PP21_OFFSET,
+  LPC17_IOCON_PP22_OFFSET,
+  LPC17_IOCON_PP23_OFFSET,
+  LPC17_IOCON_PP24_OFFSET,
+  LPC17_IOCON_PP25_OFFSET,
+  LPC17_IOCON_PP26_OFFSET,
+  LPC17_IOCON_PP27_OFFSET,
+  LPC17_IOCON_PP28_OFFSET,
+  LPC17_IOCON_PP29_OFFSET,
+  LPC17_IOCON_PP30_OFFSET,
+  LPC17_IOCON_PP31_OFFSET
 };
+#endif
 
 /* Port 0 and Port 2 can provide a single interrupt for any combination of
- * port pins 
+ * port pins
  */
 
-const uint32_t g_intbase[GPIO_NPORTS] = 
+const uint32_t g_intbase[GPIO_NPORTS] =
 {
   LPC17_GPIOINT0_BASE,
   0,
   LPC17_GPIOINT2_BASE,
   0,
   0
+#if GPIO_NPORTS > 5
+  , 0
+#endif
 };
 
-const uint32_t g_lopinsel[GPIO_NPORTS] = 
+const uint32_t g_lopinsel[GPIO_NPORTS] =
 {
   LPC17_PINCONN_PINSEL0,
   LPC17_PINCONN_PINSEL2,
   LPC17_PINCONN_PINSEL4,
   0,
   0
+#if GPIO_NPORTS > 5
+  , 0
+#endif
 };
 
-const uint32_t g_hipinsel[GPIO_NPORTS] = 
+const uint32_t g_hipinsel[GPIO_NPORTS] =
 {
   LPC17_PINCONN_PINSEL1,
   LPC17_PINCONN_PINSEL3,
   0,
   LPC17_PINCONN_PINSEL7,
   LPC17_PINCONN_PINSEL9
+#if GPIO_NPORTS > 5
+  , 0
+#endif
 };
 
 const uint32_t g_lopinmode[GPIO_NPORTS] =
@@ -133,6 +197,9 @@ const uint32_t g_lopinmode[GPIO_NPORTS] =
   LPC17_PINCONN_PINMODE4,
   0,
   0
+#if GPIO_NPORTS > 5
+  , 0
+#endif
 };
 
 const uint32_t g_hipinmode[GPIO_NPORTS] =
@@ -142,6 +209,9 @@ const uint32_t g_hipinmode[GPIO_NPORTS] =
   0,
   LPC17_PINCONN_PINMODE7,
   LPC17_PINCONN_PINMODE9
+#if GPIO_NPORTS > 5
+  , 0
+#endif
 };
 
 const uint32_t g_odmode[GPIO_NPORTS] =
@@ -151,6 +221,9 @@ const uint32_t g_odmode[GPIO_NPORTS] =
   LPC17_PINCONN_ODMODE2,
   LPC17_PINCONN_ODMODE3,
   LPC17_PINCONN_ODMODE4
+#if GPIO_NPORTS > 5
+  , 0
+#endif
 };
 
 /****************************************************************************
@@ -348,6 +421,27 @@ static void lpc17_clropendrain(unsigned int port, unsigned int pin)
 }
 
 /****************************************************************************
+ * Name: lpc17_configiocon
+ *
+ * Description:
+ *   Set the LPC178x IOCON register
+ ****************************************************************************/
+
+#ifdef LPC178x
+static int lpc17_configiocon(unsigned int port, unsigned int pin,
+                             unsigned int value)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+
+  regaddr = (g_ioconbase[port] + g_ioconpin[pin]);
+  regval  = getreg32(regaddr);
+  regval &= value;
+  putreg32(regval, regaddr);
+}
+#endif
+
+/****************************************************************************
  * Name: lpc17_configinput
  *
  * Description:
@@ -361,9 +455,9 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un
   uint32_t fiobase;
   uint32_t intbase;
   uint32_t pinmask = (1 << pin);
- 
+
   /* Set up FIO registers */
-  
+
   fiobase = g_fiobase[port];
 
   /* Set as input */
@@ -378,13 +472,13 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un
   if (intbase != 0)
     {
       /* Disable any rising edge interrupts */
- 
+
       regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
       regval &= ~pinmask;
       putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
 
       /* Disable any falling edge interrupts */
- 
+
       regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
       regval &= ~pinmask;
       putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
@@ -396,6 +490,8 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un
 #endif
     }
 
+#ifdef defined(LPC176x)
+
   /* Set up PINSEL registers */
   /* Configure as GPIO */
 
@@ -408,6 +504,40 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un
   /* Open drain only applies to outputs */
 
   lpc17_clropendrain(port, pin);
+
+#elif defined(LPC178x)
+
+  uint32_t value;
+
+  /* Configure as GPIO */
+
+  if ((cfgset & GPIO_FILTER) != 0)
+    {
+      value = (IOCON_FUNC_GPIO | ~GPIO_IOCON_TYPE_W_MASK);
+    }
+  else
+    {
+      value = (IOCON_FUNC_GPIO | ~GPIO_IOCON_TYPE_D_MASK);
+    }
+
+  /* Set pull-up mode */
+
+  value |= ((cfgset & GPIO_PUMODE_MASK) >> GPIO_PINMODE_SHIFT);
+
+  /* Clear open drain: open drain only applies to outputs */
+
+  value &= ~IOCON_OD_MASK ;
+
+  /* Clear input hysteresis, invertion, slew */
+
+  value &= ~(IOCON_HYS_MASK | IOCON_INV_MASK | IOCON_SLEW_MASK);
+
+  /* Set IOCON register */
+
+  lpc17_configiocon(port, pin, value);
+
+#endif
+
   return OK;
 }
 
@@ -541,7 +671,7 @@ int lpc17_configgpio(lpc17_pinset_t cfgset)
   unsigned int port;
   unsigned int pin;
   int ret = -EINVAL;
- 
+
   /* Verify that this hardware supports the select GPIO port */
 
   port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
@@ -581,6 +711,26 @@ int lpc17_configgpio(lpc17_pinset_t cfgset)
           ret = lpc17_configalternate(cfgset, port, pin, PINCONN_PINSEL_ALT3);
           break;
 
+#ifdef LPC178x
+
+        case GPIO_ALT4:    /* Alternate function 4 */
+          ret =  ;
+          break;
+
+        case GPIO_ALT5:    /* Alternate function 5 */
+          ret =  ;
+          break;
+
+        case GPIO_ALT6:    /* Alternate function 6 */
+          ret =  ;
+          break;
+
+        case GPIO_ALT7:    /* Alternate function 7 */
+          ret =  ;
+          break;
+
+#endif
+
         default:
           break;
         }
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
index 993369aa2..62bf2d018 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -187,19 +187,20 @@
  */
 
 #define GPIO_IOCON_TYPE_D_MASK (0x0000067f) /* All port except where ADC/DAC, USB, I2C is present */
-#define GPIO_IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12 to 13, P0:23 to 26, P1:30 to 31 */
+#define GPIO_IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */
 #define GPIO_IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */
-#define GPIO_IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27 to 28, P5:2 to 3  */
-#define GPIO_IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7 to 9 */
-
-# define GPIO_HYS            (1 << 16) /* Bit 16: HYSTERESIS: 0-Disable, 1-Enabled */
-# define GPIO_INV            (1 << 17) /* Bit 17: Input: 0-Not Inverted, 1-Inverted */
-# define GPIO_SLEW           (1 << 18) /* Bit 18: Rate Control: 0-Standard mode, 1-Fast mode */
-# define GPIO_ADMODE         (1 << 19) /* Bit 19: A/D Modes: 0-Analog, 1-Digital  */
-# define GPIO_FILTER         (1 << 20) /* Bit 20: Filter: 0-Off, 1-ON */
-# define GPIO_DACEN          (1 << 21) /* Bit 21: DAC: 0-Disabled, 1-Enabled, P0:26 only */
-# define GPIO_I2CHS          (1 << 22) /* Bit 22: Filter and Rate Control: 0-Enabled, 1-Disabled */
-# define GPIO_HIDRIVE        (1 << 23) /* Bit 23: Current Sink: 0-4mA, 1-20mA  P5:2 and P5:3 only,*/
+#define GPIO_IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3  */
+#define GPIO_IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
+
+#define GPIO_IOCON_MASK       (0x00FF0000)
+#  define GPIO_HYS            (1 << 16) /* Bit 16: HYSTERESIS: 0-Disable, 1-Enabled */
+#  define GPIO_INV            (1 << 17) /* Bit 17: Input: 0-Not Inverted, 1-Inverted */
+#  define GPIO_SLEW           (1 << 18) /* Bit 18: Rate Control: 0-Standard mode, 1-Fast mode */
+#  define GPIO_ADMODE         (1 << 19) /* Bit 19: A/D Modes: 0-Analog, 1-Digital  */
+#  define GPIO_FILTER         (1 << 20) /* Bit 20: Filter: 0-Off, 1-ON */
+#  define GPIO_DACEN          (1 << 21) /* Bit 21: DAC: 0-Disabled, 1-Enabled, P0:26 only */
+#  define GPIO_I2CHS          (1 << 22) /* Bit 22: Filter and Rate Control: 0-Enabled, 1-Disabled */
+#  define GPIO_HIDRIVE        (1 << 23) /* Bit 23: Current Sink: 0-4mA, 1-20mA  P5:2 and P5:3 only,*/
 
 /* Pin Function bits: FFFF
  * Only meaningful when the GPIO function is GPIO_PIN
@@ -239,12 +240,13 @@
 
 /* Pin Mode: MM */
 
+#define GPIO_PINMODE_SHIFT	 (7)
 #define GPIO_PUMODE_SHIFT    (10)      /* Bits 10-11: Pin pull-up mode */
 #define GPIO_PUMODE_MASK     (3 << GPIO_PUMODE_SHIFT)
-#  define GPIO_PULLUP        (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
-#  define GPIO_REPEATER      (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
-#  define GPIO_FLOAT         (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
-#  define GPIO_PULLDN        (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
+#  define GPIO_FLOAT         (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
+#  define GPIO_PULLDN        (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
+#  define GPIO_PULLUP        (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
+#  define GPIO_REPEATER      (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
 
 /* Open drain: O */
 
@@ -350,6 +352,10 @@ EXTERN const uint32_t g_hipinsel[GPIO_NPORTS];
 EXTERN const uint32_t g_lopinmode[GPIO_NPORTS];
 EXTERN const uint32_t g_hipinmode[GPIO_NPORTS];
 EXTERN const uint32_t g_odmode[GPIO_NPORTS];
+#ifdef LPC178x
+EXTERN const uint32_t g_ioconport[GPIO_NPORTS];
+EXTERN const uint32_t g_ioconpin[32];
+#endif
 
 /****************************************************************************
  * Public Functions