Add LPC43 ADC, DAC, RTC, SPI, I2S, I2C, and QEI header files from LPC17

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4894 42af7a65-404d-4744-a932-0658087f49c3

3 files changed, 14 insertions, 17 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h
index 93a3daad7..6b9a58345 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h
@@ -1,8 +1,8 @@
 /************************************************************************************

  * arch/arm/src/lpc17xx/lpc17_adc.h

  *

- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.

- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <gnutt@nuttx.org>

  *

  * Redistribution and use in source and binary forms, with or without

  * modification, are permitted provided that the following conditions

@@ -51,7 +51,6 @@
 

 /* Register offsets *****************************************************************/

 

-

 #define LPC17_ADC_CR_OFFSET      0x0000  /* A/D Control Register */

 #define LPC17_ADC_GDR_OFFSET     0x0004  /* A/D Global Data Register */

 #define LPC17_ADC_INTEN_OFFSET   0x000c  /* A/D Interrupt Enable Register */

@@ -71,7 +70,6 @@
 

 /* Register addresses ***************************************************************/

 

-

 #define LPC17_ADC_CR             (LPC17_ADC_BASE+LPC17_ADC_CR_OFFSET)

 #define LPC17_ADC_GDR            (LPC17_ADC_BASE+LPC17_ADC_GDR_OFFSET)

 #define LPC17_ADC_INTEN          (LPC17_ADC_BASE+LPC17_ADC_INTEN_OFFSET)

@@ -115,10 +113,10 @@
                                            /* Bits 28-31: Reserved */

 /* A/D Global Data Register AND Channel 0-7 Data Register */

                                            /* Bits 0-3: Reserved */

-#define ADC_DR_RESULT_SHIFT      (4)       /* Bits 4-15: Result of conversion (DONE==1)*/

+#define ADC_DR_RESULT_SHIFT      (4)       /* Bits 4-15: Result of conversion (DONE==1) */

 #define ADC_DR_RESULT_MASK       (0x0fff << ADC_DR_RESULT_SHIFT)

                                            /* Bits 16-23: Reserved */

-#define ADC_DR_CHAN_SHIFT        (24)      /* Bits 24-26: Channel converted*/

+#define ADC_DR_CHAN_SHIFT        (24)      /* Bits 24-26: Channel converted */

 #define ADC_DR_CHAN_MASK         (3 << ADC_DR_CHN_SHIFT)

                                            /* Bits 27-29: Reserved */

 #define ADC_DR_OVERRUN           (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h
index 61651fa95..638d40178 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h
@@ -1,8 +1,8 @@
 /************************************************************************************

  * arch/arm/src/lpc17xx/lpc17_i2s

  *

- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.

- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <gnutt@nuttx.org>

  *

  * Redistribution and use in source and binary forms, with or without

  * modification, are permitted provided that the following conditions

@@ -91,7 +91,7 @@
 #define I2S_DAO_WDWID_MASK          (3 << I2S_DAO_WDWID_SHIFT)

 #  define I2S_DAO_WDWID_8BITS       (0 << I2S_DAO_WDWID_SHIFT)

 #  define I2S_DAO_WDWID_16BITS      (1 << I2S_DAO_WDWID_SHIFT)

-#  define I2S_DAO_WDWID_32BITS      (2 << I2S_DAO_WDWID_SHIFT)

+#  define I2S_DAO_WDWID_32BITS      (3 << I2S_DAO_WDWID_SHIFT)

 #define I2S_DAO_MONO                (1 << 2)  /* Bit 2:  Mono format */

 #define I2S_DAO_STOP                (1 << 3)  /* Bit 3:  Disable FIFOs / mute mode */

 #define I2S_DAO_RESET               (1 << 4)  /* Bit 4:  Reset TX channel and FIFO */

@@ -106,7 +106,7 @@
 #define I2S_DAI_WDWID_MASK          (3 << I2S_DAI_WDWID_SHIFT)

 #  define I2S_DAI_WDWID_8BITS       (0 << I2S_DAI_WDWID_SHIFT)

 #  define I2S_DAI_WDWID_16BITS      (1 << I2S_DAI_WDWID_SHIFT)

-#  define I2S_DAI_WDWID_32BITS      (2 << I2S_DAI_WDWID_SHIFT)

+#  define I2S_DAI_WDWID_32BITS      (3 << I2S_DAI_WDWID_SHIFT)

 #define I2S_DAI_MONO                (1 << 2)  /* Bit 2:  Mono format */

 #define I2S_DAI_STOP                (1 << 3)  /* Bit 3:  Disable FIFOs / mute mode */

 #define I2S_DAI_RESET               (1 << 4)  /* Bit 4:  Reset TX channel and FIFO */

@@ -133,7 +133,7 @@
 

 #define I2S_DMA_RXDMAEN             (1 << 0)  /* Bit 0:  Enable DMA1 for I2S receive */

 #define I2S_DMA_TXDMAEN             (1 << 1)  /* Bit 1:  Enable DMA1 for I2S transmit */

-                                              /* Bits 3-7: Reserved */

+                                              /* Bits 2-7: Reserved */

 #define I2S_DMA_RXDEPTH_SHIFT       (8)       /* Bits 8-11: FIFO level that triggers RX request on DMA1 */

 #define I2S_DMA_RXDEPTH_MASK        (15 << I2S_DMA_RXDEPTH_SHIFT)

                                               /* Bits 12-15: Reserved */

@@ -142,10 +142,9 @@
                                               /* Bits 20-31: Reserved */

 /* Interrupt Request Control Register */

 

-#define I2S_IRQ_

 #define I2S_IRQ_RXEN                (1 << 0)  /* Bit 0:  Enable I2S receive interrupt */

 #define I2S_IRQ_TXEN                (1 << 1)  /* Bit 1:  Enable I2S transmit interrupt */

-                                              /* Bits 3-7: Reserved */

+                                              /* Bits 2-7: Reserved */

 #define I2S_IRQ_RXDEPTH_SHIFT       (8)       /* Bits 8-11: Set FIFO level for irq request */

 #define I2S_IRQ_RXDEPTH_MASK        (15 << I2S_IRQ_RXDEPTH_SHIFT)

                                               /* Bits 12-15: Reserved */

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h
index e92ada029..195e403c1 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h
@@ -1,8 +1,8 @@
 /************************************************************************************

  * arch/arm/src/lpc17xx/lpc17_rtc.h

  *

- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.

- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <gnutt@nuttx.org>

  *

  * Redistribution and use in source and binary forms, with or without

  * modification, are permitted provided that the following conditions

@@ -222,7 +222,7 @@
 #define RTC_CTIME1_YEAR_SHIFT   (16)      /* Bits 16-27: Year */

 #define RTC_CTIME1_YEAR_MASK    (0x0fff << RTC_CTIME1_YEAR_SHIFT)

                                           /* Bits 28-31: Reserved */

-/* Consolidated Time Register 2 (Shouldn't DOY width be 9 bits?) */

+/* Consolidated Time Register 2 */

 

 #define RTC_CTIME2_DOY_SHIFT    (0)       /* Bits 0-11: Day of Year */

 #define RTC_CTIME2_DOY_MASK     (0x0fff << RTC_CTIME2_DOY_SHIFT)

@@ -243,7 +243,7 @@
 #define RTC_CALIB_CALVAL_SHIFT  (0)       /* Bits 0-16: calibration counter counts to this value */

 #define RTC_CALIB_CALVAL_MASK   (0xffff << RTC_CALIB_CALVAL_SHIFT)

 #define RTC_CALIB_CALDIR        (1 << 17) /* Bit 17: Calibration direction */

-                                          /* Bits 12-31: Reserved */

+                                          /* Bits 18-31: Reserved */

 /* Alarm register group */

 

 #define RTC_ALSEC_MASK          (0x003f)