Make number of user endpoints configurable

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3196 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 417 insertions, 119 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
index 5bf482799..4507679a5 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
@@ -51,6 +51,7 @@
 
 #include "lpc17_memorymap.h"
 #include "lpc17_emacram.h"
+#include "lpc17_ohciram.h"
 
 /****************************************************************************
  * Private Definitions
@@ -79,25 +80,88 @@
 #  warning "CONFIG_DRAM_END is before end of CPU SRAM... not all of CPU SRAM used"
 #endif
 
-/* Sanity checking */
+/* Figure out how much heap be have in AHB SRAM (if any).  Complications:
+ * 1) AHB SRAM Bank 0 or 1 may on may not be supported in the hardware.
+ * 2) Some or all of Bank 0 may be used for Ethernet Packet buffering.
+ *    Ethernet packet buffering is used from the beginning of Bank 0 and
+ *    any free memory at the end of Bank 0 will be contiguous with any
+ *    free memory at the beginning of Bank 1.
+ * 3) Some or all of Bank 1 may be used for OHCI descriptor memory.  OCHI
+ *    memory is used from the end of Bank 1 and any free memory at the
+ *    beginning of Bank 1 will be contiguous with any free memory at the
+ *    end of Bank 0.
+ */
+
+#undef LPC17_AHB_HEAPBASE /* Assume that nothing is available */
+#undef LPC17_AHB_HEAPSIZE
+
+/* If we have Bank 0, then we may possibly also have Bank 1 */
 
 #ifdef LPC17_HAVE_BANK0
-#  if defined(LPC17_BANK0_HEAPSIZE) || defined(LPC17_HAVE_BANK1)
-#    if CONFIG_MM_REGIONS < 2
-#      warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank(s) not included in HEAP"
-#    endif
-#    if CONFIG_MM_REGIONS > 2
-#      warning "CONFIG_MM_REGIONS > 2: Additional regions handled by application?"
-#    endif
-#  else
-#    if CONFIG_MM_REGIONS > 1
-#      warning "CONFIG_MM_REGIONS > 1: This MCU has no available AHB SRAM Bank0/1"
-#    endif
+
+  /* We have BANK0 (and, hence, possibly Bank1).  Is Bank0 all used for
+   * Ethernet packet buffering?  Or is there any part of Bank0 available for
+   * the heap.
+   */
+
+#  ifdef LPC17_BANK0_HEAPSIZE
+
+     /* Some or all of Bank0 is available for the heap.  The heap will begin
+      * in bank 1.
+      */
+
+#     define LPC17_AHB_HEAPBASE LPC17_BANK0_HEAPBASE
+
+     /* Is Bank1 present? Has there available heap memory in Bank 1? */
+
+#    if defined(LPC17_HAVE_BANK1) && defined(LPC17_BANK1_HEAPSIZE)
+
+       /* Yes... the heap space available is the unused memory at the end
+        * of Bank0 plus the unused memory at the beginning of Bank 1.
+        */
+
+#       define LPC17_AHB_HEAPSIZE (LPC17_BANK0_HEAPSIZE + LPC17_BANK1_HEAPSIZE)
+#    else
+
+        /* No... the heap space available is only the unused memory at the
+         * end of Bank 0.
+         */
+
+#       define LPC17_AHB_HEAPSIZE LPC17_BANK0_HEAPSIZE
+
+#    endif /* LPC17_HAVE_BANK1 && LPC17_BANK1_HEAPSIZE */
+#  else /* !LPC17_BANK0_HEAPSIZE */
+
+     /* We have Bnak 0, but no memory is available for the heap there.
+      * Do we have Bank 1? Is any heap memory available in Bank 1?
+      */
+
+#    if defined(LPC17_HAVE_BANK1) && defined(LPC17_BANK1_HEAPSIZE)
+
+       /* Yes... the heap space available is the unused memory at the
+        * beginning of Bank1.
+        */
+
+#      define LPC17_AHB_HEAPBASE LPC17_BANK1_HEAPBASE
+#      define LPC17_AHB_HEAPSIZE LPC17_BANK1_HEAPSIZE
+
+#    endif /* LPC17_HAVE_BANK1 && LPC17_BANK1_HEAPSIZE */
+#  endif /* LPC17_BANK0_HEAPSIZE */
+#endif /* LPC17_HAVE_BANK0 */
+
+/* Sanity checking */
+
+#ifdef LPC17_AHB_HEAPBASE
+#  if CONFIG_MM_REGIONS < 2
+#    warning "CONFIG_MM_REGIONS < 2: Available AHB SRAM Bank(s) not included in HEAP"
+#  endif
+#  if CONFIG_MM_REGIONS > 2
+#    warning "CONFIG_MM_REGIONS > 2: Are additional regions handled by application?"
 #  endif
 #else
 #  if CONFIG_MM_REGIONS > 1
-#    warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0/1"
-#    warning "                       Other memory regions handled by application?"
+#    warning "CONFIG_MM_REGIONS > 1: This configuration has no available AHB SRAM Bank0/1"
+#    warning "CONFIG_MM_REGIONS > 1: Are additional regions handled by application?"
 #  endif
 #endif
 
@@ -147,43 +211,19 @@ void up_addregion(void)
    * contiguous 32Kb memory region.
    *
    * If Ethernet is enabled, it will take some or all of bank 0 for packet
-   * buffering and descriptor tables.
-   */
-
-#ifdef LPC17_HAVE_BANK0
-
-  /* We have BANK0 (and, hence, possibly Bank1).  Is Bank0 all used for
-   * Ethernet packet buffering?  Or is there any part of Bank0 available for
-   * the heap.
-   */
-
-# ifdef LPC17_BANK0_HEAPSIZE
-
-  /* Some or all of Bank0 is available for the heap.  Is Bank1 present? */
-
-#  ifdef LPC17_HAVE_BANK1
-
-  /* Yes... the heap space available is the unused memory at the end of
-   * Bank0 plus all of Bank1.
+   * buffering and descriptor tables; If USB host is enabled, it will take
+   * some or all of bank 1 for descriptor memory.  The complex conditional
+   * compilation above should boil this all down to a very simple check
+   * here:
+   *
+   * Is any memory available in AHB SRAM for the heap?
    */
 
-   mm_addregion((FAR void*)LPC17_BANK0_HEAPBASE, LPC17_BANK0_HEAPSIZE+LPC17_BANK1_SIZE);
-#  else
-
-   /* No... only the unused memory at the end of Bank0 is available for the
-    * heap/
-    */
+#ifdef LPC17_AHB_HEAPBASE
 
-   mm_addregion((FAR void*)LPC17_BANK0_HEAPBASE, LPC17_BANK0_HEAPSIZE);
-#  endif
-# else
+  /* Yes... Add the AHB SRAM heap region. */
 
-  /* Nothing is available in Bank0.  Is Bank1 available? */
-
-#  ifdef LPC17_HAVE_BANK1
-   mm_addregion((FAR void*)LPC17_SRAM_BANK1, LPC17_BANK1_SIZE);
-#  endif
-# endif
+   mm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
 #endif
 }
 #endif
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h b/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h
index 3759ccb9e..98eaa91b9 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h
@@ -101,7 +101,7 @@
 #  error "EMAC RAM size must be in multiples of 32-bit words"

 #endif

 

-/* Determine is there is any meaning space left at the end of AHB Bank 0 that

+/* Determine is there is any meaningful space left at the end of AHB Bank 0 that

  * could be added to the heap.

  */

 

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h
new file mode 100755
index 000000000..453c55d7a
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h
@@ -0,0 +1,221 @@
+/************************************************************************************

+ * arch/arm/src/lpc17xx/lpc17_ohciram.h

+ *

+ *   Copyright (C) 2010 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions

+ * are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright

+ *    notice, this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright

+ *    notice, this list of conditions and the following disclaimer in

+ *    the documentation and/or other materials provided with the

+ *    distribution.

+ * 3. Neither the name NuttX nor the names of its contributors may be

+ *    used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ ************************************************************************************/

+

+#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H

+#define __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H

+

+/************************************************************************************

+ * Included Files

+ ************************************************************************************/

+

+#include <nuttx/config.h>

+#include "chip.h"

+#include "lpc17_memorymap.h"

+

+/************************************************************************************

+ * Pre-processor Definitions

+ ************************************************************************************/

+/* Default, no-OHCI Case ************************************************************/

+/* Assume that all of AHB SRAM will be available for heap. If this is not true, then

+ * LPC17_BANK1_HEAPSIZE will be undefined but redefined below.

+ */

+

+#undef LPC17_BANK1_HEAPBASE

+#undef LPC17_BANK1_HEAPSIZE

+#ifdef LPC17_HAVE_BANK1

+#  define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1

+#  define LPC17_BANK1_HEAPSIZE LPC17_BANK1_SIZE

+#endif

+

+/* Is networking enabled?  Is the LPC17xx Ethernet device enabled? Does this chip have

+ * and Ethernet controlloer?  Yes... then we will replace the above default definitions.

+ */

+

+#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_USBHOST) && LPC17_NUSBHOST > 0

+

+/* OHCI RAM Configuration ***********************************************************/

+/* Is AHB SRAM available? */

+

+#ifndef LPC17_HAVE_BANK1

+#  error "AHB SRAM Bank1 is not available for OHCI RAM"

+#endif

+

+/* OHCI/Heap Memory Allocation ******************************************************/

+/* Configured Size of the region at the end of AHB SRAM BANK1 set set aside for the

+ * OHCI. This size must fit within AHB SRAM Bank 1 and also be a multiple of 256

+ * bytes.

+ */

+

+#ifndef CONFIG_USBHOST_OHCIRAM_SIZE

+#  define CONFIG_USBHOST_OHCIRAM_SIZE LPC17_BANK1_SIZE

+#endif

+

+#if CONFIG_USBHOST_OHCIRAM_SIZE > LPC17_BANK1_SIZE

+#  error "OHCI RAM size cannot exceed the size of AHB SRAM Bank 1"

+#endif

+

+#if (CONFIG_USBHOST_OHCIRAM_SIZE & 0xff) != 0

+#  error "OHCI RAM size must be in multiples of 256 bytes"

+#endif

+

+/* Then position the OHCI RAM at the end of AHB SRAM Bank 1 */

+

+#define LPC17_OHCIRAM_END  (LPC17_SRAM_BANK1 + LPC17_BANK1_SIZE)

+#define LPC17_OHCIRAM_BASE (LPC17_OHCIRAM_END - CONFIG_USBHOST_OHCIRAM_SIZE)

+#define LPC17_OHCIRAM_SIZE  CONFIG_USBHOST_OHCIRAM_SIZE

+

+/* Determine is there is any meaningful space left at the beginning of AHB Bank 1

+ * that could be added to the heap.

+ */

+

+#undef LPC17_BANK1_HEAPBASE

+#undef LPC17_BANK1_HEAPSIZE

+#if LPC17_OHCIRAM_SIZE < (LPC17_BANK1_SIZE-128)

+#  define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1

+#  define LPC17_BANK1_HEAPSIZE (LPC17_BANK1_SIZE - LPC17_OHCIRAM_SIZE)

+#endif

+

+/* Numbers and Sizes of Things ******************************************************/

+/* Fixed size of the OHCI control area */

+

+#define LPC17_HCCA_SIZE 256

+

+/* Fixed endpoint and transfer descriptor sizes */

+

+#define LPC17_TD_SIZE   16

+#define LPC17_ED_SIZE   16

+

+/* Configurable number of user endpoint descriptors (EDs).  This number excludes

+ * the control endpoint that is always allocated.

+ */

+

+#ifndef CONFIG_USBHOST_NEDS

+#  define CONFIG_USBHOST_NEDS 2

+#endif

+

+/* Derived size of user endpoint descriptor (ED) memory. */

+

+#define LPC17_FREEED_SIZE (CONFIG_USBHOST_NEDS * LPC17_ED_SIZE)

+

+/* Configurable number of descriptor buffer (TDBUFFER) */

+

+#ifndef CONFIG_USBHOST_TDBUFFERS

+#  define CONFIG_USBHOST_TDBUFFERS 1

+#endif

+

+#if CONFIG_USBHOST_TDBUFFERS < 1

+#  error "At least one TD buffer is required"

+#endif

+

+/* Configurable size of a TD buffer */

+

+#if CONFIG_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_USBHOST_TDBUFSIZE)

+#  define CONFIG_USBHOST_TDBUFSIZE 128

+#endif

+#define LPC17_TDBUFFER_SIZE (CONFIG_USBHOST_TDBUFFERS * CONFIG_USBHOST_TDBUFSIZE)

+

+/* Configurable size of an IO buffer.  The number of IO buffers will be determined

+ * by what is left at the end of the BANK1 memory setup aside of OHCI RAM.

+ */

+

+#ifndef CONFIG_USBHOST_IOBUFSIZE

+#  define CONFIG_USBHOST_IOBUFSIZE 512

+#endif

+

+/* OHCI Memory Layout ***************************************************************/

+/* Example:

+ *  Hardware:

+ *    LPC17_SRAM_BANK1            0x20008000

+ *    LPC17_BANK1_SIZE            16384

+ *

+ *  Configuration:

+ *    CONFIG_USBHOST_OHCIRAM_SIZE 1024

+ *    CONFIG_USBHOST_NTDS         1

+ *    CONFIG_USBHOST_NEDS         2

+ *    CONFIG_USBHOST_TDBUFFERS    1

+ *    CONFIG_USBHOST_TDBUFSIZE    128

+ *    CONFIG_USBHOST_IOBUFSIZE    512

+ *

+ *  Sizes of things

+ *    CONFIG_USBHOST_NEDS         2

+ *    LPC17_FREEED_SIZE           48

+ *    LPC17_TDBUFFER_SIZE         128

+ *    LPC17_TDBUFFER_SIZE         512

+ *

+ *  Memory Layout

+ *    LPC17_OHCIRAM_END          (0x20008000 + 16384) = 0x2000c000

+ *    LPC17_OHCIRAM_BASE         (0x2000c000 - 1024) = 0x2000bc00

+ *    LPC17_OHCIRAM_SIZE          1024

+ *    LPC17_BANK1_HEAPBASE        0x20008000

+ *    LPC17_BANK1_HEAPSIZE       (16384 - 1024) = 15360

+ *

+ *    LPC17_HCCA_BASE             0x2000bc00

+ *    LPC17_TDHEAD_ADDR           0x2000bd00

+ *    LPC17_TDTAIL_ADDR           0x2000bd10

+ *    LPC17_EDCTRL_ADDR           0x2000bd20

+ *    LPC17_FREEED_BASE           0x2000bd30

+ *    LPC17_TDBUFFER_BASE         0x2000bd50

+ *    LPC17_IOBUFFER_BASE         0x2000bdd0

+ *    LPC17_IOBUFFERS            (0x2000c000 + 0x2000bdd0) / 512 = 560/512 = 1

+ *

+ *  Wasted memory:                560-512 = 48 bytes

+ */

+

+#define LPC17_HCCA_BASE     (LPC17_OHCIRAM_BASE)

+#define LPC17_TDHEAD_ADDR   (LPC17_OHCIRAM_BASE + LPC17_HCCA_SIZE)

+#define LPC17_TDTAIL_ADDR   (LPC17_TDHEAD_ADDR + LPC17_TD_SIZE)

+#define LPC17_EDCTRL_ADDR   (LPC17_TDTAIL_ADDR + LPC17_TD_SIZE)

+#define LPC17_FREEED_BASE   (LPC17_EDCTRL_ADDR + LPC17_ED_SIZE)

+#define LPC17_TDBUFFER_BASE (LPC17_FREEED_BASE + LPC17_FREEED_SIZE)

+#define LPC17_IOBUFFER_BASE (LPC17_TDBUFFER_BASE + LPC17_TDBUFFER_SIZE)

+

+/* Finally, use the remainder of the allocated OHCI for IO buffers */

+

+#define LPC17_IOBUFFERS     ((LPC17_OHCIRAM_END - LPC17_IOBUFFER_BASE) / CONFIG_USBHOST_IOBUFSIZE)

+

+/************************************************************************************

+ * Public Types

+ ************************************************************************************/

+

+/************************************************************************************

+ * Public Data

+ ************************************************************************************/

+

+/************************************************************************************

+ * Public Functions

+ ************************************************************************************/

+

+#endif /* CONFIG_USBHOST && CONFIG_LPC17_USBHOST && LPC17_NUSBHOST > 0*/

+#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H */

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c b/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c
index 026db2815..1f6552a4a 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -64,6 +64,7 @@
 #include "lpc17_internal.h"
 #include "lpc17_usb.h"
 #include "lpc17_syscon.h"
+#include "lpc17_ohciram.h"
 
 /*******************************************************************************
  * Definitions
@@ -94,8 +95,15 @@
 
 /* USB Host Memory *************************************************************/
 
-#warning "Needs to be removed from the heap in lpc17_allocateheap.c"
-#define USBHOST_SRAM_BASE LPC17_SRAM_BANK1
+/* Helper definitions */
+
+#define HCCA        ((volatile struct lpc17_hcca_s *)LPC17_HCCA_BASE)
+#define TDHEAD      ((volatile struct lpc17_hctd_s *)LPC17_TDHEAD_ADDR)
+#define TDTAIL      ((volatile struct lpc17_hctd_s *)LPC17_TDTAIL_ADDR)
+#define EDCTRL      ((volatile struct lpc17_hced_s *)LPC17_EDCTRL_ADDR)
+#define FREEEDS     ((volatile struct lpc17_hced_s *)LPC17_FREEED_BASE)
+
+#define TDBuffer    ((volatile uint8_t *)(LPC17_TDBUFFER_BASE)
 
 /* Debug ***********************************************************************/
 
@@ -125,46 +133,44 @@ struct lpc17_usbhost_s
   struct usbhost_class_s *class;
 };
 
-/* HostController EndPoint Descriptor */
+/* Host Controller Communication Area */
 
-struct usbhost_hced_s
+struct lpc17_hcca_s
 {
-  volatile  uint32_t  control;         /* Endpoint descriptor control */
-  volatile  uint32_t  tailtd;          /* Physical address of tail in Transfer descriptor list */
-  volatile  uint32_t  headtd;          /* Physical address of head in Transfer descriptor list */
-  volatile  uint32_t  hext;            /* Physical address of next Endpoint descriptor */
+  volatile  uint32_t  inttbl[32];       /* Interrupt table */
+  volatile  uint32_t  frameno;          /* Frame number */
+  volatile  uint32_t  donehead;         /* Done head */
+  volatile  uint8_t   reserved[116];    /* Reserved for future use */
+  volatile  uint8_t   unused[4];        /* Unused */
 };
 
 /* HostController Transfer Descriptor */
 
-struct usbhost_hctd_s
+struct lpc17_hctd_s
 {                       
-  volatile  uint32_t  control;         /* Transfer descriptor control */
-  volatile  uint32_t  currbufptr;      /* Physical address of current buffer pointer */
-  volatile  uint32_t  bext;            /* Physical pointer to next Transfer Descriptor */
+  volatile  uint32_t  ctrl;            /* Transfer descriptor control */
+  volatile  uint32_t  currptr;         /* Physical address of current buffer pointer */
+  volatile  uint32_t  next;            /* Physical pointer to next Transfer Descriptor */
   volatile  uint32_t  bufend;          /* Physical address of end of buffer */
 };
 
-/* Host Controller Communication Area */
+/* HostController EndPoint Descriptor */
 
-struct usbhost_hcca_s
+struct lpc17_hced_s
 {
-  volatile  uint32_t  inttable[32];     /* Interrupt table */
-  volatile  uint32_t  framenumber;      /* Frame number */
-  volatile  uint32_t  donehead;         /* Done head */
-  volatile  uint8_t   reserved[116];    /* Reserved for future use */
-  volatile  uint8_t   unknown[4];       /* Unused */
+  volatile  uint32_t  ctrl;            /* Endpoint descriptor control */
+  volatile  uint32_t  tailtd;          /* Physical address of tail in Transfer descriptor list */
+  volatile  uint32_t  headtd;          /* Physical address of head in Transfer descriptor list */
+  volatile  uint32_t  next;            /* Physical address of next Endpoint descriptor */
 };
 
-/* Helper definitions */
+/* The following is used manage a list of free EDs */
 
-#define Hcca        ((volatile struct usbhost_hcca_s *)(USBHOST_SRAM_BASE + 0x000))
-#define TDHead      ((volatile struct usbhost_hctd_s *)(USBHOST_SRAM_BASE + 0x100))
-#define TDTail      ((volatile struct usbhost_hctd_s *)(USBHOST_SRAM_BASE + 0x110))
-#define EDCtrl      ((volatile struct usbhost_hced_s *)(USBHOST_SRAM_BASE + 0x120))
-#define EDBulkIn    ((volatile struct usbhost_hced_s *)(USBHOST_SRAM_BASE + 0x130))
-#define EDBulkOut   ((volatile struct usbhost_hced_s *)(USBHOST_SRAM_BASE + 0x140))
-#define TDBuffer    ((volatile uint8_t *)(USBHOST_SRAM_BASE + 0x150))
+struct lpc17_edmem_s
+{
+  struct lpc17_edmem_s *flink;         /* Link to next ED in the list */
+  uint32_t              pad[3];        /* To make the same size as struct lpc17_hced_s */
+};
 
 /*******************************************************************************
  * Private Function Prototypes
@@ -188,22 +194,22 @@ static int lpc17_usbinterrupt(int irq, FAR void *context);
 
 /* USB host controller operations **********************************************/
 
-static int usbhost_enumerate(FAR struct usbhost_driver_s *drvr);
-static int usbhost_alloc(FAR struct usbhost_driver_s *drvr,
+static int lpc17_enumerate(FAR struct usbhost_driver_s *drvr);
+static int lpc17_alloc(FAR struct usbhost_driver_s *drvr,
                          FAR uint8_t **buffer, FAR size_t *maxlen);
-static int usbhost_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer);
-static int usbhost_control(FAR struct usbhost_driver_s *drvr,
+static int lpc17_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer);
+static int lpc17_control(FAR struct usbhost_driver_s *drvr,
                            const struct usb_ctrlreq_s *req, FAR uint8_t *buffer);
-static int usbhost_transfer(FAR struct usbhost_driver_s *drvr,
+static int lpc17_transfer(FAR struct usbhost_driver_s *drvr,
                             FAR struct usbhost_epdesc_s *ed,
                             FAR uint8_t *buffer, size_t buflen);
-static void usbhost_disconnect(FAR struct usbhost_driver_s *drvr);
+static void lpc17_disconnect(FAR struct usbhost_driver_s *drvr);
   
 /* Initializaion ***************************************************************/
 
-static void usbhost_tdinit(volatile struct usbhost_hctd_s *td);
-static void usbhost_edinit(volatile struct usbhost_hced_s *ed);
-static void usbhost_hccainit(volatile struct usbhost_hcca_s *hcca);
+static void lpc17_tdinit(volatile struct lpc17_hctd_s *td);
+static void lpc17_edinit(volatile struct lpc17_hced_s *ed);
+static void lpc17_hccainit(volatile struct lpc17_hcca_s *hcca);
 
 /*******************************************************************************
  * Private Data
@@ -218,16 +224,20 @@ static struct lpc17_usbhost_s g_usbhost =
 {
   .usbhost        =
     {
-      .enumerate  = usbhost_enumerate,
-      .alloc      = usbhost_alloc,
-      .free       = usbhost_free,
-      .control    = usbhost_control,
-      .transfer   = usbhost_transfer,
-      .disconnect = usbhost_disconnect,
+      .enumerate  = lpc17_enumerate,
+      .alloc      = lpc17_alloc,
+      .free       = lpc17_free,
+      .control    = lpc17_control,
+      .transfer   = lpc17_transfer,
+      .disconnect = lpc17_disconnect,
     },
   .class          = NULL,
 };
 
+/* This is a free list of EDs */
+
+static struct lpc17_edmem_s *g_freeeds;
+
 /*******************************************************************************
  * Public Data
  *******************************************************************************/
@@ -383,7 +393,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
  *******************************************************************************/
 
 /************************************************************************************
- * Name: usbhost_enumerate
+ * Name: lpc17_enumerate
  *
  * Description:
  *   Enumerate the connected device.  This function will enqueue the
@@ -409,14 +419,14 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
  *
  ************************************************************************************/
 
-static int usbhost_enumerate(FAR struct usbhost_driver_s *drvr)
+static int lpc17_enumerate(FAR struct usbhost_driver_s *drvr)
 {
 # warning "Not Implemented"
   return -ENOSYS;
 }
 
 /************************************************************************************
- * Name: usbhost_alloc
+ * Name: lpc17_alloc
  *
  * Description:
  *   Some hardware supports special memory in which transfer descriptors can
@@ -441,15 +451,15 @@ static int usbhost_enumerate(FAR struct usbhost_driver_s *drvr)
  *
  ************************************************************************************/
 
- static int usbhost_alloc(FAR struct usbhost_driver_s *drvr,
-                         FAR uint8_t **buffer, FAR size_t *maxlen)
+ static int lpc17_alloc(FAR struct usbhost_driver_s *drvr,
+                        FAR uint8_t **buffer, FAR size_t *maxlen)
 {
 # warning "Not Implemented"
   return -ENOSYS;
 }
 
 /************************************************************************************
- * Name: usbhost_free
+ * Name: lpc17_free
  *
  * Description:
  *   Some hardware supports special memory in which transfer descriptors can
@@ -471,14 +481,14 @@ static int usbhost_enumerate(FAR struct usbhost_driver_s *drvr)
  *
  ************************************************************************************/
 
-static int usbhost_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
+static int lpc17_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
 {
 # warning "Not Implemented"
   return -ENOSYS;
 }
 
 /************************************************************************************
- * Name: usbhost_control
+ * Name: lpc17_control
  *
  * Description:
  *   Enqueue a request on the control endpoint.  This method will enqueue
@@ -507,15 +517,15 @@ static int usbhost_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer)
  *
  ************************************************************************************/
 
-static int usbhost_control(FAR struct usbhost_driver_s *drvr,
-                           const struct usb_ctrlreq_s *req, FAR uint8_t *buffer)
+static int lpc17_control(FAR struct usbhost_driver_s *drvr,
+                         const struct usb_ctrlreq_s *req, FAR uint8_t *buffer)
 {
 # warning "Not Implemented"
   return -ENOSYS;
 }
 
 /************************************************************************************
- * Name: usbhost_transfer
+ * Name: lpc17_transfer
  *
  * Description:
  *   Enqueue a request to handle a transfer descriptor.  This method will
@@ -544,16 +554,16 @@ static int usbhost_control(FAR struct usbhost_driver_s *drvr,
  *
  ************************************************************************************/
 
-static int usbhost_transfer(FAR struct usbhost_driver_s *drvr,
-                            FAR struct usbhost_epdesc_s *ed,
-                            FAR uint8_t *buffer, size_t buflen)
+static int lpc17_transfer(FAR struct usbhost_driver_s *drvr,
+                          FAR struct usbhost_epdesc_s *ed,
+                          FAR uint8_t *buffer, size_t buflen)
 {
 # warning "Not Implemented"
   return -ENOSYS;
 }
 
 /************************************************************************************
- * Name: usbhost_disconnect
+ * Name: lpc17_disconnect
  *
  * Description:
  *   Called by the class when an error occurs and driver has been disconnected.
@@ -574,7 +584,7 @@ static int usbhost_transfer(FAR struct usbhost_driver_s *drvr,
  *
  ************************************************************************************/
 
-static void usbhost_disconnect(FAR struct usbhost_driver_s *drvr)
+static void lpc17_disconnect(FAR struct usbhost_driver_s *drvr)
 {
 # warning "Not Implemented"
 }
@@ -583,19 +593,33 @@ static void usbhost_disconnect(FAR struct usbhost_driver_s *drvr)
  * Initialization
  *******************************************************************************/
 
-static void usbhost_tdinit(volatile struct usbhost_hctd_s *td)
+static void lpc17_tdinit(volatile struct lpc17_hctd_s *td)
 {
-# warning "Not Implemented"
+  td->ctrl    = 0;
+  td->currptr = 0;
+  td->next    = 0;
+  td->bufend  = 0;
 }
 
-static void usbhost_edinit(volatile struct usbhost_hced_s *ed)
+static void lpc17_edinit(volatile struct lpc17_hced_s *ed)
 {
-# warning "Not Implemented"
+  ed->ctrl    = 0;
+  ed->tailtd  = 0;
+  ed->headtd  = 0;
+  ed->next    = 0;
 }
 
-static void usbhost_hccainit(volatile struct usbhost_hcca_s *hcca)
+static void lpc17_hccainit(volatile struct lpc17_hcca_s *hcca)
 {
-# warning "Not Implemented"
+  int  i;
+
+  for (i = 0; i < 32; i++)
+    {
+      hcca->inttbl[i] = 0;
+    }
+
+  hcca->frameno   = 0;
+  hcca->donehead  = 0;
 }
 
 /*******************************************************************************
@@ -662,12 +686,25 @@ void up_usbhostinitialize(void)
 
   /* Initialize all the TDs, EDs and HCCA to 0 */
 
-  usbhost_edinit(EDCtrl);
-  usbhost_edinit(EDBulkIn);
-  usbhost_edinit(EDBulkOut);
-  usbhost_tdinit(TDHead);
-  usbhost_tdinit(TDTail);
-  usbhost_hccainit(Hcca);
+  lpc17_hccainit(HCCA);
+  lpc17_tdinit(TDHEAD);
+  lpc17_tdinit(TDTAIL);
+  lpc17_edinit(EDCTRL);
+
+  for (i = 0; i < CONFIG_USBHOST_NEDS; i++)
+    {
+      struct lpc17_edmem_s *freeed;
+
+      /* Initialize the ED */
+
+      lpc17_edinit(&FREEEDS[i]);
+
+      /* Put the ED in a free list */
+
+      freeed        = (struct lpc17_edmem_s *)&FREEEDS[i];
+      freeed->flink = g_freeeds;
+      g_freeeds     = freeed;
+    }
 
   /* Wait 50MS then perform hardware reset */
 
@@ -698,7 +735,7 @@ void up_usbhostinitialize(void)
 
   /* Set HCCA base address */
 
-  lpc17_putreg((uint32_t)Hcca, LPC17_USBHOST_HCCA);
+  lpc17_putreg((uint32_t)HCCA, LPC17_USBHOST_HCCA);
 
   /* Clear pending interrupts */