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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-08-05 21:57:49 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-08-05 21:57:49 +0000 |
| commit | dc0299c4649815ba8b5740fc8b211dad1d7bc3bd (patch) | |
| tree | aad85b8a93bf5ca1c243fb8ec154dd7c0e0ccd2e /nuttx/arch/arm/src/lpc17xx | |
| parent | 8f0b435a518c39a6141bbf888aa4bcd879808d44 (diff) | |
| download | px4-nuttx-dc0299c4649815ba8b5740fc8b211dad1d7bc3bd.tar.gz px4-nuttx-dc0299c4649815ba8b5740fc8b211dad1d7bc3bd.tar.bz2 px4-nuttx-dc0299c4649815ba8b5740fc8b211dad1d7bc3bd.zip | |
Name change: Change Cortex-M3 naming to ARMv7-M naming so support Cortex-M4
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3846 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lpc17xx')
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_irq.c | 4 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index cf3467833..577ec6747 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -308,7 +308,7 @@ void up_irqinitialize(void) * Fault handler. */ -#ifdef CONFIG_CORTEXM3_MPU +#ifdef CONFIG_ARMV7M_MPU irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); up_enable_irq(LPC17_IRQ_MEMFAULT); #endif @@ -317,7 +317,7 @@ void up_irqinitialize(void) #ifdef CONFIG_DEBUG irq_attach(LPC17_IRQ_NMI, lpc17_nmi); -#ifndef CONFIG_CORTEXM3_MPU +#ifndef CONFIG_ARMV7M_MPU irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); #endif irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h index 59a6fd51e..da69f1481 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h @@ -61,7 +61,7 @@ # define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
-#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
+#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define LPC17_SCS_BASE 0xe000e000
#define LPC17_DEBUGMCU_BASE 0xe0042000
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