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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-04-29 21:29:30 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2007-04-29 21:29:30 +0000 |
| commit | 6463ba69dad3e46bde7b61c0d31262fd26a954b8 (patch) | |
| tree | 5e00202991a2ea33cf79ac787e6c28c209bcae66 /nuttx/arch/arm/src/lpc214x/Startup.s | |
| parent | d712452b2adfbdd2b6aaee11e88b176f8911d718 (diff) | |
| download | px4-nuttx-6463ba69dad3e46bde7b61c0d31262fd26a954b8.tar.gz px4-nuttx-6463ba69dad3e46bde7b61c0d31262fd26a954b8.tar.bz2 px4-nuttx-6463ba69dad3e46bde7b61c0d31262fd26a954b8.zip | |
Initial lpc214x support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@193 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lpc214x/Startup.s')
| -rw-r--r-- | nuttx/arch/arm/src/lpc214x/Startup.s | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/lpc214x/Startup.s b/nuttx/arch/arm/src/lpc214x/Startup.s new file mode 100644 index 000000000..ecf692747 --- /dev/null +++ b/nuttx/arch/arm/src/lpc214x/Startup.s @@ -0,0 +1,80 @@ +/*
+ * The STARTUP.S code is executed after CPU Reset. This file may be
+ * translated with the following SET symbols. In uVision these SET
+ * symbols are entered under Options - ASM - Set.
+ *
+ * REMAP: when set the startup code initializes the register MEMMAP
+ * which overwrites the settings of the CPU configuration pins. The
+ * startup and interrupt vectors are remapped from:
+ * 0x00000000 default setting (not remapped)
+ * 0x80000000 when EXTMEM_MODE is used
+ * 0x40000000 when RAM_MODE is used
+ *
+ * EXTMEM_MODE: when set the device is configured for code execution
+ * from external memory starting at address 0x80000000. The startup
+ * vectors are located to 0x80000000.
+ *
+ * RAM_MODE: when set the device is configured for code execution
+ * from on-chip RAM starting at address 0x40000000. The startup
+ * vectors are located to 0x40000000.
+ */
+
+Reset_Handler:
+
+
+
+/* Memory Mapping */
+
+
+/* Setup Stack for each mode */
+ ldr r0, =Top_Stack
+
+/* Enter Undefined Instruction Mode and set its Stack Pointer */
+ msr CPSR_c, #UND_MODE | PSR_I_BIT | PSR_F_BIT
+ mov SP, r0
+ sub r0, r0, #UND_Stack_Size
+
+/* Enter Abort Mode and set its Stack Pointer */
+ msr CPSR_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT
+ mov SP, r0
+ sub r0, r0, #ABT_Stack_Size
+
+/* Enter FIQ Mode and set its Stack Pointer */
+ msr CPSR_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+ mov SP, r0
+ sub r0, r0, #FIQ_Stack_Size
+
+/* Enter IRQ Mode and set its Stack Pointer */
+ msr CPSR_c, #IRQ_MODE | PSR_I_BIT | PSR_F_BIT
+ mov SP, r0
+ sub r0, r0, #IRQ_Stack_Size
+
+/* Enter Supervisor Mode and set its Stack Pointer */
+ msr CPSR_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT
+ mov SP, r0
+ sub r0, r0, #SVC_Stack_Size
+
+/* Enter User Mode and set its Stack Pointer */
+ msr CPSR_c, #USR_MODE
+ mov SP, r0
+
+/* Enter the C code */
+ ldr r0,=?C?INIT
+ tst r0,#1 ; Bit-0 set: INIT is Thumb
+ ldreq LR,=exit?A ; ARM Mode
+ ldrne LR,=exit?T ; Thumb Mode
+ bx r0
+ ENDP
+
+PUBLIC exit?A
+exit?A PROC CODE32
+ B exit?A
+ ENDP
+
+PUBLIC exit?T
+exit?T PROC CODE16
+exit: B exit?T
+ ENDP
+
+
+ END
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