Add LPC43 clock initialization logic

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4910 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 111 insertions, 7 deletions

diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
index 972591019..0b917a8ea 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
@@ -33,6 +33,27 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  ****************************************************************************/
+/*
+ * Power-Up Reset Overview
+ * -----------------------
+ *
+ * The ARM core starts executing code on reset with the program counter set
+ * to 0x0000:0000.  The LPC43xx contains a shadow pointer register that
+ * allows areas of memory to be mapped to address 0x0000:0000. The default,
+ * reset value of the shadow pointer is 0x1040:0000 so that on reset code in
+ * the boot ROM is always executed first.
+ *
+ * The boot starts after reset is released.  The IRC is selected as CPU clock
+ * and the Cortex-M4 starts the boot loader. By default the JTAG access to the
+ * chip is disabled at reset.  The boot ROM determines the boot mode based on
+ * the OTP BOOT_SRC value or reset state pins.  For flash-based parts, the part
+ * boots from internal flash by default.  Otherwse, the boot ROM copies the
+ * image to internal SRAM at location 0x1000:0000, sets the ARM's shadow
+ * pointer to 0x1000:0000, and jumps to that location.
+ *
+ * However, using JTAG the executable image can be also loaded directly into
+ * and executed from SRAM.
+ */
 
 #include <nuttx/config.h>
 
@@ -45,16 +66,20 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
+#include "nvic.h"
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
+#include "chip/lpc43_creg.h"
 
 #include "lpc43_rgu.h"
 #include "lpc43_cgu.h"
+#include "lpc43_emc.h"
 #include "lpc43_lowputc.h"
 
 /****************************************************************************
+ * Preprocessor Definitions
+ ****************************************************************************/
+
+ /****************************************************************************
  * Name: showprogress
  *
  * Description:
@@ -73,6 +98,71 @@
  ****************************************************************************/
 
 /****************************************************************************
+ * Name: lpc43_setbootrom
+ *
+ * Description:
+ *   Set the shadow register to 0x1040:0000 and the VTOR to 0x0000:0000 so
+ *   that any exceptions (particulary things like hard faults) that occur
+ *   before we are initialized are caught by the BOOT ROM.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_setbootrom(void)
+{
+  /* Set the shadow register to the beginning of the boot ROM (Only bits 12-31) */
+
+  putreg32(LPC43_ROM_BASE, LPC43_CREG_M4MEMMAP);
+
+  /* Address zero now maps to the Boot ROM.  Make sure the the VTOR will
+   * use the ROM vector table at that address.
+   */
+
+  putreg32(0, NVIC_VECTAB);
+}
+
+/****************************************************************************
+ * Name: lpc43_enabuffering
+ *
+ * Description:
+ *   If we are executing from external FLASH, then enable buffering.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_BOOT_CS0FLASH) || defined(CONFIG_BOOT_CS1FLASH) || \
+    defined(CONFIG_BOOT_CS2FLASH) || defined(CONFIG_BOOT_CS3FLASH)
+static inline void lpc43_enabuffering(void)
+{
+  uint32_t regval;
+
+#ifdef CONFIG_BOOT_CS0FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG0);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG0);
+#endif
+
+#ifdef CONFIG_BOOT_CS1FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG1);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG1);
+#endif
+
+#ifdef CONFIG_BOOT_CS2FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG2);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG2);
+#endif
+
+#ifdef CONFIG_BOOT_CS3FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG3);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG3);
+#endif
+}
+#else
+#  define lpc43_enabuffering()
+#endif
+
+/****************************************************************************
  * Name: lpc43_fpuconfig
  *
  * Description:
@@ -190,15 +280,24 @@ void __start(void)
   lpc43_softreset();
 #endif
 
+  /* Make sure that any exceptions (such as hard faults) that occur before
+   * we are initialized are caught by the BOOT ROM.
+   */
+
+  lpc43_setbootrom();
+
   /* Configure the CGU clocking and the console uart so that we can get
    * debug output as soon as possible.
    */
 
   lpc43_clockconfig();
-  lpc43_fpuconfig();
   lpc43_lowsetup();
   showprogress('A');
 
+  /* If we are executing from external FLASH, then enable buffering */
+
+  lpc43_enabuffering();
+
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
    * certain that there are no issues with the state of global variables.
    */
@@ -221,17 +320,22 @@ void __start(void)
     }
   showprogress('C');
 
+  /* Initialize the FPU (if configured) */
+
+  lpc43_fpuconfig();
+  showprogress('D');
+
   /* Perform early serial initialization */
 
 #ifdef USE_EARLYSERIALINIT
   up_earlyserialinit();
 #endif
-  showprogress('D');
+  showprogress('E');
 
   /* Initialize onboard resources */
 
   lpc43_boardinitialize();
-  showprogress('E');
+  showprogress('F');
 
   /* Then start NuttX */
 
@@ -239,7 +343,7 @@ void __start(void)
   showprogress('\n');
   os_start();
 
-  /* Shoulnd't get here */
+  /* Shouldn't get here */
 
   for(;;);
 }