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| author | Lorenz Meier <lm@inf.ethz.ch> | 2013-06-13 09:14:40 +0200 |
|---|---|---|
| committer | Lorenz Meier <lm@inf.ethz.ch> | 2013-06-13 09:14:40 +0200 |
| commit | c255df1df9c1cd51e6d0e71ee5f2e92a22eac5cf (patch) | |
| tree | 2254ceb7c66ba63b6cb6738af92c839f3868c748 /nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h | |
| parent | bc5c15a4909386a1efd556f4648385440379b164 (diff) | |
| download | px4-nuttx-c255df1df9c1cd51e6d0e71ee5f2e92a22eac5cf.tar.gz px4-nuttx-c255df1df9c1cd51e6d0e71ee5f2e92a22eac5cf.tar.bz2 px4-nuttx-c255df1df9c1cd51e6d0e71ee5f2e92a22eac5cf.zip | |
Merged in upstream, took upstream UART driver without changes, needs re-evaluation (minor diffs to local version)
Diffstat (limited to 'nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h')
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h index 7e66c0b50..e1b9822b2 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h @@ -91,7 +91,7 @@ # define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ /* 0x400e2600-0x400fffff: Reserved */ /* 0x40100000-0x41ffffff: Reserved */ -# define SAM_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ +# define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ /* 0x44000000-0x5fffffff: Reserved */ #define SAM_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ # define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ @@ -111,14 +111,14 @@ #define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ #define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ #define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ -#define SAM_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ +#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ #define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ #define SAM_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ -# define SAM_EEFCN_BASE(n) (0x400e0800+((n)<<9)) +# define SAM_EEFCN_BASE(n) (0x400e0800 + ((n) << 9)) # define SAM_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */ # define SAM_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */ #define SAM_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */ -# define SAM_PION_BASE(n) (0x400e0c00+((n)<<9)) +# define SAM_PION_BASE(n) (0x400e0c00 + ((n) << 9)) # define SAM_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */ # define SAM_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */ # define SAM_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */ |