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authorLorenz Meier <lm@inf.ethz.ch>2013-06-13 09:14:40 +0200
committerLorenz Meier <lm@inf.ethz.ch>2013-06-13 09:14:40 +0200
commitc255df1df9c1cd51e6d0e71ee5f2e92a22eac5cf (patch)
tree2254ceb7c66ba63b6cb6738af92c839f3868c748 /nuttx/arch/arm/src/sam34/chip/sam_rstc.h
parentbc5c15a4909386a1efd556f4648385440379b164 (diff)
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Merged in upstream, took upstream UART driver without changes, needs re-evaluation (minor diffs to local version)
Diffstat (limited to 'nuttx/arch/arm/src/sam34/chip/sam_rstc.h')
-rw-r--r--nuttx/arch/arm/src/sam34/chip/sam_rstc.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h
index 3a620d7ef..3b278d45f 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h
@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rstc.h
+ * Reset Controller (RSTC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -68,6 +69,7 @@
#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */
#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
+# define RSTC_CR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */
#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */
@@ -86,6 +88,7 @@
#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT)
#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
+# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
/****************************************************************************************
* Public Types