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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-06-02 13:57:22 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-06-02 13:57:22 -0600 |
| commit | 3d0cc6467f1ce5a998aca982ccbd32d8c886e1b1 (patch) | |
| tree | fa9f3e4347deba93f0fb4c43c543492d37ab66ac /nuttx/arch/arm/src/sam34/chip | |
| parent | 0baf7136f9db7b14d5ed01cf753a86d0d38972b5 (diff) | |
| download | px4-nuttx-3d0cc6467f1ce5a998aca982ccbd32d8c886e1b1.tar.gz px4-nuttx-3d0cc6467f1ce5a998aca982ccbd32d8c886e1b1.tar.bz2 px4-nuttx-3d0cc6467f1ce5a998aca982ccbd32d8c886e1b1.zip | |
Rename sam3u/ architecture directories to sam34/ to include the SAM4L
Diffstat (limited to 'nuttx/arch/arm/src/sam34/chip')
28 files changed, 6352 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h new file mode 100644 index 000000000..ea61f57d8 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_memorymap.h @@ -0,0 +1,145 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam3u_memorymap.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM34_SAM3U_MEMORYMAP_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ +# define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */ +# define SAM_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */ +# define SAM_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */ +# define SAM_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */ + /* 0x00200000-0x1fffffff: Reserved */ +#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ +# define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 (see chip.h) */ +# define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 (see chip.h) */ +# define SAM_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */ +# define SAM_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */ + /* 0x20200000-0x2fffffff: Undefined */ +# define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */ + /* 0x24000000-0x3fffffff: Undefined */ +#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ +# define SAM_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ +# define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ +# define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ + /* 0x4000c000-0x4007ffff: Reserved */ +# define SAM_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */ +# define SAM_TCN_BASE(n) (0x40080000+((n)<<6)) +# define SAM_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */ +# define SAM_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */ +# define SAM_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */ +# define SAM_TWI_BASE 0x40084000 /* 0x40084000-0x4008ffff: Two-Wire Interface */ +# define SAM_TWIN_BASE(n) (0x40084000+((n)<<14)) +# define SAM_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */ +# define SAM_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */ +# define SAM_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */ +# define SAM_USART_BASE 0x40090000 /* 0x40090000-0x4009ffff: USART */ +# define SAM_USARTN_BASE(n) (0x40090000+((n)<<14)) +# define SAM_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */ +# define SAM_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */ +# define SAM_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */ +# define SAM_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */ + /* 0x400a0000-0x400a3fff: Reserved */ +# define SAM_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */ +# define SAM_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */ +# define SAM_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */ +# define SAM_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */ + /* 0x400b4000-0x400dffff: Reserved */ +# define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ + /* 0x400e2600-0x400fffff: Reserved */ + /* 0x40100000-0x41ffffff: Reserved */ +# define SAM_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ + /* 0x44000000-0x5fffffff: Reserved */ +#define SAM_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ +# define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ +# define SAM_EXTCSN_BASE(n) (0x60000000*((n)<<24)) +# define SAM_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */ +# define SAM_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */ +# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ +# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ + /* 0x64000000-0x67ffffff: Reserved */ +# define SAM_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */ + /* 0x69000000-0x9fffffff: Reserved */ + /* 0xa0000000-0xdfffffff: Reserved */ +#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ + +/* System Controller Register Blocks: 0x400e0000-0x4007ffff */ + +#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ +#define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ +#define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ +#define SAM_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ +#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ +#define SAM_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ +# define SAM_EEFCN_BASE(n) (0x400e0800+((n)<<9)) +# define SAM_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */ +# define SAM_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */ +#define SAM_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */ +# define SAM_PION_BASE(n) (0x400e0c00+((n)<<9)) +# define SAM_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */ +# define SAM_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */ +# define SAM_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */ +#define SAM_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */ +#define SAM_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */ +#define SAM_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */ +#define SAM_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */ +#define SAM_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */ +#define SAM_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */ + /* 0x490e1400-0x4007ffff: Reserved */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h new file mode 100644 index 000000000..fbcffbfd0 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h @@ -0,0 +1,223 @@ +/************************************************************************************ + * arch/arm/src/sam34/chip/sam3u_pinmap.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam_gpio.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* GPIO pin definitions *************************************************************/ + +#define GPIO_ADC0_AD0 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21) +#define GPIO_ADC0_AD1 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30) +#define GPIO_ADC0_AD2 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN3) +#define GPIO_ADC0_AD3 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN4) +#define GPIO_ADC0_AD4 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN15) +#define GPIO_ADC0_AD5 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN16) +#define GPIO_ADC0_AD6 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN17) +#define GPIO_ADC0_AD7 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN18) + +#define GPIO_CAN_XCVR_RS (GPIO_OUTPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_OUTPUT_SET|GPIO_PIN23) +#define GPIO_CAN1_XCVR_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN27) +#define GPIO_CAN1_XCVR_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN26) +#define GPIO_CAN2_XCVR_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN29) +#define GPIO_CAN2_XCVR_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN28) + +#define GPIO_SMC_D0 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN9) /* Check! */ +#define GPIO_SMC_D1 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN10) /* Check! */ +#define GPIO_SMC_D2 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN11) /* Check! */ +#define GPIO_SMC_D3 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN12) /* Check! */ +#define GPIO_SMC_D4 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN13) /* Check! */ +#define GPIO_SMC_D5 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN14) /* Check! */ +#define GPIO_SMC_D6 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN15) /* Check! */ +#define GPIO_SMC_D7 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN16) /* Check! */ +#define GPIO_SMC_D8 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN25) /* Check! */ +#define GPIO_SMC_D9 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN26) /* Check! */ +#define GPIO_SMC_D10 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN27) /* Check! */ +#define GPIO_SMC_D11 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN28) /* Check! */ +#define GPIO_SMC_D12 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN29) /* Check! */ +#define GPIO_SMC_D13 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN30) /* Check! */ +#define GPIO_SMC_D14 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN31) /* Check! */ +#define GPIO_SMC_D15 (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN6) /* Check! */ +#define GPIO_SMC_NCS0 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN20) +#define GPIO_SMC_NRD (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN19) +#define GPIO_SMC_NWE (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN23) +#define GPIO_SMC_PSRAM_A0 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN0) /* Check! */ +#define GPIO_SMC_PSRAM_A1 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN1) /* Check! */ +#define GPIO_SMC_PSRAM_A2 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN2) /* Check! */ +#define GPIO_SMC_PSRAM_A3 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN3) /* Check! */ +#define GPIO_SMC_PSRAM_A4 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN4) /* Check! */ +#define GPIO_SMC_PSRAM_A5 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN5) /* Check! */ +#define GPIO_SMC_PSRAM_A6 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN6) /* Check! */ +#define GPIO_SMC_PSRAM_A7 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN7) /* Check! */ +#define GPIO_SMC_PSRAM_A8 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN8) /* Check! */ +#define GPIO_SMC_PSRAM_A9 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN9) /* Check! */ +#define GPIO_SMC_PSRAM_A10 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN10) /* Check! */ +#define GPIO_SMC_PSRAM_A11 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN11) /* Check! */ +#define GPIO_SMC_PSRAM_A12 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN24) /* Check! */ +#define GPIO_SMC_PSRAM_A13 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN25) /* Check! */ +#define GPIO_SMC_PSRAM_A14 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN26) /* Check! */ +#define GPIO_SMC_PSRAM_A15 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN27) /* Check! */ +#define GPIO_SMC_PSRAM_A16 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN27) /* Check! */ +#define GPIO_SMC_PSRAM_A17 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN28) /* Check! */ +#define GPIO_SMC_PSRAM_A18 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN29) /* Check! */ +#define GPIO_SMC_PSRAM_NBS0 (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN7) /* Check! */ +#define GPIO_SMC_PSRAM_NBS1 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|GPIO_PIN15) +#define GPIO_SMC_A1 (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN8) +#define GPIO_SMC_NCS2 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|GPIO_PIN16) +#define GPIO_SMC_LCD_RS (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN8) + +#define GPIO_MCI_DAT0 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5) +#define GPIO_MCI_DAT1 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN6) +#define GPIO_MCI_DAT2 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN7) +#define GPIO_MCI_DAT3 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN8) +#define GPIO_MCI_DAT4 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN28) +#define GPIO_MCI_DAT5 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN29) +#define GPIO_MCI_DAT6 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN30) +#define GPIO_MCI_DAT7 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN31) +#define GPIO_MCI_CK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN3) +#define GPIO_MCI_DA (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN4) +#define GPIO_MCI_DAT0IN (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5) + +#define GPIO_PWMC_PWMH0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0) +#define GPIO_PWMC_PWML0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7) +#define GPIO_PWMC_PWMH1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1) +#define GPIO_PWMC_PWML1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8) +#define GPIO_PWMC_PWMH2 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2) +#define GPIO_PWMC_PWML2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) + +#define GPIO_SPI0_MISO (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN13) +#define GPIO_SPI0_MOSI (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN14) +#define GPIO_SPI0_SPCK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN15) +#define GPIO_SPI0_NPCS0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN16) + +#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0) +#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN3) +#define GPIO_SPI0_NPCS1_3 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19) +#define GPIO_SPI0_NPCS2_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN1) +#define GPIO_SPI0_NPCS2_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN4) +#define GPIO_SPI0_NPCS2_3 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN14) +#define GPIO_SPI0_NPCS3_1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19) +#define GPIO_SPI0_NPCS3_2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN5) + +#define GPIO_SSC_TD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN26) +#define GPIO_SSC_TK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN28) +#define GPIO_SSC_TF (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30) + +#define GPIO_PCK0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21) + +#define GPIO_TWI_TWD0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) +#define GPIO_TWI_TWCK0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10) +#define GPIO_TWI_TWD1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) +#define GPIO_TWI_TWCK1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) + +#define GPIO_UART_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12) +#define GPIO_UART_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11) + +#define GPIO_USART0_CTS (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN8) +#define GPIO_USART0_DCD (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN11) +#define GPIO_USART0_DSR (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN10) +#define GPIO_USART0_DTR (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN9) +#define GPIO_USART0_RI (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN12) +#define GPIO_USART0_RTS (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN7) +#define GPIO_USART0_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19) +#define GPIO_USART0_SCK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN17) +#define GPIO_USART0_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN18) + +#define GPIO_USART1_CTS (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN23) +#define GPIO_USART1_RTS (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN22) +#define GPIO_USART1_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21) +#define GPIO_USART1_SCK (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) +#define GPIO_USART1_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN20) + +#define GPIO_USART2_CTS (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN22) +#define GPIO_USART2_RTS (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN21) +#define GPIO_USART2_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN23) +#define GPIO_USART2_SCK (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) +#define GPIO_USART2_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN22) + +#define GPIO_USART3_CTS (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN10) +#define GPIO_USART3_RTS (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN11) +#define GPIO_USART3_RXD (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN13) +#define GPIO_USART3_SCK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19) +#define GPIO_USART3_TXD (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN12) + +#define GPIO_USB_VBUS (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h new file mode 100644 index 000000000..d1828ddd8 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h @@ -0,0 +1,90 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam3u_vectors.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ +/* This file is included by sam_vectors.S. It provides the macro VECTOR that + * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h. + * sam_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + * + * + * Vectors for low and medium density devices + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 46 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 46 + +#else + VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */ + VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */ + VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */ + VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */ + VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */ + VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ + VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */ + VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */ + VECTOR(sam_uart, SAM_IRQ_UART) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */ + VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+9: Static Memory Controller */ + VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+10: Parallel I/O Controller A */ + VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+11: Parallel I/O Controller B */ + VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+12: Parallel I/O Controller C */ + VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+13: USART 0 */ + VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+14: USART 1 */ + VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+15: USART 2 */ + VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+16: USART 3 */ + VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+17: High Speed Multimedia Card Interface */ + VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+18: Two-Wire Interface 0 */ + VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+19: Two-Wire Interface 1 */ + VECTOR(sam_spi, SAM_IRQ_SPI) /* Vector 16+20: Serial Peripheral Interface */ + VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+21: Synchronous Serial Controller */ + VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+22: Timer Counter 0 */ + VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+23: Timer Counter 1 */ + VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+24: Timer Counter 2 */ + VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+25: Pulse Width Modulation Controller */ + VECTOR(sam_adc12b, SAM_IRQ_ADC12B) /* Vector 16+26: 12-bit ADC Controller */ + VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+27: 10-bit ADC Controller */ + VECTOR(sam_dmac, SAM_IRQ_DMAC) /* Vector 16+28: DMA Controller */ + VECTOR(sam_udphs, SAM_IRQ_UDPHS) /* Vector 16+29: USB Device High Speed */ +#endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_adc.h b/nuttx/arch/arm/src/sam34/chip/sam_adc.h new file mode 100644 index 000000000..802fdcd2c --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_adc.h @@ -0,0 +1,236 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_adc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM_CHIP_SAM_ADC_H +#define __ARCH_ARM_SRC_SAM_CHIP_SAM_ADC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* ADC register offsets ****************************************************************/ + +#define SAM_ADC_CR_OFFSET 0x00 /* Control Register (Both) */ +#define SAM_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */ + /* 0x08: Reserved */ + /* 0x0c: Reserved */ +#define SAM_ADC_CHER_OFFSET 0x10 /* Channel Enable Register (Both) */ +#define SAM_ADC_CHDR_OFFSET 0x14 /* Channel Disable Register (Both) */ +#define SAM_ADC_CHSR_OFFSET 0x18 /* Channel Status Register (Both) */ +#define SAM_ADC_SR_OFFSET 0x1c /* Status Register (Both) */ +#define SAM_ADC_LCDR_OFFSET 0x20 /* Last Converted Data Register (Both) */ +#define SAM_ADC_IER_OFFSET 0x24 /* Interrupt Enable Register (Both) */ +#define SAM_ADC_IDR_OFFSET 0x28 /* Interrupt Disable Register (Both) */ +#define SAM_ADC_IMR_OFFSET 0x2c /* Interrupt Mask Register (Both) */ +#define SAM_ADC_CDR_OFFSET(n) (0x30+((n)<<2)) +#define SAM_ADC_CDR0_OFFSET 0x30 /* Channel Data Register 0 (Both) */ +#define SAM_ADC_CDR1_OFFSET 0x34 /* Channel Data Register 1 (Both) */ +#define SAM_ADC_CDR2_OFFSET 0x38 /* Channel Data Register 2 (Both) */ +#define SAM_ADC_CDR3_OFFSET 0x3c /* Channel Data Register 3 (Both) */ +#define SAM_ADC_CDR4_OFFSET 0x40 /* Channel Data Register 4 (Both) */ +#define SAM_ADC_CDR5_OFFSET 0x44 /* Channel Data Register 5 (Both) */ +#define SAM_ADC_CDR6_OFFSET 0x48 /* Channel Data Register 6 (Both) */ +#define SAM_ADC_CDR7_OFFSET 0x4c /* Channel Data Register 7 (Both) */ +#define SAM_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */ +#define SAM_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */ + +/* ADC register adresses ***************************************************************/ + +#define SAM_ADC12B_CR (SAM_ADC12B_BASE+SAM_ADC_CR_OFFSET) +#define SAM_ADC12B_MR (SAM_ADC12B_BASE+SAM_ADC_MR_OFFSET) +#define SAM_ADC12B_CHER (SAM_ADC12B_BASE+SAM_ADC_CHER_OFFSET) +#define SAM_ADC12B_CHDR (SAM_ADC12B_BASE+SAM_ADC_CHDR_OFFSET) +#define SAM_ADC12B_CHSR (SAM_ADC12B_BASE+SAM_ADC_CHSR_OFFSET) +#define SAM_ADC12B_SR (SAM_ADC12B_BASE+SAM_ADC_SR_OFFSET) +#define SAM_ADC12B_LCDR_ (SAM_ADC12B_BASE+SAM_ADC_LCDR_OFFSET) +#define SAM_ADC12B_IER (SAM_ADC12B_BASE+SAM_ADC_IER_OFFSET) +#define SAM_ADC12B_IDR (SAM_ADC12B_BASE+SAM_ADC_IDR_OFFSET) +#define SAM_ADC12B_IMR (SAM_ADC12B_BASE+SAM_ADC_IMR_OFFSET) +#define SAM_ADC12B_CDR(n)) (SAM_ADC12B_BASE+SAM_ADC_CDR_OFFSET(n)) +#define SAM_ADC12B_CDR0 (SAM_ADC12B_BASE+SAM_ADC_CDR0_OFFSET) +#define SAM_ADC12B_CDR1 (SAM_ADC12B_BASE+SAM_ADC_CDR1_OFFSET) +#define SAM_ADC12B_CDR2 (SAM_ADC12B_BASE+SAM_ADC_CDR2_OFFSET) +#define SAM_ADC12B_CDR3 (SAM_ADC12B_BASE+SAM_ADC_CDR3_OFFSET) +#define SAM_ADC12B_CDR4 (SAM_ADC12B_BASE+SAM_ADC_CDR4_OFFSET) +#define SAM_ADC12B_CDR5 (SAM_ADC12B_BASE+SAM_ADC_CDR5_OFFSET) +#define SAM_ADC12B_CDR6 (SAM_ADC12B_BASE+SAM_ADC_CDR6_OFFSET) +#define SAM_ADC12B_CDR7 (SAM_ADC12B_BASE+SAM_ADC_CDR7_OFFSET) +#define SAM_ADC12B_ACR (SAM_ADC12B_BASE+SAM_ADC12B_ACR_OFFSET) +#define SAM_ADC12B_EMR (SAM_ADC12B_BASE+SAM_ADC12B_EMR_OFFSET) + +#define SAM_ADC_CR (SAM_ADC_BASE+SAM_ADC_CR_OFFSET) +#define SAM_ADC_MR (SAM_ADC_BASE+SAM_ADC_MR_OFFSET) +#define SAM_ADC_CHER (SAM_ADC_BASE+SAM_ADC_CHER_OFFSET) +#define SAM_ADC_CHDR (SAM_ADC_BASE+SAM_ADC_CHDR_OFFSET) +#define SAM_ADC_CHSR (SAM_ADC_BASE+SAM_ADC_CHSR_OFFSET) +#define SAM_ADC_SR (SAM_ADC_BASE+SAM_ADC_SR_OFFSET) +#define SAM_ADC_LCDR (SAM_ADC_BASE+SAM_ADC_LCDR_OFFSET) +#define SAM_ADC_IER (SAM_ADC_BASE+SAM_ADC_IER_OFFSET) +#define SAM_ADC_IDR (SAM_ADC_BASE+SAM_ADC_IDR_OFFSET) +#define SAM_ADC_IMR (SAM_ADC_BASE+SAM_ADC_IMR_OFFSET) +#define SAM_ADC_CDR(n)) (SAM_ADC_BASE+SAM_ADC_CDR_OFFSET(n)) +#define SAM_ADC_CDR0 (SAM_ADC_BASE+SAM_ADC_CDR0_OFFSET) +#define SAM_ADC_CDR1 (SAM_ADC_BASE+SAM_ADC_CDR1_OFFSET) +#define SAM_ADC_CDR2 (SAM_ADC_BASE+SAM_ADC_CDR2_OFFSET) +#define SAM_ADC_CDR3 (SAM_ADC_BASE+SAM_ADC_CDR3_OFFSET) +#define SAM_ADC_CDR4 (SAM_ADC_BASE+SAM_ADC_CDR4_OFFSET) +#define SAM_ADC_CDR5 (SAM_ADC_BASE+SAM_ADC_CDR5_OFFSET) +#define SAM_ADC_CDR6 (SAM_ADC_BASE+SAM_ADC_CDR6_OFFSET) +#define SAM_ADC_CDR7 (SAM_ADC_BASE+SAM_ADC_CDR7_OFFSET) + +/* ADC register bit definitions ********************************************************/ + +/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */ + +#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */ +#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */ + +/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */ + +#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */ +#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */ +#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT) +#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */ +#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ +#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */ +#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT) +#define ADB12B_MRSTARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */ +#define ADB12B_MRSTARTUP_MASK (0xff << ADB12B_MRSTARTUP_SHIFT +#define ADB10B_MRSTARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */ +#define ADB10B_MRSTARTUP_MASK (0x7f << ADB10B_MRSTARTUP_SHIFT) +#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */ +#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT) + +/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel + * Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register, + * and ADC(10B) Channel Status Register common bit-field definitions + */ + +#define ADC_CH(n) (1 << (n)) +#define ADC_CH0 (1 << 0) /* Bit 0: Channel x Enable */ +#define ADC_CH1 (1 << 1) /* Bit 1: Channel x Enable */ +#define ADC_CH2 (1 << 2) /* Bit 2: Channel x Enable */ +#define ADC_CH3 (1 << 3) /* Bit 3: Channel x Enable */ +#define ADC_CH4 (1 << 4) /* Bit 4: Channel x Enable */ +#define ADC_CH5 (1 << 5) /* Bit 5: Channel x Enable */ +#define ADC_CH6 (1 << 6) /* Bit 6: Channel x Enable */ +#define ADC_CH7 (1 << 7) /* Bit 7: Channel x Enable */ + +/* ADC12B Analog Control Register (ADC12B only) */ + +#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */ +#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT) +#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */ +#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT) +#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */ +#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */ + +/* ADC12B Extended Mode Register (ADC12B only) */ + +#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */ +#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */ +#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT) + +/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt + * Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register, + * ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and + * ADC(10B) Interrupt Mask Register common bit-field definitions + */ + +#define ADC_INT_EOC(n) (1<<(n)) +#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */ +#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */ +#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */ +#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */ +#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */ +#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */ +#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */ +#define ADC_INT_EOC7 (1 << 7) /* Bit 0: End of Conversion 7 */ +#define ADC_INT_OVRE(n) (1<<((n)+8)) +#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */ +#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */ +#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */ +#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */ +#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */ +#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */ +#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */ +#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */ +#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */ +#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */ +#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */ +#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */ + +/* ADC12B Last Converted Data Register */ + +#define ADC12B_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */ +#define ADC12B_LCDR_DATA_MASK (0xfff << ADC12B_LCDR_DATA_SHIFT) + +/* ADC(10B) Last Converted Data Register */ + +#define ADC10B_LCDR_DATA_SHIFT (0) /* Bits 0-9: Last Data Converted */ +#define ADC10B_LCDR_DATA_MASK (0x1ff << ADC10B_LCDR_DATA_SHIFT) + +/* ADC12B Channel Data Register */ + +#define ADC12B_CDR_DATA_SHIFT (0) /* Bits 0-11: Converted Data */ +#define ADC12B_CDR_DATA_MASK (0xfff << ADC12B_CDR_DATA_SHIFT) + +/* ADC(10B) Channel Data Register */ + +#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */ +#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM_CHIP_SAM_ADC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_chipid.h b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h new file mode 100644 index 000000000..1c1e972b7 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_chipid.h @@ -0,0 +1,167 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_chipid.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_CHIPID_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_CHIPID_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* CHIPID register offsets **************************************************************/ + +#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */ +#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */ + +/* CHIPID register adresses *************************************************************/ + +#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR) +#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID) + +/* CHIPID register bit definitions ******************************************************/ + +#define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */ +#define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT) +#define CHIPID_CIDR_EPROC_SHIFT (5) /* Bits 5-7: Embedded Processor */ +#define CHIPID_CIDR_EPROC_MASK (7 << CHIPID_CIDR_EPROC_SHIFT) +# define CHIPID_CIDR_EPROC_ARM946ES (1 << CHIPID_CIDR_EPROC_SHIFT) /* ARM946E-S */ +# define CHIPID_CIDR_EPROC_ARM7TDMI (2 << CHIPID_CIDR_EPROC_SHIFT) /* ARM7TDMI */ +# define CHIPID_CIDR_EPROC_CORTEXM3 (3 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M3 */ +# define CHIPID_CIDR_EPROC_ARM920T (4 << CHIPID_CIDR_EPROC_SHIFT) /* ARM920T */ +# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */ +#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) +# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ +# define CHIPID_CIDR_NVPSIZ_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_NVPSIZ_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_NVPSIZ_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_NVPSIZ_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_NVPSIZ_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_NVPSIZ_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ +# define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ +# define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ +#define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) +# define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ +# define CHIPID_CIDR_NVPSIZ2_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_NVPSIZ2_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_NVPSIZ2_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_NVPSIZ2_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_NVPSIZ2_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_NVPSIZ2_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ +# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ +# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ +#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) +# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ +# define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */ +# define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ +# define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ +# define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ +# define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ +# define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ +# define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ +# define CHIPID_CIDR_SRAMSIZ_8KB (8 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_SRAMSIZ_16KB (9 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_SRAMSIZ_32KB (10 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_SRAMSIZ_64KB (11 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_SRAMSIZ_128KB (12 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */ +# define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */ +#define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */ +#define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT) +# define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM9XEXX (0x29 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9XExx Series */ +# define CHIPID_CIDR_ARCH_AT91X34 (0x34 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x34 Series */ +# define CHIPID_CIDR_ARCH_CAP7 (0x37 << CHIPID_CIDR_ARCH_SHIFT) /* CAP7 Series */ +# define CHIPID_CIDR_ARCH_CAP9 (0x39 << CHIPID_CIDR_ARCH_SHIFT) /* CAP9 Series */ +# define CHIPID_CIDR_ARCH_CAP11 (0x3b << CHIPID_CIDR_ARCH_SHIFT) /* CAP11 Series */ +# define CHIPID_CIDR_ARCH_AT91X40 (0x40 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x40 Series */ +# define CHIPID_CIDR_ARCH_AT91X42 (0x42 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x42 Series */ +# define CHIPID_CIDR_ARCH_AT91X55 (0x55 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x55 Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7AXX (0x60 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Axx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7AQXX (0x61 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7AQxx Series */ +# define CHIPID_CIDR_ARCH_AT91X63 (0x63 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x63 Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SXX (0x70 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Sxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7XCXX (0x71 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7XCxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SEXX (0x72 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SExx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7LXX (0x73 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Lxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7XXX (0x75 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Xxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SLXX (0x76 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SLxx Series */ +# define CHIPID_CIDR_ARCH_SAM3UXC (0x80 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3UXE (0x81 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxE Series (144-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3AXC (0x83 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3AxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXC (0x84 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ +# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ +#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) +# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ +# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ +# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ +# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ +#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_CHIPID_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_dmac.h b/nuttx/arch/arm/src/sam34/chip/sam_dmac.h new file mode 100644 index 000000000..388383b1e --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_dmac.h @@ -0,0 +1,440 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_dmac.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* DMAC register offsets ****************************************************************/ + +/* Global Registers */ + +#define SAM_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */ +#define SAM_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */ +#define SAM_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */ +#define SAM_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */ +#define SAM_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */ + /* 0x014-0x18: Reserved */ +#define SAM_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */ +#define SAM_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */ +#define SAM_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */ +#define SAM_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */ +#define SAM_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */ +#define SAM_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */ +#define SAM_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */ + /* 0x034-0x38: Reserved */ +/* DMA channel registers */ + +#define SAM_DMACHAN_OFFSET(n) (0x3c+((n)*0x28)) +#define SAM_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */ +#define SAM_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */ +#define SAM_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */ +#define SAM_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */ + +#define SAM_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */ +#define SAM_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */ +#define SAM_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */ +#define SAM_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */ +#define SAM_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */ +#define SAM_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */ + /* 0x18-0x24: Reserved */ + /* 0x017c-0x1fc: Reserved */ + +/* DMAC register adresses ***************************************************************/ + +/* Global Registers */ + +#define SAM_DMAC_GCFG (SAM_DMAC_BASE+SAM_DMAC_GCFG_OFFSET) +#define SAM_DMAC_EN (SAM_DMAC_BASE+SAM_DMAC_EN_OFFSET) +#define SAM_DMAC_SREQ (SAM_DMAC_BASE+SAM_DMAC_SREQ_OFFSET) +#define SAM_DMAC_CREQ (SAM_DMAC_BASE+SAM_DMAC_CREQ_OFFSET) +#define SAM_DMAC_LAST (SAM_DMAC_BASE+SAM_DMAC_LAST_OFFSET) +#define SAM_DMAC_EBCIER (SAM_DMAC_BASE+SAM_DMAC_EBCIER_OFFSET) +#define SAM_DMAC_EBCIDR (SAM_DMAC_BASE+SAM_DMAC_EBCIDR_OFFSET) +#define SAM_DMAC_EBCIMR (SAM_DMAC_BASE+SAM_DMAC_EBCIMR_OFFSET) +#define SAM_DMAC_EBCISR (SAM_DMAC_BASE+SAM_DMAC_EBCISR_OFFSET) +#define SAM_DMAC_CHER (SAM_DMAC_BASE+SAM_DMAC_CHER_OFFSET) +#define SAM_DMAC_CHDR (SAM_DMAC_BASE+SAM_DMAC_CHDR_OFFSET) +#define SAM_DMAC_CHSR (SAM_DMAC_BASE+SAM_DMAC_CHSR_OFFSET) + +/* DMA channel registers */ + +#define SAM_DMACHAN_BASE(n) (SAM_DMAC_BASE+SAM_DMACHAN_OFFSET(n)) +#define SAM_DMACHAN0_BASE (SAM_DMAC_BASE+SAM_DMACHAN0_OFFSET) +#define SAM_DMACHAN1_BASE (SAM_DMAC_BASE+SAM_DMACHAN1_OFFSET) +#define SAM_DMACHAN2_BASE (SAM_DMAC_BASE+SAM_DMACHAN2_OFFSET) +#define SAM_DMACHAN3_BASE (SAM_DMAC_BASE+SAM_DMACHAN3_OFFSET) + +#define SAM_DMACHAN_SADDR(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_SADDR_OFFSET) +#define SAM_DMACHAN_DADDR(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_DADDR_OFFSET) +#define SAM_DMACHAN_DSCR(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_DSCR_OFFSET) +#define SAM_DMACHAN_CTRLA(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_CTRLA_OFFSET) +#define SAM_DMACHAN_CTRLB(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_CTRLB_OFFSET) +#define SAM_DMACHAN_CFG(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_CFG_OFFSET) + +#define SAM_DMACHAN0_SADDR (SAM_DMACHAN0_BASE+SAM_DMACHAN_SADDR_OFFSET) +#define SAM_DMACHAN0_DADDR (SAM_DMACHAN0_BASE+SAM_DMACHAN_DADDR_OFFSET) +#define SAM_DMACHAN0_DSCR (SAM_DMACHAN0_BASE+SAM_DMACHAN_DSCR_OFFSET) +#define SAM_DMACHAN0_CTRLA (SAM_DMACHAN0_BASE+SAM_DMACHAN_CTRLA_OFFSET) +#define SAM_DMACHAN0_CTRLB (SAM_DMACHAN0_BASE+SAM_DMACHAN_CTRLB_OFFSET) +#define SAM_DMACHAN0_CFG (SAM_DMACHAN0_BASE+SAM_DMACHAN_CFG_OFFSET) + +#define SAM_DMACHAN1_SADDR (SAM_DMACHAN1_BASE+SAM_DMACHAN_SADDR_OFFSET) +#define SAM_DMACHAN1_DADDR (SAM_DMACHAN1_BASE+SAM_DMACHAN_DADDR_OFFSET) +#define SAM_DMACHAN1_DSCR (SAM_DMACHAN1_BASE+SAM_DMACHAN_DSCR_OFFSET) +#define SAM_DMACHAN1_CTRLA (SAM_DMACHAN1_BASE+SAM_DMACHAN_CTRLA_OFFSET) +#define SAM_DMACHAN1_CTRLB (SAM_DMACHAN1_BASE+SAM_DMACHAN_CTRLB_OFFSET) +#define SAM_DMACHAN1_CFG (SAM_DMACHAN1_BASE+SAM_DMACHAN_CFG_OFFSET) + +#define SAM_DMACHAN2_SADDR (SAM_DMACHAN2_BASE+SAM_DMACHAN_SADDR_OFFSET) +#define SAM_DMACHAN2_DADDR (SAM_DMACHAN2_BASE+SAM_DMACHAN_DADDR_OFFSET) +#define SAM_DMACHAN2_DSCR (SAM_DMACHAN2_BASE+SAM_DMACHAN_DSCR_OFFSET) +#define SAM_DMACHAN2_CTRLA (SAM_DMACHAN2_BASE+SAM_DMACHAN_CTRLA_OFFSET) +#define SAM_DMACHAN2_CTRLB (SAM_DMACHAN2_BASE+SAM_DMACHAN_CTRLB_OFFSET) +#define SAM_DMACHAN2_CFG (SAM_DMACHAN2_BASE+SAM_DMACHAN_CFG_OFFSET) + +#define SAM_DMACHAN3_SADDR (SAM_DMACHAN3_BASE+SAM_DMACHAN_SADDR_OFFSET) +#define SAM_DMACHAN3_DADDR (SAM_DMACHAN3_BASE+SAM_DMACHAN_DADDR_OFFSET) +#define SAM_DMACHAN3_DSCR (SAM_DMACHAN3_BASE+SAM_DMACHAN_DSCR_OFFSET) +#define SAM_DMACHAN3_CTRLA (SAM_DMACHAN3_BASE+SAM_DMACHAN_CTRLA_OFFSET) +#define SAM_DMACHAN3_CTRLB (SAM_DMACHAN3_BASE+SAM_DMACHAN_CTRLB_OFFSET) +#define SAM_DMACHAN3_CFG (SAM_DMACHAN3_BASE+SAM_DMACHAN_CFG_OFFSET) + +/* DMAC register bit definitions ********************************************************/ + +/* Global Registers */ + +/* DMAC Global Configuration Register */ + +#define DMAC_GCFG_ARB_CFG (1 << 4) /* Bit 4: Round robin (vs fixed) arbiter */ + +/* DMAC Enable Register */ + +#define DMAC_EN_ENABLE (1 << 0) /* Bit 0: DMA controller enable */ + +/* DMAC Software Single Request Register */ + +#define DMAC_SREQ_SHIFT(n) ((n)<<1) +#define DMAC_SREQ_MASK(n) (3 << DMAC_SREQ_SHIFT(n)) +#define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT) +#define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT) +#define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT) +#define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT) + +#define DMAC_SREQ_SSREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source single transfer */ +# define DMAC_SREQ_SSREQ(n) (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ_SHIFT(n))) +# define DMAC_SREQ_SSREQ0 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ0_SHIFT) +# define DMAC_SREQ_SSREQ1 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ1_SHIFT) +# define DMAC_SREQ_SSREQ2 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ2_SHIFT) +# define DMAC_SREQ_SSREQ3 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ3_SHIFT) +#define DMAC_SREQ_DSREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination single transfer */ +# define DMAC_SREQ_DSREQ(n) (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ_SHIFT(n)))) +# define DMAC_SREQ_DSREQ0 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ0_SHIFT) +# define DMAC_SREQ_DSREQ1 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ1_SHIFT) +# define DMAC_SREQ_DSREQ2 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ2_SHIFT) +# define DMAC_SREQ_DSREQ3 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ3_SHIFT) + +/* DMAC Software Chunk Transfer Request Register */ + +#define DMAC_CREQ_SHIFT(n) ((n)<<1) +#define DMAC_CREQ_MASK(n) (3 << DMAC_CREQ_SHIFT(n)) +#define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT) +#define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT) +#define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT) +#define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT) + +#define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */ +# define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n))) +# define DMAC_CREQ_SCREQ0 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ0_SHIFT)) +# define DMAC_CREQ_SCREQ1 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ1_SHIFT)) +# define DMAC_CREQ_SCREQ2 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ2_SHIFT)) +# define DMAC_CREQ_SCREQ3 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ3_SHIFT)) +#define DMAC_CREQ_DCREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination chunk transfer */ +# define DMAC_CREQ_DCREQ(n) (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ_SHIFT(n))) +# define DMAC_CREQ_DCREQ0 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ0_SHIFT)) +# define DMAC_CREQ_DCREQ1 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ1_SHIFT)) +# define DMAC_CREQ_DCREQ2 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ2_SHIFT)) +# define DMAC_CREQ_DCREQ3 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ3_SHIFT)) + +/* DMAC Software Last Transfer Flag Register */ + +#define DMAC_LAST_SHIFT(n) ((n)<<1) +#define DMAC_LAST_MASK(n) (3 << DMAC_LAST_SHIFT(n)) +#define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT) +#define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT) +#define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT) +#define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT) + +#define DMAC_LAST_SLAST_SHIFT (0) /* Bits 0, 2, 4, 6: Indicates the last transfer */ +# define DMAC_LAST_SLAST(n) (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST_SHIFT(n))) +# define DMAC_LAST_SLAST0 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST0_SHIFT) +# define DMAC_LAST_SLAST1 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST1_SHIFT) +# define DMAC_LAST_SLAST2 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST2_SHIFT) +# define DMAC_LAST_SLAST3 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST3_SHIFT) +#define DMAC_LAST_DLAST_SHIFT (1) /* Bits 1, 3, 5, 7: Indicates the last transfer */ +# define DMAC_LAST_DLAST(n) (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST_SHIFT(n)))) +# define DMAC_LAST_DLAST0 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST0_SHIFT) +# define DMAC_LAST_DLAST1 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST1_SHIFT) +# define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT) +# define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT) + +/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common + * bit field definitions + */ + +#define DMAC_EBC_BTC_SHIFT (0) /* Bits 0-3: Buffer Transfer Completed Interrupt Enable */ +#define DMAC_EBC_BTC_MASK (15 << DMAC_EBC_BTC_SHIFT) +# define DMAC_EBC_BTC(n) (1 << (DMAC_EBC_BTC_SHIFT+(n))) +# define DMAC_EBC_BTC0 (1 << (DMAC_EBC_BTC_SHIFT+0)) +# define DMAC_EBC_BTC1 (1 << (DMAC_EBC_BTC_SHIFT+1)) +# define DMAC_EBC_BTC2 (1 << (DMAC_EBC_BTC_SHIFT+2)) +# define DMAC_EBC_BTC3 (1 << (DMAC_EBC_BTC_SHIFT+3)) +#define DMAC_EBC_CBTC_SHIFT (8) /* Bits 8-11: Chained Buffer Transfer Completed Interrupt Enable */ +#define DMAC_EBC_CBTC_MASK (15 << DMAC_EBC_CBTC_SHIFT) +# define DMAC_EBC_CBTC(n) (1 << (DMAC_EBC_CBTC_SHIFT+(n))) +# define DMAC_EBC_CBTC0 (1 << (DMAC_EBC_CBTC_SHIFT+0)) +# define DMAC_EBC_CBTC1 (1 << (DMAC_EBC_CBTC_SHIFT+1)) +# define DMAC_EBC_CBTC2 (1 << (DMAC_EBC_CBTC_SHIFT+2)) +# define DMAC_EBC_CBTC3 (1 << (DMAC_EBC_CBTC_SHIFT+3)) +#define DMAC_EBC_ERR_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ +#define DMAC_EBC_ERR_MASK (15 << DMAC_EBC_ERR_SHIFT) +# define DMAC_EBC_ERR(n) (1 << (DMAC_EBC_ERR_SHIFT+(n))) +# define DMAC_EBC_ERR0 (1 << (DMAC_EBC_ERR_SHIFT+0)) +# define DMAC_EBC_ERR1 (1 << (DMAC_EBC_ERR_SHIFT+1)) +# define DMAC_EBC_ERR2 (1 << (DMAC_EBC_ERR_SHIFT+2)) +# define DMAC_EBC_ERR3 (1 << (DMAC_EBC_ERR_SHIFT+3)) + +#define DMAC_EBC_BTCINTS(n) (0x00010001 << (n)) /* BTC + ERR interrupts */ +#define DMAC_EBC_CBTCINTS(n) (0x00010100 << (n)) /* CBT + ERR interrupts */ +#define DMAC_EBC_CHANINTS(n) (0x00010101 << (n)) /* All channel interrupts */ +#define DMAC_EBC_ALLINTS (0x000f0f0f) /* All interrupts */ + +/* DMAC Channel Handler Enable Register */ + +#define DMAC_CHER_ENA_SHIFT (0) /* Bits 0-3: Enable channel */ +#define DMAC_CHER_ENA_MASK (15 << DMAC_CHER_ENA_SHIFT) +# define DMAC_CHER_ENA(n) (1 << (DMAC_CHER_ENA_SHIFT+(n))) +# define DMAC_CHER_ENA0 (1 << (DMAC_CHER_ENA_SHIFT+0)) +# define DMAC_CHER_ENA1 (1 << (DMAC_CHER_ENA_SHIFT+1)) +# define DMAC_CHER_ENA2 (1 << (DMAC_CHER_ENA_SHIFT+2)) +# define DMAC_CHER_ENA3 (1 << (DMAC_CHER_ENA_SHIFT+3)) +#define DMAC_CHER_SUSP_SHIFT (8) /* Bits 8-11: Freeze channel and its context */ +#define DMAC_CHER_SUSP_MASK (15 << DMAC_CHER_SUSP_SHIFT) +# define DMAC_CHER_SUSP(n) (1 << (DMAC_CHER_SUSP_SHIFT+(n))) +# define DMAC_CHER_SUSP0 (1 << (DMAC_CHER_SUSP_SHIFT+0)) +# define DMAC_CHER_SUSP1 (1 << (DMAC_CHER_SUSP_SHIFT+1)) +# define DMAC_CHER_SUSP2 (1 << (DMAC_CHER_SUSP_SHIFT+2)) +# define DMAC_CHER_SUSP3 (1 << (DMAC_CHER_SUSP_SHIFT+3)) +#define DMAC_CHER_KEEP_SHIFT (24) /* Bits 24-27: Resume channel from automatic stall */ +#define DMAC_CHER_KEEP_MASK (15 << DMAC_CHER_KEEP_SHIFT) +# define DMAC_CHER_KEEP(n) (1 << (DMAC_CHER_KEEP_SHIFT+(n))) +# define DMAC_CHER_KEEP0 (1 << (DMAC_CHER_KEEP_SHIFT+0)) +# define DMAC_CHER_KEEP1 (1 << (DMAC_CHER_KEEP_SHIFT+1)) +# define DMAC_CHER_KEEP2 (1 << (DMAC_CHER_KEEP_SHIFT+2)) +# define DMAC_CHER_KEEP3 (1 << (DMAC_CHER_KEEP_SHIFT+3)) + +/* DMAC Channel Handler Disable Register */ + +#define DMAC_CHDR_DIS_SHIFT (0) /* Bits 0-3: Disable DMAC channel */ +#define DMAC_CHDR_DIS_MASK (15 << DMAC_CHDR_DIS_SHIFT) +# define DMAC_CHDR_DIS(n) (1 << (DMAC_CHDR_DIS_SHIFT+(n))) +# define DMAC_CHDR_DIS0 (1 << (DMAC_CHDR_DIS_SHIFT+0)) +# define DMAC_CHDR_DIS1 (1 << (DMAC_CHDR_DIS_SHIFT+1)) +# define DMAC_CHDR_DIS2 (1 << (DMAC_CHDR_DIS_SHIFT+2)) +# define DMAC_CHDR_DIS3 (1 << (DMAC_CHDR_DIS_SHIFT+3)) +# define DMAC_CHDR_DIS_ALL DMAC_CHDR_DIS_MASK +#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-11: Resume trasnfer, restoring context */ +#define DMAC_CHDR_RES_MASK (15 << DMAC_CHDR_RES_SHIFT) +# define DMAC_CHDR_RES(n) (1 << (DMAC_CHDR_RES_SHIFT+(n))) +# define DMAC_CHDR_RES0 (1 << (DMAC_CHDR_RES_SHIFT+0)) +# define DMAC_CHDR_RES1 (1 << (DMAC_CHDR_RES_SHIFT+1)) +# define DMAC_CHDR_RES2 (1 << (DMAC_CHDR_RES_SHIFT+2)) +# define DMAC_CHDR_RES3 (1 << (DMAC_CHDR_RES_SHIFT+3)) + +/* DMAC Channel Handler Status Register */ + +#define DMAC_CHSR_ENA_SHIFT (0) /* Bits 0-3: Indicates that the channel is stalling */ +#define DMAC_CHSR_ENA_MASK (15 << DMAC_CHSR_ENA_SHIFT) +# define DMAC_CHSR_ENA(n) (1 << (DMAC_CHSR_ENA_SHIFT+(n))) +# define DMAC_CHSR_ENA0 (1 << (DMAC_CHSR_ENA_SHIFT+0)) +# define DMAC_CHSR_ENA1 (1 << (DMAC_CHSR_ENA_SHIFT+1)) +# define DMAC_CHSR_ENA2 (1 << (DMAC_CHSR_ENA_SHIFT+2)) +# define DMAC_CHSR_ENA3 (1 << (DMAC_CHSR_ENA_SHIFT+3)) +#define DMAC_CHSR_SUSP_SHIFT (8) /* Bits 8-11: Indicates that the channel is empty */ +#define DMAC_CHSR_SUSP_MASK (15 << DMAC_CHSR_SUSP_SHIFT) +# define DMAC_CHSR_SUSP(n) (1 << (DMAC_CHSR_SUSP_SHIFT+(n))) +# define DMAC_CHSR_SUSP0 (1 << (DMAC_CHSR_SUSP_SHIFT+0)) +# define DMAC_CHSR_SUSP1 (1 << (DMAC_CHSR_SUSP_SHIFT+1)) +# define DMAC_CHSR_SUSP2 (1 << (DMAC_CHSR_SUSP_SHIFT+2)) +# define DMAC_CHSR_SUSP3 (1 << (DMAC_CHSR_SUSP_SHIFT+3)) +#define DMAC_CHSR_EMPT_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ +#define DMAC_CHSR_EMPT_MASK (15 << DMAC_CHSR_EMPT_SHIFT) +# define DMAC_CHSR_EMPT(n) (1 << (DMAC_CHSR_EMPT_SHIFT+(n))) +# define DMAC_CHSR_EMPT0 (1 << (DMAC_CHSR_EMPT_SHIFT+0)) +# define DMAC_CHSR_EMPT1 (1 << (DMAC_CHSR_EMPT_SHIFT+1)) +# define DMAC_CHSR_EMPT2 (1 << (DMAC_CHSR_EMPT_SHIFT+2)) +# define DMAC_CHSR_EMPT3 (1 << (DMAC_CHSR_EMPT_SHIFT+3)) +#define DMAC_CHSR_STAL_SHIFT (24) /* Bits 24-27: Access Error Interrupt Enable */ +#define DMAC_CHSR_STAL_MASK (15 << DMAC_CHSR_STAL_SHIFT) +# define DMAC_CHSR_STAL(n) (1 << (DMAC_CHSR_STAL_SHIFT+(n))) +# define DMAC_CHSR_STAL0 (1 << (DMAC_CHSR_STAL_SHIFT+0)) +# define DMAC_CHSR_STAL1 (1 << (DMAC_CHSR_STAL_SHIFT+1)) +# define DMAC_CHSR_STAL2 (1 << (DMAC_CHSR_STAL_SHIFT+2)) +# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3)) + +/* DMA channel registers */ +/* DMAC Channel n [n = 0..3] Control A Register */ + +#define DMACHAN_CTRLA_BTSIZE_MAX (0xfff) +#define DMACHAN_CTRLA_BTSIZE_SHIFT (0) /* Bits 0-11: Buffer Transfer Size */ +#define DMACHAN_CTRLA_BTSIZE_MASK (DMACHAN_CTRLA_BTSIZE_MAX << DMACHAN_CTRLA_BTSIZE_SHIFT) +#define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */ +# define DMACHAN_CTRLA_SCSIZE_1 (0) +# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE +#define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */ +# define DMACHAN_CTRLA_DCSIZE_1 (0) +# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE +#define DMACHAN_CTRLA_SRCWIDTH_SHIFT (24) /* Bits 24-25 */ +#define DMACHAN_CTRLA_SRCWIDTH_MASK (3 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_BYTE (0 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_HWORD (1 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_WORD (2 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +#define DMACHAN_CTRLA_DSTWIDTH_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CTRLA_DSTWIDTH_MASK (3 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_BYTE (0 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_HWORD (1 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_WORD (2 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +#define DMACHAN_CTRLA_DONE (1 << 31) /* Bit 31: Auto disable DMAC */ + +/* DMAC Channel n [n = 0..3] Control B Register */ + +#define DMACHAN_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */ +#define DMACHAN_CTRLB_DSTDSCR (1 << 20) /* Bit 20: Dest buffer descriptor fetch operation disabled */ +#define DMACHAN_CTRLB_FC_SHIFT (21) /* Bits 21-22: Flow controller */ +#define DMACHAN_CTRLB_FC_MASK (3 << DMACHAN_CTRLB_FC_SHIFT) +# define DMACHAN_CTRLB_FC_M2M (0 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Memory */ +# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */ +# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */ +# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */ +#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ +#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT) +# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */ +# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */ +#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT) +# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */ +# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */ +#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */ + +/* DMAC Channel n [n = 0..3] Configuration Register */ + +#define DMACHAN_CFG_SRCPER_SHIFT (0) /* Bits 0-3: Channel source associated with peripheral ID */ +#define DMACHAN_CFG_SRCPER_MASK (15 << DMACHAN_CFG_SRCPER_SHIFT) +#define DMACHAN_CFG_DSTPER_SHIFT (4) /* Bits 4-7: Channel dest associated with peripheral ID */ +#define DMACHAN_CFG_DSTPER_MASK (15 << DMACHAN_CFG_DSTPER_SHIFT) +#define DMACHAN_CFG_SRCH2SEL (1 << 9) /* Bit 9: HW handshake triggers transfer */ +#define DMACHAN_CFG_DSTH2SEL (1 << 13) /* Bit 13: HW handshake trigger transfer */ +#define DMACHAN_CFG_SOD (1 << 16) /* Bit 16: Stop on done */ +#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */ +#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */ +#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */ +#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */ +#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT) +#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT) +# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */ +# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */ +# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */ + +/* DMA Peripheral IDs *******************************************************************/ + +#define DMACHAN_PID_MCI0 0 +#define DMACHAN_PID_SSC 3 +#define DMACHAN_PID_MCI1 13 + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/* DMA multi buffer transfer link list entry structure */ + +struct dma_linklist_s +{ + uint32_t src; /* Source address */ + uint32_t dest; /* Destination address */ + uint32_t ctrla; /* Control A value */ + uint32_t ctrlb; /* Control B value */ + uint32_t next; /* Next descriptor address */ +}; + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_eefc.h b/nuttx/arch/arm/src/sam34/chip/sam_eefc.h new file mode 100644 index 000000000..546b6334c --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_eefc.h @@ -0,0 +1,120 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_eefc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* EEFC register offsets ****************************************************************/ + +#define SAM_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */ +#define SAM_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */ +#define SAM_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */ +#define SAM_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */ + +/* EEFC register adresses ***************************************************************/ + +#define SAM_EEFC_FMR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FMR_OFFSET) +#define SAM_EEFC_FCR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FCR_OFFSET) +#define SAM_EEFC_FSR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FSR_OFFSET) +#define SAM_EEFC_FRR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FRR_OFFSET) + +#define SAM_EEFC0_FMR (SAM_EEFC0_BASE+SAM_EEFC_FMR_OFFSET) +#define SAM_EEFC0_FCR (SAM_EEFC0_BASE+SAM_EEFC_FCR_OFFSET) +#define SAM_EEFC0_FSR (SAM_EEFC0_BASE+SAM_EEFC_FSR_OFFSET) +#define SAM_EEFC0_FRR (SAM_EEFC0_BASE+SAM_EEFC_FRR_OFFSET) + +#define SAM_EEFC1_FMR (SAM_EEFC1_BASE+SAM_EEFC_FMR_OFFSET) +#define SAM_EEFC1_FCR (SAM_EEFC1_BASE+SAM_EEFC_FCR_OFFSET) +#define SAM_EEFC1_FSR (SAM_EEFC1_BASE+SAM_EEFC_FSR_OFFSET) +#define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET) + +/* EEFC register bit definitions ********************************************************/ + +#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ +#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */ +#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT) +#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */ + +#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */ +#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT) +# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */ +# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */ +# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */ +# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */ +# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */ +# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */ +# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */ +# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */ +# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */ +# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */ +# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */ +# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */ +# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */ +# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */ +#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ +#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) +#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */ +#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT) + +#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */ +#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_gpbr.h b/nuttx/arch/arm/src/sam34/chip/sam_gpbr.h new file mode 100644 index 000000000..f439be79a --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_gpbr.h @@ -0,0 +1,90 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_gpbr.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_GPBR_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_GPBR_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* GPBR register offsets ****************************************************************/ + +#define SAM_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */ +#define SAM_GPBR0_OFFSET 0x00 +#define SAM_GPBR1_OFFSET 0x04 +#define SAM_GPBR2_OFFSET 0x08 +#define SAM_GPBR3_OFFSET 0x0c +#define SAM_GPBR4_OFFSET 0x10 +#define SAM_GPBR5_OFFSET 0x14 +#define SAM_GPBR6_OFFSET 0x18 +#define SAM_GPBR7_OFFSET 0x1c + +/* GPBR register adresses ***************************************************************/ + +#define SAM_GPBR(n)) (SAM_GPBR_BASE+SAM_GPBR_OFFSET(n)) +#define SAM_GPBR0 (SAM_GPBR_BASE+SAM_GPBR0_OFFSET) +#define SAM_GPBR1 (SAM_GPBR_BASE+SAM_GPBR1_OFFSET) +#define SAM_GPBR2 (SAM_GPBR_BASE+SAM_GPBR2_OFFSET) +#define SAM_GPBR3 (SAM_GPBR_BASE+SAM_GPBR3_OFFSET) +#define SAM_GPBR4 (SAM_GPBR_BASE+SAM_GPBR4_OFFSET) +#define SAM_GPBR5 (SAM_GPBR_BASE+SAM_GPBR5_OFFSET) +#define SAM_GPBR6 (SAM_GPBR_BASE+SAM_GPBR6_OFFSET) +#define SAM_GPBR7 (SAM_GPBR_BASE+SAM_GPBR7_OFFSET) + +/* GPBR register bit definitions ********************************************************/ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_GPBR_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h new file mode 100644 index 000000000..dfee208c3 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h @@ -0,0 +1,297 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_hsmci.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_HSMCI_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_HSMCI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* HSMCI register offsets ***************************************************************/ + +#define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */ +#define SAM_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */ +#define SAM_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */ +#define SAM_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */ +#define SAM_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */ +#define SAM_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */ +#define SAM_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */ +#define SAM_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */ +#define SAM_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */ +#define SAM_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */ +#define SAM_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */ +#define SAM_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */ +#define SAM_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */ + /* 0x0038-0x003c: Reserved */ +#define SAM_HSMCI_SR_OFFSET 0x0040 /* Status Register */ +#define SAM_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */ +#define SAM_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */ +#define SAM_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */ +#define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ +#define SAM_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */ + /* 0x0058-0x00e0: Reserved */ +#define SAM_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */ +#define SAM_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ + /* 0x00ec-0x00fc: Reserved */ + /* 0x0100-0x0124: Reserved */ +#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ + +/* HSMCI register adresses **************************************************************/ + +#define SAM_HSMCI_CR (SAM_MCI_BASE+SAM_HSMCI_CR_OFFSET) +#define SAM_HSMCI_MR (SAM_MCI_BASE+SAM_HSMCI_MR_OFFSET) +#define SAM_HSMCI_DTOR (SAM_MCI_BASE+SAM_HSMCI_DTOR_OFFSET) +#define SAM_HSMCI_SDCR (SAM_MCI_BASE+SAM_HSMCI_SDCR_OFFSET) +#define SAM_HSMCI_ARGR (SAM_MCI_BASE+SAM_HSMCI_ARGR_OFFSET) +#define SAM_HSMCI_CMDR (SAM_MCI_BASE+SAM_HSMCI_CMDR_OFFSET) +#define SAM_HSMCI_BLKR (SAM_MCI_BASE+SAM_HSMCI_BLKR_OFFSET) +#define SAM_HSMCI_CSTOR (SAM_MCI_BASE+SAM_HSMCI_CSTOR_OFFSET) +#define SAM_HSMCI_RSPR0 (SAM_MCI_BASE+SAM_HSMCI_RSPR0_OFFSET) +#define SAM_HSMCI_RSPR1 (SAM_MCI_BASE+SAM_HSMCI_RSPR1_OFFSET) +#define SAM_HSMCI_RSPR2 (SAM_MCI_BASE+SAM_HSMCI_RSPR2_OFFSET) +#define SAM_HSMCI_RSPR3 (SAM_MCI_BASE+SAM_HSMCI_RSPR3_OFFSET) +#define SAM_HSMCI_RDR (SAM_MCI_BASE+SAM_HSMCI_RDR_OFFSET) +#define SAM_HSMCI_TDR (SAM_MCI_BASE+SAM_HSMCI_TDR_OFFSET) +#define SAM_HSMCI_SR (SAM_MCI_BASE+SAM_HSMCI_SR_OFFSET) +#define SAM_HSMCI_IER (SAM_MCI_BASE+SAM_HSMCI_IER_OFFSET) +#define SAM_HSMCI_IDR (SAM_MCI_BASE+SAM_HSMCI_IDR_OFFSET) +#define SAM_HSMCI_IMR (SAM_MCI_BASE+SAM_HSMCI_IMR_OFFSET) +#define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET) +#define SAM_HSMCI_CFG (SAM_MCI_BASE+SAM_HSMCI_CFG_OFFSET) +#define SAM_HSMCI_WPMR (SAM_MCI_BASE+SAM_HSMCI_WPMR_OFFSET) +#define SAM_HSMCI_WPSR (SAM_MCI_BASE+SAM_HSMCI_WPSR_OFFSET) +#define SAM_HSMCI_FIFO (SAM_MCI_BASE+SAM_HSMCI_FIFO_OFFSET) + +/* HSMCI register bit definitions *******************************************************/ + +/* HSMCI Control Register */ + +#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */ +#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ + +/* HSMCI Mode Register */ + +#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */ +#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */ +#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT) +# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT) +#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */ +#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */ +#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */ +#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */ +#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) + +/* HSMCI Data Timeout Register */ + +#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT) +# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT) +#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT) + +/* HSMCI SDCard/SDIO Register */ + +#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) +# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) +#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT) + +/* HSMCI Command Register */ + +#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */ +#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT) +#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */ +#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT) +# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */ +# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */ +# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */ +# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */ +#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */ +#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT) +# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */ +# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */ +# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */ +# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */ +# define HSMCI_CMDR_SPCMD_INTCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */ +# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */ +# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */ +# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */ +#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */ +#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */ +#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */ +#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT) +# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */ +# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */ +# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */ +#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */ +# define HSMCI_CMDR_TRDIR_WRITE (0 << 18) +# define HSMCI_CMDR_TRDIR_READ (1 << 18) +#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */ +#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT) +# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */ +# define HSMCI_CMDR_TRTYP_MULTI (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */ +# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */ +# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */ +# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT) +# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */ +# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ +# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ +#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */ + +/* HSMCI Block Register */ + +#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT) +#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT) + +/* HSMCI Completion Signal Timeout Register */ + +#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT) +#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) + +/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable + * Register, and HSMCI Interrupt Mask Register common bit-field definitions + */ + +#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */ +#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */ +#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */ +#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */ +#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */ +#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */ +#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */ +#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */ +#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */ +#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */ +#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */ +#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */ +#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */ +#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */ +#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */ +#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */ +#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */ +#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ +#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ +#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */ +#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */ +#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */ +#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */ +#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */ +#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */ + +/* HSMCI DMA Configuration Register */ + +#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ +#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) +#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ +#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ + +/* HSMCI Configuration Register */ + +#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */ +#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */ + +/* HSMCI Write Protect Mode Register */ + +#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */ +#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT) + +/* HSMCI Write Protect Status Register */ + +#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT) +#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_HSMCI_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_matrix.h b/nuttx/arch/arm/src/sam34/chip/sam_matrix.h new file mode 100644 index 000000000..6fed14092 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_matrix.h @@ -0,0 +1,214 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_matric.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* MATRIX register offsets **************************************************************/ + +#define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2) +#define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ +#define SAM_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */ +#define SAM_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */ +#define SAM_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */ +#define SAM_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */ + /* 0x0014-0x003c: Reserved */ +#define SAM_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2)) +#define SAM_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */ +#define SAM_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */ +#define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ +#define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ +#define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ +#define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ +#define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ +#define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ +#define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ +#define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ + /* 0x0068-0x007c: Reserved */ +#define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) +#define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ + /* 0x0084: Reserved */ +#define SAM_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */ + /* 0x008c: Reserved */ +#define SAM_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */ + /* 0x0094: Reserved */ +#define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ + /* 0x009c: Reserved */ +#define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ + /* 0x00a4: Reserved */ +#define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ + /* 0x00ac: Reserved */ +#define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ + /* 0x00b4: Reserved */ +#define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ + /* 0x00bc: Reserved */ +#define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ + /* 0x00c4: Reserved */ +#define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ + /* 0x00cc-0x00fc: Reserved */ +#define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ + /* 0x0104-0x010c: Reserved */ +#define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ +#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ + /* 0x0110 - 0x01fc: Reserved */ + +/* MATRIX register adresses *************************************************************/ + +#define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n)) +#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET) +#define SAM_MATRIX_MCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG1_OFFSET) +#define SAM_MATRIX_MCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET) +#define SAM_MATRIX_MCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET) +#define SAM_MATRIX_MCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET) + +#define SAM_MATRIX_SCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n)) +#define SAM_MATRIX_SCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET) +#define SAM_MATRIX_SCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG1_OFFSET) +#define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET) +#define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET) +#define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET) +#define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) +#define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) +#define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) +#define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) +#define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) + +#define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n)) +#define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET) +#define SAM_MATRIX_PRAS1 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS1_OFFSET) +#define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET) +#define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET) +#define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET) +#define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) +#define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) +#define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) +#define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) +#define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) + +#define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) +#define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) +#define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) + +/* MATRIX register bit definitions ******************************************************/ + +#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) +# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */ +# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */ +# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */ +# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */ +# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */ + +#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT) +#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ +#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */ +#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) + +#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */ +#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT) +# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */ +# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */ + +#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) +#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) +#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ +#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT) +#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */ +#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT) +#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */ +#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT) +#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */ +#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT) +#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */ +#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) + +#define MATRIX_MRCR_RCB(x) (1 << (x)) +#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ +#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ +#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ +#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ +#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ + +#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) + +#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ +#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h new file mode 100644 index 000000000..ad4a6018c --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_memorymap.h @@ -0,0 +1,53 @@ +/************************************************************************************ + * arch/arm/src/sam34/chip/sam_memorymap.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_memorymap.h" +#else +# Unrecognized SAM architecture +#endif + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MEMORYMAP_H */ + diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pdc.h b/nuttx/arch/arm/src/sam34/chip/sam_pdc.h new file mode 100644 index 000000000..40ae4e91a --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_pdc.h @@ -0,0 +1,103 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_pdc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PDC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PDC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PDC register offsets *****************************************************************/ + +#define SAM_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */ +#define SAM_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */ +#define SAM_PDC_TPR_OFFSET 0x108 /* Transmit Pointer Register */ +#define SAM_PDC_TCR_OFFSET 0x10c /* Transmit Counter Register */ +#define SAM_PDC_RNPR_OFFSET 0x110 /* Receive Next Pointer Register */ +#define SAM_PDC_RNCR_OFFSET 0x114 /* Receive Next Counter Register */ +#define SAM_PDC_TNPR_OFFSET 0x118 /* Transmit Next Pointer Register */ +#define SAM_PDC_TNCR_OFFSET 0x11c /* Transmit Next Counter Register */ +#define SAM_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */ +#define SAM_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */ + +/* PDC register adresses ****************************************************************/ + +/* These 10 registers are mapped in the peripheral memory space at the same offset. */ + +/* PDC register bit definitions *********************************************************/ + +#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */ +#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT) + +#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */ +#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT) + +#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */ +#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT) + +#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */ +#define PDC_TNCR_TXNCTR_MASK (0xffff << PDC_TNCR_TXNCTR_SHIFT) + +#define PDC_PTCR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ +#define PDC_PTCR_RXTDIS (1 << 1) /* Bit 1: Receiver Transfer Disable */ +#define PDC_PTCR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ +#define PDC_PTCR_TXTDIS (1 << 9) /* Bit 9: Transmitter Transfer Disable */ + +#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ +#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PDC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h new file mode 100644 index 000000000..2adfac974 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_pinmap.h @@ -0,0 +1,53 @@ +/************************************************************************************ + * arch/arm/src/sam34/chip/sam_pinmap.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_pinmap.h" +#else +# Unrecognized SAM architecture +#endif + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H */ + diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pio.h b/nuttx/arch/arm/src/sam34/chip/sam_pio.h new file mode 100644 index 000000000..f6cef564b --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_pio.h @@ -0,0 +1,324 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_pio.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PIO register offsets *****************************************************************/ + +#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ +#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ +#define SAM_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */ + /* 0x000c: Reserved */ +#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ +#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ +#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ + /* 0x001c: Reserved */ +#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ +#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ +#define SAM_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */ + /* 0x002c: Reserved */ +#define SAM_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */ +#define SAM_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */ +#define SAM_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */ +#define SAM_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */ +#define SAM_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */ +#define SAM_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */ +#define SAM_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */ +#define SAM_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */ +#define SAM_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */ +#define SAM_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */ +#define SAM_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */ + /* 0x005c: Reserved */ +#define SAM_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */ +#define SAM_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */ +#define SAM_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */ + /* 0x006c: Reserved */ +#define SAM_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */ + /* 0x0074-0x007c: Reserved */ +#define SAM_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */ +#define SAM_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */ +#define SAM_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ + /* 0x0090-0x009c: Reserved */ +#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ +#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ +#define SAM_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */ + /* 0x00ac: Reserved */ +#define SAM_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */ +#define SAM_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */ +#define SAM_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */ + /* 0x00bc: Reserved */ +#define SAM_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */ +#define SAM_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */ +#define SAM_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */ + /* 0x00cc: Reserved */ +#define SAM_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */ +#define SAM_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */ +#define SAM_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */ + /* 0x00dc: Reserved */ +#define SAM_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */ +#define SAM_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x00ec-0x00f8: Reserved */ + /* 0x0100-0x0144: Reserved */ + +/* PIO register adresses ****************************************************************/ + +#define PIOA (0) +#define PIOB (1) +#define PIOC (2) +#define NPIO (3) + +#define SAM_PIO_PER(n) (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET) +#define SAM_PIO_PDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET) +#define SAM_PIO_PSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET) +#define SAM_PIO_OER(n) (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET) +#define SAM_PIO_ODR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET) +#define SAM_PIO_OSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET) +#define SAM_PIO_IFER(n) (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET) +#define SAM_PIO_IFDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET) +#define SAM_PIO_IFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET) +#define SAM_PIO_SODR(n) (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET) +#define SAM_PIO_CODR(n) (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET) +#define SAM_PIO_ODSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET) +#define SAM_PIO_PDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET) +#define SAM_PIO_IER(n) (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET) +#define SAM_PIO_IDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET) +#define SAM_PIO_IMR(n) (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET) +#define SAM_PIO_ISR(n) (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET) +#define SAM_PIO_MDER(n) (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET) +#define SAM_PIO_MDDR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET) +#define SAM_PIO_MDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET) +#define SAM_PIO_PUDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET) +#define SAM_PIO_PUER(n) (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET) +#define SAM_PIO_PUSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET) +#define SAM_PIO_ABSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ABSR_OFFSET) +#define SAM_PIO_SCIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIO_DIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIO_IFDGSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIO_SCDR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET) +#define SAM_PIO_OWER(n) (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET) +#define SAM_PIO_OWDR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET) +#define SAM_PIO_OWSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET) +#define SAM_PIO_AIMER(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET) +#define SAM_PIO_AIMDR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIO_AIMMR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIO_ESR(n) (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET) +#define SAM_PIO_LSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET) +#define SAM_PIO_ELSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET) +#define SAM_PIO_FELLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIO_REHLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIO_FRLHSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIO_LOCKSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIO_WPMR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET) +#define SAM_PIO_WPSR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET) + +#define SAM_PIOA_PER (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOA_PDR (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOA_PSR (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOA_OER (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOA_ODR (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOA_OSR (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOA_IFER (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOA_IFDR (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOA_IFSR (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOA_SODR (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOA_CODR (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOA_ODSR (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOA_PDSR (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOA_IER (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOA_IDR (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOA_IMR (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOA_ISR (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOA_MDER (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOA_MDDR (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOA_MDSR (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOA_PUDR (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOA_PUER (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOA_PUSR (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOA_ABSR (SAM_PIOA_BASE+SAM_PIO_ABSR_OFFSET) +#define SAM_PIOA_SCIFSR (SAM_PIOA_BASE+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIOA_DIFSR (SAM_PIOA_BASE+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIOA_IFDGSR (SAM_PIOA_BASE+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIOA_SCDR (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOA_OWER (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOA_OWDR (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOA_OWSR (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOA_AIMER (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOA_AIMDR (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOA_AIMMR (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOA_ESR (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOA_LSR (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOA_ELSR (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOA_FELLSR (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOA_REHLSR (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOA_FRLHSR (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOA_LOCKSR (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOA_WPMR (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOA_WPSR (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET) + +#define SAM_PIOB_PER (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOB_PDR_ (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOB_PSR (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOB_OER (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOB_ODR (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOB_OSR (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOB_IFER (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOB_IFDR (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOB_IFSR (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOB_SODR (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOB_CODR (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOB_ODSR (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOB_PDSR (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOB_IER (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOB_IDR (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOB_IMR (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOB_ISR (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOB_MDER (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOB_MDDR (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOB_MDSR (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOB_PUDR (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOB_PUER (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOB_PUSR (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOB_ABSR (SAM_PIOB_BASE+SAM_PIO_ABSR_OFFSET) +#define SAM_PIOB_SCIFSR (SAM_PIOB_BASE+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIOB_DIFSR (SAM_PIOB_BASE+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIOB_IFDGSR (SAM_PIOB_BASE+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIOB_SCDR (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOB_OWER (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOB_OWDR (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOB_OWSR (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOB_AIMER (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOB_AIMDR (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOB_AIMMR (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOB_ESR (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOB_LSR (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOB_ELSR (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOB_FELLSR (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOB_REHLSR (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOB_FRLHSR (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOB_LOCKSR (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOB_WPMR (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOB_WPSR (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET) + +#define SAM_PIOC_PER (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET) +#define SAM_PIOC_PDR_ (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET) +#define SAM_PIOC_PSR (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET) +#define SAM_PIOC_OER (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET) +#define SAM_PIOC_ODR (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET) +#define SAM_PIOC_OSR (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET) +#define SAM_PIOC_IFER (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET) +#define SAM_PIOC_IFDR (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET) +#define SAM_PIOC_IFSR (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET) +#define SAM_PIOC_SODR (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET) +#define SAM_PIOC_CODR (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET) +#define SAM_PIOC_ODSR (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET) +#define SAM_PIOC_PDSR (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET) +#define SAM_PIOC_IER (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET) +#define SAM_PIOC_IDR (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET) +#define SAM_PIOC_IMR (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET) +#define SAM_PIOC_ISR (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET) +#define SAM_PIOC_MDER (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET) +#define SAM_PIOC_MDDR (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET) +#define SAM_PIOC_MDSR (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET) +#define SAM_PIOC_PUDR (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET) +#define SAM_PIOC_PUER (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET) +#define SAM_PIOC_PUSR (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET) +#define SAM_PIOC_ABSR (SAM_PIOC_BASE+SAM_PIO_ABSR_OFFSET) +#define SAM_PIOC_SCIFSR (SAM_PIOC_BASE+SAM_PIO_SCIFSR_OFFSET) +#define SAM_PIOC_DIFSR (SAM_PIOC_BASE+SAM_PIO_DIFSR_OFFSET) +#define SAM_PIOC_IFDGSR (SAM_PIOC_BASE+SAM_PIO_IFDGSR_OFFSET) +#define SAM_PIOC_SCDR (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET) +#define SAM_PIOC_OWER (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET) +#define SAM_PIOC_OWDR (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET) +#define SAM_PIOC_OWSR (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET) +#define SAM_PIOC_AIMER (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET) +#define SAM_PIOC_AIMDR (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET) +#define SAM_PIOC_AIMMR (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET) +#define SAM_PIOC_ESR (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET) +#define SAM_PIOC_LSR (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET) +#define SAM_PIOC_ELSR (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET) +#define SAM_PIOC_FELLSR (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET) +#define SAM_PIOC_REHLSR (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET) +#define SAM_PIOC_FRLHSR (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET) +#define SAM_PIOC_LOCKSR (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET) +#define SAM_PIOC_WPMR (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET) +#define SAM_PIOC_WPSR (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET) + +/* PIO register bit definitions *********************************************************/ + +/* Common bit definitions for ALMOST all IO registers (exceptions follow) */ + +#define PIO(n) (1<<(n)) /* Bit n: PIO n */ + +/* PIO Write Protect Mode Register */ + +#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */ +#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */ +#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT) + +/* PIO Write Protect Status Register */ + +#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */ +#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PIO_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam_pmc.h new file mode 100644 index 000000000..f6a98e3ee --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_pmc.h @@ -0,0 +1,315 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_pmc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PMC register offsets *****************************************************************/ + +#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ +#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ +#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ + /* 0x000c: Reserved */ +#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ +#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ +#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ +#define SAM_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ +#define SAM_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ +#define SAM_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ +#define SAM_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ + /* 0x002c: Reserved */ +#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ + /* 0x0034-0x003C Reserved */ +#define SAM_PMC_PCK_OFFSET(n) (0x0040+((n)<<2)) +#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ +#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ +#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ + /* 0x004c-0x005c: Reserved */ +#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ +#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ +#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ +#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ +#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ +#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ +#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ + /* 0x007c-0x00fc: Reserved */ +#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + +/* PMC register adresses ****************************************************************/ + +#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) +#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) +#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) +#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) +#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) +#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) +#define SAM_CKGR_UCKR (SAM_PMC_BASE+SAM_CKGR_UCKR_OFFSET) +#define SAM_CKGR_MOR (SAM_PMC_BASE+SAM_CKGR_MOR_OFFSET) +#define SAM_CKGR_MCFR (SAM_PMC_BASE+SAM_CKGR_MCFR_OFFSET) +#define SAM_CKGR_PLLAR (SAM_PMC_BASE+SAM_CKGR_PLLAR_OFFSET) +#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET) +#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n)) +#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET) +#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET) +#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET) +#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET) +#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET) +#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET) +#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET) +#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET) +#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET) +#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET) +#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET) +#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET) + +/* PMC register bit definitions *********************************************************/ + +/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System + * Clock Status Register common bit-field definitions + */ + +#define PMC_PCK(n) (1 <<((n)+8) +#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ +#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ +#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ + +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC + * Peripheral Clock Status Register common bit-field definitions. + */ + +#define PMC_PID(n) (1<<(n)) +#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ +#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ +#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ +#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ +#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ +#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ +#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ +#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ +#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ +#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ +#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ +#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ +#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ +#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ +#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ +#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ +#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ +#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ +#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ +#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ +#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ +#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ +#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ +#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ +#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ +#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ +#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ +#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ +#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ +#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ + +/* PMC UTMI Clock Configuration Register */ + +#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT) + +/* PMC Clock Generator Main Oscillator Register */ + +#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ +#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT) +#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT) +#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ +#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT) +#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ + +/* PMC Clock Generator Main Clock Frequency Register */ + +#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ +#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT) +#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ + +/* PMC Clock Generator PLLA Register */ + +#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */ +#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT) +# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */ +# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */ +# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */ +#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) +#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ +#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT) +# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ +# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ +#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT) +#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ + +/* PMC Master Clock Register */ + +#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ +#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) +# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ +# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ +# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ +#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ +#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) +# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ +# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ +# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ +#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ + +/* PMC Programmable Clock Register (0,1,2) */ + +#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ +#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) +# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ +# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ +# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ +# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ +# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */ +#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ + +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, + * and PMC Interrupt Mask Register common bit-field definitions + */ + +#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ +#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ +#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ +#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ +#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ +#define PMC_INT_PCKRDY(n) (1 << ((n)+8) +#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ +#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ +#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ +#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ +#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ +#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ +#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ + +/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field + * definitions + */ + +#define PMC_FSTI(n) (1 << (n)) +#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ +#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ +#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ +#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ +#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ +#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ +#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ +#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ +#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ +#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ +#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ +#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ +#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ +#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ +#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ +#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ + +#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ +#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ +#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ +#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ + +/* PMC Fault Output Clear Register */ + +#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ + +/* PMC Write Protect Mode Register */ + +#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) + +/* PMC Write Protect Status Register */ + +#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pwm.h b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h new file mode 100644 index 000000000..fe3bf04a1 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h @@ -0,0 +1,633 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_pwm.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PWM_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PWM_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PWM register offsets *****************************************************************/ + +#define SAM_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */ +#define SAM_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */ +#define SAM_PWM_DIS_OFFSET 0x008 /* PWM Disable Register */ +#define SAM_PWM_SR_OFFSET 0x00c /* PWM Status Register */ +#define SAM_PWM_IER1_OFFSET 0x010 /* PWM Interrupt Enable Register 1 */ +#define SAM_PWM_IDR1_OFFSET 0x014 /* PWM Interrupt Disable Register 1 */ +#define SAM_PWM_IMR1_OFFSET 0x018 /* PWM Interrupt Mask Register 1 */ +#define SAM_PWM_ISR1_OFFSET 0x01c /* PWM Interrupt Status Register 1 */ +#define SAM_PWM_SCM_OFFSET 0x020 /* PWM Sync Channels Mode Register */ + /* 0x024: Reserved */ +#define SAM_PWM_SCUC_OFFSET 0x028 /* PWM Sync Channels Update Control Register */ +#define SAM_PWM_SCUP_OFFSET 0x02c /* PWM Sync Channels Update Period Register */ +#define SAM_PWM_SCUPUPD_OFFSET 0x030 /* PWM Sync Channels Update Period Update Register */ +#define SAM_PWM_IER2_OFFSET 0x034 /* PWM Interrupt Enable Register 2 */ +#define SAM_PWM_IDR2_OFFSET 0x038 /* PWM Interrupt Disable Register 2 */ +#define SAM_PWM_IMR2_OFFSET 0x03c /* PWM Interrupt Mask Register 2 */ +#define SAM_PWM_ISR2_OFFSET 0x040 /* PWM Interrupt Status Register 2 */ +#define SAM_PWM_OOV_OFFSET 0x044 /* PWM Output Override Value Register */ +#define SAM_PWM_OS_OFFSET 0x048 /* PWM Output Selection Register */ +#define SAM_PWM_OSS_OFFSET 0x04c /* PWM Output Selection Set Register */ +#define SAM_PWM_OSC_OFFSET 0x050 /* PWM Output Selection Clear Register */ +#define SAM_PWM_OSSUPD_OFFSET 0x054 /* PWM Output Selection Set Update Register */ +#define SAM_PWM_OSCUPD_OFFSET 0x058 /* PWM Output Selection Clear Update Register */ +#define SAM_PWM_FMR_OFFSET 0x05c /* PWM Fault Mode Register */ +#define SAM_PWM_FSR_OFFSET 0x060 /* PWM Fault Status Register */ +#define SAM_PWM_FCR_OFFSET 0x064 /* PWM Fault Clear Register */ +#define SAM_PWM_FPV_OFFSET 0x068 /* PWM Fault Protection Value Register */ +#define SAM_PWM_FPE_OFFSET 0x06c /* PWM Fault Protection Enable Register */ + /* 0x070-0x078: Reserved */ +#define SAM_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */ +#define SAM_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */ + /* 0x084-0x0ac: Reserved */ + /* 0x0b4-0x0e0: Reserved */ +#define SAM_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */ +#define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */ + /* 0x100-0x128: Reserved for PDC registers */ + /* 0x12c: Reserved */ +/* PWM Comparison Registers */ + +#define SAM_PWMCMP_OFFSET(n) (0x130+((n)<<4)) +#define SAM_PWMCMP_V_OFFSET 0x00 /* PWM Comparison Value Register */ +#define SAM_PWMCMP_VUPD_OFFSET 0x04 /* PWM Comparison Value Update Register */ +#define SAM_PWMCMP_M_OFFSET 0x08 /* PWM Comparison Mode Register */ +#define SAM_PWMCMP_MUPD_OFFSET 0x0c /* PWM Comparison Mode Update Register */ + +#define SAM_PWMCMP0_V_OFFSET 0x130 /* PWM Comparison 0 Value Register */ +#define SAM_PWMCMP0_VUPD_OFFSET 0x134 /* PWM Comparison 0 Value Update Register */ +#define SAM_PWMCMP0_M_OFFSET 0x138 /* PWM Comparison 0 Mode Register */ +#define SAM_PWMCMP0_MUPD_OFFSET 0x13c /* PWM Comparison 0 Mode Update Register */ + +#define SAM_PWMCMP1_V_OFFSET 0x140 /* PWM Comparison 1 Value Register */ +#define SAM_PWMCMP1_VUPD_OFFSET 0x144 /* PWM Comparison 1 Value Update Register */ +#define SAM_PWMCMP1_M_OFFSET 0x148 /* PWM Comparison 1 Mode Register */ +#define SAM_PWMCMP1_MUPD_OFFSET 0x14c /* PWM Comparison 1 Mode Update Register */ + +#define SAM_PWMCMP2_V_OFFSET 0x150 /* PWM Comparison 2 Value Register */ +#define SAM_PWMCMP2_VUPD_OFFSET 0x154 /* PWM Comparison 2 Value Update Register */ +#define SAM_PWMCMP2_M_OFFSET 0x158 /* PWM Comparison 2 Mode Register */ +#define SAM_PWMCMP2_MUPD_OFFSET 0x15c /* PWM Comparison 2 Mode Update Register */ + +#define SAM_PWMCMP3_V_OFFSET 0x160 /* PWM Comparison 3 Value Register */ +#define SAM_PWMCMP3_VUPD_OFFSET 0x164 /* PWM Comparison 3 Value Update Register */ +#define SAM_PWMCMP3_M_OFFSET 0x168 /* PWM Comparison 3 Mode Register */ +#define SAM_PWMCMP3_MUPD_OFFSET 0x16c /* PWM Comparison 3 Mode Update Register */ + +#define SAM_PWMCMP4_V_OFFSET 0x170 /* PWM Comparison 4 Value Register */ +#define SAM_PWMCMP4_VUPD_OFFSET 0x174 /* PWM Comparison 4 Value Update Register */ +#define SAM_PWMCMP4_M_OFFSET 0x178 /* PWM Comparison 4 Mode Register */ +#define SAM_PWMCMP4_MUPD_OFFSET 0x17c /* PWM Comparison 4 Mode Update Register */ + +#define SAM_PWMCMP5_V_OFFSET 0x180 /* PWM Comparison 5 Value Register */ +#define SAM_PWMCMP5_VUPD_OFFSET 0x184 /* PWM Comparison 5 Value Update Register */ +#define SAM_PWMCMP5_M_OFFSET 0x188 /* PWM Comparison 5 Mode Register */ +#define SAM_PWMCMP5_MUPD_OFFSET 0x18c /* PWM Comparison 5 Mode Update Register */ + +#define SAM_PWMCMP6_V_OFFSET 0x190 /* PWM Comparison 6 Value Register */ +#define SAM_PWMCMP6_VUPD_OFFSET 0x194 /* PWM Comparison 6 Value Update Register */ +#define SAM_PWMCMP6_M_OFFSET 0x198 /* PWM Comparison 6 Mode Register */ +#define SAM_PWMCMP6_MUPD_OFFSET 0x19c /* PWM Comparison 6 Mode Update Register */ + +#define SAM_PWMCMP7_V_OFFSET 0x1a0 /* PWM Comparison 7 Value Register */ +#define SAM_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */ +#define SAM_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */ +#define SAM_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */ + /* 0x1b0-0x1fc: Reserved */ +/* PWM Channel Registers */ + +#define SAM_PWMCH_OFFSET(n) (0x200+((n)<< 5)) +#define SAM_PWMCH_MR_OFFSET 0x00 /* PWM Channel Mode Register */ +#define SAM_PWMCH_DTY_OFFSET 0x04 /* PWM Channel Duty Cycle Register */ +#define SAM_PWMCH_DTYUPD_OFFSET 0x08 /* PWM Channel Duty Cycle Update Register */ +#define SAM_PWMCH_PRD_OFFSET 0x0c /* PWM Channel Period Register */ +#define SAM_PWMCH_PRDUPD_OFFSET 0x10 /* PWM Channel Period Update Register */ +#define SAM_PWMCH_CCNT_OFFSET 0x14 /* PWM Channel Counter Register */ +#define SAM_PWMCH_DT_OFFSET 0x18 /* PWM Channel Dead Time Register */ +#define SAM_PWMCH_DTUPD_OFFSET 0x1c /* PWM Channel Dead Time Update Register */ + +#define SAM_PWMCH0_MR_OFFSET 0x200 /* PWM Channel 0 Mode Register */ +#define SAM_PWMCH0_DTY_OFFSET 0x204 /* PWM Channel 0 Duty Cycle Register */ +#define SAM_PWMCH0_DTYUPD_OFFSET 0x208 /* PWM Channel 0 Duty Cycle Update Register */ +#define SAM_PWMCH0_PRD_OFFSET 0x20c /* PWM Channel 0 Period Register */ +#define SAM_PWMCH0_PRDUPD_OFFSET 0x210 /* PWM Channel 0 Period Update Register */ +#define SAM_PWMCH0_CCNT_OFFSET 0x214 /* PWM Channel 0 Counter Register */ +#define SAM_PWMCH0_DT_OFFSET 0x218 /* PWM Channel 0 Dead Time Register */ +#define SAM_PWMCH0_DTUPD_OFFSET 0x21c /* PWM Channel 0 Dead Time Update Register */ + +#define SAM_PWMCH1_MR_OFFSET 0x220 /* PWM Channel 1 Mode Register */ +#define SAM_PWMCH1_DTY_OFFSET 0x224 /* PWM Channel 1 Duty Cycle Register */ +#define SAM_PWMCH1_DTYUPD_OFFSET 0x228 /* PWM Channel 1 Duty Cycle Update Register */ +#define SAM_PWMCH1_PRD_OFFSET 0x22c /* PWM Channel 1 Period Register */ +#define SAM_PWMCH1_PRDUPD_OFFSET 0x230 /* PWM Channel 1 Period Update Register */ +#define SAM_PWMCH1_CCNT_OFFSET 0x234 /* PWM Channel 1 Counter Register */ +#define SAM_PWMCH1_DT_OFFSET 0x238 /* PWM Channel 1 Dead Time Register */ +#define SAM_PWMCH1_DTUPD_OFFSET 0x23c /* PWM Channel 1 Dead Time Update Register */ + +#define SAM_PWMCH2_MR_OFFSET 0x240 /* PWM Channel 2 Mode Register */ +#define SAM_PWMCH2_DTY_OFFSET 0x244 /* PWM Channel 2 Duty Cycle Register */ +#define SAM_PWMCH2_DTYUPD_OFFSET 0x248 /* PWM Channel 2 Duty Cycle Update Register */ +#define SAM_PWMCH2_PRD_OFFSET 0x24c /* PWM Channel 2 Period Register */ +#define SAM_PWMCH2_PRDUPD_OFFSET 0x250 /* PWM Channel 2 Period Update Register */ +#define SAM_PWMCH2_CCNT_OFFSET 0x254 /* PWM Channel 2 Counter Register */ +#define SAM_PWMCH2_DT_OFFSET 0x258 /* PWM Channel 2 Dead Time Register */ +#define SAM_PWMCH2_DTUPD_OFFSET 0x25c /* PWM Channel 2 Dead Time Update Register */ + +#define SAM_PWMCH3_MR_OFFSET 0x260 /* PWM Channel 3 Mode Register */ +#define SAM_PWMCH3_DTY_OFFSET 0x264 /* PWM Channel 3 Duty Cycle Register */ +#define SAM_PWMCH3_DTYUPD_OFFSET 0x268 /* PWM Channel 3 Duty Cycle Update Register */ +#define SAM_PWMCH3_PRD_OFFSET 0x26c /* PWM Channel 3 Period Register */ +#define SAM_PWMCH3_PRDUPD_OFFSET 0x270 /* PWM Channel 3 Period Update Register */ +#define SAM_PWMCH3_CCNT_OFFSET 0x274 /* PWM Channel 3 Counter Register */ +#define SAM_PWMCH3_DT_OFFSET 0x278 /* PWM Channel 3 Dead Time Register */ +#define SAM_PWMCH3_DTUPD_OFFSET 0x27c /* PWM Channel 3 Dead Time Update Register */ + +/* PWM register adresses ****************************************************************/ + +#define SAM_PWM_CLK (SAM_PWM_BASE+SAM_PWM_CLK_OFFSET) +#define SAM_PWM_ENA (SAM_PWM_BASE+SAM_PWM_ENA_OFFSET) +#define SAM_PWM_DIS (SAM_PWM_BASE+SAM_PWM_DIS_OFFSET) +#define SAM_PWM_SR (SAM_PWM_BASE+SAM_PWM_SR_OFFSET) +#define SAM_PWM_IER1 (SAM_PWM_BASE+SAM_PWM_IER1_OFFSET) +#define SAM_PWM_IDR1 (SAM_PWM_BASE+SAM_PWM_IDR1_OFFSET) +#define SAM_PWM_IMR1 (SAM_PWM_BASE+SAM_PWM_IMR1_OFFSET) +#define SAM_PWM_ISR1 (SAM_PWM_BASE+SAM_PWM_ISR1_OFFSET) +#define SAM_PWM_SCM (SAM_PWM_BASE+SAM_PWM_SCM_OFFSET) +#define SAM_PWM_SCUC (SAM_PWM_BASE+SAM_PWM_SCUC_OFFSET) +#define SAM_PWM_SCUP (SAM_PWM_BASE+SAM_PWM_SCUP_OFFSET) +#define SAM_PWM_SCUPUPD (SAM_PWM_BASE+SAM_PWM_SCUPUPD_OFFSET) +#define SAM_PWM_IER2 (SAM_PWM_BASE+SAM_PWM_IER2_OFFSET) +#define SAM_PWM_IDR2 (SAM_PWM_BASE+SAM_PWM_IDR2_OFFSET) +#define SAM_PWM_IMR2 (SAM_PWM_BASE+SAM_PWM_IMR2_OFFSET) +#define SAM_PWM_ISR2 (SAM_PWM_BASE+SAM_PWM_ISR2_OFFSET) +#define SAM_PWM_OOV (SAM_PWM_BASE+SAM_PWM_OOV_OFFSET) +#define SAM_PWM_OS (SAM_PWM_BASE+SAM_PWM_OS_OFFSET) +#define SAM_PWM_OSS (SAM_PWM_BASE+SAM_PWM_OSS_OFFSET) +#define SAM_PWM_OSC (SAM_PWM_BASE+SAM_PWM_OSC_OFFSET) +#define SAM_PWM_OSSUPD (SAM_PWM_BASE+SAM_PWM_OSSUPD_OFFSET) +#define SAM_PWM_OSCUPD (SAM_PWM_BASE+SAM_PWM_OSCUPD_OFFSET) +#define SAM_PWM_FMR (SAM_PWM_BASE+SAM_PWM_FMR_OFFSET) +#define SAM_PWM_FSR (SAM_PWM_BASE+SAM_PWM_FSR_OFFSET) +#define SAM_PWM_FCR (SAM_PWM_BASE+SAM_PWM_FCR_OFFSET) +#define SAM_PWM_FPV (SAM_PWM_BASE+SAM_PWM_FPV_OFFSET) +#define SAM_PWM_FPE (SAM_PWM_BASE+SAM_PWM_FPE_OFFSET) +#define SAM_PWM_EL0MR (SAM_PWM_BASE+SAM_PWM_EL0MR_OFFSET) +#define SAM_PWM_EL1MR (SAM_PWM_BASE+SAM_PWM_EL1MR_OFFSET) +#define SAM_PWM_WPCR (SAM_PWM_BASE+SAM_PWM_WPCR_OFFSET) +#define SAM_PWM_WPSR (SAM_PWM_BASE+SAM_PWM_WPSR_OFFSET) + +/* PWM Comparison Registers */ + +#define SAM_PWCMP_BASE(n) (SAM_PWM_BASE+SAM_PWCMP_OFFSET(n)) +#define SAM_PWMCMP0_BASE (SAM_PWM_BASE+0x0130) +#define SAM_PWMCMP1_BASE (SAM_PWM_BASE+0x0140) +#define SAM_PWMCMP2_BASE (SAM_PWM_BASE+0x0150) +#define SAM_PWMCMP3_BASE (SAM_PWM_BASE+0x0160) +#define SAM_PWMCMP4_BASE (SAM_PWM_BASE+0x0170) +#define SAM_PWMCMP5_BASE (SAM_PWM_BASE+0x0180) +#define SAM_PWMCMP6_BASE (SAM_PWM_BASE+0x0190) +#define SAM_PWMCMP7_BASE (SAM_PWM_BASE+0x01a0) + +#define SAM_PWMCMP0_V (SAM_PWMCMP0_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP0_VUPD (SAM_PWMCMP0_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP0_M (SAM_PWMCMP0_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP0_MUPD (SAM_PWMCMP0_BASE+SAM_PWMCMP_MUPD_OFFSET) + +#define SAM_PWMCMP1_V (SAM_PWMCMP1_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP1_VUPD (SAM_PWMCMP1_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP1_M (SAM_PWMCMP1_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP1_MUPD (SAM_PWMCMP1_BASE+SAM_PWMCMP_MUPD_OFFSET) + +#define SAM_PWMCMP2_V (SAM_PWMCMP2_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP2_VUPD (SAM_PWMCMP2_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP2_M (SAM_PWMCMP2_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP2_MUPD (SAM_PWMCMP2_BASE+SAM_PWMCMP_MUPD_OFFSET) + +#define SAM_PWMCMP3_V (SAM_PWMCMP3_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP3_VUPD (SAM_PWMCMP3_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP3_M (SAM_PWMCMP3_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP3_MUPD (SAM_PWMCMP3_BASE+SAM_PWMCMP_MUPD_OFFSET) + +#define SAM_PWMCMP4_V (SAM_PWMCMP4_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP4_VUPD (SAM_PWMCMP4_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP4_M (SAM_PWMCMP4_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP4_MUPD (SAM_PWMCMP4_BASE+SAM_PWMCMP_MUPD_OFFSET) + +#define SAM_PWMCMP5_V (SAM_PWMCMP5_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP5_VUPD (SAM_PWMCMP5_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP5_M (SAM_PWMCMP5_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP5_MUPD (SAM_PWMCMP5_BASE+SAM_PWMCMP_MUPD_OFFSET) + +#define SAM_PWMCMP6_V (SAM_PWMCMP6_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP6_VUPD (SAM_PWMCMP6_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP6_M (SAM_PWMCMP6_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP6_MUPD (SAM_PWMCMP6_BASE+SAM_PWMCMP_MUPD_OFFSET) + +#define SAM_PWMCMP7_V (SAM_PWMCMP7_BASE+SAM_PWMCMP_V_OFFSET) +#define SAM_PWMCMP7_VUPD (SAM_PWMCMP7_BASE+SAM_PWMCMP_VUPD_OFFSET) +#define SAM_PWMCMP7_M (SAM_PWMCMP7_BASE+SAM_PWMCMP_M_OFFSET) +#define SAM_PWMCMP7_MUPD (SAM_PWMCMP7_BASE+SAM_PWMCMP_MUPD_OFFSET) + +/* PWM Channel Registers */ + +#define SAM_PWCH_BASE(n) (SAM_PWM_BASE+SAM_PWCH_OFFSET(n)) +#define SAM_PWMCH0_BASE (SAM_PWM_BASE+0x0200) +#define SAM_PWMCH1_BASE (SAM_PWM_BASE+0x0220) +#define SAM_PWMCH2_BASE (SAM_PWM_BASE+0x0240) +#define SAM_PWMCH3_BASE (SAM_PWM_BASE+0x0260) + +#define SAM_PWMCH0_MR (SAM_PWMCH0_BASE+SAM_PWMCH_MR_OFFSET) +#define SAM_PWMCH0_DTY (SAM_PWMCH0_BASE+SAM_PWMCH_DTY_OFFSET) +#define SAM_PWMCH0_DTYUPD (SAM_PWMCH0_BASE+SAM_PWMCH_DTYUPD_OFFSET) +#define SAM_PWMCH0_PRD (SAM_PWMCH0_BASE+SAM_PWMCH_PRD_OFFSET) +#define SAM_PWMCH0_PRDUPD (SAM_PWMCH0_BASE+SAM_PWMCH_PRDUPD_OFFSET) +#define SAM_PWMCH0_CCNT (SAM_PWMCH0_BASE+SAM_PWMCH_CCNT_OFFSET) +#define SAM_PWMCH0_DT (SAM_PWMCH0_BASE+SAM_PWMCH_DT_OFFSET) +#define SAM_PWMCH0_DTUPD (SAM_PWMCH0_BASE+SAM_PWMCH_DTUPD_OFFSET) + +#define SAM_PWMCH1_MR (SAM_PWMCH1_BASE+SAM_PWMCH_MR_OFFSET) +#define SAM_PWMCH1_DTY (SAM_PWMCH1_BASE+SAM_PWMCH_DTY_OFFSET) +#define SAM_PWMCH1_DTYUPD (SAM_PWMCH1_BASE+SAM_PWMCH_DTYUPD_OFFSET) +#define SAM_PWMCH1_PRD (SAM_PWMCH1_BASE+SAM_PWMCH_PRD_OFFSET) +#define SAM_PWMCH1_PRDUPD (SAM_PWMCH1_BASE+SAM_PWMCH_PRDUPD_OFFSET) +#define SAM_PWMCH1_CCNT (SAM_PWMCH1_BASE+SAM_PWMCH_CCNT_OFFSET) +#define SAM_PWMCH1_DT (SAM_PWMCH1_BASE+SAM_PWMCH_DT_OFFSET) +#define SAM_PWMCH1_DTUPD (SAM_PWMCH1_BASE+SAM_PWMCH_DTUPD_OFFSET) + +#define SAM_PWMCH2_MR (SAM_PWMCH2_BASE+SAM_PWMCH_MR_OFFSET) +#define SAM_PWMCH2_DTY (SAM_PWMCH2_BASE+SAM_PWMCH_DTY_OFFSET) +#define SAM_PWMCH2_DTYUPD (SAM_PWMCH2_BASE+SAM_PWMCH_DTYUPD_OFFSET) +#define SAM_PWMCH2_PRD (SAM_PWMCH2_BASE+SAM_PWMCH_PRD_OFFSET) +#define SAM_PWMCH2_PRDUPD (SAM_PWMCH2_BASE+SAM_PWMCH_PRDUPD_OFFSET) +#define SAM_PWMCH2_CCNT (SAM_PWMCH2_BASE+SAM_PWMCH_CCNT_OFFSET) +#define SAM_PWMCH2_DT (SAM_PWMCH2_BASE+SAM_PWMCH_DT_OFFSET) +#define SAM_PWMCH2_DTUPD (SAM_PWMCH2_BASE+SAM_PWMCH_DTUPD_OFFSET) + +#define SAM_PWMCH3_MR (SAM_PWMCH3_BASE+SAM_PWMCH_MR_OFFSET) +#define SAM_PWMCH3_DTY (SAM_PWMCH3_BASE+SAM_PWMCH_DTY_OFFSET) +#define SAM_PWMCH3_DTYUPD (SAM_PWMCH3_BASE+SAM_PWMCH_DTYUPD_OFFSET) +#define SAM_PWMCH3_PRD (SAM_PWMCH3_BASE+SAM_PWMCH_PRD_OFFSET) +#define SAM_PWMCH3_PRDUPD (SAM_PWMCH3_BASE+SAM_PWMCH_PRDUPD_OFFSET) +#define SAM_PWMCH3_CCNT (SAM_PWMCH3_BASE+SAM_PWMCH_CCNT_OFFSET) +#define SAM_PWMCH3_DT (SAM_PWMCH3_BASE+SAM_PWMCH_DT_OFFSET) +#define SAM_PWMCH3_DTUPD (SAM_PWMCH3_BASE+SAM_PWMCH_DTUPD_OFFSET) + +/* PWM register bit definitions *********************************************************/ + +/* PWM Clock Register */ + +#define PWM_CLK_DIVA_SHIFT (0) /* Bits 0-7: CLKA Divide Factor */ +#define PWM_CLK_DIVA_MASK (0xff << PWM_CLK_DIVA_SHIFT) +#define PWM_CLK_PREA_SHIFT (8) /* Bits 8-11: CLKA Source Clock Selection */ +#define PWM_CLK_PREA_MASK (15 << PWM_CLK_PREA_SHIFT) +# define PWM_CLK_PREA_MCK (0 << PWM_CLK_PREA_SHIFT) /* MCK */ +# define PWM_CLK_PREA_MCKDIV2 (1 << PWM_CLK_PREA_SHIFT) /* MCK/2 */ +# define PWM_CLK_PREA_MCKDIV4 (2 << PWM_CLK_PREA_SHIFT) /* MCK/4 */ +# define PWM_CLK_PREA_MCKDIV8 (3 << PWM_CLK_PREA_SHIFT) /* MCK/8 */ +# define PWM_CLK_PREA_MCKDIV16 (4 << PWM_CLK_PREA_SHIFT) /* MCK/16 */ +# define PWM_CLK_PREA_MCKDIV32 (5 << PWM_CLK_PREA_SHIFT) /* MCK/32 */ +# define PWM_CLK_PREA_MCKDIV64 (6 << PWM_CLK_PREA_SHIFT) /* MCK/64 */ +# define PWM_CLK_PREA_MCKDIV128 (7 << PWM_CLK_PREA_SHIFT) /* MCK/128 */ +# define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */ +# define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */ +# define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */ +#define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ +#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT) +#define PWM_CLK_PREB_SHIFT (24) /* Bit 24-27: CLKB Source Clock Selection */ +#define PWM_CLK_PREB_MASK (15 << PWM_CLK_PREB_SHIFT) +# define PWM_CLK_PREB_MCK (0 << PWM_CLK_PREB_SHIFT) /* MCK */ +# define PWM_CLK_PREB_MCKDIV2 (1 << PWM_CLK_PREB_SHIFT) /* MCK/2 */ +# define PWM_CLK_PREB_MCKDIV4 (2 << PWM_CLK_PREB_SHIFT) /* MCK/4 */ +# define PWM_CLK_PREB_MCKDIV8 (3 << PWM_CLK_PREB_SHIFT) /* MCK/8 */ +# define PWM_CLK_PREB_MCKDIV16 (4 << PWM_CLK_PREB_SHIFT) /* MCK/16 */ +# define PWM_CLK_PREB_MCKDIV32 (5 << PWM_CLK_PREB_SHIFT) /* MCK/32 */ +# define PWM_CLK_PREB_MCKDIV64 (6 << PWM_CLK_PREB_SHIFT) /* MCK/64 */ +# define PWM_CLK_PREB_MCKDIV128 (7 << PWM_CLK_PREB_SHIFT) /* MCK/128 */ +# define PWM_CLK_PREB_MCKDIV256 (8 << PWM_CLK_PREB_SHIFT) /* MCK/256 */ +# define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */ +# define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */ + +/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */ + +#define SAM_ENAB_CHID(n) (1 << ((n)) +#define SAM_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ +#define SAM_ENAB_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ +#define SAM_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ +#define SAM_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ + +/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt + * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions + */ + +#define SAM_INT_CHID(n) (1 << (n)) +#define SAM_INT_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ +#define SAM_INT_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ +#define SAM_INT_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ +#define SAM_INT_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ +#define SAM_INT_FCHID(n) (1 << ((n)+16)) +#define SAM_INT_FCHID0 (1 << 16) /* Bit 16: Fault Protection Trigger Channel 0 Interrupt */ +#define SAM_INT_FCHID1 (1 << 17) /* Bit 17: Fault Protection Trigger Channel 1 Interrupt */ +#define SAM_INT_FCHID2 (1 << 18) /* Bit 18: Fault Protection Trigger Channel 2 Interrupt */ +#define SAM_INT_FCHID3 (1 << 19) /* Bit 19: Fault Protection Trigger Channel 3 Interrupt */ + +/* PWM Sync Channels Mode Register */ + +#define PWM_SCM_SYNC(n) (1 << (n)) +#define PWM_SCM_SYNC0 (1 << 0) /* Bit 0: Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (1 << 1) /* Bit 1: Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (1 << 2) /* Bit 2: Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (1 << 3) /* Bit 3: Synchronous Channel 3 */ +#define PWM_SCM_UPDM_SHIFT (16) /* Bits 16-17: Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM_MASK (3 << PWM_SCM_UPDM_SHIFT) +# define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */ +# define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */ +# define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */ +#define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT) + +/* PWM Sync Channels Update Control Register */ + +#define PWM_SCUC_UPDULOCK (1 << 0) /* Bit 0: Synchronous Channels Update Unlock */ + +/* PWM Sync Channels Update Period Register */ + +#define PWM_SCUP_UPR_SHIFT (0) /* Bits 0-3: Update Period */ +#define PWM_SCUP_UPR_MASK (15 << PWM_SCUP_UPR_MASK) +#define PWM_SCUP_UPRCNT_SHIFT (4) /* Bits 4-7: Update Period Counter */ +#define PWM_SCUP_UPRCNT_MASK (15 << PWM_SCUP_UPRCNT_SHIFT) + +/* PWM Sync Channels Update Period Update Register */ + +#define PWM_SCUPUPD_SHIFT (0) /* Bits 0-3: Update Period Update */ +#define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT) + +/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */ + +#define SAM_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */ +#define SAM_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */ +#define SAM_INT_TXBUFE (1 << 2) /* Bit 2: PDC TX Buffer Empty Interrupt */ +#define SAM_INT_UNRE (1 << 3) /* Bit 3: Synch Update Underrun Error Interrupt */ +#define SAM_INT_CMPM(n) (1 << ((n)+8)) +#define SAM_INT_CMPM0 (1 << 8) /* Bit 8: Comparison 0 Match Interrupt */ +#define SAM_INT_CMPM1 (1 << 9) /* Bit 9: Comparison 1 Match Interrupt */ +#define SAM_INT_CMPM2 (1 << 10) /* Bit 10: Comparison 2 Match Interrupt */ +#define SAM_INT_CMPM3 (1 << 11) /* Bit 11: Comparison 3 Match Interrupt */ +#define SAM_INT_CMPM4 (1 << 12) /* Bit 12: Comparison 4 Match Interrupt */ +#define SAM_INT_CMPM5 (1 << 13) /* Bit 13: Comparison 5 Match Interrupt */ +#define SAM_INT_CMPM6 (1 << 14) /* Bit 14: Comparison 6 Match Interrupt */ +#define SAM_INT_CMPM7 (1 << 15) /* Bit 15: Comparison 7 Match Interrupt */ +#define SAM_INT_CMPU(n) (1 << ((n)+16)) +#define SAM_INT_CMPU0 (1 << 16) /* Bit 16: Comparison o Update Interrupt */ +#define SAM_INT_CMPU1 (1 << 17) /* Bit 17: Comparison 1 Update Interrupt */ +#define SAM_INT_CMPU2 (1 << 18) /* Bit 18: Comparison 2 Update Interrupt */ +#define SAM_INT_CMPU3 (1 << 19) /* Bit 19: Comparison 3 Update Interrupt */ +#define SAM_INT_CMPU4 (1 << 20) /* Bit 20: Comparison 4 Update Interrupt */ +#define SAM_INT_CMPU5 (1 << 21) /* Bit 21: Comparison 5 Update Interrupt */ +#define SAM_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */ +#define SAM_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */ + +/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output + * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection + * Set Update Register, and PWM Output Selection Clear Update Register common bit-field + * definitions + */ + +#define PWM_OUT_OH(n) (1 << (n)) +#define PWM_OUT_OH0 (1 << 0) /* Bit 0: Value for PWMH output of the channel 0 */ +#define PWM_OUT_OH1 (1 << 1) /* Bit 1: Value for PWMH output of the channel 1 */ +#define PWM_OUT_OH2 (1 << 2) /* Bit 2: Value for PWMH output of the channel 2 */ +#define PWM_OUT_OH3 (1 << 3) /* Bit 3: Value for PWMH output of the channel 3 */ +#define PWM_OUT_OL(n) (1 << ((n)+16)) +#define PWM_OUT_OL0 (1 << 16) /* Bit 16: Value for PWML output of the channel 0 */ +#define PWM_OUT_OL1 (1 << 17) /* Bit 17: Value for PWML output of the channel 1 */ +#define PWM_OUT_OL2 (1 << 18) /* Bit 18: Value for PWML output of the channel 2 */ +#define PWM_OUT_OL3 (1 << 19) /* Bit 19: Value for PWML output of the channel 3 */ + +/* PWM Fault Mode Register */ + +#define PWM_FMR_FPOL(n) (1 << (n)) +#define PWM_FMR_FPOL0 (1 << 0) /* Bit 0: Fault 0 Polarity */ +#define PWM_FMR_FPOL1 (1 << 1) /* Bit 1: Fault 1 Polarity */ +#define PWM_FMR_FPOL2 (1 << 2) /* Bit 2: Fault 2 Polarity */ +#define PWM_FMR_FPOL3 (1 << 3) /* Bit 3: Fault 3 Polarity */ +#define PWM_FMR_FMOD(n) (1 << ((n)+8)) +#define PWM_FMR_FMOD0 (1 << 8) /* Bit 8: Fault 0 Activation Mode */ +#define PWM_FMR_FMOD1 (1 << 9) /* Bit 9: Fault 1 Activation Mode */ +#define PWM_FMR_FMOD2 (1 << 10) /* Bit 10: Fault 2 Activation Mode */ +#define PWM_FMR_FMOD3 (1 << 11) /* Bit 11: Fault 3 Activation Mode */ +#define PWM_FMR_FFIL(n) (1 << ((n)+16)) +#define PWM_FMR_FFIL0 (1 << 16) /* Bit 16: Fault 0 Filter */ +#define PWM_FMR_FFIL1 (1 << 17) /* Bit 17: Fault 1 Filter */ +#define PWM_FMR_FFIL2 (1 << 18) /* Bit 18: Fault 2 Filter */ +#define PWM_FMR_FFIL3 (1 << 19) /* Bit 19: Fault 3 Filter */ + +/* PWM Fault Status Register */ + +#define PWM_FSR_FIV(n) (1 << (n)) +#define PWM_FSR_FIV0 (1 << 0) /* Bit 0: Fault Input 0 Value */ +#define PWM_FSR_FIV1 (1 << 1) /* Bit 1: Fault Input 1 Value */ +#define PWM_FSR_FIV2 (1 << 2) /* Bit 2: Fault Input 2 Value */ +#define PWM_FSR_FIV3 (1 << 3) /* Bit 3: Fault Input 3 Value */ +#define PWM_FSR_FS(n) (1 << ((n)+8)) +#define PWM_FSR_FS0 (1 << 8) /* Bit 8: Fault 0 Status */ +#define PWM_FSR_FS1 (1 << 9) /* Bit 9: Fault 1 Status */ +#define PWM_FSR_FS2 (1 << 10) /* Bit 10: Fault 2 Status */ +#define PWM_FSR_FS3 (1 << 11) /* Bit 11: Fault 3 Status */ + +/* PWM Fault Clear Register */ + +#define PWM_FCR_FCLR(n) (1 << (n)) +#define PWM_FCR_FCLR0 (1 << 0) /* Bit 0: Fault 0 Clear */ +#define PWM_FCR_FCLR1 (1 << 1) /* Bit 1: Fault 1 Clear */ +#define PWM_FCR_FCLR2 (1 << 2) /* Bit 2: Fault 2 Clear */ +#define PWM_FCR_FCLR3 (1 << 3) /* Bit 3: Fault 3 Clear */ + +/* PWM Fault Protection Value Register */ + +#define PWM_FPV_FPVH(n) (1 << (n)) +#define PWM_FPV_FPVH0 (1 << 0) /* Bit 0: Fault Protection Value PWMH output channel 0 */ +#define PWM_FPV_FPVH1 (1 << 1) /* Bit 1: Fault Protection Value PWMH output channel 1 */ +#define PWM_FPV_FPVH2 (1 << 2) /* Bit 2: Fault Protection Value PWMH output channel 2 */ +#define PWM_FPV_FPVH3 (1 << 3) /* Bit 3: Fault Protection Value PWMH output channel 3 */ +#define PWM_FPV_FPVL(n) (1 << ((n)+16)) +#define PWM_FPV_FPVL0 (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */ +#define PWM_FPV_FPVL1 (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */ +#define PWM_FPV_FPVL2 (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */ +#define PWM_FPV_FPVL3 (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */ + +/* PWM Fault Protection Enable Register */ + +#define PWM_FPE_FPEN(n,y) (1 << (((n)<<8)+y)) +#define PWM_FPE_FPE0(y) (1 << (y)) /* Bits 0-7: Fault Protection Enable Fault=y chan=0 */ +#define PWM_FPE_FPE1(y) (1 << ((y)+8)) /* Bits 8-15: Fault Protection Enable Fault=y chan=1 */ +#define PWM_FPE_FPE2(y) (1 << ((y)+16)) /* Bits 16-23: Fault Protection Enable Fault=y chan=2 */ +#define PWM_FPE_FPE3(y) (1 << ((y)+24) /* Bits 24-31: Fault Protection Enable Fault=y chan=3 */ + +/* PWM Event Line 1/2 Register */ + +#define PWM_ELMR_CSEL(n) (1 << (n)) +#define PWM_ELMR_CSEL0 (1 << 0) /* Bit 0: Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (1 << 1) /* Bit 1: Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (1 << 2) /* Bit 2: Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (1 << 3) /* Bit 3: Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (1 << 4) /* Bit 4: Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (1 << 5) /* Bit 5: Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */ + +/* PWM Write Protect Control Register */ + +#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */ +#define PWM_WPCR_WPCMD_MASK (3 << PWM_WPCR_WPCMD_SHIFT) +#define PWM_WPCR_WPRG(n) (1 << ((n)+2)) +#define PWM_WPCR_WPRG0 (1 << 2) /* Bit 2: Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (1 << 3) /* Bit 3: Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (1 << 4) /* Bit 4: Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (1 << 5) /* Bit 5: Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (1 << 6) /* Bit 6: Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (1 << 7) /* Bit 7: Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */ +#define PWM_WPCR_WPKEY_MASK (0x00ffffff << PWM_WPCR_WPKEY_SHIFT) + +/* PWM Write Protect Status Register */ + +#define PWM_WPSR_WPSWS(n) (1 << (n)) +#define PWM_WPSR_WPSWS0 (1 << 0) /* Bit 0: Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (1 << 1) /* Bit 1: Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (1 << 2) /* Bit 2: Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (1 << 3) /* Bit 3: Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (1 << 4) /* Bit 4: Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (1 << 5) /* Bit 5: Write Protect SW Status */ +#define PWM_WPSR_WPVS (1 << 7) /* Bit 7: Write Protect Violation Status */ +#define PWM_WPSR_WPHWS(n) (1 << ((n)+8)) +#define PWM_WPSR_WPHWS0 (1 << 8) /* Bit 8: Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (1 << 9) /* Bit 9: Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (1 << 10) /* Bit 10: Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (1 << 11) /* Bit 11: Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (1 << 12) /* Bit 12: Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (1 << 13) /* Bit 13: Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */ +#define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT) + +/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */ + +#define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */ +#define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT) +#define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */ + +/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */ + +#define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */ +#define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */ +#define PWMCMP_CTR_MASK (15 << PWMCMP_CTR_SHIFT) +#define PWMCMP_CPR_SHIFT (8) /* Bits 8-11: Comparison x Period */ +#define PWMCMP_CPR_MASK (15 << PWMCMP_CPR_SHIFT) +#define PWMCMP_M_CPRCNT_SHIFT (12) /* Bits 12-15: Comparison x Period Count (M only) */ +#define PWMCMP_M_CPRCNT_MASK (15 << PWMCMP_M_CPRCNT_SHIFT) +#define PWMCMP_CUPR_SHIFT (16) /* Bits 16-19: Comparison x Update Period */ +#define PWMCMP_CUPR_MASK (15 << PWMCMP_CUPR_SHIFT) +#define PWMCMP_M_CUPRCNT_SHIFT (20) /* Bits 20-23: Comparison x Update Period Counter (M only) */ +#define PWMCMP_M_CUPRCNT_MASK (15 << PWMCMP_M_CUPRCNT_SHIFT) + +/* PWM Channel Mode Register */ + +#define PWMCH_MR_CPRE_SHIFT (0) /* Bits 0-3: Channel Pre-scaler */ +#define PWMCH_MR_CPRE_MASK (15 << PWMCH_MR_CPRE_SHIFT) +# define PWMCH_MR_CPRE_MCK (0 << PWMCH_MR_CPRE_SHIFT) /* MCK */ +# define PWMCH_MR_CPRE_MCKDIV2 (1 << PWMCH_MR_CPRE_SHIFT) /* MCK/2 */ +# define PWMCH_MR_CPRE_MCKDIV4 (2 << PWMCH_MR_CPRE_SHIFT) /* MCK/4 */ +# define PWMCH_MR_CPRE_MCKDIV8 (3 << PWMCH_MR_CPRE_SHIFT) /* MCK/8 */ +# define PWMCH_MR_CPRE_MCKDIV16 (4 << PWMCH_MR_CPRE_SHIFT) /* MCK/16 */ +# define PWMCH_MR_CPRE_MCKDIV32 (5 << PWMCH_MR_CPRE_SHIFT) /* MCK/32 */ +# define PWMCH_MR_CPRE_MCKDIV64 (6 << PWMCH_MR_CPRE_SHIFT) /* MCK/64 */ +# define PWMCH_MR_CPRE_MCKDIV128 (7 << PWMCH_MR_CPRE_SHIFT) /* MCK/128 */ +# define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */ +# define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */ +# define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */ +# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */ +# define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */ +#define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */ +#define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */ +#define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */ +#define PWMCH_MR_DTE (1 << 16) /* Bit 16: Dead-Time Generator Enable */ +#define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */ +#define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */ + +/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */ + +#define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */ +#define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT) + +/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */ + +#define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */ +#define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT) + +/* PWM Channel Counter Register */ + +#define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */ +#define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT) + +/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */ + +#define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */ +#define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT) +#define PWMCH_DTL_SHIFT (16) /* Bits 16-31: Dead-Time Value for PWMLx Output */ +#define PWMCH_DTL_MASK (0xffff << PWMCH_DTL_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PWM_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h new file mode 100644 index 000000000..3a620d7ef --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h @@ -0,0 +1,102 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_rstc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSTC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSTC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RSTC register offsets ****************************************************************/ + +#define SAM_RSTC_CR_OFFSET 0x00 /* Control Register */ +#define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */ +#define SAM_RSTC_MR_OFFSET 0x08 /* Mode Register */ + +/* RSTC register adresses ***************************************************************/ + +#define SAM_RSTC_CR (SAM_RSTC_BASE+SAM_RSTC_CR_OFFSET) +#define SAM_RSTC_SR (SAM_RSTC_BASE+SAM_RSTC_SR_OFFSET) +#define SAM_RSTC_MR (SAM_RSTC_BASE+SAM_RSTC_MR_OFFSET) + +/* RSTC register bit definitions ********************************************************/ + +#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */ +#define RSTC_CR_PERRST (1 << 2) /* Bit 2: Peripheral Reset */ +#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */ +#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) + +#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */ +#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */ +#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT) +# define RSTC_SR_RSTTYP_PWRUP (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */ +# define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */ +# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */ +# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */ +# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */ +#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */ +#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */ + +#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */ +#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */ +#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT) +#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSTC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtc.h b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h new file mode 100644 index 000000000..5c0a2e15e --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h @@ -0,0 +1,184 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_rtc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RTC register offsets *****************************************************************/ + +#define SAM_RTC_CR_OFFSET 0x00 /* Control Register */ +#define SAM_RTC_MR_OFFSET 0x04 /* Mode Register */ +#define SAM_RTC_TIMR_OFFSET 0x08 /* Time Register */ +#define SAM_RTC_CALR_OFFSET 0x0c /* Calendar Register */ +#define SAM_RTC_TIMALR_OFFSET 0x10 /* Time Alarm Register */ +#define SAM_RTC_CALALR_OFFSET 0x14 /* Calendar Alarm Register */ +#define SAM_RTC_SR_OFFSET 0x18 /* Status Register */ +#define SAM_RTC_SCCR_OFFSET 0x1c /* Status Clear Command Register */ +#define SAM_RTC_IER_OFFSET 0x20 /* Interrupt Enable Register */ +#define SAM_RTC_IDR_OFFSET 0x24 /* Interrupt Disable Register */ +#define SAM_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */ +#define SAM_RTC_VER_OFFSET 0x2c /* Valid Entry Register */ + +/* RTC register adresses ****************************************************************/ + +#define SAM_RTC_CR (SAM_RTC_BASE+SAM_RTC_CR_OFFSET) +#define SAM_RTC_MR (SAM_RTC_BASE+SAM_RTC_MR_OFFSET) +#define SAM_RTC_TIMR (SAM_RTC_BASE+SAM_RTC_TIMR_OFFSET) +#define SAM_RTC_CALR (SAM_RTC_BASE+SAM_RTC_CALR_OFFSET) +#define SAM_RTC_TIMALR (SAM_RTC_BASE+SAM_RTC_TIMALR_OFFSET) +#define SAM_RTC_CALALR (SAM_RTC_BASE+SAM_RTC_CALALR_OFFSET) +#define SAM_RTC_SR (SAM_RTC_BASE+SAM_RTC_SR_OFFSET) +#define SAM_RTC_SCCR (SAM_RTC_BASE+SAM_RTC_SCCR_OFFSET) +#define SAM_RTC_IER (SAM_RTC_BASE+SAM_RTC_IER_OFFSET) +#define SAM_RTC_IDR (SAM_RTC_BASE+SAM_RTC_IDR_OFFSET) +#define SAM_RTC_IMR (SAM_RTC_BASE+SAM_RTC_IMR_OFFSET) +#define SAM_RTC_VER (SAM_RTC_BASE+SAM_RTC_VER_OFFSET) + +/* RTC register bit definitions *********************************************************/ + +#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */ +#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */ +#define RTC_CR_TIMEVSEL_MASK (3 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_MIN (0 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_HOUR (1 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_MIDNIGHT (2 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_NOON (3 << RTC_CR_TIMEVSEL_SHIFT) +#define RTC_CR_CALEVSEL_SHIFT (16) /* Bits 16-17: Calendar Event Selection */ +#define RTC_CR_CALEVSEL_MASK (3 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_WEEK (0 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT) + +#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */ + +#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */ +#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT) +#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */ +#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT) +#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */ +#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT) +#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */ + +#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */ +#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT) +#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */ +#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT) +#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */ +#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT) +#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */ +#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT) +#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */ +#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT) + +#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */ +#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT) +#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */ +#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */ +#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT) +#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */ +#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT) +#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */ + +#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */ +#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT) +#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */ +#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */ +#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT) +#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */ + +#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */ +#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */ +#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */ +#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */ +#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */ + +#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */ +#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */ +#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */ +#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */ + +#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */ +#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */ +#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */ + +#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */ + +#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */ +#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */ +#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */ +#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */ + +#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */ +#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */ +#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtt.h b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h new file mode 100644 index 000000000..75b0d361e --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h @@ -0,0 +1,89 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_rtt.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RTT register offsets *****************************************************************/ + +#define SAM_RTT_MR_OFFSET 0x00 /* Mode Register */ +#define SAM_RTT_AR_OFFSET 0x04 /* Alarm Register */ +#define SAM_RTT_VR_OFFSET 0x08 /* Value Register */ +#define SAM_RTT_SR_OFFSET 0x0c /* Status Register */ + +/* RTT register adresses ***************************************************************/ + +#define SAM_RTT_MR (SAM_RTT_BASE+SAM_RTT_MR_OFFSET) +#define SAM_RTT_AR (SAM_RTT_BASE+SAM_RTT_AR_OFFSET) +#define SAM_RTT_VR (SAM_RTT_BASE+SAM_RTT_VR_OFFSET) +#define SAM_RTT_SR (SAM_RTT_BASE+SAM_RTT_SR_OFFSET) + +/* RTT register bit definitions ********************************************************/ + +#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT) +#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */ +#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */ + +#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */ +#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTT_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_smc.h b/nuttx/arch/arm/src/sam34/chip/sam_smc.h new file mode 100644 index 000000000..ba67d6608 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_smc.h @@ -0,0 +1,432 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_smc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SMC register offsets *****************************************************************/ + +#define SAM_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */ +#define SAM_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */ +#define SAM_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */ +#define SAM_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */ +#define SAM_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */ +#define SAM_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */ +#define SAM_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */ +#define SAM_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */ +#define SAM_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */ +#define SAM_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */ +#define SAM_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */ +#define SAM_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */ +#define SAM_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */ +#define SAM_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */ +#define SAM_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */ +#define SAM_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */ +#define SAM_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */ +#define SAM_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */ +#define SAM_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */ +#define SAM_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */ +#define SAM_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */ +#define SAM_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */ +#define SAM_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */ +#define SAM_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */ +#define SAM_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */ +#define SAM_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */ +#define SAM_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */ +#define SAM_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */ + +#define SAM_SMCCS_OFFSET(n) (0x070+((n)*0x014)) +#define SAM_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */ +#define SAM_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */ +#define SAM_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */ +#define SAM_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */ +#define SAM_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */ + +#define SAM_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */ +#define SAM_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */ +#define SAM_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */ +#define SAM_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */ +#define SAM_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */ + +/* SMC register adresses ****************************************************************/ + +#define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET) +#define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET) +#define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET) +#define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET) +#define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET) +#define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET) +#define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET) +#define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET) +#define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET) +#define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET) +#define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET) +#define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET) +#define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET) +#define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET) +#define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET) +#define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET) +#define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET) +#define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET) +#define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET) +#define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET) +#define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET) +#define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET) +#define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET) +#define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET) +#define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET) +#define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET) +#define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET) +#define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET) + +#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) +# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0)) +# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1)) +# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2)) +# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3)) +#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET) +#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET) +#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET) +#define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET) +#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET) + +#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET) +#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET) +#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET) +#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET) +#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET) + +/* SMC register bit definitions *********************************************************/ + +/* SMC NFC Configuration Register */ + +#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ +#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) +# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ +# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ +# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ +# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ +#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ +#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ +#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ +#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ +#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ +#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) +#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ +#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) + +/* SMC NFC Control Register */ + +#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ +#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ + +/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt + * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions + */ + +#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ +#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ +#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ +#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ +#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ +#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ +#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ +#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ +#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ +#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ +#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ +#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ +#define SMC_INT_RBEDGE(n) (1<<((n)+24)) +#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ +#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ +#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ +#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ +#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ +#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ +#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ +#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ + +/* SMC NFC Address Cycle Zero Register */ + +#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ +#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ + +/* SMC NFC Bank Register */ + +#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ +#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) + +/* SMC ECC Control Register */ + +#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ +#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ + +/* SMC ECC MODE Register */ + +#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ +#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ +#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) +# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ +# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ +# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ + +/* SMC ECC Status Register 1 */ + +#define _RECERR (0) /* Recoverable Error */ +#define _ECCERR (1) /* ECC Error */ +#define _MULERR (2) /* Multiple Error */ + +#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) +#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) +#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) + +#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) +#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) +#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) +#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) +#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) +#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) +#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) +#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) +#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) +#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) +#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) +#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) +#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) +#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) +#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) +#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) +#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) +#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) +#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) +#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) +#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) +#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) +#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) +#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) + +/* SMC ECC Status Register 2 */ + +#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) +#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) +#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) + +#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) +#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) +#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) +#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) +#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) +#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) +#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) +#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) +#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) +#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) +#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) +#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) +#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) +#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) +#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) +#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) +#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) +#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) +#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) +#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) +#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) +#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) +#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) +#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) + +/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */ +/* SMC_ECC_PR0 */ + +#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) +#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) + +#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ +#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) + +/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */ + +#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) +#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) +#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ +#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) + +/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */ + +#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ +#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) +#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ +#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) +#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ +#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) + +/* SMC Setup Register */ + +#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ +#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) +#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ +#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) +#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ +#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) +#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ +#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) + +/* SMC Pulse Register */ + +#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ +#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) +#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ +#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) +#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ +#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT) +#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ +#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) + +/* SMC Cycle Register */ + +#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ +#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) +#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ +#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) + +/* SMC Timings Register */ + +#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ +#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) +#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ +#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) +#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ +#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) +#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ +#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ +#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) +#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ +#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) +#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ +#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) +#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ + +/* SMC Mode Register */ + +#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ +#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ +#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ +#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) +#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ +#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ +#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) +# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ +# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ +# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ +#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ +#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) +#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ +#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ +#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ +#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) +# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ +# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ +# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ +# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ + +/* SMC OCMS Register */ + +#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ + +/* SMC Write Protection Control */ + +#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ +#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ +#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) + +/* SMC Write Protection Status */ + +#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) +# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ +# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ +# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ +# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ +#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_spi.h b/nuttx/arch/arm/src/sam34/chip/sam_spi.h new file mode 100644 index 000000000..91720647f --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_spi.h @@ -0,0 +1,189 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_spi.h + * + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SPI register offsets *****************************************************************/ + +#define SAM_SPI_CR_OFFSET 0x00 /* Control Register */ +#define SAM_SPI_MR_OFFSET 0x04 /* Mode Register */ +#define SAM_SPI_RDR_OFFSET 0x08 /* Receive Data Register */ +#define SAM_SPI_TDR_OFFSET 0x0c /* Transmit Data Register */ +#define SAM_SPI_SR_OFFSET 0x10 /* Status Register */ +#define SAM_SPI_IER_OFFSET 0x14 /* Interrupt Enable Register */ +#define SAM_SPI_IDR_OFFSET 0x18 /* Interrupt Disable Register */ +#define SAM_SPI_IMR_OFFSET 0x1c /* Interrupt Mask Register */ + /* 0x20-0x2c: Reserved */ +#define SAM_SPI_CSR0_OFFSET 0x30 /* Chip Select Register 0 */ +#define SAM_SPI_CSR1_OFFSET 0x34 /* Chip Select Register 1 */ +#define SAM_SPI_CSR2_OFFSET 0x38 /* Chip Select Register 2 */ +#define SAM_SPI_CSR3_OFFSET 0x3c /* Chip Select Register 3 */ + /* 0x40-0xe0: Reserved */ +#define SAM_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */ +#define SAM_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */ + /* 0xec-0xf8: Reserved*/ + +/* SPI register adresses ****************************************************************/ + +#define SAM_SPI_CR (SAM_SPI_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ +#define SAM_SPI_MR (SAM_SPI_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ +#define SAM_SPI_RDR (SAM_SPI_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */ +#define SAM_SPI_TDR (SAM_SPI_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */ +#define SAM_SPI_SR (SAM_SPI_BASE+SAM_SPI_SR_OFFSET) /* Status Register */ +#define SAM_SPI_IER (SAM_SPI_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */ +#define SAM_SPI_IDR (SAM_SPI_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */ +#define SAM_SPI_IMR (SAM_SPI_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */ +#define SAM_SPI_CSR0 (SAM_SPI_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */ +#define SAM_SPI_CSR1 (SAM_SPI_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */ +#define SAM_SPI_CSR2 (SAM_SPI_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */ +#define SAM_SPI_CSR3 (SAM_SPI_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */ +#define SAM_SPI_WPCR (SAM_SPI_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */ +#define SAM_SPI_WPSR (SAM_SPI_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */ + +/* SPI register bit definitions *********************************************************/ + +/* SPI Control Register */ + +#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */ +#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */ +#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */ +#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ + +/* SPI Mode Register */ + +#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */ +#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */ +#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */ +#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */ +#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */ +#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */ +#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ +#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT) +#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ +#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) + +/* SPI Receive Data Register */ + +#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */ +#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT) +#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ +#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT) + +/* SPI Transmit Data Register */ + +#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */ +#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT) +#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ +#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT) +#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ + +/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, + * and SPI Interrupt Mask Register (common bit fields) + */ + +#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */ +#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */ +#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */ +#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */ +#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */ +#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */ +#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */ +#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */ + +/* SPI Chip Select Registers 0-3 */ + +#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */ +#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */ +#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */ +#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */ +#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */ +#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT) +# define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */ +# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */ +# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */ +# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */ +# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */ +# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */ +# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */ +# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */ +# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */ +# define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */ +#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ +#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT) +#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */ +#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT) +#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT) + +/* SPI Write Protection Control Register */ + +#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ +#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ +#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT) + +/* SPI Write Protection Status Register */ + +#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */ +#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT) +#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ +#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_ssc.h b/nuttx/arch/arm/src/sam34/chip/sam_ssc.h new file mode 100644 index 000000000..552659260 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_ssc.h @@ -0,0 +1,292 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_ssc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SSC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SSC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SSC register offsets *****************************************************************/ + +#define SAM_SSC_CR_OFFSET 0x000 /* Control Register */ +#define SAM_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */ + /* 0x008: Reserved */ + /* 0x00c: Reserved */ +#define SAM_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */ +#define SAM_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */ +#define SAM_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */ +#define SAM_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */ +#define SAM_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */ +#define SAM_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */ + /* 0x028: Reserved */ + /* 0x02c: Reserved */ +#define SAM_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */ +#define SAM_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */ +#define SAM_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */ +#define SAM_SSC_RC1R_OFFSET 0x03c /* Receive Compare 1 Register */ +#define SAM_SSC_SR_OFFSET 0x040 /* Status Register */ +#define SAM_SSC_IER_OFFSET 0x044 /* Interrupt Enable Register */ +#define SAM_SSC_IDR_OFFSET 0x048 /* Interrupt Disable Register */ +#define SAM_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */ +#define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */ +#define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */ + /* 0x050-0x0fc: Reserved */ + /* 0x100-0x124: Reserved */ + +/* SSC register adresses ****************************************************************/ + +#define SAM_SSC_CR (SAM_SSC_BASE+SAM_SSC_CR_OFFSET) +#define SAM_SSC_CMR (SAM_SSC_BASE+SAM_SSC_CMR_OFFSET) +#define SAM_SSC_RCMR (SAM_SSC_BASE+SAM_SSC_RCMR_OFFSET) +#define SAM_SSC_RFMR (SAM_SSC_BASE+SAM_SSC_RFMR_OFFSET) +#define SAM_SSC_TCMR (SAM_SSC_BASE+SAM_SSC_TCMR_OFFSET) +#define SAM_SSC_TFMR (SAM_SSC_BASE+SAM_SSC_TFMR_OFFSET) +#define SAM_SSC_RHR (SAM_SSC_BASE+SAM_SSC_RHR_OFFSET) +#define SAM_SSC_THR (SAM_SSC_BASE+SAM_SSC_THR_OFFSET) +#define SAM_SSC_RSHR (SAM_SSC_BASE+SAM_SSC_RSHR_OFFSET) +#define SAM_SSC_TSHR (SAM_SSC_BASE+SAM_SSC_TSHR_OFFSET) +#define SAM_SSC_RC0R (SAM_SSC_BASE+SAM_SSC_RC0R_OFFSET) +#define SAM_SSC_RC1R (SAM_SSC_BASE+SAM_SSC_RC1R_OFFSET) +#define SAM_SSC_SR (SAM_SSC_BASE+SAM_SSC_SR_OFFSET) +#define SAM_SSC_IER (SAM_SSC_BASE+SAM_SSC_IER_OFFSET) +#define SAM_SSC_IDR (SAM_SSC_BASE+SAM_SSC_IDR_OFFSET) +#define SAM_SSC_IMR (SAM_SSC_BASE+SAM_SSC_IMR_OFFSET) +#define SAM_SSC_WPMR (SAM_SSC_BASE+SAM_SSC_WPMR_OFFSET) +#define SAM_SSC_WPSR (SAM_SSC_BASE+SAM_SSC_WPSR_OFFSET) + +/* SSC register bit definitions *********************************************************/ + +/* SSC Control Register */ + +#define SSC_CR_RXEN (1 << 0) /* Bit 0: Receive Enable */ +#define SSC_CR_RXDIS (1 << 1) /* Bit 1: Receive Disable */ +#define SSC_CR_TXEN (1 << 8) /* Bit 8: Transmit Enable */ +#define SSC_CR_TXDIS (1 << 9) /* Bit 9: Transmit Disable */ +#define SSC_CR_SWRST (1 << 15) /* Bit 15: Software Reset */ + +/* SSC Clock Mode Register */ + +#define SSC_CMR_DIV_SHIFT (0) /* Bits 0-11: Clock Divider */ +#define SSC_CMR_DIV_MASK (0xfff << SSC_CMR_DIV_SHIFT) + +/* SSC Receive Clock Mode Register */ + +#define SSC_RCMR_CKS_SHIFT (0) /* Bits 0-1: Receive Clock Selection */ +#define SSC_RCMR_CKS_MASK (3 << SSC_RCMR_CKS_SHIFT) +# define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */ +# define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */ +# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ +#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) +# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ +# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */ +# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */ +#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ +#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) +# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */ +# define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */ +# define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ +#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) +# define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */ +# define SSC_RCMR_START_START (1 << SSC_RCMR_START_SHIFT) /* Transmit start */ +# define SSC_RCMR_START_RFLOW (2 << SSC_RCMR_START_SHIFT) /* Low level on RF signal */ +# define SSC_RCMR_START_RFHIGH (3 << SSC_RCMR_START_SHIFT) /* High level on RF signal */ +# define SSC_RCMR_START_RFFALL (4 << SSC_RCMR_START_SHIFT) /* Falling edge on RF signal */ +# define SSC_RCMR_START_RFRISE (5 << SSC_RCMR_START_SHIFT) /* Rising edge on RF signal */ +# define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */ +# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */ +# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ +#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */ +#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */ +#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) +#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT) + + +/* SSC Receive Frame Mode Register */ + +#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ +#define SSC_RFMR_DATLEN_MASK (31 << SSC_RFMR_DATLEN_SHIFT) +#define SSC_RFMR_LOOP (1 << 5) /* Bit 5: Loop Mode */ +#define SSC_RFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ +#define SSC_RFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */ +#define SSC_RFMR_DATNB_MASK (15 << SSC_RFMR_DATNB_SHIFT) +#define SSC_RFMR_FSLEN_SHIFT (16) /* Bits 16-19: Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN_MASK (15 << SSC_RFMR_FSLEN_SHIFT) +#define SSC_RFMR_FSOS_SHIFT (20) /* Bits 20-22: Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT) +# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */ +# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ +# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ +# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ +# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ +#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */ +#define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ +#define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT) + +/* SSC Transmit Clock Mode Register */ + +#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */ +#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT) +# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ +# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */ +# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */ +#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) +# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ +# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */ +# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */ +#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ +#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) +# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */ +# define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */ +# define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */ +#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ +#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) +# define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */ +# define SSC_TCMR_START_START (1 << SSC_TCMR_START_SHIFT) /* Receive start */ +# define SSC_TCMR_START_TFLOW (2 << SSC_TCMR_START_SHIFT) /* Low level on TF signal */ +# define SSC_TCMR_START_TFHIGH (3 << SSC_TCMR_START_SHIFT) /* High level on TF signal */ +# define SSC_TCMR_START_TFFALL (4 << SSC_TCMR_START_SHIFT) /* Falling edge on TF signal */ +# define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */ +# define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */ +# define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */ +#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */ +#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) +#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD_MASK (0xff << SSC_TCMR_PERIOD_SHIFT) + +/* SSC Transmit Frame Mode Register */ + +#define SSC_TFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ +#define SSC_TFMR_DATLEN_MASK (31 << SSC_TFMR_DATLEN_SHIFT) +#define SSC_TFMR_DATDEF (1 << 5) /* Bit 5: Data Default Value */ +#define SSC_TFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ +#define SSC_TFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per frame */ +#define SSC_TFMR_DATNB_MASK (15 << SSC_TFMR_DATNB_SHIFT) +#define SSC_TFMR_FSLEN_SHIFT (16) /* Bits 16-19: Transmit Frame Syn Length */ +#define SSC_TFMR_FSLEN_MASK (15 << SSC_TFMR_FSLEN_SHIFT) +#define SSC_TFMR_FSOS_SHIFT (20) /* Bits 20-22: Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT) +# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */ +# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ +# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ +# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ +# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ +#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ +#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT) + +/* SSC Receive Synchronization Holding Register */ + +#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */ +#define SSC_RSHR_RSDAT_MASK (0xffff << SSC_RSHR_RSDAT_SHIFT) + +/* SSC Transmit Synchronization Holding Register */ + +#define SSC_TSHR_TSDAT_SHIFT (0) /* Bits 0-15: Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT_MASK (0xffff << SSC_TSHR_TSDAT_SHIFT) + +/* SSC Receive Compare 0 Register */ + +#define SSC_RC0R_CP0_SHIFT (0) /* Bits 0-15: Receive Compare Data 0 */ +#define SSC_RC0R_CP0_MASK (0xffff << SSC_RC0R_CP0_SHIFT) + +/* SSC Receive Compare 1 Register */ + +#define SSC_RC1R_CP1_SHIFT (0) /* Bits 0-15: Receive Compare Data 1 */ +#define SSC_RC1R_CP1_MASK (0xffff << SSC_RC1R_CP1_SHIFT) + +/* SSC Status Register, SSC Interrupt Enable Register, SSC Interrupt Disable + * Register, and SSC Interrupt Mask Register commin bit-field definitions + */ + +#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */ +#define SSC_INT_TXEMPTY (1 << 1) /* Bit 1: Transmit Empty */ +#define SSC_INT_ENDTX (1 << 2) /* Bit 2: End of Transmission */ +#define SSC_INT_TXBUFE (1 << 3) /* Bit 3: Transmit Buffer Empty */ +#define SSC_INT_RXRDY (1 << 4) /* Bit 4: Receive Ready */ +#define SSC_INT_OVRUN (1 << 5) /* Bit 5: Receive Overrun */ +#define SSC_INT_ENDRX (1 << 6) /* Bit 6: End of Reception */ +#define SSC_INT_RXBUFF (1 << 7) /* Bit 7: Receive Buffer Full */ +#define SSC_INT_CP0 (1 << 8) /* Bit 8: Compare 0 */ +#define SSC_INT_CP1 (1 << 9) /* Bit 9: Compare 1 */ +#define SSC_INT_TXSYN (1 << 10) /* Bit 10: Transmit Sync */ +#define SSC_INT_RXSYN (1 << 11) /* Bit 11: Receive Sync */ +#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable (SR only) */ +#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable (SR only) */ + +/* SSC Write Protect Mode Register */ + +#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT) + +/* SSC Write Protect Status Register */ + +#define SSC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SSC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_supc.h b/nuttx/arch/arm/src/sam34/chip/sam_supc.h new file mode 100644 index 000000000..1be920d0d --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_supc.h @@ -0,0 +1,164 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_supc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SUPC register offsets ****************************************************************/ + +#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ +#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ +#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ +#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ +#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ +#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ + +/* SUPC register adresses ***************************************************************/ + +#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) +#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) +#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET) +#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET) +#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) +#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) + +/* SUPC register bit definitions ********************************************************/ + +#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ +#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ +#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) + +#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) +# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ +# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ +# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ +# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ +# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ +# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ +# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ +# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ +# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ +# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ +# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ +# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ +# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ +#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) +# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ +# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ +# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ + +#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ +#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ +#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ +#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ +#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ +#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) + +#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ +#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ +#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) + #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ + #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) +# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ + +#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ +#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ +#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) +#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) + +#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ +#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */ +#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */ +#define SUPC_SR_SMRSTS (1 << 4) /* Bit 4: Supply Monitor Reset Status */ +#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */ +#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ +#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ +#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ +#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ +#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_tc.h b/nuttx/arch/arm/src/sam34/chip/sam_tc.h new file mode 100644 index 000000000..de2046852 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_tc.h @@ -0,0 +1,347 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam_tc.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_TC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_TC_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* TC register offsets **************************************************************************/ + +/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ + +#define SAM_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */ +#define SAM_TCN_CCR_OFFSET 0x00 /* Channel Control Register */ +#define SAM_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */ + /* 0x08 Reserved */ + /* 0x0c Reserved */ +#define SAM_TCN_CV_OFFSET 0x10 /* Counter Value */ +#define SAM_TCN_RA_OFFSET 0x14 /* Register A */ +#define SAM_TCN_RB_OFFSET 0x18 /* Register B */ +#define SAM_TCN_RC_OFFSET 0x1c /* Register C */ +#define SAM_TCN_SR_OFFSET 0x20 /* Status Register */ +#define SAM_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */ +#define SAM_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */ +#define SAM_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */ + +/* Timer common registers */ + +#define SAM_TC_BCR_OFFSET 0xc0 /* Block Control Register */ +#define SAM_TC_BMR_OFFSET 0xc4 /* Block Mode Register */ +#define SAM_TC_QIER_OFFSET 0xc8 /* QDEC Interrupt Enable Register */ +#define SAM_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */ +#define SAM_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */ +#define SAM_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */ + /* 0xd8 Reserved */ + /* 0xe4 Reserved */ + +/* TC register adresses *************************************************************************/ + +/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ + +#define SAM_TC_CCR(n) (SAM_TCN_BASE(n)+SAM_TCN_CCR_OFFSET) +#define SAM_TC_CMR(n) (SAM_TCN_BASE(n)+SAM_TCN_CMR_OFFSET) +#define SAM_TC_CV(n) (SAM_TCN_BASE(n)+SAM_TCN_CV_OFFSET) +#define SAM_TC_RA(n) (SAM_TCN_BASE(n)+SAM_TCN_RA_OFFSET) +#define SAM_TC_RB(n) (SAM_TCN_BASE(n)+SAM_TCN_RB_OFFSET) +#define SAM_TC_RC(n) (SAM_TCN_BASE(n)+SAM_TCN_RC_OFFSET) +#define SAM_TC_SR(n) (SAM_TCN_BASE(n)+SAM_TCN_SR_OFFSET) +#define SAM_TC_IER(n) (SAM_TCN_BASE(n)+SAM_TCN_IER_OFFSET) +#define SAM_TC_IDR(n) (SAM_TCN_BASE(n)+SAM_TCN_IDR_OFFSET) +#define SAM_TC_IMR(n) (SAM_TCN_BASE(n)+SAM_TCN_IMR_OFFSET) + +#define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TCN_CMR_OFFSET) +#define SAM_TC0_CV (SAM_TC0_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC0_RA (SAM_TC0_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC0_RB (SAM_TC0_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC0_RC (SAM_TC0_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC0_SR (SAM_TC0_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC0_IER (SAM_TC0_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TCN_IMR_OFFSET) + +#define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TCN_CMR_OFFSET) +#define SAM_TC1_CV (SAM_TC1_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC1_RA (SAM_TC1_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC1_RB (SAM_TC1_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC1_RC (SAM_TC1_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC1_SR (SAM_TC1_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC1_IER (SAM_TC1_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TCN_IMR_OFFSET) + +#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TCN_CCR_OFFSET) +#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TCN_CMR_OFFSET) +#define SAM_TC2_CV (SAM_TC2_BASE+SAM_TCN_CV_OFFSET) +#define SAM_TC2_RA (SAM_TC2_BASE+SAM_TCN_RA_OFFSET) +#define SAM_TC2_RB (SAM_TC2_BASE+SAM_TCN_RB_OFFSET) +#define SAM_TC2_RC (SAM_TC2_BASE+SAM_TCN_RC_OFFSET) +#define SAM_TC2_SR (SAM_TC2_BASE+SAM_TCN_SR_OFFSET) +#define SAM_TC2_IER (SAM_TC2_BASE+SAM_TCN_IER_OFFSET) +#define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TCN_IDR_OFFSET) +#define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TCN_IMR_OFFSET) + +/* Timer common registers */ + +#define SAM_TC_BCR (SAM_TC_BASE+SAM_TC_BCR_OFFSET) +#define SAM_TC_BMR (SAM_TC_BASE+SAM_TC_BMR_OFFSET) +#define SAM_TC_QIER (SAM_TC_BASE+SAM_TC_QIER_OFFSET) +#define SAM_TC_QIDR (SAM_TC_BASE+SAM_TC_QIDR_OFFSET) +#define SAM_TC_QIMR (SAM_TC_BASE+SAM_TC_QIMR_OFFSET) +#define SAM_TC_QISR (SAM_TC_BASE+SAM_TC_QISR_OFFSET) + +/* TC register bit definitions ******************************************************************/ + +/* Timer common registers */ +/* TC Block Control Register */ + +#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command + +/* TC Block Mode Register */ + +#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_NONE (1 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) +#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_MASK) +# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_NONE (1 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) +#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) +#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */ +#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */ +#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: Edge on PHA count mode */ +#define TC_BMR_INVA (1 << 13) /* Bit 13: Inverted PHA */ +#define TC_BMR_INVB (1 << 14) /* Bit 14: Inverted PHB */ +#define TC_BMR_SWAP (1 << 15) /* Bit 15: Swap PHA and PHB */ +#define TC_BMR_INVIDX (1 << 16) /* Bit 16: Inverted Index */ +#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: Index pin is PHB pin */ +#define TC_BMR_FILTER (1 << 19) /* Bit 19 */ +#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: Maximum Filter */ +#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) + +/* TC QDEC Interrupt Enable Register, TC QDEC Interrupt Disable Register, + * TC QDEC Interrupt Mask Register, TC QDEC Interrupt Status Register common + * bit field definitions + */ + +#define TC_QINT_IDX (1 << 0) /* Bit 0: Index (Common) */ +#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction Change (Common) */ +#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature Error (Common) */ +#define TC_QISR_DIR (1 << 8) /* Bit 8: Direction (QISR only) */ + +/* Timer Channel Registers */ +/* TC Channel Control Register */ + +#define TCN_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */ +#define TCN_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */ +#define TCN_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */ + +/* TC Channel Mode Register */ + +#define TCN_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection (Common) */ +#define TCN_CMR_TCCLKS_MASK (7 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK1 (0 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK2 (1 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK3 (2 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK4 (3 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK5 (4 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC0 (5 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC1 (6 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC2 (7 << TCN_CMR_TCCLKS_SHIFT) +#define TCN_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert (Common) */ +#define TCN_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection (Common) */ +#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) +#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) +# define TCN_CMR_BURST_NOTGATED (0 << TCN_CMR_BURST_MASK) /* Nott gated by external signal */ +# define TCN_CMR_BURST_XC0 (1 << TCN_CMR_BURST_MASK) /* XC0 ANDed with selected clock */ +# define TCN_CMR_BURST_XC1 (2 << TCN_CMR_BURST_MASK) /* XC1 ANDed with selected clock */ +# define TCN_CMR_BURST_XC2 (3 << TCN_CMR_BURST_MASK) /* XC2 ANDed with selected clock */ +#define TCN_CMR_WAVE (1 << 15) /* Bit 15: (Common) */ + +#define TCN_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading (Capture mode) */ +#define TCN_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading (Capture mode) */ +#define TCN_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection (Capture mode) */ +#define TCN_CMR_ETRGEDG_MASK (3 << TCN_CMR_ETRGEDG_SHIFT) +# define TCN_CMR_ETRGEDG_NONE (0 << TCN_CMR_ETRGEDG_SHIFT) /* None */ +# define TCN_CMR_ETRGEDG_REDGE (1 << TCN_CMR_ETRGEDG_SHIFT) /* Rising edge */ +# define TCN_CMR_ETRGEDG_FEDGE (2 << TCN_CMR_ETRGEDG_SHIFT) /* Falling edge */ +# define TCN_CMR_ETRGEDG_EACH (3 << TCN_CMR_ETRGEDG_SHIFT) /* Each */ +#define TCN_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection (Capture mode) */ +#define TCN_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable (Capture mode) */ +#define TCN_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection (Capture mode) */ +#define TCN_CMR_LDRA_MASK (3 << TCN_CMR_LDRA_SHIFT) +# define TCN_CMR_LDRA_NONE (0 << TCN_CMR_LDRA_SHIFT) /* None */ +# define TCN_CMR_LDRA_REDGE (1 << TCN_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ +# define TCN_CMR_LDRA_FEDGE (2 << TCN_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ +# define TCN_CMR_LDRA_EACH (3 << TCN_CMR_LDRA_SHIFT) /* Each edge of TIOA */ +#define TCN_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection (Capture mode) */ +#define TCN_CMR_LDRB_MASK (3 << TCN_CMR_LDRB_SHIFT) +# define TCN_CMR_LDRB_NONE (0 << TCN_CMR_LDRB_SHIFT) /* None */ +# define TCN_CMR_LDRB_REDGE (1 << TCN_CMR_LDRB_SHIFT) /* Rising edge of TIOB */ +# define TCN_CMR_LDRB_FEDGE (2 << TCN_CMR_LDRB_SHIFT) /* Falling edge of TIOB */ +# define TCN_CMR_LDRB_EACH (3 << TCN_CMR_LDRB_SHIFT) /* Each edge of TIOB */ + +#define TCN_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */ +#define TCN_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */ +#define TCN_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */ +#define TCN_CMR_EEVTEDG_MASK (3 << TCN_CMR_EEVTEDG_SHIFT) +# define TCN_CMR_EEVTEDG_NONE (0 << TCN_CMR_EEVTEDG_SHIFT) /* None */ +# define TCN_CMR_EEVTEDG_REDGE (1 << TCN_CMR_EEVTEDG_SHIFT) /* Rising edge */ +# define TCN_CMR_EEVTEDG_FEDGE (2 << TCN_CMR_EEVTEDG_SHIFT) /* Falling edge */ +# define TCN_CMR_EEVTEDG_EACH (3 << TCN_CMR_EEVTEDG_SHIFT) /* Each edge */ +#define TCN_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */ +#define TCN_CMR_EEVT_MASK (3 << TCN_CMR_EEVT_SHIFT) +# define TCN_CMR_EEVT_TIOB (0 << TCN_CMR_EEVT_SHIFT) /* TIOB input */ +# define TCN_CMR_EEVT_XC0 (1 << TCN_CMR_EEVT_SHIFT) /* XC0 output */ +# define TCN_CMR_EEVT_XC1 (2 << TCN_CMR_EEVT_SHIFT) /* XC1 output */ +# define TCN_CMR_EEVT_XC2 (3 << TCN_CMR_EEVT_SHIFT) /* XC2 output */ +#define TCN_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */ +#define TCN_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */ +#define TCN_CMR_WAVSEL_MASK (3 << TCN_CMR_WAVSEL_SHIFT) +# define TCN_CMR_WAVSEL_UP (0 << TCN_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPAUTO (1 << TCN_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPDWN (2 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPDWNAUTO (3 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */ +#define TCN_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ACPA_MASK (3 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_NONE (0 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_SET (1 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_CLEAR (2 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_TOGGLE (3 << TCN_CMR_ACPA_SHIFT) +#define TCN_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ACPC_MASK (3 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_NONE (0 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_SET (1 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_CLEAR (2 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_TOGGLE (3 << TCN_CMR_ACPC_SHIFT) +#define TCN_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */ +#define TCN_CMR_AEEVT_MASK (3 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_NONE (0 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_SET (1 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_CLEAR (2 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_TOGGLE (3 << TCN_CMR_AEEVT_SHIFT) +#define TCN_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ASWTRG_MASK (3 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_NONE (0 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_SET (1 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_CLEAR (2 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_TOGGLE (3 << TCN_CMR_ASWTRG_SHIFT) +#define TCN_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BCPB_MASK (3 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_NONE (0 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_SET (1 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_CLEAR (2 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_TOGGLE (3 << TCN_CMR_BCPB_SHIFT) +#define TCN_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BCPC_MASK (3 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_NONE (0 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_SET (1 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_CLEAR (2 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_TOGGLE (3 << TCN_CMR_BCPC_SHIFT) +#define TCN_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BEEVT_MASK (3 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_NONE (0 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_SET (1 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_CLEAR (2 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_TOGGLE (3 << TCN_CMR_BEEVT_SHIFT) +#define TCN_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BSWTRG_MASK (3 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_NONE (0 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_SET (1 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT) + +/* TC Counter Value Register */ + +#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */ +#define TCN_CV_MASK (0xffff << TCN_CV_SHIFT) + +/* TC Register A, B, C */ + +#define TCN_RVALUE_SHIFT (0) /* Bits 0-15: Register A, B, or C value */ +#define TCN_RVALUE_MASK (0xffff << TCN_RVALUE_SHIFT) + +/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */ + +#define TCN_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */ +#define TCN_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */ +#define TCN_INT_CPAS (1 << 2) /* Bit 2: RA Compare */ +#define TCN_INT_CPBS (1 << 3) /* Bit 3: RB Compare */ +#define TCN_INT_CPCS (1 << 4) /* Bit 4: RC Compare */ +#define TCN_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */ +#define TCN_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */ +#define TCN_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */ +#define TCN_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */ +#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ +#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_TC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_twi.h b/nuttx/arch/arm/src/sam34/chip/sam_twi.h new file mode 100644 index 000000000..056f1062e --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_twi.h @@ -0,0 +1,192 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_twi.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_TWI_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_TWI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* TWI register offsets *****************************************************************/ + +#define SAM_TWI_CR_OFFSET 0x00 /* Control Register */ +#define SAM_TWI_MMR_OFFSET 0x04 /* Master Mode Register */ +#define SAM_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */ +#define SAM_TWI_IADR_OFFSET 0x0c /* Internal Address Register */ +#define SAM_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */ +#define SAM_TWI_SR_OFFSET 0x20 /* Status Register */ +#define SAM_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */ +#define SAM_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */ +#define SAM_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */ +#define SAM_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */ +#define SAM_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */ + /* 0x38-0xfc: Reserved */ + /* 0x100-0x124: Reserved for the PDC */ + +/* TWI register adresses ****************************************************************/ + +#define SAM_TWI_CR(n) (SAM_TWIN_BASE(n)+SAM_TWI_CR_OFFSET) +#define SAM_TWI_MMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_MMR_OFFSET) +#define SAM_TWI_SMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_SMR_OFFSET) +#define SAM_TWI_IADR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IADR_OFFSET) +#define SAM_TWI_CWGR(n) (SAM_TWIN_BASE(n)+SAM_TWI_CWGR_OFFSET) +#define SAM_TWI_SR(n) (SAM_TWIN_BASE(n)+SAM_TWI_SR_OFFSET) +#define SAM_TWI_IER(n) (SAM_TWIN_BASE(n)+SAM_TWI_IER_OFFSET) +#define SAM_TWI_IDR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IDR_OFFSET) +#define SAM_TWI_IMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IMR_OFFSET) +#define SAM_TWI_RHR(n) (SAM_TWIN_BASE(n)+SAM_TWI_RHR_OFFSET) +#define SAM_TWI_THR(n) (SAM_TWIN_BASE(n)+SAM_TWI_THR_OFFSET) + +#define SAM_TWI0_CR (SAM_TWI0_BASE+SAM_TWI_CR_OFFSET) +#define SAM_TWI0_MMR (SAM_TWI0_BASE+SAM_TWI_MMR_OFFSET) +#define SAM_TWI0_SMR (SAM_TWI0_BASE+SAM_TWI_SMR_OFFSET) +#define SAM_TWI0_IADR (SAM_TWI0_BASE+SAM_TWI_IADR_OFFSET) +#define SAM_TWI0_CWGR (SAM_TWI0_BASE+SAM_TWI_CWGR_OFFSET) +#define SAM_TWI0_SR (SAM_TWI0_BASE+SAM_TWI_SR_OFFSET) +#define SAM_TWI0_IER (SAM_TWI0_BASE+SAM_TWI_IER_OFFSET) +#define SAM_TWI0_IDR (SAM_TWI0_BASE+SAM_TWI_IDR_OFFSET) +#define SAM_TWI0_IMR (SAM_TWI0_BASE+SAM_TWI_IMR_OFFSET) +#define SAM_TWI0_RHR (SAM_TWI0_BASE+SAM_TWI_RHR_OFFSET) +#define SAM_TWI0_THR (SAM_TWI0_BASE+SAM_TWI_THR_OFFSET) + +#define SAM_TWI1_CR (SAM_TWI1_BASE+SAM_TWI_CR_OFFSET) +#define SAM_TWI1_MMR (SAM_TWI1_BASE+SAM_TWI_MMR_OFFSET) +#define SAM_TWI1_SMR (SAM_TWI1_BASE+SAM_TWI_SMR_OFFSET) +#define SAM_TWI1_IADR (SAM_TWI1_BASE+SAM_TWI_IADR_OFFSET) +#define SAM_TWI1_CWGR (SAM_TWI1_BASE+SAM_TWI_CWGR_OFFSET) +#define SAM_TWI1_SR (SAM_TWI1_BASE+SAM_TWI_SR_OFFSET) +#define SAM_TWI1_IER (SAM_TWI1_BASE+SAM_TWI_IER_OFFSET) +#define SAM_TWI1_IDR (SAM_TWI1_BASE+SAM_TWI_IDR_OFFSET) +#define SAM_TWI1_IMR (SAM_TWI1_BASE+SAM_TWI_IMR_OFFSET) +#define SAM_TWI1_RHR (SAM_TWI1_BASE+SAM_TWI_RHR_OFFSET) +#define SAM_TWI1_THR (SAM_TWI1_BASE+SAM_TWI_THR_OFFSET) + +/* TWI register bit definitions *********************************************************/ + +/* TWI Control Register */ + +#define TWI_CR_START (1 << 0) /* Bit 0: Send a START Condition */ +#define TWI_CR_STOP (1 << 1) /* Bit 1: Send a STOP Condition */ +#define TWI_CR_MSEN (1 << 2) /* Bit 2: TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (1 << 3) /* Bit 3: TWI Master Mode Disabled */ +#define TWI_CR_SVEN (1 << 4) /* Bit 4: TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (1 << 5) /* Bit 5: TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (1 << 6) /* Bit 6: SMBUS Quick Command */ +#define TWI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ + +/* TWI Master Mode Register */' + +#define TWI_MMR_IADRSZ_SHIFT (8) /* Bits 8-9: Internal Device Address Size */ +#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_SHIFT) +# define TWI_MMR_IADRSZ_NONE (0 << TWI_MMR_IADRSZ_SHIFT) /* No internal device address */ +# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ +# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ +# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ +#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ +#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */ +#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT) + +/* TWI Slave Mode Register */ + +#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */ +#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT) + +/* TWI Internal Address Register */ + +#define TWI_IADR_SHIFT (0) /* Bits 0-23: Internal Address */ +#define TWI_IADR_MASK (0x00ffffff << TWI_IADR_SHIFT) + +/* TWI Clock Waveform Generator Register */ + +#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */ +#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */ +#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */ +#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT) + +/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable + * Register, and TWI Interrupt Mask Register common bit fields. + */ + +#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */ +#define TWI_INT_RXRDY (1 << 1) /* Bit 1: Receive Holding Register */ +#define TWI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Holding Register Ready */ +#define TWI_SR_SVREAD (1 << 3) /* Bit 3: Slave Read (SR only) */ +#define TWI_INT_SVACC (1 << 4) /* Bit 4: Slave Access */ +#define TWI_INT_GACC (1 << 5) /* Bit 5: General Call Access */ +#define TWI_INT_OVRE (1 << 6) /* Bit 6: Overrun Error */ +#define TWI_INT_NACK (1 << 8) /* Bit 8: Not Acknowledged */ +#define TWI_INT_ARBLST (1 << 9) /* Bit 9: Arbitration Lost */ +#define TWI_INT_SCLWS (1 << 10) /* Bit 10: Clock Wait State */ +#define TWI_INT_EOSACC (1 << 11) /* Bit 11: End Of Slave Access */ +#define TWI_INT_ENDRX (1 << 12) /* Bit 12: End of RX buffer */ +#define TWI_INT_ENDTX (1 << 13) /* Bit 13: End of TX buffer */ +#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */ +#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */ + +/* TWI Receive Holding Register */ + +#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */ +#define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT) + +/* TWI Transmit Holding Register */ + +#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_TWI_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_uart.h b/nuttx/arch/arm/src/sam34/chip/sam_uart.h new file mode 100644 index 000000000..4825435fd --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_uart.h @@ -0,0 +1,391 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam_uart.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* UART register offsets ************************************************************************/ + +#define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ +#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ +#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ +#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ +#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ +#define SAM_UART_SR_OFFSET 0x0014 /* Status Register (Common) */ +#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ +#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ +#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ + /* 0x0024-0x003c: Reserved (UART) */ +#define SAM_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ +#define SAM_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ + /* 0x002c-0x003c: Reserved (UART) */ +#define SAM_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ +#define SAM_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ + /* 0x0048: Reserved (USART) */ +#define SAM_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */ +#define SAM_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ +#define SAM_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ +#define SAM_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ + /* 0x005c-0xf008: Reserved (USART) */ +#define SAM_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ + /* 0x0100-0x0124: PDC Area (Common) */ + +/* UART register adresses ***********************************************************************/ + +#define SAM_UART_CR (SAM_UART_BASE+SAM_UART_CR_OFFSET) +#define SAM_UART_MR (SAM_UART_BASE+SAM_UART_MR_OFFSET) +#define SAM_UART_IER (SAM_UART_BASE+SAM_UART_IER_OFFSET) +#define SAM_UART_IDR (SAM_UART_BASE+SAM_UART_IDR_OFFSET) +#define SAM_UART_IMR (SAM_UART_BASE+SAM_UART_IMR_OFFSET) +#define SAM_UART_SR (SAM_UART_BASE+SAM_UART_SR_OFFSET) +#define SAM_UART_RHR (SAM_UART_BASE+SAM_UART_RHR_OFFSET) +#define SAM_UART_THR (SAM_UART_BASE+SAM_UART_THR_OFFSET) +#define SAM_UART_BRGR (SAM_UART_BASE+SAM_UART_BRGR_OFFSET) + +#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) +#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) +#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET) +#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET) +#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET) +#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET) +#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET) +#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET) +#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET) +#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_USART_RTOR_OFFSET) +#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_USART_TTGR_OFFSET) +#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_USART_FIDI_OFFSET) +#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_USART_NER_OFFSET) +#define SAM_USART_IF(n) (SAM_USARTN_BASE(n)+SAM_USART_IF_OFFSET) +#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_USART_MAN_OFFSET) +#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPMR_OFFSET) +#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPSR_OFFSET) +#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_USART_VERSION_OFFSET) + +#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_USART_RTOR_OFFSET) +#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_USART_TTGR_OFFSET) +#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_USART_FIDI_OFFSET) +#define SAM_USART0_NER (SAM_USART0_BASE+SAM_USART_NER_OFFSET) +#define SAM_USART0_IF (SAM_USART0_BASE+SAM_USART_IF_OFFSET) +#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_USART_MAN_OFFSET) +#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_USART_WPMR_OFFSET) +#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_USART_WPSR_OFFSET) +#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_USART_VERSION_OFFSET) + +#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_USART_RTOR_OFFSET) +#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_USART_TTGR_OFFSET) +#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_USART_FIDI_OFFSET) +#define SAM_USART1_NER (SAM_USART1_BASE+SAM_USART_NER_OFFSET) +#define SAM_USART1_IF (SAM_USART1_BASE+SAM_USART_IF_OFFSET) +#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_USART_MAN_OFFSET) +#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_USART_WPMR_OFFSET) +#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_USART_WPSR_OFFSET) +#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_USART_VERSION_OFFSET) + +#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_USART_RTOR_OFFSET) +#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_USART_TTGR_OFFSET) +#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_USART_FIDI_OFFSET) +#define SAM_USART2_NER (SAM_USART2_BASE+SAM_USART_NER_OFFSET) +#define SAM_USART2_IF (SAM_USART2_BASE+SAM_USART_IF_OFFSET) +#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_USART_MAN_OFFSET) +#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_USART_WPMR_OFFSET) +#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_USART_WPSR_OFFSET) +#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_USART_VERSION_OFFSET) + +#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) +#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) +#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) +#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) +#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET) +#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET) +#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET) +#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_USART_RTOR_OFFSET) +#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_USART_TTGR_OFFSET) +#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_USART_FIDI_OFFSET) +#define SAM_USART3_NER (SAM_USART3_BASE+SAM_USART_NER_OFFSET) +#define SAM_USART3_IF (SAM_USART3_BASE+SAM_USART_IF_OFFSET) +#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_USART_MAN_OFFSET) +#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_USART_WPMR_OFFSET) +#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_USART_WPSR_OFFSET) +#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_USART_VERSION_OFFSET) + +/* UART register bit definitions ****************************************************************/ + +/* UART Control Register */ + +#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ +#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ +#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ +#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ +#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ +#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ +#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ +#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ +#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ +#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ +#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ +#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ +#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ +#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ +#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ +#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */ +#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ +#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */ + +/* UART Mode Register */ + +#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ +#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT) +# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */ +# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */ +# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */ +# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ +# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ +# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */ +# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */ +# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */ +#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ +#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT) +# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */ +# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ +# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */ +#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ +#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT) +# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */ +# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */ +# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */ +# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */ +#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ +#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */ +#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ +#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) +# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ +# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ +# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ +# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ +# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ +# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ +#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ +#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT) +# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ +# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ +# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ +#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ +#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) +# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ +# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ +# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ +# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ +#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */ +#define USART_MR_CPOL (1 << 16) +#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ +#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ +#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ +#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ +#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ +#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ +#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ +#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ +#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT) +#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ +#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ +#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ +#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ + +/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask + * Register, and UART Status Register common bit field definitions + */ + +#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ +#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ +#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ +#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ +#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ +#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ +#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ +#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ +#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ +#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ +#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ +#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */ +#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ +#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ +#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ +#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ +#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ + +/* UART Receiver Holding Register */ + +#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ +#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) +#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ +#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) +#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ + +/* UART Transmit Holding Register */ + +#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ +#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) +#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ +#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT) +#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ + +/* UART Baud Rate Generator Register */ + +#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ +#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) +#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ +#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) + +/* USART Receiver Time-out Register (USART only) */ + +#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ +#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT) + +/* USART Transmitter Timeguard Register (USART only) */ + +#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ +#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT) + +/* USART FI DI RATIO Register (USART only) */ + +#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ +#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT) + +/* USART Number of Errors Register (USART only) */ + +#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ +#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT) + +/* USART IrDA FILTER Register (USART only) */ + +#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ +#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT) + +/* USART Manchester Configuration Register (USART only) */ + +#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ +#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT) +#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ +#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT) +# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */ +# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ +# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ +# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ +#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ +#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ +#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT) +#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ +#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT) +# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */ +# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */ +# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */ +# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */ +#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ +#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ + +/* USART Write Protect Mode Register (USART only) */ + +#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ +#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ +#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT) + +/* USART Write Protect Status Register (USART only) */ + +#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ +#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ +#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT) + +/* USART Version Register */ + +#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ +#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT) +#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ +#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT) + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_udphs.h b/nuttx/arch/arm/src/sam34/chip/sam_udphs.h new file mode 100644 index 000000000..9229cd837 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_udphs.h @@ -0,0 +1,371 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_udphs.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDPHS_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDPHS_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* UDPHS register offsets ***************************************************************/ + +#define SAM_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */ +#define SAM_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */ + /* 0x08-0x0C: Reserved */ +#define SAM_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */ +#define SAM_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */ +#define SAM_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */ +#define SAM_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */ + /* 0x20-0xcc: Reserved */ +#define SAM_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */ + /* 0xE4-0xE8: Reserved */ +#define SAM_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */ +#define SAM_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */ +#define SAM_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */ + +/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180, + * 0x1a0, and 0x1c0 + */ + +#define SAM_UDPHSEP_OFFSET(n) (0x100+((n)<<5)) +#define SAM_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */ +#define SAM_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */ +#define SAM_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */ +#define SAM_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */ + /* 0x10: Reserved */ +#define SAM_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */ +#define SAM_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */ +#define SAM_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */ + /* 0x1e0-0x300: Reserved */ + /* 0x300-0x30c: Reserved */ +/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and + * 0x360. NOTE that there is no DMA channel 0. + */ + +#define SAM_UDPHSDMA_OFFSET(n) (0x310+((n)<<4)) +#define SAM_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */ +#define SAM_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */ +#define SAM_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */ +#define SAM_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */ + +/* UDPHS register adresses **************************************************************/ + +#define SAM_UDPHS_CTRL (SAM_UDPHS_BASE+SAM_UDPHS_CTRL_OFFSET) +#define SAM_UDPHS_FNUM (SAM_UDPHS_BASE+SAM_UDPHS_FNUM_OFFSET) +#define SAM_UDPHS_IEN (SAM_UDPHS_BASE+SAM_UDPHS_IEN_OFFSET) +#define SAM_UDPHS_INTSTA (SAM_UDPHS_BASE+SAM_UDPHS_INTSTA_OFFSET) +#define SAM_UDPHS_CLRINT (SAM_UDPHS_BASE+ SAM_UDPHS_CLRINT_OFFSET) +#define SAM_UDPHS_EPTRST (SAM_UDPHS_BASE+SAM_UDPHS_EPTRST_OFFSET) +#define SAM_UDPHS_TST (SAM_UDPHS_BASE+SAM_UDPHS_TST_OFFSET) +#define SAM_UDPHS_IPNAME1 (SAM_UDPHS_BASE+SAM_UDPHS_IPNAME1_OFFSET) +#define SAM_UDPHS_IPNAME2 (SAM_UDPHS_BASE+SAM_UDPHS_IPNAME2_OFFSET) +#define SAM_UDPHS_IPFEATURES (SAM_UDPHS_BASE+SAM_UDPHS_IPFEATURES_OFFSET) + +/* Endpoint registers */ + +#define SAM_UDPHSEP_BASE(n)) (SAM_UDPHS_BASE+SAM_UDPHSEP_OFFSET(n)) +#define SAM_UDPHSEP_CFG(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CFG_OFFSET) +#define SAM_UDPHSEP_CTLENB(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CTLENB_OFFSET) +#define SAM_UDPHSEP_CTLDIS(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CTLDIS_OFFSET) +#define SAM_UDPHSEP_CTL(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CTL_OFFSET) +#define SAM_UDPHSEP_SETSTA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_SETSTA_OFFSET) +#define SAM_UDPHSEP_CLRSTA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CLRSTA_OFFSET) +#define SAM_UDPHSEP_STA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_STA_OFFSET) + +/* DMA Channel Registers*/ + +#define SAM_UDPHSDMA_BASE(n) (SAM_UDPHS_BASE+SAM_UDPHSDMA_OFFSET(n)) +#define SAM_UDPHSDMA_NXTDSC(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_NXTDSC_OFFSET) +#define SAM_UDPHSDMA_ADDRESS(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_ADDRESS_OFFSET) +#define SAM_UDPHSDMA_CONTROL(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_CONTROL_OFFSET) +#define SAM_UDPHSDMA_STATUS(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_STATUS_OFFSET) + +/* UDPHS register bit definitions *******************************************************/ +/* UDPHS Control Register */ + +#define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */ +#define UDPHS_CTRL_DEVADDR_MASK (0x7f << UDPHS_CTRL_DEVADDR_SHIFT) +#define UDPHS_CTRL_FADDREN (1 << 7) /* Bit 7: Function Address Enable */ +#define UDPHS_CTRL_ENUDPHS (1 << 8) /* Bit 8: UDPHS Enable */ +#define UDPHS_CTRL_DETACH (1 << 9) /* Bit 9: Detach Command */ +#define UDPHS_CTRL_REWAKEUP (1 << 10) /* Bit 10: Send Remote Wake Up */ +#define UDPHS_CTRL_PULLDDIS (1 << 11) /* Bit 11: Pull-Down Disable */ + +/* UDPHS Frame Number Register */ + +#define UDPHS_FNUM_MICROFRAMENUM_SHIFT (0) /* Bits 0-2: Microframe Num */ +#define UDPHS_FNUM_MICROFRAMENUM_MASK (7 << UDPHS_FNUM_MICROFRAMENUM_SHIFT) +#define UDPHS_FNUM_FRAMENUMBER_SHIFT (3) /* Bits 3-7: Frame Number in Packet Field Formats */ +#define UDPHS_FNUM_FRAMENUMBER_MASK (31 << UDPHS_FNUM_FRAMENUMBER_SHIFT) +#define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */ +#define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT) + +/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear + * Interrupt Register common bit-field definitions + */ + +#define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */ +#define USBPHS_INT_MICROSOF (1 << 2) /* Bit 2: Micro-SOF Interrupt (Common) */ +#define USBPHS_INT_INTSOF (1 << 3) /* Bit 3: SOF Interrupt (Common) */ +#define USBPHS_INT_ENDRESET (1 << 4) /* Bit 4: End Of Reset Interrupt (Common) */ +#define USBPHS_INT_WAKEUP (1 << 5) /* Bit 5: Wake Up CPU Interrupt (Common) */ +#define USBPHS_INT_ENDOFRSM (1 << 6) /* Bit 6: End Of Resume Interrupt (Common) */ +#define USBPHS_INT_UPSTRRES (1 << 7) /* Bit 7: Upstream Resume Interrupt (Common) */ +#define USBPHS_INT_EPT(n) (1 << ((n)+8)) +#define USBPHS_INT_EPT0 (1 << 8) /* Bit 8: Endpoint 0 Interrupt (not Clear) */ +#define USBPHS_INT_EPT1 (1 << 9) /* Bit 9: Endpoint 1 Interrupt (not Clear) */ +#define USBPHS_INT_EPT2 (1 << 10) /* Bit 10: Endpoint 2 Interrupt (not Clear) */ +#define USBPHS_INT_EPT3 (1 << 11) /* Bit 11: Endpoint 3 Interrupt (not Clear) */ +#define USBPHS_INT_EPT4 (1 << 12) /* Bit 12: Endpoint 4 Interrupt (not Clear) */ +#define USBPHS_INT_EPT5 (1 << 13) /* Bit 13: Endpoint 5 Interrupt (not Clear) */ +#define USBPHS_INT_EPT6 (1 << 13) /* Bit 14: Endpoint 6 Interrupt (not Clear) */ +#define USBPHS_INT_DMA(n) (1<<((n)+24)) +#define USBPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt (not Clear) */ +#define USBPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt (not Clear) */ +#define USBPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt (not Clear) */ +#define USBPHS_INT_DMA4 (1 << 28) /* Bit 28: DMA Channel 4 Interrupt (not Clear) */ +#define USBPHS_INT_DMA5 (1 << 29) /* Bit 29: DMA Channel 5 Interrupt (not Clear) */ +#define USBPHS_INT_DMA6 (1 << 30) /* Bit 30: DMA Channel 6 Interrupt (not Clear) */ + +/* UDPHS Endpoints Reset Register */ + +#define UDPHS_EPTRST_EPT(n) (1<<(n)) /* Bit 0-6: Endpoint n Reset */ + +/* UDPHS Test Register */ + +#define UDPHS_TST_SPEEDCFG_SHIFT (0) /* Bits 0-1: Speed Configuration */ +#define UDPHS_TST_SPEEDCFG_MASK (3 << UDPHS_TST_SPEEDCFG_SHIFT) +# define UDPHS_TST_SPEEDCFG_NORMAL (0 << UDPHS_TST_SPEEDCFG_SHIFT) /* Normal Mode */ +# define UDPHS_TST_SPEEDCFG_HIGH (2 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force High Speed */ +# define UDPHS_TST_SPEEDCFG_FULL (3 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force Full Speed */ +#define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */ +#define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */ +#define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */ +#define UDPHS_TST_OPMODE2 (1 << 5) /* Bit 5: OpMode2 */ + +/* UDPHS Features Register */ + +#define UDPHS_IPFEATURES_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Max Number of Endpoints */ +#define UDPHS_IPFEATURES_EPTNBRMAX_MASK (15 << UDPHS_IPFEATURES_EPTNBRMAX_SHIFT) +#define UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */ +#define UDPHS_IPFEATURES_DMACHANNELNBR_MASK (7 << UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT) +#define UDPHS_IPFEATURES_DMABSIZ (1 << 7) /* Bit 7: DMA Buffer Size */ +#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */ +#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_MASK (15 << UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT) +# define UDPHS_IPFEATURES_DMAFIFOWDDEPTH(n) ((n)&15) +#define UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT (12) /* Bits 12-14: DPRAM Size */ +#define UDPHS_IPFEATURES_FIFOMAXSIZE_MASK (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) +# define UDPHS_IPFEATURES_FIFOMAXSIZE_128b (0 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 128 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_256b (1 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 256 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_512b (2 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 512 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_1Kb (3 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 1024 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_2Kb (4 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 2048 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */ +#define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */ +#define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */ +#define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16) +#define UDPHS_IPFEATURES_ISOEPT1 (1 << 17) /* Bit 17: EP1 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT2 (1 << 18) /* Bit 18: EP2 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT3 (1 << 19) /* Bit 19: EP3 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT4 (1 << 20) /* Bit 20: EP4 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT5 (1 << 21) /* Bit 21: EP5 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT6 (1 << 22) /* Bit 22: EP6 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */ + +/* UDPHS Endpoint Configuration Register (0-6) */ + +#define UDPHSEP_CFG_SIZE_SHIFT (0) /* Bits 0-2: Endpoint Size */ +#define UDPHSEP_CFG_SIZE_MASK (7 << UDPHSEP_CFG_SIZE_SHIFT) +# define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */ +# define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */ +# define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */ +# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */ +# define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */ +# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */ +# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */ +# define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */ +#define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */ +#define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */ +#define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT) +# define UDPHSEP_CFG_TYPE_CNTRL (0 << UDPHSEP_CFG_TYPE_SHIFT) /* Control endpoint */ +# define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */ +# define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */ +# define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */ +#define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */ +#define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) +# define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */ +# define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */ +# define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */ +# define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */ +#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */ +#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT) +#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */ + +/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register, + * and UDPHS Endpoint Control Register common bit-field definitions + */ + +#define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */ +#define UDPHSEP_INT_AUTOVALID (1 << 1) /* Bit 1: Packet Auto-Valid */ +#define UDPHSEP_INT_INTDISDMA (1 << 3) /* Bit 3: Interrupts Disable DMA */ +#define UDPHSEP_INT_NYETDIS (1 << 4) /* Bit 4: NYET Disable (HS Bulk OUT EPs) */ +#define UDPHSEP_INT_DATAXRX (1 << 6) /* Bit 6: DATAx Interrupt Enable (High B/W Isoc OUT EPs) */ +#define UDPHSEP_INT_MDATARX (1 << 7) /* Bit 7: MDATA Interrupt Enable (High B/W Isoc OUT EPs) */ +#define UDPHSEP_INT_ERROVFLW (1 << 8) /* Bit 8: Overflow Error Interrupt */ +#define UDPHSEP_INT_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Interrupt */ +#define UDPHSEP_INT_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Interrupt */ +#define UDPHSEP_INT_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Interrupt */ +#define UDPHSEP_INT_ERRTRANS (1 << 11) /* Bit 11: Transaction Error Interrupt */ +#define UDPHSEP_INT_RXSETUP (1 << 12) /* Bit 12: Received SETUP Interrupt */ +#define UDPHSEP_INT_ERRFLISO (1 << 12) /* Bit 12: Error Flow Interrupt */ +#define UDPHSEP_INT_STALLSNT (1 << 13) /* Bit 13: Stall Sent Interrupt */ +#define UDPHSEP_INT_ERRCRISO (1 << 13) /* Bit 13: ISO CRC Error Error Interrupt */ +#define UDPHSEP_INT_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Interrupt */ +#define UDPHSEP_INT_NAKIN (1 << 14) /* Bit 14: NAKIN Interrupt */ +#define UDPHSEP_INT_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Interrupt */ +#define UDPHSEP_INT_NAKOUT (1 << 15) /* Bit 15: NAKOUT Interrupt */ +#define UDPHSEP_INT_BUSYBANK (1 << 18) /* Bit 18: Busy Bank Interrupt */ +#define UDPHSEP_INT_SHRTPCKT (1 << 31) /* Bit 31: Short Packet Send/Short Packet Interrupt */ + +/* UDPHS Endpoint Set Status Register */ + +#define UDPHSEP_SETSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Set */ +#define UDPHSEP_SETSTA_KILLBANK (1 << 9) /* Bit 9: KILL Bank Set (for IN Endpoint) */ +#define UDPHSEP_SETSTA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Set */ + +/* UDPHS Endpoint Clear Status Register */ + +#define UDPHSEP_CLRSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Clear */ +#define UDPHSEP_CLRSTA_TOGGLESQ (1 << 6) /* Bit 6: Data Toggle Clear */ +#define UDPHSEP_CLRSTA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Clear */ +#define UDPHSEP_CLRSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Clear */ +#define UDPHSEP_CLRSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP Clear */ +#define UDPHSEP_CLRSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow Clear */ +#define UDPHSEP_CLRSTA_STALL_NT (1 << 13) /* Bit 13: Stall Sent Clear */ +#define UDPHSEP_CLRSTA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Clear */ +#define UDPHSEP_CLRSTA_NAKIN (1 << 14) /* Bit 14: NAKIN Clear */ +#define UDPHSEP_CLRSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Clear */ +#define UDPHSEP_CLRSTA_NAKOUT (1 << 15) /* Bit 15: NAKOUT Clear */ + +/* UDPHS Endpoint Status Register */ + +#define UDPHSEP_STA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request */ +#define UDPHSEP_STA_TOGGLESQSTA_SHIFT (6) /* Bits 6-7: Toggle Sequencing */ +#define UDPHSEP_STA_TOGGLESQSTA_MASK (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) +# define UDPHSEP_STA_TOGGLESQSTA_DATA0 (0 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data0 */ +# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */ +# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */ +# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */ +#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */ +#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */ +#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */ +#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */ +#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */ +#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */ +#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */ +#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */ +#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */ +#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */ +#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */ +#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */ +#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */ +#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */ +#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */ +#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK) +#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */ +#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT) +#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */ +#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT) +#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */ +#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT) +#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet + +/* UDPHS DMA Channel Control Register */ + +#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */ +#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */ +#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */ +#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */ +#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */ +#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */ +#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */ +#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */ +#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */ +#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT) + +/* UDPHS DMA Channel Status Register */ + +#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */ +#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */ +#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */ +#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */ +#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */ +#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */ +#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDPHS_H */ + diff --git a/nuttx/arch/arm/src/sam34/chip/sam_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam_wdt.h new file mode 100644 index 000000000..ffe0cb96d --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam_wdt.h @@ -0,0 +1,96 @@ +/**************************************************************************************** + * arch/arm/src/sam34/chip/sam_wdt.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM_WDT_CR_OFFSET 0x00 /* Control Register */ +#define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */ +#define SAM_WDT_SR_OFFSET 0x08 /* Status Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET) +#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) + +/* WDT register bit definitions ********************************************************/ + +#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ +#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) + +#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ +#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) +#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ +#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ +#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) +#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ + +#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ +#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H */ |