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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2010-01-03 13:01:35 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2010-01-03 13:01:35 +0000
commitf7e6efe48c4897cb302c3bc07fcae704546e6975 (patch)
treefbe79a0ea0162252cd8a0e2c16e4b502bb0553d4 /nuttx/arch/arm/src/sam3u/chip.h
parent96c2aa8f19b09d215c24e088947179ab182264a0 (diff)
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Add interrupt management logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2494 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/sam3u/chip.h')
-rwxr-xr-xnuttx/arch/arm/src/sam3u/chip.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/sam3u/chip.h b/nuttx/arch/arm/src/sam3u/chip.h
index 749459ca9..3f675a6f2 100755
--- a/nuttx/arch/arm/src/sam3u/chip.h
+++ b/nuttx/arch/arm/src/sam3u/chip.h
@@ -54,6 +54,16 @@
#include "sam3u_memorymap.h"
+/* NVIC priority levels *************************************************************/
+/* Each priority field holds a priority value, 0-15. The lower the value, the greater
+ * the priority of the corresponding interrupt. The processor implements only
+ * bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+
/************************************************************************************
* Public Types
************************************************************************************/