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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-01-02 18:57:46 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-01-02 18:57:46 +0000 |
| commit | 0d56bf6beab7be8e47be45bed325259adb8f4a2f (patch) | |
| tree | 21777ff5810d40e896540fa3ec14ae3761f036ae /nuttx/arch/arm/src/sam3u/sam3u_tc.h | |
| parent | 17c0d8941dbf5492e402761e33a4b6e9f92e92db (diff) | |
| download | px4-nuttx-0d56bf6beab7be8e47be45bed325259adb8f4a2f.tar.gz px4-nuttx-0d56bf6beab7be8e47be45bed325259adb8f4a2f.tar.bz2 px4-nuttx-0d56bf6beab7be8e47be45bed325259adb8f4a2f.zip | |
Clean up addressing
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2491 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/sam3u/sam3u_tc.h')
| -rwxr-xr-x | nuttx/arch/arm/src/sam3u/sam3u_tc.h | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_tc.h b/nuttx/arch/arm/src/sam3u/sam3u_tc.h index 0b4231039..1c330d38b 100755 --- a/nuttx/arch/arm/src/sam3u/sam3u_tc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_tc.h @@ -53,19 +53,19 @@ /* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */
-#define SAM3U_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */
-#define SAM3U_TCN_CCR_OFFSET 0x00 /* Channel Control Register */
-#define SAM3U_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */
+#define SAM3U_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */
+#define SAM3U_TCN_CCR_OFFSET 0x00 /* Channel Control Register */
+#define SAM3U_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */
/* 0x08 Reserved */
/* 0x0c Reserved */
-#define SAM3U_TCN_CV_OFFSET 0x10 /* Counter Value */
-#define SAM3U_TCN_RA_OFFSET 0x14 /* Register A */
-#define SAM3U_TCN_RB_OFFSET 0x18 /* Register B */
-#define SAM3U_TCN_RC_OFFSET 0x1c /* Register C */
-#define SAM3U_TCN_SR_OFFSET 0x20 /* Status Register */
-#define SAM3U_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */
-#define SAM3U_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */
-#define SAM3U_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */
+#define SAM3U_TCN_CV_OFFSET 0x10 /* Counter Value */
+#define SAM3U_TCN_RA_OFFSET 0x14 /* Register A */
+#define SAM3U_TCN_RB_OFFSET 0x18 /* Register B */
+#define SAM3U_TCN_RC_OFFSET 0x1c /* Register C */
+#define SAM3U_TCN_SR_OFFSET 0x20 /* Status Register */
+#define SAM3U_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */
+#define SAM3U_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */
+#define SAM3U_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */
/* Timer common registers */
@@ -82,16 +82,16 @@ /* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */
-#define SAM3U_TC_CCR(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_CCR_OFFSET)
-#define SAM3U_TC_CMR(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_CMR_OFFSET)
-#define SAM3U_TC_CV(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_CV_OFFSET)
-#define SAM3U_TC_RA(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_RA_OFFSET)
-#define SAM3U_TC_RB(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_RB_OFFSET)
-#define SAM3U_TC_RC(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_RC_OFFSET)
-#define SAM3U_TC_SR(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_SR_OFFSET)
-#define SAM3U_TC_IER(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_IER_OFFSET)
-#define SAM3U_TC_IDR(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_IDR_OFFSET)
-#define SAM3U_TC_IMR(n) (SAM3U_TC_BASE(n)+SAM3U_TCN_IMR_OFFSET)
+#define SAM3U_TC_CCR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CCR_OFFSET)
+#define SAM3U_TC_CMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CMR_OFFSET)
+#define SAM3U_TC_CV(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CV_OFFSET)
+#define SAM3U_TC_RA(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RA_OFFSET)
+#define SAM3U_TC_RB(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RB_OFFSET)
+#define SAM3U_TC_RC(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RC_OFFSET)
+#define SAM3U_TC_SR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_SR_OFFSET)
+#define SAM3U_TC_IER(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IER_OFFSET)
+#define SAM3U_TC_IDR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IDR_OFFSET)
+#define SAM3U_TC_IMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IMR_OFFSET)
#define SAM3U_TC0_CCR (SAM3U_TC0_BASE+SAM3U_TCN_CCR_OFFSET)
#define SAM3U_TC0_CMR (SAM3U_TC0_BASE+SAM3U_TCN_CMR_OFFSET)
@@ -128,12 +128,12 @@ /* Timer common registers */
-#define SAM3U_TC_BCR (SAM3U_TC0_BASE+SAM3U_TC_BCR_OFFSET)
-#define SAM3U_TC_BMR (SAM3U_TC0_BASE+SAM3U_TC_BMR_OFFSET)
-#define SAM3U_TC_QIER (SAM3U_TC0_BASE+SAM3U_TC_QIER_OFFSET)
-#define SAM3U_TC_QIDR (SAM3U_TC0_BASE+SAM3U_TC_QIDR_OFFSET)
-#define SAM3U_TC_QIMR (SAM3U_TC0_BASE+SAM3U_TC_QIMR_OFFSET)
-#define SAM3U_TC_QISR (SAM3U_TC0_BASE+SAM3U_TC_QISR_OFFSET)
+#define SAM3U_TC_BCR (SAM3U_TC_BASE+SAM3U_TC_BCR_OFFSET)
+#define SAM3U_TC_BMR (SAM3U_TC_BASE+SAM3U_TC_BMR_OFFSET)
+#define SAM3U_TC_QIER (SAM3U_TC_BASE+SAM3U_TC_QIER_OFFSET)
+#define SAM3U_TC_QIDR (SAM3U_TC_BASE+SAM3U_TC_QIDR_OFFSET)
+#define SAM3U_TC_QIMR (SAM3U_TC_BASE+SAM3U_TC_QIMR_OFFSET)
+#define SAM3U_TC_QISR (SAM3U_TC_BASE+SAM3U_TC_QISR_OFFSET)
/* TC register bit definitions ******************************************************************/
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