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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-01-01 17:39:58 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-01-01 17:39:58 +0000 |
| commit | 1d28f0a58dbb6091ac2081ed4ebdc79ecfe6b254 (patch) | |
| tree | 6ad4f7b194f95459b73797efa188f719f88722e9 /nuttx/arch/arm/src/sam3u/sam3u_wdt.h | |
| parent | 517c7e1e531449c0660be0fa107bf7c0e9ebc590 (diff) | |
| download | px4-nuttx-1d28f0a58dbb6091ac2081ed4ebdc79ecfe6b254.tar.gz px4-nuttx-1d28f0a58dbb6091ac2081ed4ebdc79ecfe6b254.tar.bz2 px4-nuttx-1d28f0a58dbb6091ac2081ed4ebdc79ecfe6b254.zip | |
Add SUPC register definition file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2480 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/sam3u/sam3u_wdt.h')
| -rwxr-xr-x | nuttx/arch/arm/src/sam3u/sam3u_wdt.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_wdt.h b/nuttx/arch/arm/src/sam3u/sam3u_wdt.h index ae418d723..b885608d7 100755 --- a/nuttx/arch/arm/src/sam3u/sam3u_wdt.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_wdt.h @@ -51,35 +51,35 @@ /* WDT register offsets ****************************************************************/
-#define SAM3U_WDT_CR_OFFSET 0x00 /* Control Register */
-#define SAM3U_WDT_MR_OFFSET 0x04 /* Mode Register */
-#define SAM3U_WDT_SR_OFFSET 0x08 /* Status Register */
+#define SAM3U_WDT_CR_OFFSET 0x00 /* Control Register */
+#define SAM3U_WDT_MR_OFFSET 0x04 /* Mode Register */
+#define SAM3U_WDT_SR_OFFSET 0x08 /* Status Register */
/* WDT register adresses ***************************************************************/
-#define SAM3U_WDT_CR (SAM3U_WDT_BASE+SAM3U_WDT_CR_OFFSET)
-#define SAM3U_WDT_MR (SAM3U_WDT_BASE+SAM3U_WDT_MR_OFFSET)
-#define SAM3U_WDT_SR (SAM3U_WDT_BASE+SAM3U_WDT_SR_OFFSET)
+#define SAM3U_WDT_CR (SAM3U_WDT_BASE+SAM3U_WDT_CR_OFFSET)
+#define SAM3U_WDT_MR (SAM3U_WDT_BASE+SAM3U_WDT_MR_OFFSET)
+#define SAM3U_WDT_SR (SAM3U_WDT_BASE+SAM3U_WDT_SR_OFFSET)
/* WDT register bit definitions ********************************************************/
-#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
-#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
-#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
-
-#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
-#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT)
-#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
-#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
-#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
-#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
-#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */
-#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT)
-#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
-#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
-
-#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
-#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
+#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
+#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
+#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
+
+#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
+#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT)
+#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
+#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
+#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */
+#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT)
+#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
+
+#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
+#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
/****************************************************************************************
* Public Types
|