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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-01-01 17:46:29 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-01-01 17:46:29 +0000 |
commit | 8881f3e01c47c433e6c87e11fcb2034e1bc5ed2a (patch) | |
tree | f870b4ce09f2ca1d0a7034cd22b6795e8abdd7e6 /nuttx/arch/arm/src/sam3u | |
parent | 1d28f0a58dbb6091ac2081ed4ebdc79ecfe6b254 (diff) | |
download | px4-nuttx-8881f3e01c47c433e6c87e11fcb2034e1bc5ed2a.tar.gz px4-nuttx-8881f3e01c47c433e6c87e11fcb2034e1bc5ed2a.tar.bz2 px4-nuttx-8881f3e01c47c433e6c87e11fcb2034e1bc5ed2a.zip |
Add GPBR register definition file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2481 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/sam3u')
-rwxr-xr-x | nuttx/arch/arm/src/sam3u/sam3u_gpbr.h | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_gpbr.h b/nuttx/arch/arm/src/sam3u/sam3u_gpbr.h new file mode 100755 index 000000000..e3ac0c128 --- /dev/null +++ b/nuttx/arch/arm/src/sam3u/sam3u_gpbr.h @@ -0,0 +1,90 @@ +/****************************************************************************************
+ * arch/arm/src/sam3u/sam3u_gpbr.h
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H
+#define __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "sam3u_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* GPBR register offsets ****************************************************************/
+
+#define SAM3U_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */
+#define SAM3U_GPBR0_OFFSET 0x00
+#define SAM3U_GPBR1_OFFSET 0x04
+#define SAM3U_GPBR2_OFFSET 0x08
+#define SAM3U_GPBR3_OFFSET 0x0c
+#define SAM3U_GPBR4_OFFSET 0x10
+#define SAM3U_GPBR5_OFFSET 0x14
+#define SAM3U_GPBR6_OFFSET 0x18
+#define SAM3U_GPBR7_OFFSET 0x1c
+
+/* GPBR register adresses ***************************************************************/
+
+#define SAM3U_GPBR(n)) (SAM3U_GPBR_BASE+SAM3U_GPBR_OFFSET(n))
+#define SAM3U_GPBR0 (SAM3U_GPBR_BASE+SAM3U_GPBR0_OFFSET)
+#define SAM3U_GPBR1 (SAM3U_GPBR_BASE+SAM3U_GPBR1_OFFSET)
+#define SAM3U_GPBR2 (SAM3U_GPBR_BASE+SAM3U_GPBR2_OFFSET)
+#define SAM3U_GPBR3 (SAM3U_GPBR_BASE+SAM3U_GPBR3_OFFSET)
+#define SAM3U_GPBR4 (SAM3U_GPBR_BASE+SAM3U_GPBR4_OFFSET)
+#define SAM3U_GPBR5 (SAM3U_GPBR_BASE+SAM3U_GPBR5_OFFSET)
+#define SAM3U_GPBR6 (SAM3U_GPBR_BASE+SAM3U_GPBR6_OFFSET)
+#define SAM3U_GPBR7 (SAM3U_GPBR_BASE+SAM3U_GPBR7_OFFSET)
+
+/* GPBR register bit definitions ********************************************************/
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Functions
+ ****************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H */
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