Eliminated sam3u_internal.h. Use separate header files instead. More renaming from sam3u_ to sam_ to make room in the namespce for the sam4l_

29 files changed, 2420 insertions, 1596 deletions

diff --git a/nuttx/arch/arm/src/sam3u/Make.defs b/nuttx/arch/arm/src/sam3u/Make.defs
index 1092090a0..025ad0be4 100644
--- a/nuttx/arch/arm/src/sam3u/Make.defs
+++ b/nuttx/arch/arm/src/sam3u/Make.defs
@@ -35,7 +35,7 @@
 
 # The start-up, "head", file
 
-HEAD_ASRC = sam3u_vectors.S
+HEAD_ASRC = sam_vectors.S
 
 # Common ARM and Cortex-M3 files
 
@@ -77,24 +77,24 @@ endif
 # Required SAM3/4 files
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = sam3u_allocateheap.c sam3u_clockconfig.c sam3u_gpioirq.c
-CHIP_CSRCS += sam3u_irq.c sam3u_lowputc.c sam3u_pio.c sam3u_serial.c
-CHIP_CSRCS += sam3u_start.c sam3u_timerisr.c
+CHIP_CSRCS  = sam_allocateheap.c sam_clockconfig.c sam_gpioirq.c
+CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_gpio.c sam_serial.c
+CHIP_CSRCS += sam_start.c sam_timerisr.c
 
 # Configuration-dependent SAM3/4 files
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)
-CHIP_CSRCS += sam3u_userspace.c sam3u_mpuinit.c
+CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
 endif
 
 ifeq ($(CONFIG_SAM34_DMA),y)
-CHIP_CSRCS += sam3u_dmac.c
+CHIP_CSRCS += sam_dmac.c
 endif
 
 ifeq ($(CONFIG_SAM34_HSMCI),y)
-CHIP_CSRCS += sam3u_hsmci.c
+CHIP_CSRCS += sam_hsmci.c
 endif
 
 ifeq ($(CONFIG_SAM34_SPI),y)
-CHIP_CSRCS += sam3u_spi.c
+CHIP_CSRCS += sam_spi.c
 endif
diff --git a/nuttx/arch/arm/src/sam3u/chip/sam3u_pinmap.h b/nuttx/arch/arm/src/sam3u/chip/sam3u_pinmap.h
new file mode 100644
index 000000000..17287b05f
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/chip/sam3u_pinmap.h
@@ -0,0 +1,223 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/chip/sam3u_pinmap.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM3U_PINMAP_H
+#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM3U_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "sam_gpio.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* GPIO pin definitions *************************************************************/
+
+#define GPIO_ADC0_AD0       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
+#define GPIO_ADC0_AD1       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30)
+#define GPIO_ADC0_AD2       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN3)
+#define GPIO_ADC0_AD3       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN4)
+#define GPIO_ADC0_AD4       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN15)
+#define GPIO_ADC0_AD5       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN16)
+#define GPIO_ADC0_AD6       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN17)
+#define GPIO_ADC0_AD7       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN18)
+
+#define GPIO_CAN_XCVR_RS    (GPIO_OUTPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_OUTPUT_SET|GPIO_PIN23)
+#define GPIO_CAN1_XCVR_TXD  (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN27)
+#define GPIO_CAN1_XCVR_RXD  (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN26)
+#define GPIO_CAN2_XCVR_TXD  (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN29)
+#define GPIO_CAN2_XCVR_RXD  (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN28)
+
+#define GPIO_SMC_D0         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN9)  /* Check! */
+#define GPIO_SMC_D1         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN10) /* Check! */
+#define GPIO_SMC_D2         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN11) /* Check! */
+#define GPIO_SMC_D3         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN12) /* Check! */
+#define GPIO_SMC_D4         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN13) /* Check! */
+#define GPIO_SMC_D5         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN14) /* Check! */
+#define GPIO_SMC_D6         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN15) /* Check! */
+#define GPIO_SMC_D7         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN16) /* Check! */
+#define GPIO_SMC_D8         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN25) /* Check! */
+#define GPIO_SMC_D9         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN26) /* Check! */
+#define GPIO_SMC_D10        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN27) /* Check! */
+#define GPIO_SMC_D11        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN28) /* Check! */
+#define GPIO_SMC_D12        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN29) /* Check! */
+#define GPIO_SMC_D13        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN30) /* Check! */
+#define GPIO_SMC_D14        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN31) /* Check! */
+#define GPIO_SMC_D15        (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN6)   /* Check! */
+#define GPIO_SMC_NCS0       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN20)
+#define GPIO_SMC_NRD        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN19)
+#define GPIO_SMC_NWE        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN23)
+#define GPIO_SMC_PSRAM_A0   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN0)  /* Check! */
+#define GPIO_SMC_PSRAM_A1   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN1)  /* Check! */
+#define GPIO_SMC_PSRAM_A2   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN2)  /* Check! */
+#define GPIO_SMC_PSRAM_A3   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN3)  /* Check! */
+#define GPIO_SMC_PSRAM_A4   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN4)  /* Check! */
+#define GPIO_SMC_PSRAM_A5   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN5)  /* Check! */
+#define GPIO_SMC_PSRAM_A6   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN6)  /* Check! */
+#define GPIO_SMC_PSRAM_A7   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN7)  /* Check! */
+#define GPIO_SMC_PSRAM_A8   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN8)  /* Check! */
+#define GPIO_SMC_PSRAM_A9   (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN9)  /* Check! */
+#define GPIO_SMC_PSRAM_A10  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN10) /* Check! */
+#define GPIO_SMC_PSRAM_A11  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN11) /* Check! */
+#define GPIO_SMC_PSRAM_A12  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN24) /* Check! */
+#define GPIO_SMC_PSRAM_A13  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN25) /* Check! */
+#define GPIO_SMC_PSRAM_A14  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN26) /* Check! */
+#define GPIO_SMC_PSRAM_A15  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN27) /* Check! */
+#define GPIO_SMC_PSRAM_A16  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN27) /* Check! */
+#define GPIO_SMC_PSRAM_A17  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN28) /* Check! */
+#define GPIO_SMC_PSRAM_A18  (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN29) /* Check! */
+#define GPIO_SMC_PSRAM_NBS0 (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN7)   /* Check! */
+#define GPIO_SMC_PSRAM_NBS1 (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|GPIO_PIN15)
+#define GPIO_SMC_A1         (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN8)
+#define GPIO_SMC_NCS2       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|GPIO_PIN16)
+#define GPIO_SMC_LCD_RS     (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN8)
+
+#define GPIO_MCI_DAT0       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5)
+#define GPIO_MCI_DAT1       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN6)
+#define GPIO_MCI_DAT2       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN7)
+#define GPIO_MCI_DAT3       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN8)
+#define GPIO_MCI_DAT4       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN28)
+#define GPIO_MCI_DAT5       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN29)
+#define GPIO_MCI_DAT6       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN30)
+#define GPIO_MCI_DAT7       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN31)
+#define GPIO_MCI_CK         (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN3)
+#define GPIO_MCI_DA         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN4)
+#define GPIO_MCI_DAT0IN     (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5)
+
+#define GPIO_PWMC_PWMH0     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0)
+#define GPIO_PWMC_PWML0     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7)
+#define GPIO_PWMC_PWMH1     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1)
+#define GPIO_PWMC_PWML1     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8)
+#define GPIO_PWMC_PWMH2     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2)
+#define GPIO_PWMC_PWML2     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9)
+
+#define GPIO_SPI0_MISO      (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN13)
+#define GPIO_SPI0_MOSI      (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN14)
+#define GPIO_SPI0_SPCK      (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN15)
+#define GPIO_SPI0_NPCS0     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN16)
+
+#define GPIO_SPI0_NPCS1_1   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
+#define GPIO_SPI0_NPCS1_2   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN3)
+#define GPIO_SPI0_NPCS1_3   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19)
+#define GPIO_SPI0_NPCS2_1   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN1)
+#define GPIO_SPI0_NPCS2_2   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN4)
+#define GPIO_SPI0_NPCS2_3   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN14)
+#define GPIO_SPI0_NPCS3_1   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19)
+#define GPIO_SPI0_NPCS3_2   (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN5)
+
+#define GPIO_SSC_TD         (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN26)
+#define GPIO_SSC_TK         (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN28)
+#define GPIO_SSC_TF         (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30)
+
+#define GPIO_PCK0           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
+
+#define GPIO_TWI_TWD0       (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9)
+#define GPIO_TWI_TWCK0      (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10)
+#define GPIO_TWI_TWD1       (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24)
+#define GPIO_TWI_TWCK1      (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25)
+
+#define GPIO_UART_TXD       (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12)
+#define GPIO_UART_RXD       (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11)
+
+#define GPIO_USART0_CTS     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN8)
+#define GPIO_USART0_DCD     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN11)
+#define GPIO_USART0_DSR     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN10)
+#define GPIO_USART0_DTR     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN9)
+#define GPIO_USART0_RI      (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN12)
+#define GPIO_USART0_RTS     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN7)
+#define GPIO_USART0_RXD     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19)
+#define GPIO_USART0_SCK     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN17)
+#define GPIO_USART0_TXD     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN18)
+
+#define GPIO_USART1_CTS     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN23)
+#define GPIO_USART1_RTS     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN22)
+#define GPIO_USART1_RXD     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
+#define GPIO_USART1_SCK     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24)
+#define GPIO_USART1_TXD     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN20)
+
+#define GPIO_USART2_CTS     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN22)
+#define GPIO_USART2_RTS     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN21)
+#define GPIO_USART2_RXD     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN23)
+#define GPIO_USART2_SCK     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25)
+#define GPIO_USART2_TXD     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN22)
+
+#define GPIO_USART3_CTS     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN10)
+#define GPIO_USART3_RTS     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN11)
+#define GPIO_USART3_RXD     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN13)
+#define GPIO_USART3_SCK     (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19)
+#define GPIO_USART3_TXD     (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN12)
+
+#define GPIO_USB_VBUS       (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM3U_PINMAP_H */
diff --git a/nuttx/arch/arm/src/sam3u/chip/sam3u_vectors.h b/nuttx/arch/arm/src/sam3u/chip/sam3u_vectors.h
new file mode 100644
index 000000000..cdc5948c2
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/chip/sam3u_vectors.h
@@ -0,0 +1,90 @@
+/************************************************************************************************
+ * arch/arm/src/sam3u/chip/sam3u_vectors.h
+ *
+ *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************************/
+/* This file is included by sam_vectors.S.  It provides the macro VECTOR that
+ * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an
+ * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h.
+ * sam_vectors.S will defined the VECTOR in different ways in order to generate
+ * the interrupt vectors and handlers in their final form.
+ *
+ *
+ * Vectors for low and medium density devices
+ */
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 46 interrupt table entries for I/O interrupts. */
+
+# define ARMV7M_PERIPHERAL_INTERRUPTS 46
+
+#else
+  VECTOR(sam_supc, SAM_IRQ_SUPC)      /* Vector 16+0:  Supply Controller */
+  VECTOR(sam_rstc, SAM_IRQ_RSTC)      /* Vector 16+1:  Reset Controller */
+  VECTOR(sam_rtc, SAM_IRQ_RTC)        /* Vector 16+2:  Real Time Clock */
+  VECTOR(sam_rtt, SAM_IRQ_RTT)        /* Vector 16+3:  Real Time Timer */
+  VECTOR(sam_wdt, SAM_IRQ_WDT)        /* Vector 16+4:  Watchdog Timer */
+  VECTOR(sam_pmc, SAM_IRQ_PMC)        /* Vector 16+5:  Power Management Controller */
+  VECTOR(sam_eefc0, SAM_IRQ_EEFC0)    /* Vector 16+6:  Enhanced Embedded Flash Controller 0 */
+  VECTOR(sam_eefc1, SAM_IRQ_EEFC1)    /* Vector 16+7:  Enhanced Embedded Flash Controller 1 */
+  VECTOR(sam_uart, SAM_IRQ_UART)      /* Vector 16+8:  Universal Asynchronous Receiver Transmitter */
+  VECTOR(sam_smc, SAM_IRQ_SMC)        /* Vector 16+9:  Static Memory Controller */
+  VECTOR(sam_pioa, SAM_IRQ_PIOA)      /* Vector 16+10: Parallel I/O Controller A */
+  VECTOR(sam_piob, SAM_IRQ_PIOB)      /* Vector 16+11: Parallel I/O Controller B */
+  VECTOR(sam_pioc, SAM_IRQ_PIOC)      /* Vector 16+12: Parallel I/O Controller C */
+  VECTOR(sam_usart0, SAM_IRQ_USART0)  /* Vector 16+13: USART 0 */
+  VECTOR(sam_usart1, SAM_IRQ_USART1)  /* Vector 16+14: USART 1 */
+  VECTOR(sam_usart2, SAM_IRQ_USART2)  /* Vector 16+15: USART 2 */
+  VECTOR(sam_usart3, SAM_IRQ_USART3)  /* Vector 16+16: USART 3 */
+  VECTOR(sam_hsmci, SAM_IRQ_HSMCI)    /* Vector 16+17: High Speed Multimedia Card Interface */
+  VECTOR(sam_twi0, SAM_IRQ_TWI0)      /* Vector 16+18: Two-Wire Interface 0 */
+  VECTOR(sam_twi1, SAM_IRQ_TWI1)      /* Vector 16+19: Two-Wire Interface 1 */
+  VECTOR(sam_spi, SAM_IRQ_SPI)        /* Vector 16+20: Serial Peripheral Interface */
+  VECTOR(sam_ssc, SAM_IRQ_SSC)        /* Vector 16+21: Synchronous Serial Controller */
+  VECTOR(sam_tc0, SAM_IRQ_TC0)        /* Vector 16+22: Timer Counter 0 */
+  VECTOR(sam_tc1, SAM_IRQ_TC1)        /* Vector 16+23: Timer Counter 1 */
+  VECTOR(sam_tc2, SAM_IRQ_TC2)        /* Vector 16+24: Timer Counter 2 */
+  VECTOR(sam_pwm, SAM_IRQ_PWM)        /* Vector 16+25: Pulse Width Modulation Controller */
+  VECTOR(sam_adc12b, SAM_IRQ_ADC12B)  /* Vector 16+26: 12-bit ADC Controller */
+  VECTOR(sam_adc, SAM_IRQ_ADC)        /* Vector 16+27: 10-bit ADC Controller */
+  VECTOR(sam_dmac, SAM_IRQ_DMAC)      /* Vector 16+28: DMA Controller */
+  VECTOR(sam_udphs, SAM_IRQ_UDPHS)    /* Vector 16+29: USB Device High Speed */
+#endif
diff --git a/nuttx/arch/arm/src/sam3u/chip/sam_memorymap.h b/nuttx/arch/arm/src/sam3u/chip/sam_memorymap.h
index 5e9d38579..c403aa541 100644
--- a/nuttx/arch/arm/src/sam3u/chip/sam_memorymap.h
+++ b/nuttx/arch/arm/src/sam3u/chip/sam_memorymap.h
@@ -43,7 +43,11 @@
 #include <nuttx/config.h>
 #include "chip.h"
 
-#include "chip/sam3u_memorymap.h"
+#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#  include "chip/sam3u_memorymap.h"
+#else
+#  Unrecognized SAM architecture
+#endif
 
 #endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_MEMORYMAP_H */
 
diff --git a/nuttx/arch/arm/src/sam3u/chip/sam_pinmap.h b/nuttx/arch/arm/src/sam3u/chip/sam_pinmap.h
new file mode 100644
index 000000000..1de42f4a1
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/chip/sam_pinmap.h
@@ -0,0 +1,53 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/chip/sam_pinmap.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PINMAP_H
+#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#  include "chip/sam3u_pinmap.h"
+#else
+#  Unrecognized SAM architecture
+#endif
+
+#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PINMAP_H */
+
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_internal.h b/nuttx/arch/arm/src/sam3u/sam3u_internal.h
deleted file mode 100644
index 3633e898c..000000000
--- a/nuttx/arch/arm/src/sam3u/sam3u_internal.h
+++ /dev/null
@@ -1,911 +0,0 @@
-/************************************************************************************
- * arch/arm/src/sam3u/sam3u_internal.h
- *
- *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_INTERNAL_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_INTERNAL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "up_internal.h"
-#include "chip.h"
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* Configuration ********************************************************************/
-
-#if defined(CONFIG_GPIOA_IRQ) || defined(CONFIG_GPIOB_IRQ) || defined(CONFIG_GPIOC_IRQ)
-#  define CONFIG_GPIO_IRQ 1
-#else
-#  undef CONFIG_GPIO_IRQ
-#endif
-
-#ifndef CONFIG_DEBUG
-#  undef CONFIG_DEBUG_GPIO
-#  undef CONFIG_DEBUG_DMA
-#endif
-
-/* Bit-encoded input to sam3u_configgpio() ******************************************/
-
-/* 16-bit Encoding:
- * MMCC CII. VPPB BBBB
- */
-
-/* Input/Output mode:
- *
- * MM.. .... .... ....
- */
-
-#define GPIO_MODE_SHIFT            (14)        /* Bits 14-15: GPIO mode */
-#define GPIO_MODE_MASK             (3 << GPIO_MODE_SHIFT)
-#  define GPIO_INPUT               (0 << GPIO_MODE_SHIFT) /* Input */
-#  define GPIO_OUTPUT              (1 << GPIO_MODE_SHIFT) /* Output */
-#  define GPIO_PERIPHA             (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
-#  define GPIO_PERIPHB             (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
-
-/* These bits set the configuration of the pin:
- * ..CC C... .... ....
- */
-
-#define GPIO_CFG_SHIFT             (11)        /* Bits 11-13: GPIO configuration bits */
-#define GPIO_CFG_MASK              (7 << GPIO_CFG_SHIFT)
-#  define GPIO_CFG_DEFAULT         (0 << GPIO_CFG_SHIFT) /* Default, no attribute */
-#  define GPIO_CFG_PULLUP          (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
-#  define GPIO_CFG_DEGLITCH        (2 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
-#  define GPIO_CFG_OPENDRAIN       (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
-
-/* Additional interrupt modes:
- * .... .II. .... ....
- */
-
-#define GPIO_INT_SHIFT             (9)        /* Bits 9-10: GPIO configuration bits */
-#define GPIO_INT_MASK              (3 << GPIO_INT_SHIFT)
-#  define GPIO_INT_LEVEL           (1 << 10)   /* Bit 10: Level detection interrupt */
-#  define GPIO_INT_EDGE            (0)         /*        (vs. Edge detection interrupt) */
-#  define GPIO_INT_HIGHLEVEL       (1 << 9)    /* Bit 9: High level detection interrupt */
-#  define GPIO_INT_LOWLEVEL        (0)         /*        (vs. Low level detection interrupt) */
-#  define GPIO_INT_RISING          (1 << 9)    /* Bit 9: Rising edge detection interrupt */
-#  define GPIO_INT_FALLING         (0)         /*        (vs. Falling edge detection interrupt) */
-
-/* If the pin is an GPIO output, then this identifies the initial output value:
- * .... .... V... ....
- */
-
-#define GPIO_OUTPUT_SET            (1 << 7)    /* Bit 7: Inital value of output */
-#define GPIO_OUTPUT_CLEAR          (0)
-
-/* This identifies the GPIO port:
- * .... .... .PP. ....
- */
-
-#define GPIO_PORT_SHIFT            (5)         /* Bit 5-6:  Port number */
-#define GPIO_PORT_MASK             (3 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT_PIOA           (0 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT_PIOB           (1 << GPIO_PORT_SHIFT)
-#  define GPIO_PORT_PIOC           (2 << GPIO_PORT_SHIFT)
-
-/* This identifies the bit in the port:
- * .... .... ...B BBBB
- */
-
-#define GPIO_PIN_SHIFT             0        /* Bits 0-4: GPIO number: 0-31 */
-#define GPIO_PIN_MASK              (31 << GPIO_PIN_SHIFT)
-#define GPIO_PIN0                  (0  << GPIO_PIN_SHIFT)
-#define GPIO_PIN1                  (1  << GPIO_PIN_SHIFT)
-#define GPIO_PIN2                  (2  << GPIO_PIN_SHIFT)
-#define GPIO_PIN3                  (3  << GPIO_PIN_SHIFT)
-#define GPIO_PIN4                  (4  << GPIO_PIN_SHIFT)
-#define GPIO_PIN5                  (5  << GPIO_PIN_SHIFT)
-#define GPIO_PIN6                  (6  << GPIO_PIN_SHIFT)
-#define GPIO_PIN7                  (7  << GPIO_PIN_SHIFT)
-#define GPIO_PIN8                  (8  << GPIO_PIN_SHIFT)
-#define GPIO_PIN9                  (9  << GPIO_PIN_SHIFT)
-#define GPIO_PIN10                 (10 << GPIO_PIN_SHIFT)
-#define GPIO_PIN11                 (11 << GPIO_PIN_SHIFT)
-#define GPIO_PIN12                 (12 << GPIO_PIN_SHIFT)
-#define GPIO_PIN13                 (13 << GPIO_PIN_SHIFT)
-#define GPIO_PIN14                 (14 << GPIO_PIN_SHIFT)
-#define GPIO_PIN15                 (15 << GPIO_PIN_SHIFT)
-#define GPIO_PIN16                 (16 << GPIO_PIN_SHIFT)
-#define GPIO_PIN17                 (17 << GPIO_PIN_SHIFT)
-#define GPIO_PIN18                 (18 << GPIO_PIN_SHIFT)
-#define GPIO_PIN19                 (19 << GPIO_PIN_SHIFT)
-#define GPIO_PIN20                 (20 << GPIO_PIN_SHIFT)
-#define GPIO_PIN21                 (21 << GPIO_PIN_SHIFT)
-#define GPIO_PIN22                 (22 << GPIO_PIN_SHIFT)
-#define GPIO_PIN23                 (23 << GPIO_PIN_SHIFT)
-#define GPIO_PIN24                 (24 << GPIO_PIN_SHIFT)
-#define GPIO_PIN25                 (25 << GPIO_PIN_SHIFT)
-#define GPIO_PIN26                 (26 << GPIO_PIN_SHIFT)
-#define GPIO_PIN27                 (27 << GPIO_PIN_SHIFT)
-#define GPIO_PIN28                 (28 << GPIO_PIN_SHIFT)
-#define GPIO_PIN29                 (29 << GPIO_PIN_SHIFT)
-#define GPIO_PIN30                 (30 << GPIO_PIN_SHIFT)
-#define GPIO_PIN31                 (31 << GPIO_PIN_SHIFT)
-
-/* GPIO pin definitions *************************************************************/
-
-#define GPIO_ADC0_AD0             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
-#define GPIO_ADC0_AD1             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30)
-#define GPIO_ADC0_AD2             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN3)
-#define GPIO_ADC0_AD3             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN4)
-#define GPIO_ADC0_AD4             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN15)
-#define GPIO_ADC0_AD5             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN16)
-#define GPIO_ADC0_AD6             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN17)
-#define GPIO_ADC0_AD7             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN18)
-
-#define GPIO_CAN_XCVR_RS          (GPIO_OUTPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_OUTPUT_SET|GPIO_PIN23)
-#define GPIO_CAN1_XCVR_TXD        (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN27)
-#define GPIO_CAN1_XCVR_RXD        (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN26)
-#define GPIO_CAN2_XCVR_TXD        (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN29)
-#define GPIO_CAN2_XCVR_RXD        (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN28)
-
-#define GPIO_SMC_D0               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN9)  /* Check! */
-#define GPIO_SMC_D1               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN10) /* Check! */
-#define GPIO_SMC_D2               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN11) /* Check! */
-#define GPIO_SMC_D3               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN12) /* Check! */
-#define GPIO_SMC_D4               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN13) /* Check! */
-#define GPIO_SMC_D5               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN14) /* Check! */
-#define GPIO_SMC_D6               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN15) /* Check! */
-#define GPIO_SMC_D7               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN16) /* Check! */
-#define GPIO_SMC_D8               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN25) /* Check! */
-#define GPIO_SMC_D9               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN26) /* Check! */
-#define GPIO_SMC_D10              (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN27) /* Check! */
-#define GPIO_SMC_D11              (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN28) /* Check! */
-#define GPIO_SMC_D12              (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN29) /* Check! */
-#define GPIO_SMC_D13              (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN30) /* Check! */
-#define GPIO_SMC_D14              (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|{GPIO_PIN31) /* Check! */
-#define GPIO_SMC_D15              (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN6)   /* Check! */
-#define GPIO_SMC_NCS0             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN20)
-#define GPIO_SMC_NRD              (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN19)
-#define GPIO_SMC_NWE              (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN23)
-#define GPIO_SMC_PSRAM_A0         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN0)  /* Check! */
-#define GPIO_SMC_PSRAM_A1         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN1)  /* Check! */
-#define GPIO_SMC_PSRAM_A2         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN2)  /* Check! */
-#define GPIO_SMC_PSRAM_A3         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN3)  /* Check! */
-#define GPIO_SMC_PSRAM_A4         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN4)  /* Check! */
-#define GPIO_SMC_PSRAM_A5         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN5)  /* Check! */
-#define GPIO_SMC_PSRAM_A6         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN6)  /* Check! */
-#define GPIO_SMC_PSRAM_A7         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN7)  /* Check! */
-#define GPIO_SMC_PSRAM_A8         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN8)  /* Check! */
-#define GPIO_SMC_PSRAM_A9         (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN9)  /* Check! */
-#define GPIO_SMC_PSRAM_A10        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN10) /* Check! */
-#define GPIO_SMC_PSRAM_A11        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN11) /* Check! */
-#define GPIO_SMC_PSRAM_A12        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN24) /* Check! */
-#define GPIO_SMC_PSRAM_A13        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN25) /* Check! */
-#define GPIO_SMC_PSRAM_A14        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN26) /* Check! */
-#define GPIO_SMC_PSRAM_A15        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN27) /* Check! */
-#define GPIO_SMC_PSRAM_A16        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN27) /* Check! */
-#define GPIO_SMC_PSRAM_A17        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN28) /* Check! */
-#define GPIO_SMC_PSRAM_A18        (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|{GPIO_PIN29) /* Check! */
-#define GPIO_SMC_PSRAM_NBS0       (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN7)   /* Check! */
-#define GPIO_SMC_PSRAM_NBS1       (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|GPIO_PIN15)
-#define GPIO_SMC_A1               (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN8)
-#define GPIO_SMC_NCS2             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOC|GPIO_PIN16)
-#define GPIO_SMC_LCD_RS           (GPIO_PERIPHB|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN8)
-
-#define GPIO_MCI_DAT0             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5)
-#define GPIO_MCI_DAT1             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN6)
-#define GPIO_MCI_DAT2             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN7)
-#define GPIO_MCI_DAT3             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN8)
-#define GPIO_MCI_DAT4             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN28)
-#define GPIO_MCI_DAT5             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN29)
-#define GPIO_MCI_DAT6             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN30)
-#define GPIO_MCI_DAT7             (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOB|GPIO_PIN31)
-#define GPIO_MCI_CK               (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN3)
-#define GPIO_MCI_DA               (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN4)
-#define GPIO_MCI_DAT0IN           (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5)
-
-#define GPIO_PWMC_PWMH0           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0)
-#define GPIO_PWMC_PWML0           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7)
-#define GPIO_PWMC_PWMH1           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1)
-#define GPIO_PWMC_PWML1           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8)
-#define GPIO_PWMC_PWMH2           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2)
-#define GPIO_PWMC_PWML2           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9)
-
-#define GPIO_SPI0_MISO            (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN13)
-#define GPIO_SPI0_MOSI            (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN14)
-#define GPIO_SPI0_SPCK            (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN15)
-#define GPIO_SPI0_NPCS0           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN16)
-
-#define GPIO_SPI0_NPCS1_1         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
-#define GPIO_SPI0_NPCS1_2         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN3)
-#define GPIO_SPI0_NPCS1_3         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19)
-#define GPIO_SPI0_NPCS2_1         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN1)
-#define GPIO_SPI0_NPCS2_2         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN4)
-#define GPIO_SPI0_NPCS2_3         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN14)
-#define GPIO_SPI0_NPCS3_1         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19)
-#define GPIO_SPI0_NPCS3_2         (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN5)
-
-#define GPIO_SSC_TD               (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN26)
-#define GPIO_SSC_TK               (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN28)
-#define GPIO_SSC_TF               (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30)
-
-#define GPIO_PCK0                 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
-
-#define GPIO_TWI_TWD0             (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9)
-#define GPIO_TWI_TWCK0            (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10)
-#define GPIO_TWI_TWD1             (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24)
-#define GPIO_TWI_TWCK1            (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25)
-
-#define GPIO_UART_TXD             (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12)
-#define GPIO_UART_RXD             (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11)
-
-#define GPIO_USART0_CTS           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN8)
-#define GPIO_USART0_DCD           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN11)
-#define GPIO_USART0_DSR           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN10)
-#define GPIO_USART0_DTR           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN9)
-#define GPIO_USART0_RI            (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN12)
-#define GPIO_USART0_RTS           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN7)
-#define GPIO_USART0_RXD           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN19)
-#define GPIO_USART0_SCK           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN17)
-#define GPIO_USART0_TXD           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN18)
-
-#define GPIO_USART1_CTS           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN23)
-#define GPIO_USART1_RTS           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN22)
-#define GPIO_USART1_RXD           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
-#define GPIO_USART1_SCK           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24)
-#define GPIO_USART1_TXD           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN20)
-
-#define GPIO_USART2_CTS           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN22)
-#define GPIO_USART2_RTS           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN21)
-#define GPIO_USART2_RXD           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN23)
-#define GPIO_USART2_SCK           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25)
-#define GPIO_USART2_TXD           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN22)
-
-#define GPIO_USART3_CTS           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN10)
-#define GPIO_USART3_RTS           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN11)
-#define GPIO_USART3_RXD           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN13)
-#define GPIO_USART3_SCK           (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN19)
-#define GPIO_USART3_TXD           (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOC|GPIO_PIN12)
-
-#define GPIO_USB_VBUS             (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
-
-/* DMA ******************************************************************************/
-
-/* Flags used to characterize the desired DMA channel.  The naming convention is that
- * one side is the peripheral and the other is memory (however, the interface could still
- * be used if, for example, both sides were memory although the naming would be awkward)
- */
-
-/* Unchange-able properties of the channel */
-
-#define DMACH_FLAG_FLOWCONTROL                (1 << 0)  /* Bit 0: Channel supports flow control */
-#define DMACH_FLAG_FIFOSIZE_SHIFT             (1)       /* Bit 1: Size of DMA FIFO */
-#define DMACH_FLAG_FIFOSIZE_MASK              (1 << DMACH_FLAG_FIFOSIZE_SHIFT)
-#  define DMACH_FLAG_FIFO_8BYTES              (0 << DMACH_FLAG_FIFOSIZE_SHIFT) /* 8 bytes */
-#  define DMACH_FLAG_FIFO_32BYTES             (1 << DMACH_FLAG_FIFOSIZE_SHIFT) /* 32 bytes */
-
-/* Configurable properties of the channel */
-
-#define DMACH_FLAG_BURST_LARGEST              0  /* Largest length AHB burst */
-#define DMACH_FLAG_BURST_HALF                 1  /* Half FIFO size */
-#define DMACH_FLAG_BURST_SINGLE               2  /* Single AHB access */
-
-#define DMACH_FLAG_FIFOCFG_SHIFT              (2)       /* Bits 2-3: FIFO configuration */
-#define DMACH_FLAG_FIFOCFG_MASK               (3 << DMACH_FLAG_FIFOCFG_SHIFT)
-#  define DMACH_FLAG_FIFOCFG_LARGEST          (DMACH_FLAG_BURST_LARGEST << DMACH_FLAG_FIFOCFG_SHIFT)
-#  define DMACH_FLAG_FIFOCFG_HALF             (DMACH_FLAG_BURST_HALF << DMACH_FLAG_FIFOCFG_SHIFT)
-#  define DMACH_FLAG_FIFOCFG_SINGLE           (DMACH_FLAG_BURST_SINGLE << DMACH_FLAG_FIFOCFG_SHIFT)
-
-/* Peripheral endpoint characteristics */
-
-#define DMACH_FLAG_PERIPHPID_SHIFT            (4)       /* Bits 4-7: Peripheral PID */
-#define DMACH_FLAG_PERIPHPID_MASK             (15 << DMACH_FLAG_PERIPHPID_SHIFT)
-#define DMACH_FLAG_PERIPHH2SEL                (1 << 8)  /* Bits 8: HW handshaking */
-#define DMACH_FLAG_PERIPHISPERIPH             (1 << 9)  /* Bits 9: 0=memory; 1=peripheral */
-#define DMACH_FLAG_PERIPHWIDTH_SHIFT          (10)      /* Bits 10-11: Peripheral width */
-#define DMACH_FLAG_PERIPHWIDTH_MASK           (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT)
-#  define DMACH_FLAG_PERIPHWIDTH_8BITS        (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */
-#  define DMACH_FLAG_PERIPHWIDTH_16BITS       (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */
-#  define DMACH_FLAG_PERIPHWIDTH_32BITS       (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */
-#define DMACH_FLAG_PERIPHINCREMENT            (1 << 12) /* Bit 12: Autoincrement peripheral address */
-#define DMACH_FLAG_PERIPHCHUNKSIZE            (1 << 13) /* Bit 13: Peripheral chunk size */
-#  define DMACH_FLAG_PERIPHCHUNKSIZE_1        (0)                        /* Peripheral chunksize = 1 */
-#  define DMACH_FLAG_PERIPHCHUNKSIZE_4        DMACH_FLAG_PERIPHCHUNKSIZE /* Peripheral chunksize = 4 */
-
-/* Memory endpoint characteristics */
-
-#define DMACH_FLAG_MEMPID_SHIFT               (14)      /* Bits 14-17: Memory PID */
-#define DMACH_FLAG_MEMPID_MASK                (15 << DMACH_FLAG_PERIPHPID_SHIFT)
-#define DMACH_FLAG_MEMH2SEL                   (1 << 18) /* Bits 18: HW handshaking */
-#define DMACH_FLAG_MEMISPERIPH                (1 << 19) /* Bits 19: 0=memory; 1=peripheral */
-#define DMACH_FLAG_MEMWIDTH_SHIFT             (20)      /* Bits 20-21: Memory width */
-#define DMACH_FLAG_MEMWIDTH_MASK              (3 << DMACH_FLAG_MEMWIDTH_SHIFT)
-#  define DMACH_FLAG_MEMWIDTH_8BITS           (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */
-#  define DMACH_FLAG_MEMWIDTH_16BITS          (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */
-#  define DMACH_FLAG_MEMWIDTH_32BITS          (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */
-#define DMACH_FLAG_MEMINCREMENT               (1 << 22) /* Bit 22: Autoincrement memory address */
-#define DMACH_FLAG_MEMCHUNKSIZE               (1 << 22) /* Bit 23: Memory chunk size */
-#  define DMACH_FLAG_MEMCHUNKSIZE_1           (0)                     /* Memory chunksize = 1 */
-#  define DMACH_FLAG_MEMCHUNKSIZE_4           DMACH_FLAG_MEMCHUNKSIZE /* Memory chunksize = 4 */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-typedef FAR void *DMA_HANDLE;
-typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
-
-/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
-
-#ifdef CONFIG_DEBUG_DMA
-struct sam3u_dmaregs_s
-{
-  /* Global Registers */
-
-  uint32_t gcfg;    /* DMAC Global Configuration Register */
-  uint32_t en;      /* DMAC Enable Register */
-  uint32_t sreq;    /* DMAC Software Single Request Register */
-  uint32_t creq;    /* DMAC Software Chunk Transfer Request Register */
-  uint32_t last;    /* DMAC Software Last Transfer Flag Register */
-  uint32_t ebcimr;  /* DMAC Error Mask */
-  uint32_t ebcisr;  /* DMAC Error Status */
-  uint32_t chsr;    /* DMAC Channel Handler Status Register */
-
-  /* Channel Registers */
-
-  uint32_t saddr;   /* DMAC Channel Source Address Register */
-  uint32_t daddr;   /* DMAC Channel Destination Address Register */
-  uint32_t dscr;    /* DMAC Channel Descriptor Address Register */
-  uint32_t ctrla;   /* DMAC Channel Control A Register */
-  uint32_t ctrlb;   /* DMAC Channel Control B Register */
-  uint32_t cfg;     /* DMAC Channel Configuration Register */
-};
-#endif
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-/************************************************************************************
- * Name: sam3u_clockconfig
- *
- * Description:
- *   Called to initialize the SAM3/4.  This does whatever setup is needed to put the
- *   SoC in a usable state.  This includes the initialization of clocking using the
- *   settings in board.h.  (After power-on reset, the sam3u is initiallyrunning on
- *   a 4MHz internal RC clock).  This function also performs other low-level chip
- *   initialization of the chip including EFC, master clock, IRQ and watchdog
- *   configuration.
- *
- ************************************************************************************/
-
-void sam3u_clockconfig(void);
-
-/************************************************************************************
- * Name: sam3u_lowsetup
- *
- * Description:
- *   Called at the very beginning of _start.  Performs low level initialization
- *   including setup of the console UART.  This UART done early so that the serial
- *   console is available for debugging very early in the boot sequence.
- *
- ************************************************************************************/
-
-void sam3u_lowsetup(void);
-
-/****************************************************************************
- * Name: sam3u_userspace
- *
- * Description:
- *   For the case of the separate user-/kernel-space build, perform whatever
- *   platform specific initialization of the user memory is required.
- *   Normally this just means initializing the user space .data and .bss
- *   segments.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NUTTX_KERNEL
-void sam3u_userspace(void);
-#endif
-
-/****************************************************************************
- * Name: sam3u_mpuinitialize
- *
- * Description:
- *   Configure the MPU to permit user-space access to only unrestricted SAM3/4
- *   resources.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NUTTX_KERNEL
-void sam3u_mpuinitialize(void);
-#else
-#  define sam3u_mpuinitialize()
-#endif
-
-/****************************************************************************
- * Name: sam3u_mpu_uheap
- *
- * Description:
- *  Map the user heap region.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NUTTX_KERNEL
-void sam3u_mpu_uheap(uintptr_t start, size_t size);
-#else
-#  define sam3u_mpu_uheap(start,size)
-#endif
-
-/************************************************************************************
- * Name: sam3u_gpioirqinitialize
- *
- * Description:
- *   Initialize logic to support a second level of interrupt decoding for GPIO pins.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_GPIO_IRQ
-void sam3u_gpioirqinitialize(void);
-#else
-#  define sam3u_gpioirqinitialize()
-#endif
-
-/************************************************************************************
- * Name: sam3u_configgpio
- *
- * Description:
- *   Configure a GPIO pin based on bit-encoded description of the pin.
- *
- ************************************************************************************/
-
-int sam3u_configgpio(uint16_t cfgset);
-
-/************************************************************************************
- * Name: sam3u_gpiowrite
- *
- * Description:
- *   Write one or zero to the selected GPIO pin
- *
- ************************************************************************************/
-
-void sam3u_gpiowrite(uint16_t pinset, bool value);
-
-/************************************************************************************
- * Name: sam3u_gpioread
- *
- * Description:
- *   Read one or zero from the selected GPIO pin
- *
- ************************************************************************************/
-
-bool sam3u_gpioread(uint16_t pinset);
-
-/************************************************************************************
- * Name: sam3u_gpioirq
- *
- * Description:
- *   Configure an interrupt for the specified GPIO pin.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_GPIO_IRQ
-void sam3u_gpioirq(uint16_t pinset);
-#else
-#  define sam3u_gpioirq(pinset)
-#endif
-
-/************************************************************************************
- * Name: sam3u_gpioirqenable
- *
- * Description:
- *   Enable the interrupt for specified GPIO IRQ
- *
- ************************************************************************************/
-
-#ifdef CONFIG_GPIO_IRQ
-void sam3u_gpioirqenable(int irq);
-#else
-#  define sam3u_gpioirqenable(irq)
-#endif
-
-/************************************************************************************
- * Name: sam3u_gpioirqdisable
- *
- * Description:
- *   Disable the interrupt for specified GPIO IRQ
- *
- ************************************************************************************/
-
-#ifdef CONFIG_GPIO_IRQ
-void sam3u_gpioirqdisable(int irq);
-#else
-#  define sam3u_gpioirqdisable(irq)
-#endif
-
-/************************************************************************************
- * Function:  sam3u_dumpgpio
- *
- * Description:
- *   Dump all GPIO registers associated with the base address of the provided pinset.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_DEBUG_GPIO
-int sam3u_dumpgpio(uint32_t pinset, const char *msg);
-#else
-#  define sam3u_dumpgpio(p,m)
-#endif
-
-/****************************************************************************
- * Name: sam3u_dmachannel
- *
- * Description:
- *   Allocate a DMA channel.  This function sets aside a DMA channel with
- *   the required FIFO size and flow control capabilities (determined by
- *   dma_flags) then  gives the caller exclusive access to the DMA channel.
- *
- *   The naming convention in all of the DMA interfaces is that one side is
- *   the 'peripheral' and the other is 'memory'.  Howerver, the interface
- *   could still be used if, for example, both sides were memory although
- *   the naming would be awkward.
- *
- * Returned Value:
- *   If a DMA channel if the required FIFO size is available, this function
- *   returns a non-NULL, void* DMA channel handle.  NULL is returned on any
- *   failure.
- *
- ****************************************************************************/
-
-DMA_HANDLE sam3u_dmachannel(uint32_t dmach_flags);
-
-/****************************************************************************
- * Name: sam3u_dmafree
- *
- * Description:
- *   Release a DMA channel.  NOTE:  The 'handle' used in this argument must
- *   NEVER be used again until sam3u_dmachannel() is called again to re-gain
- *   a valid handle.
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void sam3u_dmafree(DMA_HANDLE handle);
-
-/****************************************************************************
- * Name: sam3u_dmatxsetup
- *
- * Description:
- *   Configure DMA for transmit of one buffer (memory to peripheral).  This
- *   function may be called multiple times to handle large and/or dis-
- *   continuous transfers.  Calls to sam3u_dmatxsetup() and sam3u_dmatxsetup()
- *   must not be intermixed on the same transfer, however.
- *
- ****************************************************************************/
-
-int sam3u_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
-                     size_t nbytes);
-
-/****************************************************************************
- * Name: sam3u_dmarxsetup
- *
- * Description:
- *   Configure DMA for receipt of one buffer (peripheral to memory).  This
- *   function may be called multiple times to handle large and/or dis-
- *   continuous transfers.  Calls to sam3u_dmatxsetup() and sam3u_dmatxsetup()
- *   must not be intermixed on the same transfer, however.
- *
- ****************************************************************************/
-
-int sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
-                     size_t nbytes);
-
-/****************************************************************************
- * Name: sam3u_dmastart
- *
- * Description:
- *   Start the DMA transfer
- *
- ****************************************************************************/
-
-int sam3u_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
-
-/****************************************************************************
- * Name: sam3u_dmastop
- *
- * Description:
- *   Cancel the DMA.  After sam3u_dmastop() is called, the DMA channel is
- *   reset and sam3u_dmasetup() must be called before sam3u_dmastart() can be
- *   called again
- *
- ****************************************************************************/
-
-void sam3u_dmastop(DMA_HANDLE handle);
-
-/****************************************************************************
- * Name: sam3u_dmasample
- *
- * Description:
- *   Sample DMA register contents
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_DMA
-void sam3u_dmasample(DMA_HANDLE handle, struct sam3u_dmaregs_s *regs);
-#else
-#  define sam3u_dmasample(handle,regs)
-#endif
-
-/****************************************************************************
- * Name: sam3u_dmadump
- *
- * Description:
- *   Dump previously sampled DMA register contents
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_DMA
-void sam3u_dmadump(DMA_HANDLE handle, const struct sam3u_dmaregs_s *regs,
-                   const char *msg);
-#else
-#  define sam3u_dmadump(handle,regs,msg)
-#endif
-
-/****************************************************************************
- * Name: sdio_initialize
- *
- * Description:
- *   Initialize SDIO for operation.
- *
- * Input Parameters:
- *   slotno - Not used.
- *
- * Returned Values:
- *   A reference to an SDIO interface structure.  NULL is returned on failures.
- *
- ****************************************************************************/
-
-struct sdio_dev_s; /* See include/nuttx/sdio.h */
-FAR struct sdio_dev_s *sdio_initialize(int slotno);
-
-/****************************************************************************
- * Name: sdio_mediachange
- *
- * Description:
- *   Called by board-specific logic -- posssible from an interrupt handler --
- *   in order to signal to the driver that a card has been inserted or
- *   removed from the slot
- *
- * Input Parameters:
- *   dev        - An instance of the SDIO driver device state structure.
- *   cardinslot - true is a card has been detected in the slot; false if a
- *                card has been removed from the slot.  Only transitions
- *                (inserted->removed or removed->inserted should be reported)
- *
- * Returned Values:
- *   None
- *
- ****************************************************************************/
-
-void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
-
-/****************************************************************************
- * Name: sdio_wrprotect
- *
- * Description:
- *   Called by board-specific logic to report if the card in the slot is
- *   mechanically write protected.
- *
- * Input Parameters:
- *   dev       - An instance of the SDIO driver device state structure.
- *   wrprotect - true is a card is writeprotected.
- *
- * Returned Values:
- *   None
- *
- ****************************************************************************/
-
-void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
-
-/****************************************************************************
- * Name:  sam3u_spicsnumber, sam3u_spiselect, sam3u_spistatus, and
- *        sam3u_spicmddata
- *
- * Description:
- *   These external functions must be provided by board-specific logic.  They
- *   include:
- *
- *   o sam3u_spicsnumbe and sam3u_spiselect which are helper functions to
- *     manage the board-specific aspects of the unique SAM3/4 chip select
- *     architecture.
- *   o sam3u_spistatus and sam3u_spicmddata:  Implementations of the status
- *     and cmddata methods of the SPI interface defined by struct spi_ops_
- *     (see include/nuttx/spi.h). All other methods including
- *     up_spiinitialize()) are provided by common SAM3/4 logic.
- *
- *  To use this common SPI logic on your board:
- *
- *   1. Provide logic in sam3u_boardinitialize() to configure SPI chip select
- *      pins.
- *   2. Provide sam3u_spicsnumber(), sam3u_spiselect() and sam3u_spistatus()
- *      functions in your board-specific logic.  These functions will perform
- *      chip selection and status operations using GPIOs in the way your board
- *      is configured.
- *   2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
- *      sam3u_spicmddata() functions in your board-specific logic.  This
- *      function will perform cmd/data selection operations using GPIOs in
- *      the way your board is configured.
- *   3. Add a call to up_spiinitialize() in your low level application
- *      initialization logic
- *   4. The handle returned by up_spiinitialize() may then be used to bind the
- *      SPI driver to higher level logic (e.g., calling
- *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
- *      the SPI MMC/SD driver).
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SAM34_SPI
-struct spi_dev_s;
-enum spi_dev_e;
-
-/****************************************************************************
- * Name: sam3u_spicsnumber
- *
- * Description:
- *   The SAM3/4 has 4 CS registers for controlling device features.  This
- *   function must be provided by board-specific code.  Given a logical device
- *   ID, this function returns a number from 0 to 3 that identifies one of
- *   these SAM3/4 CS resources.
- *
- *   If CONFIG_SPI_OWNBUS is not defined and the GPIO is controlled by
- *   sam3u_spiselect, then the same CS register may be used to control
- *   multiple devices.
- *
- * Input Parameters:
- *   dev - SPI device info
- *   devid - Identifies the (logical) device
- *
- * Returned Values:
- *   On success, a CS number from 0 to 3 is returned; A negated errno may
- *   be returned on a failure.
- *
- ****************************************************************************/
-
-int sam3u_spicsnumber(enum spi_dev_e devid);
-
-/****************************************************************************
- * Name: sam3u_spiselect
- *
- * Description:
- *   PIO chip select pins may be programmed by the board specific logic in
- *   one of two different ways.  First, the pins may be programmed as SPI
- *   peripherals.  In that case, the pins are completely controlled by the
- *   SPI driver.  This method still needs to be provided, but it may be only
- *   a stub.
- *
- *   An alternative way to program the PIO chip select pins is as a normal
- *   GPIO output.  In that case, the automatic control of the CS pins is
- *   bypassed and this function must provide control of the chip select.
- *   NOTE:  In this case, the GPIO output pin does *not* have to be the
- *   same as the NPCS pin normal associated with the chip select number.
- *
- * Input Parameters:
- *   dev - SPI device info
- *   devid - Identifies the (logical) device
- *   selected - TRUE:Select the device, FALSE:De-select the device
- *
- * Returned Values:
- *   None
- *
- ****************************************************************************/
-
-void sam3u_spiselect(enum spi_dev_e devid, bool selected);
-
-/****************************************************************************
- * Name: sam3u_spistatus
- *
- * Description:
- *   Return status information associated with the SPI device.
- *
- * Input Parameters:
- *   dev - SPI device info
- *   devid - Identifies the (logical) device
- *
- * Returned Values:
- *   Bit-encoded SPI status (see include/nuttx/spi.h.
- *
- ****************************************************************************/
-
-uint8_t sam3u_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
-
-/****************************************************************************
- * Name: sam3u_spicmddata
- *
- * Description:
- *   Some SPI devices require an additional control to determine if the SPI
- *   data being sent is a command or is data.  If CONFIG_SPI_CMDDATA then
- *   this function will be called to different be command and data transfers.
- *
- *   This is often needed, for example, by LCD drivers.  Some LCD hardware
- *   may be configured to use 9-bit data transfers with the 9th bit
- *   indicating command or data.  That same hardware may be configurable,
- *   instead, to use 8-bit data but to require an additional, board-
- *   specific GPIO control to distinguish command and data.  This function
- *   would be needed in that latter case.
- *
- * Input Parameters:
- *   dev - SPI device info
- *   devid - Identifies the (logical) device
- *
- * Returned Values:
- *   Zero on success; a negated errno on failure.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SPI_CMDDATA
-int sam3u_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
-#endif
-#endif /* CONFIG_SAM34_SPI */
-
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_INTERNAL_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_allocateheap.c b/nuttx/arch/arm/src/sam3u/sam_allocateheap.c
index 56107c196..bf765462e 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_allocateheap.c
+++ b/nuttx/arch/arm/src/sam3u/sam_allocateheap.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/common/sam3u_allocateheap.c
+ * arch/arm/src/common/sam_allocateheap.c
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -51,7 +51,7 @@
 #include "mpu.h"
 #include "up_arch.h"
 #include "up_internal.h"
-#include "sam3u_internal.h"
+#include "sam_mpuinit.h"
 
 /****************************************************************************
  * Private Definitions
@@ -157,7 +157,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 
   /* Allow user-mode access to the user heap memory */
 
-   sam3u_mpu_uheap((uintptr_t)ubase, usize);
+   sam_mpu_uheap((uintptr_t)ubase, usize);
 #else
 
   /* Return the heap settings */
@@ -226,7 +226,7 @@ void up_addregion(void)
 {
   /* Allow user access to the heap memory */
 
-  sam3u_mpu_uheap(SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE);
+  sam_mpu_uheap(SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE);
 
   /* Add the region */
 
@@ -235,7 +235,7 @@ void up_addregion(void)
 #if CONFIG_MM_REGIONS > 2
   /* Allow user access to the heap memory */
 
-  sam3u_mpu_uheap(SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE);
+  sam_mpu_uheap(SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE);
 
   /* Add the region */
 
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam3u/sam_clockconfig.c
index b8a31caf4..df5cf59ba 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_clockconfig.c
+++ b/nuttx/arch/arm/src/sam3u/sam_clockconfig.c
@@ -1,6 +1,6 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_clockconfig.c
- * arch/arm/src/chip/sam3u_clockconfig.c
+ * arch/arm/src/sam3u/sam_clockconfig.c
+ * arch/arm/src/chip/sam_clockconfig.c
  *
  *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -48,7 +48,8 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
-#include "sam3u_internal.h"
+
+#include "sam_clockconfig.h"
 #include "chip/sam_pmc.h"
 #include "chip/sam_eefc.h"
 #include "chip/sam_wdt.h"
@@ -92,41 +93,41 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_efcsetup
+ * Name: sam_efcsetup
  *
  * Description:
  *   Configure 2 waitstates for embedded flash access
  *
  ****************************************************************************/
 
-static inline void sam3u_efcsetup(void)
+static inline void sam_efcsetup(void)
 {
   putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR);
   putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR);
 }
 
 /****************************************************************************
- * Name: sam3u_wdtsetup
+ * Name: sam_wdtsetup
  *
  * Description:
  *   Disable the watchdog timer
  *
  ****************************************************************************/
 
-static inline void sam3u_wdtsetup(void)
+static inline void sam_wdtsetup(void)
 {
   putreg32(WDT_MR_WDDIS, SAM_WDT_MR);
 }
 
 /****************************************************************************
- * Name: sam3u_supcsetup
+ * Name: sam_supcsetup
  *
  * Description:
  *   Select the external slow clock
  *
  ****************************************************************************/
 
-static inline void sam3u_supcsetup(void)
+static inline void sam_supcsetup(void)
 {
   /* Check if the 32-kHz is already selected */
 
@@ -141,14 +142,14 @@ static inline void sam3u_supcsetup(void)
 }
 
 /****************************************************************************
- * Name: sam3u_pmcwait
+ * Name: sam_pmcwait
  *
  * Description:
  *   Wait for the specide PMC status bit to become "1"
  *
  ****************************************************************************/
 
-static void sam3u_pmcwait(uint32_t bit)
+static void sam_pmcwait(uint32_t bit)
 {
   uint32_t delay;
   for (delay = 0;
@@ -157,14 +158,14 @@ static void sam3u_pmcwait(uint32_t bit)
 }
 
 /****************************************************************************
- * Name: sam3u_pmcsetup
+ * Name: sam_pmcsetup
  *
  * Description:
  *   Initialize clocking
  *
  ****************************************************************************/
 
-static inline void sam3u_pmcsetup(void)
+static inline void sam_pmcsetup(void)
 {
   uint32_t regval;
 
@@ -181,7 +182,7 @@ static inline void sam3u_pmcsetup(void)
        */
 
       putreg32(BOARD_CKGR_MOR, SAM_CKGR_MOR);
-      sam3u_pmcwait(PMC_INT_MOSCXTS);
+      sam_pmcwait(PMC_INT_MOSCXTS);
     }
 
   /* "Switch to the main oscillator.  The selection is made by writing the
@@ -197,7 +198,7 @@ static inline void sam3u_pmcsetup(void)
    */
 
   putreg32((BOARD_CKGR_MOR|CKGR_MOR_MOSCSEL), SAM_CKGR_MOR);
-  sam3u_pmcwait(PMC_INT_MOSCSELS);
+  sam_pmcwait(PMC_INT_MOSCSELS);
 
   /* "Select the master clock. "The Master Clock selection is made by writing
    *  the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register).
@@ -212,12 +213,12 @@ static inline void sam3u_pmcsetup(void)
   regval &= ~PMC_MCKR_CSS_MASK;
   regval |= PMC_MCKR_CSS_MAIN;
   putreg32(regval, SAM_PMC_MCKR);
-  sam3u_pmcwait(PMC_INT_MCKRDY);
+  sam_pmcwait(PMC_INT_MCKRDY);
 
   /* Settup PLLA and wait for LOCKA */
 
   putreg32(BOARD_CKGR_PLLAR, SAM_CKGR_PLLAR);
-  sam3u_pmcwait(PMC_INT_LOCKA);
+  sam_pmcwait(PMC_INT_LOCKA);
 
   /* Setup UTMI for USB and wait for LOCKU */
 
@@ -225,27 +226,27 @@ static inline void sam3u_pmcsetup(void)
   regval = getreg32(SAM_CKGR_UCKR);
   regval |= BOARD_CKGR_UCKR;
   putreg32(regval, SAM_CKGR_UCKR);
-  sam3u_pmcwait(PMC_INT_LOCKU);
+  sam_pmcwait(PMC_INT_LOCKU);
 #endif
 
   /* Switch to the fast clock and wait for MCKRDY */
 
   putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR);
-  sam3u_pmcwait(PMC_INT_MCKRDY);
+  sam_pmcwait(PMC_INT_MCKRDY);
 
   putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR);
-  sam3u_pmcwait(PMC_INT_MCKRDY);
+  sam_pmcwait(PMC_INT_MCKRDY);
 }
 
 /****************************************************************************
- * Name: sam3u_enabledefaultmaster and sam3u_disabledefaultmaster
+ * Name: sam_enabledefaultmaster and sam_disabledefaultmaster
  *
  * Description:
  *   Enable/disable default master access
  *
  ****************************************************************************/
 
-static inline void sam3u_enabledefaultmaster(void)
+static inline void sam_enabledefaultmaster(void)
 {
   uint32_t regval;
 
@@ -269,7 +270,7 @@ static inline void sam3u_enabledefaultmaster(void)
 }
 
 #if 0 /* Not used */
-static inline void sam3u_disabledefaultmaster(void)
+static inline void sam_disabledefaultmaster(void)
 {
   uint32_t regval;
 
@@ -298,7 +299,7 @@ static inline void sam3u_disabledefaultmaster(void)
  ****************************************************************************/
 
 /************************************************************************************
- * Name: sam3u_clockconfig
+ * Name: sam_clockconfig
  *
  * Description:
  *   Called to initialize the SAM3/4.  This does whatever setup is needed to put the
@@ -310,26 +311,26 @@ static inline void sam3u_disabledefaultmaster(void)
  *
  ************************************************************************************/
 
-void sam3u_clockconfig(void)
+void sam_clockconfig(void)
 {
   /* Configure embedded flash access */
 
-  sam3u_efcsetup();
+  sam_efcsetup();
 
   /* Configure the watchdog timer */
 
-  sam3u_wdtsetup();
+  sam_wdtsetup();
 
   /* Setup the supply controller to use the external slow clock */
 
-  sam3u_supcsetup();
+  sam_supcsetup();
 
   /* Initialize clocking */
 
-  sam3u_pmcsetup();
+  sam_pmcsetup();
 
   /* Optimize CPU setting for speed */
 
-  sam3u_enabledefaultmaster();
+  sam_enabledefaultmaster();
 }
 
diff --git a/nuttx/arch/arm/src/sam3u/sam_clockconfig.h b/nuttx/arch/arm/src/sam3u/sam_clockconfig.h
new file mode 100644
index 000000000..da57cb71a
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_clockconfig.h
@@ -0,0 +1,97 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_clockconfig.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_CLOCKCONFIG_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_CLOCKCONFIG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: sam_clockconfig
+ *
+ * Description:
+ *   Called to initialize the SAM3/4.  This does whatever setup is needed to put the
+ *   SoC in a usable state.  This includes the initialization of clocking using the
+ *   settings in board.h.  (After power-on reset, the sam3u is initiallyrunning on
+ *   a 4MHz internal RC clock).  This function also performs other low-level chip
+ *   initialization of the chip including EFC, master clock, IRQ and watchdog
+ *   configuration.
+ *
+ ************************************************************************************/
+
+void sam_clockconfig(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_CLOCKCONFIG_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_dmac.c b/nuttx/arch/arm/src/sam3u/sam_dmac.c
index ce0b130a1..d2871a99d 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_dmac.c
+++ b/nuttx/arch/arm/src/sam3u/sam_dmac.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam3u-ek/sam3u_dmac.c
+ * arch/arm/src/sam3u-ek/sam_dmac.c
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -55,7 +55,7 @@
 #include "os_internal.h"
 #include "chip.h"
 
-#include "sam3u_internal.h"
+#include "sam_dmac.h"
 #include "chip/sam_pmc.h"
 #include "chip/sam_dmac.h"
 
@@ -99,7 +99,7 @@
 
 /* This structure descibes one DMA channel */
 
-struct sam3u_dma_s
+struct sam_dma_s
 {
   uint8_t                chan;       /* DMA channel number (0-6) */
   bool                   inuse;      /* TRUE: The DMA channel is in use */
@@ -150,7 +150,7 @@ static struct dma_linklist_s g_linklist[CONFIG_SAM34_NLLDESC];
 
 /* This array describes the state of each DMA */
 
-static struct sam3u_dma_s g_dma[CONFIG_SAM34_NDMACHAN] =
+static struct sam_dma_s g_dma[CONFIG_SAM34_NDMACHAN] =
 {
 #ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E
   /* the AT91SAM3U4E has four DMA channels.  The FIFOs for channels 0-2 are
@@ -191,14 +191,14 @@ static struct sam3u_dma_s g_dma[CONFIG_SAM34_NDMACHAN] =
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_takechsem() and sam3u_givechsem()
+ * Name: sam_takechsem() and sam_givechsem()
  *
  * Description:
  *   Used to get exclusive access to the DMA channel table
  *
  ****************************************************************************/
 
-static void sam3u_takechsem(void)
+static void sam_takechsem(void)
 {
   /* Take the semaphore (perhaps waiting) */
 
@@ -212,20 +212,20 @@ static void sam3u_takechsem(void)
     }
 }
 
-static inline void sam3u_givechsem(void)
+static inline void sam_givechsem(void)
 {
   (void)sem_post(&g_chsem);
 }
 
 /****************************************************************************
- * Name: sam3u_takedsem() and sam3u_givedsem()
+ * Name: sam_takedsem() and sam_givedsem()
  *
  * Description:
  *   Used to wait for availability of descriptors in the descriptor table.
  *
  ****************************************************************************/
 
-static void sam3u_takedsem(void)
+static void sam_takedsem(void)
 {
   /* Take the semaphore (perhaps waiting) */
 
@@ -239,20 +239,20 @@ static void sam3u_takedsem(void)
     }
 }
 
-static inline void sam3u_givedsem(void)
+static inline void sam_givedsem(void)
 {
   (void)sem_post(&g_dsem);
 }
 
 /****************************************************************************
- * Name: sam3u_fifosize
+ * Name: sam_fifosize
  *
  * Description:
  *  Decode the FIFO size from the flags
  *
  ****************************************************************************/
 
-static unsigned int sam3u_fifosize(uint8_t dmach_flags)
+static unsigned int sam_fifosize(uint8_t dmach_flags)
 {
   dmach_flags &= DMACH_FLAG_FIFOSIZE_MASK;
   if (dmach_flags == DMACH_FLAG_FIFO_8BYTES)
@@ -266,27 +266,27 @@ static unsigned int sam3u_fifosize(uint8_t dmach_flags)
 }
 
 /****************************************************************************
- * Name: sam3u_flowcontrol
+ * Name: sam_flowcontrol
  *
  * Description:
  *  Decode the FIFO flow control from the flags
  *
  ****************************************************************************/
 
-static inline bool sam3u_flowcontrol(uint8_t dmach_flags)
+static inline bool sam_flowcontrol(uint8_t dmach_flags)
 {
   return ((dmach_flags & DMACH_FLAG_FLOWCONTROL) != 0);
 }
 
 /****************************************************************************
- * Name: sam3u_fifocfg
+ * Name: sam_fifocfg
  *
  * Description:
  *  Decode the FIFO config from the flags
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_fifocfg(struct sam3u_dma_s *dmach)
+static inline uint32_t sam_fifocfg(struct sam_dma_s *dmach)
 {
   unsigned int ndx = (dmach->flags & DMACH_FLAG_FIFOCFG_MASK) >> DMACH_FLAG_FIFOCFG_SHIFT;
   DEBUGASSERT(ndx < 3);
@@ -294,7 +294,7 @@ static inline uint32_t sam3u_fifocfg(struct sam3u_dma_s *dmach)
 }
 
 /****************************************************************************
- * Name: sam3u_txcfg
+ * Name: sam_txcfg
  *
  * Description:
  *  Decode the the flags to get the correct CFG register bit settings for
@@ -302,7 +302,7 @@ static inline uint32_t sam3u_fifocfg(struct sam3u_dma_s *dmach)
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_txcfg(struct sam3u_dma_s *dmach)
+static inline uint32_t sam_txcfg(struct sam_dma_s *dmach)
 {
   uint32_t regval;
 
@@ -312,12 +312,12 @@ static inline uint32_t sam3u_txcfg(struct sam3u_dma_s *dmach)
   regval  |=   (dmach->flags & DMACH_FLAG_MEMH2SEL) != 0 ? DMACHAN_CFG_SRCH2SEL : 0;
   regval  |= (((dmach->flags & DMACH_FLAG_PERIPHPID_MASK) >> DMACH_FLAG_PERIPHPID_SHIFT) << DMACHAN_CFG_DSTPER_SHIFT);
   regval  |=   (dmach->flags & DMACH_FLAG_PERIPHH2SEL) != 0 ? DMACHAN_CFG_DSTH2SEL : 0;
-  regval  |= sam3u_fifocfg(dmach);
+  regval  |= sam_fifocfg(dmach);
   return regval;
 }
 
 /****************************************************************************
- * Name: sam3u_rxcfg
+ * Name: sam_rxcfg
  *
  * Description:
  *  Decode the the flags to get the correct CFG register bit settings for
@@ -325,7 +325,7 @@ static inline uint32_t sam3u_txcfg(struct sam3u_dma_s *dmach)
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_rxcfg(struct sam3u_dma_s *dmach)
+static inline uint32_t sam_rxcfg(struct sam_dma_s *dmach)
 {
   uint32_t regval;
 
@@ -335,23 +335,23 @@ static inline uint32_t sam3u_rxcfg(struct sam3u_dma_s *dmach)
   regval  |=   (dmach->flags & DMACH_FLAG_PERIPHH2SEL) != 0 ? DMACHAN_CFG_SRCH2SEL : 0;
   regval  |= (((dmach->flags & DMACH_FLAG_MEMPID_MASK) >> DMACH_FLAG_MEMPID_SHIFT) << DMACHAN_CFG_DSTPER_SHIFT);
   regval  |=   (dmach->flags & DMACH_FLAG_MEMH2SEL) != 0 ? DMACHAN_CFG_DSTH2SEL : 0;
-  regval  |= sam3u_fifocfg(dmach);
+  regval  |= sam_fifocfg(dmach);
   return regval;
 }
 
 /****************************************************************************
- * Name: sam3u_txctrlabits
+ * Name: sam_txctrlabits
  *
  * Description:
  *  Decode the the flags to get the correct CTRLA register bit settings for
  *  a transmit (memory to peripheral) transfer.  These are only the "fixed"
  *  CTRLA values and  need to be updated with the actual transfer size before
- *  being written to CTRLA sam3u_txctrla).
+ *  being written to CTRLA sam_txctrla).
  *
  ****************************************************************************/
 
 static inline uint32_t
-sam3u_txctrlabits(struct sam3u_dma_s *dmach)
+sam_txctrlabits(struct sam_dma_s *dmach)
 {
   uint32_t regval;
   unsigned int ndx;
@@ -404,15 +404,15 @@ sam3u_txctrlabits(struct sam3u_dma_s *dmach)
 }
 
 /****************************************************************************
- * Name: sam3u_txctrla
+ * Name: sam_txctrla
  *
  * Description:
  *  Or in the variable CTRLA bits
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_txctrla(struct sam3u_dma_s *dmach,
-                                     uint32_t dmasize, uint32_t txctrlabits)
+static inline uint32_t sam_txctrla(struct sam_dma_s *dmach,
+                                   uint32_t dmasize, uint32_t txctrlabits)
 {
   /* Set the buffer transfer size field.  This is the number of transfers to
    * be performed, that is, the number of source width transfers to perform.
@@ -432,17 +432,17 @@ static inline uint32_t sam3u_txctrla(struct sam3u_dma_s *dmach,
 }
 
 /****************************************************************************
- * Name: sam3u_rxctrlabits
+ * Name: sam_rxctrlabits
  *
  * Description:
  *  Decode the the flags to get the correct CTRLA register bit settings for
  *  a read (peripheral to memory) transfer. These are only the "fixed" CTRLA
  *  values and need to be updated with the actual transfer size before being
- *  written to CTRLA sam3u_rxctrla).
+ *  written to CTRLA sam_rxctrla).
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_rxctrlabits(struct sam3u_dma_s *dmach)
+static inline uint32_t sam_rxctrlabits(struct sam_dma_s *dmach)
 {
   uint32_t     regval;
   unsigned int ndx;
@@ -495,15 +495,15 @@ static inline uint32_t sam3u_rxctrlabits(struct sam3u_dma_s *dmach)
 }
 
 /****************************************************************************
- * Name: sam3u_rxctrla
+ * Name: sam_rxctrla
  *
  * Description:
  *  'OR' in the variable CTRLA bits
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_rxctrla(struct sam3u_dma_s *dmach,
-                                     uint32_t dmasize, uint32_t txctrlabits)
+static inline uint32_t sam_rxctrla(struct sam_dma_s *dmach,
+                                   uint32_t dmasize, uint32_t txctrlabits)
 {
   /* Set the buffer transfer size field.  This is the number of transfers to
    * be performed, that is, the number of source width transfers to perform.
@@ -523,7 +523,7 @@ static inline uint32_t sam3u_rxctrla(struct sam3u_dma_s *dmach,
 }
 
 /****************************************************************************
- * Name: sam3u_txctrlb
+ * Name: sam_txctrlb
  *
  * Description:
  *  Decode the the flags to get the correct CTRLB register bit settings for
@@ -531,7 +531,7 @@ static inline uint32_t sam3u_rxctrla(struct sam3u_dma_s *dmach,
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_txctrlb(struct sam3u_dma_s *dmach)
+static inline uint32_t sam_txctrlb(struct sam_dma_s *dmach)
 {
   uint32_t regval;
 
@@ -602,7 +602,7 @@ static inline uint32_t sam3u_txctrlb(struct sam3u_dma_s *dmach)
 }
 
 /****************************************************************************
- * Name: sam3u_rxctrlb
+ * Name: sam_rxctrlb
  *
  * Description:
  *  Decode the the flags to get the correct CTRLB register bit settings for
@@ -610,7 +610,7 @@ static inline uint32_t sam3u_txctrlb(struct sam3u_dma_s *dmach)
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_rxctrlb(struct sam3u_dma_s *dmach)
+static inline uint32_t sam_rxctrlb(struct sam_dma_s *dmach)
 {
   uint32_t regval;
 
@@ -681,7 +681,7 @@ static inline uint32_t sam3u_rxctrlb(struct sam3u_dma_s *dmach)
 }
 
 /****************************************************************************
- * Name: sam3u_allocdesc
+ * Name: sam_allocdesc
  *
  * Description:
  *  Allocate and add one descriptor to the DMA channel's link list.
@@ -695,8 +695,8 @@ static inline uint32_t sam3u_rxctrlb(struct sam3u_dma_s *dmach)
  ****************************************************************************/
 
 static struct dma_linklist_s *
-sam3u_allocdesc(struct sam3u_dma_s *dmach, struct dma_linklist_s *prev,
-                uint32_t src, uint32_t dest, uint32_t ctrla, uint32_t ctrlb)
+sam_allocdesc(struct sam_dma_s *dmach, struct dma_linklist_s *prev,
+              uint32_t src, uint32_t dest, uint32_t ctrla, uint32_t ctrlb)
 {
   struct dma_linklist_s *desc = NULL;
   int i;
@@ -713,7 +713,7 @@ sam3u_allocdesc(struct sam3u_dma_s *dmach, struct dma_linklist_s *prev,
        * is at least one free descriptor in the table and it is ours.
        */
 
-      sam3u_takedsem();
+      sam_takedsem();
 
       /* Examine each link list entry to find an available one -- i.e., one
        * with src == 0.  That src field is set to zero by the DMA transfer
@@ -721,7 +721,7 @@ sam3u_allocdesc(struct sam3u_dma_s *dmach, struct dma_linklist_s *prev,
        * that is an atomic operation.
        */
 
-      sam3u_takechsem();
+      sam_takechsem();
       for (i = 0; i < CONFIG_SAM34_NLLDESC; i++)
         {
           if (g_linklist[i].src == 0)
@@ -780,14 +780,15 @@ sam3u_allocdesc(struct sam3u_dma_s *dmach, struct dma_linklist_s *prev,
        * search loop should always be successful.
        */
 
-      sam3u_givechsem();
+      sam_givechsem();
       DEBUGASSERT(desc != NULL);
     }
+
   return desc;
 }
 
 /****************************************************************************
- * Name: sam3u_freelinklist
+ * Name: sam_freelinklist
  *
  * Description:
  *  Free all descriptors in the DMA channel's link list.
@@ -796,7 +797,7 @@ sam3u_allocdesc(struct sam3u_dma_s *dmach, struct dma_linklist_s *prev,
  *
  ****************************************************************************/
 
-static void sam3u_freelinklist(struct sam3u_dma_s *dmach)
+static void sam_freelinklist(struct sam_dma_s *dmach)
 {
   struct dma_linklist_s *desc;
   struct dma_linklist_s *next;
@@ -816,13 +817,13 @@ static void sam3u_freelinklist(struct sam3u_dma_s *dmach)
       next = (struct dma_linklist_s *)desc->next;
       DEBUGASSERT(desc->src != 0);
       memset(desc, 0, sizeof(struct dma_linklist_s));
-      sam3u_givedsem();
+      sam_givedsem();
       desc = next;
     }
 }
 
 /****************************************************************************
- * Name: sam3u_txbuffer
+ * Name: sam_txbuffer
  *
  * Description:
  *   Configure DMA for transmit of one buffer (memory to peripheral).  This
@@ -831,8 +832,8 @@ static void sam3u_freelinklist(struct sam3u_dma_s *dmach)
  *
  ****************************************************************************/
 
-static int sam3u_txbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
-                          uint32_t maddr, size_t nbytes)
+static int sam_txbuffer(struct sam_dma_s *dmach, uint32_t paddr,
+                        uint32_t maddr, size_t nbytes)
 {
   uint32_t regval;
   uint32_t ctrla;
@@ -849,14 +850,15 @@ static int sam3u_txbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
     }
   else
     {
-      regval = sam3u_txctrlabits(dmach);
-      ctrlb  = sam3u_txctrlb(dmach);
+      regval = sam_txctrlabits(dmach);
+      ctrlb  = sam_txctrlb(dmach);
     }
-  ctrla  = sam3u_txctrla(dmach, regval, nbytes);
+
+  ctrla = sam_txctrla(dmach, regval, nbytes);
 
   /* Add the new link list entry */
 
-  if (!sam3u_allocdesc(dmach, dmach->lltail, maddr, paddr, ctrla, ctrlb))
+  if (!sam_allocdesc(dmach, dmach->lltail, maddr, paddr, ctrla, ctrlb))
     {
       return -ENOMEM;
     }
@@ -865,12 +867,12 @@ static int sam3u_txbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
    * the DMA is started).
    */
 
-  dmach->cfg = sam3u_txcfg(dmach);
+  dmach->cfg = sam_txcfg(dmach);
   return OK;
 }
 
 /****************************************************************************
- * Name: sam3u_rxbuffer
+ * Name: sam_rxbuffer
  *
  * Description:
  *   Configure DMA for receipt of one buffer (peripheral to memory).  This
@@ -879,8 +881,8 @@ static int sam3u_txbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
  *
  ****************************************************************************/
 
-static int sam3u_rxbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
-                          uint32_t maddr, size_t nbytes)
+static int sam_rxbuffer(struct sam_dma_s *dmach, uint32_t paddr,
+                        uint32_t maddr, size_t nbytes)
 {
   uint32_t regval;
   uint32_t ctrla;
@@ -897,14 +899,14 @@ static int sam3u_rxbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
     }
   else
     {
-      regval = sam3u_rxctrlabits(dmach);
-      ctrlb  = sam3u_rxctrlb(dmach);
+      regval = sam_rxctrlabits(dmach);
+      ctrlb  = sam_rxctrlb(dmach);
     }
-   ctrla  = sam3u_rxctrla(dmach, regval, nbytes);
+   ctrla  = sam_rxctrla(dmach, regval, nbytes);
 
   /* Add the new link list entry */
 
-  if (!sam3u_allocdesc(dmach, dmach->lltail, paddr, maddr, ctrla, ctrlb))
+  if (!sam_allocdesc(dmach, dmach->lltail, paddr, maddr, ctrla, ctrlb))
     {
       return -ENOMEM;
     }
@@ -913,19 +915,19 @@ static int sam3u_rxbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
    * the DMA is started).
    */
 
-  dmach->cfg = sam3u_rxcfg(dmach);
+  dmach->cfg = sam_rxcfg(dmach);
   return OK;
 }
 
 /****************************************************************************
- * Name: sam3u_single
+ * Name: sam_single
  *
  * Description:
  *   Start a single buffer DMA.
  *
  ****************************************************************************/
 
-static inline int sam3u_single(struct sam3u_dma_s *dmach)
+static inline int sam_single(struct sam_dma_s *dmach)
 {
   struct dma_linklist_s *llhead = dmach->llhead;
 
@@ -978,14 +980,14 @@ static inline int sam3u_single(struct sam3u_dma_s *dmach)
 }
 
 /****************************************************************************
- * Name: sam3u_multiple
+ * Name: sam_multiple
  *
  * Description:
  *   Start a multiple buffer DMA.
  *
  ****************************************************************************/
 
-static inline int sam3u_multiple(struct sam3u_dma_s *dmach)
+static inline int sam_multiple(struct sam_dma_s *dmach)
 {
   struct dma_linklist_s *llhead = dmach->llhead;
 
@@ -1039,14 +1041,14 @@ static inline int sam3u_multiple(struct sam3u_dma_s *dmach)
 }
 
 /****************************************************************************
- * Name: sam3u_dmasterminate
+ * Name: sam_dmaterminate
  *
  * Description:
  *   Terminate the DMA transfer and disable the DMA channel
  *
  ****************************************************************************/
 
-static void sam3u_dmaterminate(struct sam3u_dma_s *dmach, int result)
+static void sam_dmaterminate(struct sam_dma_s *dmach, int result)
 {
   /* Disable all channel interrupts */
 
@@ -1058,7 +1060,7 @@ static void sam3u_dmaterminate(struct sam3u_dma_s *dmach, int result)
 
   /* Free the linklist */
 
-  sam3u_freelinklist(dmach);
+  sam_freelinklist(dmach);
 
   /* Perform the DMA complete callback */
 
@@ -1072,16 +1074,16 @@ static void sam3u_dmaterminate(struct sam3u_dma_s *dmach, int result)
 }
 
 /****************************************************************************
- * Name: sam3u_dmainterrupt
+ * Name: sam_dmainterrupt
  *
  * Description:
  *  DMA interrupt handler
  *
  ****************************************************************************/
 
-static int sam3u_dmainterrupt(int irq, void *context)
+static int sam_dmainterrupt(int irq, void *context)
 {
-  struct sam3u_dma_s *dmach;
+  struct sam_dma_s *dmach;
   unsigned int chndx;
   uint32_t regval;
 
@@ -1111,7 +1113,7 @@ static int sam3u_dmainterrupt(int irq, void *context)
                 {
                    /* Yes... Terminate the transfer with an error? */
 
-                  sam3u_dmaterminate(dmach, -EIO);
+                  sam_dmaterminate(dmach, -EIO);
                 }
 
               /* Is the transfer complete? */
@@ -1120,7 +1122,7 @@ static int sam3u_dmainterrupt(int irq, void *context)
                {
                   /* Yes.. Terminate the transfer with success */
 
-                  sam3u_dmaterminate(dmach, OK);
+                  sam_dmaterminate(dmach, OK);
                 }
 
               /* Otherwise, this must be a Bufffer Transfer Complete (BTC)
@@ -1144,7 +1146,7 @@ static int sam3u_dmainterrupt(int irq, void *context)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_dmainitialize
+ * Name: up_dmainitialize
  *
  * Description:
  *   Initialize the DMA subsystem
@@ -1170,7 +1172,7 @@ void weak_function up_dmainitialize(void)
 
   /* Attach DMA interrupt vector */
 
-  (void)irq_attach(SAM_IRQ_DMAC, sam3u_dmainterrupt);
+  (void)irq_attach(SAM_IRQ_DMAC, sam_dmainterrupt);
 
   /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
 
@@ -1187,7 +1189,7 @@ void weak_function up_dmainitialize(void)
 }
 
 /****************************************************************************
- * Name: sam3u_dmachannel
+ * Name: sam_dmachannel
  *
  * Description:
  *   Allocate a DMA channel.  This function sets aside a DMA channel with
@@ -1206,28 +1208,28 @@ void weak_function up_dmainitialize(void)
  *
  ****************************************************************************/
 
-DMA_HANDLE sam3u_dmachannel(uint32_t dmach_flags)
+DMA_HANDLE sam_dmachannel(uint32_t dmach_flags)
 {
-  struct sam3u_dma_s *dmach;
+  struct sam_dma_s *dmach;
   unsigned int chndx;
 
   /* Get the search parameters */
 
-  bool flowcontrol = sam3u_flowcontrol(dmach_flags);
-  unsigned int fifosize = sam3u_fifosize(dmach_flags);
+  bool flowcontrol = sam_flowcontrol(dmach_flags);
+  unsigned int fifosize = sam_fifosize(dmach_flags);
 
   /* Search for an available DMA channel with at least the requested FIFO
    * size.
    */
 
   dmach = NULL;
-  sam3u_takechsem();
+  sam_takechsem();
   for (chndx = 0; chndx < CONFIG_SAM34_NDMACHAN; chndx++)
     {
-      struct sam3u_dma_s *candidate = &g_dma[chndx];
+      struct sam_dma_s *candidate = &g_dma[chndx];
       if (!candidate->inuse &&
-          (sam3u_fifosize(candidate->flags) >= fifosize) &&
-          (!flowcontrol || sam3u_flowcontrol(dmach_flags)))
+          (sam_fifosize(candidate->flags) >= fifosize) &&
+          (!flowcontrol || sam_flowcontrol(dmach_flags)))
         {
           dmach         = candidate;
           dmach->inuse  = true;
@@ -1254,16 +1256,16 @@ DMA_HANDLE sam3u_dmachannel(uint32_t dmach_flags)
           break;
         }
     }
-  sam3u_givechsem();
+  sam_givechsem();
   return (DMA_HANDLE)dmach;
 }
 
 /****************************************************************************
- * Name: sam3u_dmafree
+ * Name: sam_dmafree
  *
  * Description:
  *   Release a DMA channel.  NOTE:  The 'handle' used in this argument must
- *   NEVER be used again until sam3u_dmachannel() is called again to re-gain
+ *   NEVER be used again until sam_dmachannel() is called again to re-gain
  *   a valid handle.
  *
  * Returned Value:
@@ -1271,9 +1273,9 @@ DMA_HANDLE sam3u_dmachannel(uint32_t dmach_flags)
  *
  ****************************************************************************/
 
-void sam3u_dmafree(DMA_HANDLE handle)
+void sam_dmafree(DMA_HANDLE handle)
 {
-  struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
+  struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
 
   /* Mark the channel no longer in use.  Clearing the inuse flag is an atomic
    * operation and so should be safe.
@@ -1285,19 +1287,19 @@ void sam3u_dmafree(DMA_HANDLE handle)
 }
 
 /****************************************************************************
- * Name: sam3u_dmatxsetup
+ * Name: sam_dmatxsetup
  *
  * Description:
  *   Configure DMA for transmit of one buffer (memory to peripheral).  This
  *   function may be called multiple times to handle large and/or dis-
- *   continuous transfers.  Calls to sam3u_dmatxsetup() and sam3u_dmarxsetup()
+ *   continuous transfers.  Calls to sam_dmatxsetup() and sam_dmarxsetup()
  *   must not be intermixed on the same transfer, however.
  *
  ****************************************************************************/
 
-int sam3u_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes)
+int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes)
 {
-  struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
+  struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
   int ret = OK;
 
   DEBUGASSERT(dmach && dmach->llhead != NULL && dmach->lltail != 0);
@@ -1308,7 +1310,7 @@ int sam3u_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t n
     {
       /* Set up the maximum size transfer */
 
-      ret = sam3u_txbuffer(dmach, paddr, maddr, DMACHAN_CTRLA_BTSIZE_MAX);
+      ret = sam_txbuffer(dmach, paddr, maddr, DMACHAN_CTRLA_BTSIZE_MAX);
       if (ret == OK);
         {
           /* Decrement the number of bytes left to transfer */
@@ -1335,25 +1337,25 @@ int sam3u_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t n
 
   if (ret == OK && nbytes > 0)
     {
-      ret = sam3u_txbuffer(dmach, paddr, maddr, nbytes);
+      ret = sam_txbuffer(dmach, paddr, maddr, nbytes);
     }
   return ret;
 }
 
 /****************************************************************************
- * Name: sam3u_dmarxsetup
+ * Name: sam_dmarxsetup
  *
  * Description:
  *   Configure DMA for receipt of one buffer (peripheral to memory).  This
  *   function may be called multiple times to handle large and/or dis-
- *   continuous transfers.  Calls to sam3u_dmatxsetup() and sam3u_dmarxsetup()
+ *   continuous transfers.  Calls to sam_dmatxsetup() and sam_dmarxsetup()
  *   must not be intermixed on the same transfer, however.
  *
  ****************************************************************************/
 
-int sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes)
+int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes)
 {
-  struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
+  struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
   int ret = OK;
 
   DEBUGASSERT(dmach && dmach->llhead != NULL && dmach->lltail != 0);
@@ -1364,7 +1366,7 @@ int sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t n
     {
       /* Set up the maximum size transfer */
 
-      ret = sam3u_rxbuffer(dmach, paddr, maddr, DMACHAN_CTRLA_BTSIZE_MAX);
+      ret = sam_rxbuffer(dmach, paddr, maddr, DMACHAN_CTRLA_BTSIZE_MAX);
       if (ret == OK);
         {
           /* Decrement the number of bytes left to transfer */
@@ -1391,22 +1393,22 @@ int sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t n
 
   if (ret == OK && nbytes > 0)
     {
-      ret = sam3u_rxbuffer(dmach, paddr, maddr, nbytes);
+      ret = sam_rxbuffer(dmach, paddr, maddr, nbytes);
     }
   return ret;
 }
 
 /****************************************************************************
- * Name: sam3u_dmastart
+ * Name: sam_dmastart
  *
  * Description:
  *   Start the DMA transfer
  *
  ****************************************************************************/
 
-int sam3u_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
+int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
 {
-  struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
+  struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
   int ret = -EINVAL;
 
   /* Verify that the DMA has been setup (i.e., at least one entry in the
@@ -1425,52 +1427,52 @@ int sam3u_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
 
       if (dmach->llhead == dmach->lltail)
         {
-          ret = sam3u_single(dmach);
+          ret = sam_single(dmach);
         }
       else
         {
-          ret = sam3u_multiple(dmach);
+          ret = sam_multiple(dmach);
         }
     }
   return ret;
 }
 
 /****************************************************************************
- * Name: sam3u_dmastop
+ * Name: sam_dmastop
  *
  * Description:
- *   Cancel the DMA.  After sam3u_dmastop() is called, the DMA channel is
- *   reset and sam3u_dmasetup() must be called before sam3u_dmastart() can be
+ *   Cancel the DMA.  After sam_dmastop() is called, the DMA channel is
+ *   reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be
  *   called again
  *
  ****************************************************************************/
 
-void sam3u_dmastop(DMA_HANDLE handle)
+void sam_dmastop(DMA_HANDLE handle)
 {
-  struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
+  struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
   irqstate_t flags;
 
   DEBUGASSERT(dmach != NULL);
   flags = irqsave();
-  sam3u_dmaterminate(dmach, -EINTR);
+  sam_dmaterminate(dmach, -EINTR);
   irqrestore(flags);
 }
 
 /****************************************************************************
- * Name: sam3u_dmasample
+ * Name: sam_dmasample
  *
  * Description:
  *   Sample DMA register contents
  *
  * Assumptions:
- *   - DMA handle allocated by sam3u_dmachannel()
+ *   - DMA handle allocated by sam_dmachannel()
  *
  ****************************************************************************/
 
 #ifdef CONFIG_DEBUG_DMA
-void sam3u_dmasample(DMA_HANDLE handle, struct sam3u_dmaregs_s *regs)
+void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
 {
-  struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
+  struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
   irqstate_t flags;
 
   /* Sample global registers.  NOTE: reading EBCISR clears interrupts, but
@@ -1502,21 +1504,21 @@ void sam3u_dmasample(DMA_HANDLE handle, struct sam3u_dmaregs_s *regs)
 #endif /* CONFIG_DEBUG_DMA */
 
 /****************************************************************************
- * Name: sam3u_dmadump
+ * Name: sam_dmadump
  *
  * Description:
  *   Dump previously sampled DMA register contents
  *
  * Assumptions:
- *   - DMA handle allocated by sam3u_dmachannel()
+ *   - DMA handle allocated by sam_dmachannel()
  *
  ****************************************************************************/
 
 #ifdef CONFIG_DEBUG_DMA
-void sam3u_dmadump(DMA_HANDLE handle, const struct sam3u_dmaregs_s *regs,
-                   const char *msg)
+void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
+                 const char *msg)
 {
-  struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
+  struct sam_dma_s *dmach = (struct sam_dma_s *)handle;
 
   dmadbg("%s\n", msg);
   dmadbg("  DMA Global Registers:\n");
diff --git a/nuttx/arch/arm/src/sam3u/sam_dmac.h b/nuttx/arch/arm/src/sam3u/sam_dmac.h
new file mode 100644
index 000000000..f07303011
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_dmac.h
@@ -0,0 +1,297 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_dmac.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_DMAC_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_DMAC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Configuration ********************************************************************/
+
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_DEBUG_DMA
+#endif
+
+/* DMA ******************************************************************************/
+
+/* Flags used to characterize the desired DMA channel.  The naming convention is that
+ * one side is the peripheral and the other is memory (however, the interface could still
+ * be used if, for example, both sides were memory although the naming would be awkward)
+ */
+
+/* Unchange-able properties of the channel */
+
+#define DMACH_FLAG_FLOWCONTROL                (1 << 0)  /* Bit 0: Channel supports flow control */
+#define DMACH_FLAG_FIFOSIZE_SHIFT             (1)       /* Bit 1: Size of DMA FIFO */
+#define DMACH_FLAG_FIFOSIZE_MASK              (1 << DMACH_FLAG_FIFOSIZE_SHIFT)
+#  define DMACH_FLAG_FIFO_8BYTES              (0 << DMACH_FLAG_FIFOSIZE_SHIFT) /* 8 bytes */
+#  define DMACH_FLAG_FIFO_32BYTES             (1 << DMACH_FLAG_FIFOSIZE_SHIFT) /* 32 bytes */
+
+/* Configurable properties of the channel */
+
+#define DMACH_FLAG_BURST_LARGEST              0  /* Largest length AHB burst */
+#define DMACH_FLAG_BURST_HALF                 1  /* Half FIFO size */
+#define DMACH_FLAG_BURST_SINGLE               2  /* Single AHB access */
+
+#define DMACH_FLAG_FIFOCFG_SHIFT              (2)       /* Bits 2-3: FIFO configuration */
+#define DMACH_FLAG_FIFOCFG_MASK               (3 << DMACH_FLAG_FIFOCFG_SHIFT)
+#  define DMACH_FLAG_FIFOCFG_LARGEST          (DMACH_FLAG_BURST_LARGEST << DMACH_FLAG_FIFOCFG_SHIFT)
+#  define DMACH_FLAG_FIFOCFG_HALF             (DMACH_FLAG_BURST_HALF << DMACH_FLAG_FIFOCFG_SHIFT)
+#  define DMACH_FLAG_FIFOCFG_SINGLE           (DMACH_FLAG_BURST_SINGLE << DMACH_FLAG_FIFOCFG_SHIFT)
+
+/* Peripheral endpoint characteristics */
+
+#define DMACH_FLAG_PERIPHPID_SHIFT            (4)       /* Bits 4-7: Peripheral PID */
+#define DMACH_FLAG_PERIPHPID_MASK             (15 << DMACH_FLAG_PERIPHPID_SHIFT)
+#define DMACH_FLAG_PERIPHH2SEL                (1 << 8)  /* Bits 8: HW handshaking */
+#define DMACH_FLAG_PERIPHISPERIPH             (1 << 9)  /* Bits 9: 0=memory; 1=peripheral */
+#define DMACH_FLAG_PERIPHWIDTH_SHIFT          (10)      /* Bits 10-11: Peripheral width */
+#define DMACH_FLAG_PERIPHWIDTH_MASK           (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT)
+#  define DMACH_FLAG_PERIPHWIDTH_8BITS        (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */
+#  define DMACH_FLAG_PERIPHWIDTH_16BITS       (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */
+#  define DMACH_FLAG_PERIPHWIDTH_32BITS       (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */
+#define DMACH_FLAG_PERIPHINCREMENT            (1 << 12) /* Bit 12: Autoincrement peripheral address */
+#define DMACH_FLAG_PERIPHCHUNKSIZE            (1 << 13) /* Bit 13: Peripheral chunk size */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_1        (0)                        /* Peripheral chunksize = 1 */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_4        DMACH_FLAG_PERIPHCHUNKSIZE /* Peripheral chunksize = 4 */
+
+/* Memory endpoint characteristics */
+
+#define DMACH_FLAG_MEMPID_SHIFT               (14)      /* Bits 14-17: Memory PID */
+#define DMACH_FLAG_MEMPID_MASK                (15 << DMACH_FLAG_PERIPHPID_SHIFT)
+#define DMACH_FLAG_MEMH2SEL                   (1 << 18) /* Bits 18: HW handshaking */
+#define DMACH_FLAG_MEMISPERIPH                (1 << 19) /* Bits 19: 0=memory; 1=peripheral */
+#define DMACH_FLAG_MEMWIDTH_SHIFT             (20)      /* Bits 20-21: Memory width */
+#define DMACH_FLAG_MEMWIDTH_MASK              (3 << DMACH_FLAG_MEMWIDTH_SHIFT)
+#  define DMACH_FLAG_MEMWIDTH_8BITS           (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */
+#  define DMACH_FLAG_MEMWIDTH_16BITS          (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */
+#  define DMACH_FLAG_MEMWIDTH_32BITS          (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */
+#define DMACH_FLAG_MEMINCREMENT               (1 << 22) /* Bit 22: Autoincrement memory address */
+#define DMACH_FLAG_MEMCHUNKSIZE               (1 << 22) /* Bit 23: Memory chunk size */
+#  define DMACH_FLAG_MEMCHUNKSIZE_1           (0)                     /* Memory chunksize = 1 */
+#  define DMACH_FLAG_MEMCHUNKSIZE_4           DMACH_FLAG_MEMCHUNKSIZE /* Memory chunksize = 4 */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+typedef FAR void *DMA_HANDLE;
+typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
+
+/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
+
+#ifdef CONFIG_DEBUG_DMA
+struct sam_dmaregs_s
+{
+  /* Global Registers */
+
+  uint32_t gcfg;    /* DMAC Global Configuration Register */
+  uint32_t en;      /* DMAC Enable Register */
+  uint32_t sreq;    /* DMAC Software Single Request Register */
+  uint32_t creq;    /* DMAC Software Chunk Transfer Request Register */
+  uint32_t last;    /* DMAC Software Last Transfer Flag Register */
+  uint32_t ebcimr;  /* DMAC Error Mask */
+  uint32_t ebcisr;  /* DMAC Error Status */
+  uint32_t chsr;    /* DMAC Channel Handler Status Register */
+
+  /* Channel Registers */
+
+  uint32_t saddr;   /* DMAC Channel Source Address Register */
+  uint32_t daddr;   /* DMAC Channel Destination Address Register */
+  uint32_t dscr;    /* DMAC Channel Descriptor Address Register */
+  uint32_t ctrla;   /* DMAC Channel Control A Register */
+  uint32_t ctrlb;   /* DMAC Channel Control B Register */
+  uint32_t cfg;     /* DMAC Channel Configuration Register */
+};
+#endif
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: sam_dmachannel
+ *
+ * Description:
+ *   Allocate a DMA channel.  This function sets aside a DMA channel with
+ *   the required FIFO size and flow control capabilities (determined by
+ *   dma_flags) then  gives the caller exclusive access to the DMA channel.
+ *
+ *   The naming convention in all of the DMA interfaces is that one side is
+ *   the 'peripheral' and the other is 'memory'.  Howerver, the interface
+ *   could still be used if, for example, both sides were memory although
+ *   the naming would be awkward.
+ *
+ * Returned Value:
+ *   If a DMA channel if the required FIFO size is available, this function
+ *   returns a non-NULL, void* DMA channel handle.  NULL is returned on any
+ *   failure.
+ *
+ ****************************************************************************/
+
+DMA_HANDLE sam_dmachannel(uint32_t dmach_flags);
+
+/****************************************************************************
+ * Name: sam_dmafree
+ *
+ * Description:
+ *   Release a DMA channel.  NOTE:  The 'handle' used in this argument must
+ *   NEVER be used again until sam_dmachannel() is called again to re-gain
+ *   a valid handle.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void sam_dmafree(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: sam_dmatxsetup
+ *
+ * Description:
+ *   Configure DMA for transmit of one buffer (memory to peripheral).  This
+ *   function may be called multiple times to handle large and/or dis-
+ *   continuous transfers.  Calls to sam_dmatxsetup() and sam_dmarxsetup()
+ *   must not be intermixed on the same transfer, however.
+ *
+ ****************************************************************************/
+
+int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
+                   size_t nbytes);
+
+/****************************************************************************
+ * Name: sam_dmarxsetup
+ *
+ * Description:
+ *   Configure DMA for receipt of one buffer (peripheral to memory).  This
+ *   function may be called multiple times to handle large and/or dis-
+ *   continuous transfers.  Calls to sam_dmatxsetup() and sam_dmarxsetup()
+ *   must not be intermixed on the same transfer, however.
+ *
+ ****************************************************************************/
+
+int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
+                   size_t nbytes);
+
+/****************************************************************************
+ * Name: sam_dmastart
+ *
+ * Description:
+ *   Start the DMA transfer
+ *
+ ****************************************************************************/
+
+int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
+
+/****************************************************************************
+ * Name: sam_dmastop
+ *
+ * Description:
+ *   Cancel the DMA.  After sam_dmastop() is called, the DMA channel is
+ *   reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be
+ *   called again
+ *
+ ****************************************************************************/
+
+void sam_dmastop(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: sam_dmasample
+ *
+ * Description:
+ *   Sample DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs);
+#else
+#  define sam_dmasample(handle,regs)
+#endif
+
+/****************************************************************************
+ * Name: sam_dmadump
+ *
+ * Description:
+ *   Dump previously sampled DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
+                 const char *msg);
+#else
+#  define sam_dmadump(handle,regs,msg)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_DMAC_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_pio.c b/nuttx/arch/arm/src/sam3u/sam_gpio.c
index b3133ebc5..ea389ec5a 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_pio.c
+++ b/nuttx/arch/arm/src/sam3u/sam_gpio.c
@@ -1,7 +1,7 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_pio.c
+ * arch/arm/src/sam3u/sam_gpio.c
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -51,7 +51,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "sam3u_internal.h"
+#include "sam_gpio.h"
 #include "chip/sam_pio.h"
 
 /****************************************************************************
@@ -74,42 +74,42 @@ static const char g_portchar[4]   = { 'A', 'B', 'C', 'D' };
  * Private Function Prototypes
  ****************************************************************************/
 /****************************************************************************
- * Name: sam3u_gpiobase
+ * Name: sam_gpiobase
  *
  * Description:
  *   Return the base address of the GPIO register set
  *
  ****************************************************************************/
 
-static inline uintptr_t sam3u_gpiobase(uint16_t cfgset)
+static inline uintptr_t sam_gpiobase(uint16_t cfgset)
 {
   int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
   return SAM_PION_BASE(port);
 }
 
 /****************************************************************************
- * Name: sam3u_gpiopin
+ * Name: sam_gpiopin
  *
  * Description:
  *   Returun the base address of the GPIO register set
  *
  ****************************************************************************/
 
-static inline int sam3u_gpiopin(uint16_t cfgset)
+static inline int sam_gpiopin(uint16_t cfgset)
 {
   return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
 }
 
 /****************************************************************************
- * Name: sam3u_configinput
+ * Name: sam_configinput
  *
  * Description:
  *   Configure a GPIO input pin based on bit-encoded description of the pin.
  *
  ****************************************************************************/
 
-static inline int sam3u_configinput(uintptr_t base, uint32_t pin,
-                                    uint16_t cfgset)
+static inline int sam_configinput(uintptr_t base, uint32_t pin,
+                                  uint16_t cfgset)
 {
   /* Disable interrupts on the pin */
 
@@ -144,22 +144,22 @@ static inline int sam3u_configinput(uintptr_t base, uint32_t pin,
 
   /* To-Do:  If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
    *         registers.  This would probably best be done with another, new
-   *         API... perhaps sam3u_configfilter()
+   *         API... perhaps sam_configfilter()
    */
 
  return OK;
 }
 
 /****************************************************************************
- * Name: sam3u_configoutput
+ * Name: sam_configoutput
  *
  * Description:
  *   Configure a GPIO output pin based on bit-encoded description of the pin.
  *
  ****************************************************************************/
 
-static inline int sam3u_configoutput(uintptr_t base, uint32_t pin,
-                                     uint16_t cfgset)
+static inline int sam_configoutput(uintptr_t base, uint32_t pin,
+                                   uint16_t cfgset)
 {
   /* Disable interrupts on the pin */
 
@@ -206,7 +206,7 @@ static inline int sam3u_configoutput(uintptr_t base, uint32_t pin,
 }
 
 /****************************************************************************
- * Name: sam3u_configperiph
+ * Name: sam_configperiph
  *
  * Description:
  *   Configure a GPIO pin driven by a peripheral A or B signal based on
@@ -214,8 +214,8 @@ static inline int sam3u_configoutput(uintptr_t base, uint32_t pin,
  *
  ****************************************************************************/
 
-static inline int sam3u_configperiph(uintptr_t base, uint32_t pin,
-                                     uint16_t cfgset)
+static inline int sam_configperiph(uintptr_t base, uint32_t pin,
+                                   uint16_t cfgset)
 {
   uint32_t regval;
 
@@ -258,32 +258,32 @@ static inline int sam3u_configperiph(uintptr_t base, uint32_t pin,
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_configgpio
+ * Name: sam_configgpio
  *
  * Description:
  *   Configure a GPIO pin based on bit-encoded description of the pin.
  *
  ****************************************************************************/
 
-int sam3u_configgpio(uint16_t cfgset)
+int sam_configgpio(uint16_t cfgset)
 {
-  uintptr_t base = sam3u_gpiobase(cfgset);
-  uint32_t  pin  = sam3u_gpiopin(cfgset);
+  uintptr_t base = sam_gpiobase(cfgset);
+  uint32_t  pin  = sam_gpiopin(cfgset);
   int       ret;
 
   switch (cfgset & GPIO_MODE_MASK)
     {
       case GPIO_INPUT:
-        ret = sam3u_configinput(base, pin, cfgset);
+        ret = sam_configinput(base, pin, cfgset);
         break;
 
       case GPIO_OUTPUT:
-        ret = sam3u_configoutput(base, pin, cfgset);
+        ret = sam_configoutput(base, pin, cfgset);
         break;
 
       case GPIO_PERIPHA:
       case GPIO_PERIPHB:
-        ret = sam3u_configperiph(base, pin, cfgset);
+        ret = sam_configperiph(base, pin, cfgset);
         break;
 
       default:
@@ -294,17 +294,17 @@ int sam3u_configgpio(uint16_t cfgset)
 }
 
 /****************************************************************************
- * Name: sam3u_gpiowrite
+ * Name: sam_gpiowrite
  *
  * Description:
  *   Write one or zero to the selected GPIO pin
  *
  ****************************************************************************/
 
-void sam3u_gpiowrite(uint16_t pinset, bool value)
+void sam_gpiowrite(uint16_t pinset, bool value)
 {
-  uintptr_t base = sam3u_gpiobase(pinset);
-  uint32_t  pin  = sam3u_gpiopin(pinset);
+  uintptr_t base = sam_gpiobase(pinset);
+  uint32_t  pin  = sam_gpiopin(pinset);
 
   if (value)
     {
@@ -317,17 +317,17 @@ void sam3u_gpiowrite(uint16_t pinset, bool value)
 }
 
 /****************************************************************************
- * Name: sam3u_gpioread
+ * Name: sam_gpioread
  *
  * Description:
  *   Read one or zero from the selected GPIO pin
  *
  ****************************************************************************/
 
-bool sam3u_gpioread(uint16_t pinset)
+bool sam_gpioread(uint16_t pinset)
 {
-  uintptr_t base = sam3u_gpiobase(pinset);
-  uint32_t  pin  = sam3u_gpiopin(pinset);
+  uintptr_t base = sam_gpiobase(pinset);
+  uint32_t  pin  = sam_gpiopin(pinset);
   uint32_t  regval;
 
   if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT)
@@ -343,7 +343,7 @@ bool sam3u_gpioread(uint16_t pinset)
 }
 
 /************************************************************************************
- * Function:  sam3u_dumpgpio
+ * Function:  sam_dumpgpio
  *
  * Description:
  *   Dump all GPIO registers associated with the base address of the provided pinset.
@@ -351,7 +351,7 @@ bool sam3u_gpioread(uint16_t pinset)
  ************************************************************************************/
 
 #ifdef CONFIG_DEBUG_GPIO
-int sam3u_dumpgpio(uint32_t pinset, const char *msg)
+int sam_dumpgpio(uint32_t pinset, const char *msg)
 {
   irqstate_t    flags;
   uintptr_t     base;
@@ -360,7 +360,7 @@ int sam3u_dumpgpio(uint32_t pinset, const char *msg)
 
   /* Get the base address associated with the PIO port */
 
-  pin  = sam3u_gpiopin(pinset);
+  pin  = sam_gpiopin(pinset);
   port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
   base = SAM_PION_BASE(port);
 
diff --git a/nuttx/arch/arm/src/sam3u/sam_gpio.h b/nuttx/arch/arm/src/sam3u/sam_gpio.h
new file mode 100644
index 000000000..2832871e8
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_gpio.h
@@ -0,0 +1,297 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_gpio.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_GPIO_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Configuration ********************************************************************/
+
+#if defined(CONFIG_GPIOA_IRQ) || defined(CONFIG_GPIOB_IRQ) || defined(CONFIG_GPIOC_IRQ)
+#  define CONFIG_GPIO_IRQ 1
+#else
+#  undef CONFIG_GPIO_IRQ
+#endif
+
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_DEBUG_GPIO
+#endif
+
+/* Bit-encoded input to sam_configgpio() ********************************************/
+
+/* 16-bit Encoding:
+ * MMCC CII. VPPB BBBB
+ */
+
+/* Input/Output mode:
+ *
+ * MM.. .... .... ....
+ */
+
+#define GPIO_MODE_SHIFT            (14)        /* Bits 14-15: GPIO mode */
+#define GPIO_MODE_MASK             (3 << GPIO_MODE_SHIFT)
+#  define GPIO_INPUT               (0 << GPIO_MODE_SHIFT) /* Input */
+#  define GPIO_OUTPUT              (1 << GPIO_MODE_SHIFT) /* Output */
+#  define GPIO_PERIPHA             (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
+#  define GPIO_PERIPHB             (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
+
+/* These bits set the configuration of the pin:
+ * ..CC C... .... ....
+ */
+
+#define GPIO_CFG_SHIFT             (11)        /* Bits 11-13: GPIO configuration bits */
+#define GPIO_CFG_MASK              (7 << GPIO_CFG_SHIFT)
+#  define GPIO_CFG_DEFAULT         (0 << GPIO_CFG_SHIFT) /* Default, no attribute */
+#  define GPIO_CFG_PULLUP          (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
+#  define GPIO_CFG_DEGLITCH        (2 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
+#  define GPIO_CFG_OPENDRAIN       (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
+
+/* Additional interrupt modes:
+ * .... .II. .... ....
+ */
+
+#define GPIO_INT_SHIFT             (9)        /* Bits 9-10: GPIO configuration bits */
+#define GPIO_INT_MASK              (3 << GPIO_INT_SHIFT)
+#  define GPIO_INT_LEVEL           (1 << 10)   /* Bit 10: Level detection interrupt */
+#  define GPIO_INT_EDGE            (0)         /*        (vs. Edge detection interrupt) */
+#  define GPIO_INT_HIGHLEVEL       (1 << 9)    /* Bit 9: High level detection interrupt */
+#  define GPIO_INT_LOWLEVEL        (0)         /*        (vs. Low level detection interrupt) */
+#  define GPIO_INT_RISING          (1 << 9)    /* Bit 9: Rising edge detection interrupt */
+#  define GPIO_INT_FALLING         (0)         /*        (vs. Falling edge detection interrupt) */
+
+/* If the pin is an GPIO output, then this identifies the initial output value:
+ * .... .... V... ....
+ */
+
+#define GPIO_OUTPUT_SET            (1 << 7)    /* Bit 7: Inital value of output */
+#define GPIO_OUTPUT_CLEAR          (0)
+
+/* This identifies the GPIO port:
+ * .... .... .PP. ....
+ */
+
+#define GPIO_PORT_SHIFT            (5)         /* Bit 5-6:  Port number */
+#define GPIO_PORT_MASK             (3 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOA           (0 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOB           (1 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_PIOC           (2 << GPIO_PORT_SHIFT)
+
+/* This identifies the bit in the port:
+ * .... .... ...B BBBB
+ */
+
+#define GPIO_PIN_SHIFT             0        /* Bits 0-4: GPIO number: 0-31 */
+#define GPIO_PIN_MASK              (31 << GPIO_PIN_SHIFT)
+#define GPIO_PIN0                  (0  << GPIO_PIN_SHIFT)
+#define GPIO_PIN1                  (1  << GPIO_PIN_SHIFT)
+#define GPIO_PIN2                  (2  << GPIO_PIN_SHIFT)
+#define GPIO_PIN3                  (3  << GPIO_PIN_SHIFT)
+#define GPIO_PIN4                  (4  << GPIO_PIN_SHIFT)
+#define GPIO_PIN5                  (5  << GPIO_PIN_SHIFT)
+#define GPIO_PIN6                  (6  << GPIO_PIN_SHIFT)
+#define GPIO_PIN7                  (7  << GPIO_PIN_SHIFT)
+#define GPIO_PIN8                  (8  << GPIO_PIN_SHIFT)
+#define GPIO_PIN9                  (9  << GPIO_PIN_SHIFT)
+#define GPIO_PIN10                 (10 << GPIO_PIN_SHIFT)
+#define GPIO_PIN11                 (11 << GPIO_PIN_SHIFT)
+#define GPIO_PIN12                 (12 << GPIO_PIN_SHIFT)
+#define GPIO_PIN13                 (13 << GPIO_PIN_SHIFT)
+#define GPIO_PIN14                 (14 << GPIO_PIN_SHIFT)
+#define GPIO_PIN15                 (15 << GPIO_PIN_SHIFT)
+#define GPIO_PIN16                 (16 << GPIO_PIN_SHIFT)
+#define GPIO_PIN17                 (17 << GPIO_PIN_SHIFT)
+#define GPIO_PIN18                 (18 << GPIO_PIN_SHIFT)
+#define GPIO_PIN19                 (19 << GPIO_PIN_SHIFT)
+#define GPIO_PIN20                 (20 << GPIO_PIN_SHIFT)
+#define GPIO_PIN21                 (21 << GPIO_PIN_SHIFT)
+#define GPIO_PIN22                 (22 << GPIO_PIN_SHIFT)
+#define GPIO_PIN23                 (23 << GPIO_PIN_SHIFT)
+#define GPIO_PIN24                 (24 << GPIO_PIN_SHIFT)
+#define GPIO_PIN25                 (25 << GPIO_PIN_SHIFT)
+#define GPIO_PIN26                 (26 << GPIO_PIN_SHIFT)
+#define GPIO_PIN27                 (27 << GPIO_PIN_SHIFT)
+#define GPIO_PIN28                 (28 << GPIO_PIN_SHIFT)
+#define GPIO_PIN29                 (29 << GPIO_PIN_SHIFT)
+#define GPIO_PIN30                 (30 << GPIO_PIN_SHIFT)
+#define GPIO_PIN31                 (31 << GPIO_PIN_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: sam_gpioirqinitialize
+ *
+ * Description:
+ *   Initialize logic to support a second level of interrupt decoding for GPIO pins.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+void sam_gpioirqinitialize(void);
+#else
+#  define sam_gpioirqinitialize()
+#endif
+
+/************************************************************************************
+ * Name: sam_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ************************************************************************************/
+
+int sam_configgpio(uint16_t cfgset);
+
+/************************************************************************************
+ * Name: sam_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ************************************************************************************/
+
+void sam_gpiowrite(uint16_t pinset, bool value);
+
+/************************************************************************************
+ * Name: sam_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ************************************************************************************/
+
+bool sam_gpioread(uint16_t pinset);
+
+/************************************************************************************
+ * Name: sam_gpioirq
+ *
+ * Description:
+ *   Configure an interrupt for the specified GPIO pin.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+void sam_gpioirq(uint16_t pinset);
+#else
+#  define sam_gpioirq(pinset)
+#endif
+
+/************************************************************************************
+ * Name: sam_gpioirqenable
+ *
+ * Description:
+ *   Enable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+void sam_gpioirqenable(int irq);
+#else
+#  define sam_gpioirqenable(irq)
+#endif
+
+/************************************************************************************
+ * Name: sam_gpioirqdisable
+ *
+ * Description:
+ *   Disable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+void sam_gpioirqdisable(int irq);
+#else
+#  define sam_gpioirqdisable(irq)
+#endif
+
+/************************************************************************************
+ * Function:  sam_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided pinset.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO
+int sam_dumpgpio(uint32_t pinset, const char *msg);
+#else
+#  define sam_dumpgpio(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_GPIO_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_gpioirq.c b/nuttx/arch/arm/src/sam3u/sam_gpioirq.c
index a08c4e754..58a5252a4 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_gpioirq.c
+++ b/nuttx/arch/arm/src/sam3u/sam_gpioirq.c
@@ -1,8 +1,7 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_gpioirq.c
- * arch/arm/src/chip/sam3u_gpioirq.c
+ * arch/arm/src/sam3u/sam_gpioirq.c
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -54,7 +53,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "sam3u_internal.h"
+#include "sam_gpio.h"
 #include "chip/sam_pio.h"
 #include "chip/sam_pmc.h"
 
@@ -77,41 +76,41 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_gpiobase
+ * Name: sam_gpiobase
  *
  * Description:
  *   Return the base address of the GPIO register set
  *
  ****************************************************************************/
 
-static inline uint32_t sam3u_gpiobase(uint16_t pinset)
+static inline uint32_t sam_gpiobase(uint16_t pinset)
 {
   int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
   return SAM_PION_BASE(port >> GPIO_PORT_SHIFT);
 }
 
 /****************************************************************************
- * Name: sam3u_gpiopin
+ * Name: sam_gpiopin
  *
  * Description:
  *   Returun the base address of the GPIO register set
  *
  ****************************************************************************/
 
-static inline int sam3u_gpiopin(uint16_t pinset)
+static inline int sam_gpiopin(uint16_t pinset)
 {
   return 1 << ((pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
 }
 
 /****************************************************************************
- * Name: sam3u_irqbase
+ * Name: sam_irqbase
  *
  * Description:
  *   Return gpio information associated with this IRQ
  *
  ****************************************************************************/
 
-static int sam3u_irqbase(int irq, uint32_t *base, int *pin)
+static int sam_irqbase(int irq, uint32_t *base, int *pin)
 {
   if (irq >= SAM_IRQ_NIRQS)
     {
@@ -200,7 +199,7 @@ static int up_gpiocinterrupt(int irq, void *context)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_gpioirqinitialize
+ * Name: sam_gpioirqinitialize
  *
  * Description:
  *   Initialize logic to support a second level of interrupt decoding for
@@ -208,7 +207,7 @@ static int up_gpiocinterrupt(int irq, void *context)
  *
  ****************************************************************************/
 
-void sam3u_gpioirqinitialize(void)
+void sam_gpioirqinitialize(void)
 {
   uint32_t pcer;
 
@@ -271,17 +270,17 @@ void sam3u_gpioirqinitialize(void)
 }
 
 /************************************************************************************
- * Name: sam3u_gpioirq
+ * Name: sam_gpioirq
  *
  * Description:
  *   Configure an interrupt for the specified GPIO pin.
  *
  ************************************************************************************/
 
-void sam3u_gpioirq(uint16_t pinset)
+void sam_gpioirq(uint16_t pinset)
 {
-  uint32_t base = sam3u_gpiobase(pinset);
-  int      pin  = sam3u_gpiopin(pinset);
+  uint32_t base = sam_gpiobase(pinset);
+  int      pin  = sam_gpiopin(pinset);
 
    /* Are any additional interrupt modes selected? */
 
@@ -322,19 +321,19 @@ void sam3u_gpioirq(uint16_t pinset)
 }
 
 /************************************************************************************
- * Name: sam3u_gpioirqenable
+ * Name: sam_gpioirqenable
  *
  * Description:
  *   Enable the interrupt for specified GPIO IRQ
  *
  ************************************************************************************/
 
-void sam3u_gpioirqenable(int irq)
+void sam_gpioirqenable(int irq)
 {
   uint32_t base;
   int      pin;
 
-  if (sam3u_irqbase(irq, &base, &pin) == OK)
+  if (sam_irqbase(irq, &base, &pin) == OK)
     {
        /* Clear (all) pending interrupts and enable this pin interrupt */
 
@@ -344,19 +343,19 @@ void sam3u_gpioirqenable(int irq)
 }
 
 /************************************************************************************
- * Name: sam3u_gpioirqdisable
+ * Name: sam_gpioirqdisable
  *
  * Description:
  *   Disable the interrupt for specified GPIO IRQ
  *
  ************************************************************************************/
 
-void sam3u_gpioirqdisable(int irq)
+void sam_gpioirqdisable(int irq)
 {
   uint32_t base;
   int      pin;
 
-  if (sam3u_irqbase(irq, &base, &pin) == OK)
+  if (sam_irqbase(irq, &base, &pin) == OK)
     {
        /* Disable this pin interrupt */
 
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_hsmci.c b/nuttx/arch/arm/src/sam3u/sam_hsmci.c
index ce1191e0f..1737faa41 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_hsmci.c
+++ b/nuttx/arch/arm/src/sam3u/sam_hsmci.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_sdio.c
+ * arch/arm/src/sam3u/sam_hsmci.c
  *
  *   Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -60,10 +60,13 @@
 #include "chip.h"
 #include "up_arch.h"
 
-#include "sam3u_internal.h"
+#include "sam_gpio.h"
+#include "sam_dmac.h"
+#include "sam_hsmci.h"
 #include "chip/sam_dmac.h"
 #include "chip/sam_pmc.h"
 #include "chip/sam_hsmci.h"
+#include "chip/sam_pinmap.h"
 
 #if CONFIG_SAM34_HSMCI
 
@@ -252,7 +255,7 @@
 
 /* This structure defines the state of the SAM3/4 HSMCI interface */
 
-struct sam3u_dev_s
+struct sam_dev_s
 {
   struct sdio_dev_s  dev;        /* Standard, base SDIO interface */
 
@@ -287,7 +290,7 @@ struct sam3u_dev_s
 /* Register logging support */
 
 #if defined(CONFIG_HSMCI_XFRDEBUG) || defined(CONFIG_HSMCI_CMDDEBUG)
-struct sam3u_hsmciregs_s
+struct sam_hsmciregs_s
 {
   uint32_t mr;    /* Mode Register */
   uint32_t dtor;  /* Data Timeout Register */
@@ -309,11 +312,11 @@ struct sam3u_hsmciregs_s
 #endif
 
 #ifdef CONFIG_HSMCI_XFRDEBUG
-struct sam3u_xfrregs_s
+struct sam_xfrregs_s
 {
-  struct sam3u_hsmciregs_s hsmci;
+  struct sam_hsmciregs_s hsmci;
 #ifdef CONFIG_DEBUG_DMA
-  struct sam3u_dmaregs_s  dma;
+  struct sam_dmaregs_s  dma;
 #endif
 };
 #endif
@@ -324,147 +327,147 @@ struct sam3u_xfrregs_s
 
 /* Low-level helpers ********************************************************/
 
-static void sam3u_takesem(struct sam3u_dev_s *priv);
-#define     sam3u_givesem(priv) (sem_post(&priv->waitsem))
-static void sam3u_enablewaitints(struct sam3u_dev_s *priv, uint32_t waitmask,
+static void sam_takesem(struct sam_dev_s *priv);
+#define     sam_givesem(priv) (sem_post(&priv->waitsem))
+static void sam_enablewaitints(struct sam_dev_s *priv, uint32_t waitmask,
               sdio_eventset_t waitevents);
-static void sam3u_disablewaitints(struct sam3u_dev_s *priv, sdio_eventset_t wkupevents);
-static void sam3u_enablexfrints(struct sam3u_dev_s *priv, uint32_t xfrmask);
-static void sam3u_disablexfrints(struct sam3u_dev_s *priv);
-static inline void sam3u_disable(void);
-static inline void sam3u_enable(void);
+static void sam_disablewaitints(struct sam_dev_s *priv, sdio_eventset_t wkupevents);
+static void sam_enablexfrints(struct sam_dev_s *priv, uint32_t xfrmask);
+static void sam_disablexfrints(struct sam_dev_s *priv);
+static inline void sam_disable(void);
+static inline void sam_enable(void);
 
 /* Register Sampling ********************************************************/
 
 #if defined(CONFIG_HSMCI_XFRDEBUG) || defined(CONFIG_HSMCI_CMDDEBUG)
-static void sam3u_hsmcisample(struct sam3u_hsmciregs_s *regs);
-static void sam3u_hsmcidump(struct sam3u_hsmciregs_s *regs, const char *msg);
+static void sam_hsmcisample(struct sam_hsmciregs_s *regs);
+static void sam_hsmcidump(struct sam_hsmciregs_s *regs, const char *msg);
 #endif
 
 #ifdef CONFIG_HSMCI_XFRDEBUG
-static void sam3u_xfrsampleinit(void);
-static void sam3u_xfrsample(struct sam3u_dev_s *priv, int index);
-static void sam3u_xfrdumpone(struct sam3u_dev_s *priv,
-              struct sam3u_xfrregs_s *regs, const char *msg);
-static void sam3u_xfrdump(struct sam3u_dev_s *priv);
+static void sam_xfrsampleinit(void);
+static void sam_xfrsample(struct sam_dev_s *priv, int index);
+static void sam_xfrdumpone(struct sam_dev_s *priv,
+              struct sam_xfrregs_s *regs, const char *msg);
+static void sam_xfrdump(struct sam_dev_s *priv);
 #else
-#  define   sam3u_xfrsampleinit()
-#  define   sam3u_xfrsample(priv,index)
-#  define   sam3u_xfrdump(priv)
+#  define   sam_xfrsampleinit()
+#  define   sam_xfrsample(priv,index)
+#  define   sam_xfrdump(priv)
 #endif
 
 #ifdef CONFIG_HSMCI_CMDDEBUG
-static void sam3u_cmdsampleinit(void);
-static inline void sam3u_cmdsample1(int index3);
-static inline void sam3u_cmdsample2(int index, uint32_t sr);
-static void sam3u_cmddump(void);
+static void sam_cmdsampleinit(void);
+static inline void sam_cmdsample1(int index3);
+static inline void sam_cmdsample2(int index, uint32_t sr);
+static void sam_cmddump(void);
 #else
-#  define   sam3u_cmdsampleinit()
-#  define   sam3u_cmdsample1(index)
-#  define   sam3u_cmdsample2(index,sr)
-#  define   sam3u_cmddump()
+#  define   sam_cmdsampleinit()
+#  define   sam_cmdsample1(index)
+#  define   sam_cmdsample2(index,sr)
+#  define   sam_cmddump()
 #endif
 
 /* DMA Helpers **************************************************************/
 
-static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result);
+static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result);
 
 /* Data Transfer Helpers ****************************************************/
 
-static void sam3u_eventtimeout(int argc, uint32_t arg);
-static void sam3u_endwait(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent);
-static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent);
-static void sam3u_notransfer(struct sam3u_dev_s *priv);
+static void sam_eventtimeout(int argc, uint32_t arg);
+static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent);
+static void sam_endtransfer(struct sam_dev_s *priv, sdio_eventset_t wkupevent);
+static void sam_notransfer(struct sam_dev_s *priv);
 
 /* Interrupt Handling *******************************************************/
 
-static int  sam3u_interrupt(int irq, void *context);
+static int  sam_interrupt(int irq, void *context);
 
 /* SDIO interface methods ***************************************************/
 
 /* Initialization/setup */
 
-static void sam3u_reset(FAR struct sdio_dev_s *dev);
-static uint8_t sam3u_status(FAR struct sdio_dev_s *dev);
-static void sam3u_widebus(FAR struct sdio_dev_s *dev, bool enable);
-static void sam3u_clock(FAR struct sdio_dev_s *dev,
+static void sam_reset(FAR struct sdio_dev_s *dev);
+static uint8_t sam_status(FAR struct sdio_dev_s *dev);
+static void sam_widebus(FAR struct sdio_dev_s *dev, bool enable);
+static void sam_clock(FAR struct sdio_dev_s *dev,
               enum sdio_clock_e rate);
-static int  sam3u_attach(FAR struct sdio_dev_s *dev);
+static int  sam_attach(FAR struct sdio_dev_s *dev);
 
 /* Command/Status/Data Transfer */
 
-static int  sam3u_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
+static int  sam_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
               uint32_t arg);
-static void sam3u_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
+static void sam_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
               unsigned int nblocks);
-static int  sam3u_cancel(FAR struct sdio_dev_s *dev);
-static int  sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd);
-static int  sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
+static int  sam_cancel(FAR struct sdio_dev_s *dev);
+static int  sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd);
+static int  sam_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
               uint32_t *rshort);
-static int  sam3u_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
+static int  sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
               uint32_t rlong[4]);
-static int  sam3u_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd,
+static int  sam_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd,
               uint32_t *rnotimpl);
 
 /* EVENT handler */
 
-static void sam3u_waitenable(FAR struct sdio_dev_s *dev,
+static void sam_waitenable(FAR struct sdio_dev_s *dev,
               sdio_eventset_t eventset);
 static sdio_eventset_t
-            sam3u_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout);
-static void sam3u_callbackenable(FAR struct sdio_dev_s *dev,
+            sam_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout);
+static void sam_callbackenable(FAR struct sdio_dev_s *dev,
               sdio_eventset_t eventset);
-static int  sam3u_registercallback(FAR struct sdio_dev_s *dev,
+static int  sam_registercallback(FAR struct sdio_dev_s *dev,
               worker_t callback, void *arg);
 
 /* DMA */
 
 #ifdef CONFIG_SDIO_DMA
-static bool sam3u_dmasupported(FAR struct sdio_dev_s *dev);
+static bool sam_dmasupported(FAR struct sdio_dev_s *dev);
 #endif
-static int  sam3u_dmarecvsetup(FAR struct sdio_dev_s *dev,
+static int  sam_dmarecvsetup(FAR struct sdio_dev_s *dev,
               FAR uint8_t *buffer, size_t buflen);
-static int  sam3u_dmasendsetup(FAR struct sdio_dev_s *dev,
+static int  sam_dmasendsetup(FAR struct sdio_dev_s *dev,
               FAR const uint8_t *buffer, size_t buflen);
 
 /* Initialization/uninitialization/reset ************************************/
 
-static void sam3u_callback(void *arg);
+static void sam_callback(void *arg);
 
 /****************************************************************************
  * Private Data
  ****************************************************************************/
 
-struct sam3u_dev_s g_sdiodev =
+struct sam_dev_s g_sdiodev =
 {
   .dev =
   {
-    .reset            = sam3u_reset,
-    .status           = sam3u_status,
-    .widebus          = sam3u_widebus,
-    .clock            = sam3u_clock,
-    .attach           = sam3u_attach,
-    .sendcmd          = sam3u_sendcmd,
-    .blocksetup       = sam3u_blocksetup,
-    .recvsetup        = sam3u_dmarecvsetup,
-    .sendsetup        = sam3u_dmasendsetup,
-    .cancel           = sam3u_cancel,
-    .waitresponse     = sam3u_waitresponse,
-    .recvR1           = sam3u_recvshort,
-    .recvR2           = sam3u_recvlong,
-    .recvR3           = sam3u_recvshort,
-    .recvR4           = sam3u_recvnotimpl,
-    .recvR5           = sam3u_recvnotimpl,
-    .recvR6           = sam3u_recvshort,
-    .recvR7           = sam3u_recvshort,
-    .waitenable       = sam3u_waitenable,
-    .eventwait        = sam3u_eventwait,
-    .callbackenable   = sam3u_callbackenable,
-    .registercallback = sam3u_registercallback,
+    .reset            = sam_reset,
+    .status           = sam_status,
+    .widebus          = sam_widebus,
+    .clock            = sam_clock,
+    .attach           = sam_attach,
+    .sendcmd          = sam_sendcmd,
+    .blocksetup       = sam_blocksetup,
+    .recvsetup        = sam_dmarecvsetup,
+    .sendsetup        = sam_dmasendsetup,
+    .cancel           = sam_cancel,
+    .waitresponse     = sam_waitresponse,
+    .recvR1           = sam_recvshort,
+    .recvR2           = sam_recvlong,
+    .recvR3           = sam_recvshort,
+    .recvR4           = sam_recvnotimpl,
+    .recvR5           = sam_recvnotimpl,
+    .recvR6           = sam_recvshort,
+    .recvR7           = sam_recvshort,
+    .waitenable       = sam_waitenable,
+    .eventwait        = sam_eventwait,
+    .callbackenable   = sam_callbackenable,
+    .registercallback = sam_registercallback,
 #ifdef CONFIG_SDIO_DMA
-    .dmasupported     = sam3u_dmasupported,
-    .dmarecvsetup     = sam3u_dmarecvsetup,
-    .dmasendsetup     = sam3u_dmasendsetup,
+    .dmasupported     = sam_dmasupported,
+    .dmarecvsetup     = sam_dmarecvsetup,
+    .dmasendsetup     = sam_dmasendsetup,
 #endif
   },
 };
@@ -472,10 +475,10 @@ struct sam3u_dev_s g_sdiodev =
 /* Register logging support */
 
 #ifdef CONFIG_HSMCI_XFRDEBUG
-static struct sam3u_xfrregs_s   g_xfrsamples[DEBUG_NDMASAMPLES];
+static struct sam_xfrregs_s   g_xfrsamples[DEBUG_NDMASAMPLES];
 #endif
 #ifdef CONFIG_HSMCI_CMDDEBUG
-static struct sam3u_hsmciregs_s g_cmdsamples[DEBUG_NCMDSAMPLES];
+static struct sam_hsmciregs_s g_cmdsamples[DEBUG_NCMDSAMPLES];
 #endif
 #if defined(CONFIG_HSMCI_XFRDEBUG) && defined(CONFIG_HSMCI_CMDDEBUG)
 static bool                     g_xfrinitialized;
@@ -490,7 +493,7 @@ static bool                     g_cmdinitialized;
  * Low-level Helpers
  ****************************************************************************/
 /****************************************************************************
- * Name: sam3u_takesem
+ * Name: sam_takesem
  *
  * Description:
  *   Take the wait semaphore (handling false alarm wakeups due to the receipt
@@ -504,7 +507,7 @@ static bool                     g_cmdinitialized;
  *
  ****************************************************************************/
 
-static void sam3u_takesem(struct sam3u_dev_s *priv)
+static void sam_takesem(struct sam_dev_s *priv)
 {
   /* Take the semaphore (perhaps waiting) */
 
@@ -519,7 +522,7 @@ static void sam3u_takesem(struct sam3u_dev_s *priv)
 }
 
 /****************************************************************************
- * Name: sam3u_enablewaitints
+ * Name: sam_enablewaitints
  *
  * Description:
  *   Enable HSMCI interrupts needed to suport the wait function
@@ -534,8 +537,8 @@ static void sam3u_takesem(struct sam3u_dev_s *priv)
  *
  ****************************************************************************/
 
-static void sam3u_enablewaitints(struct sam3u_dev_s *priv, uint32_t waitmask,
-                                 sdio_eventset_t waitevents)
+static void sam_enablewaitints(struct sam_dev_s *priv, uint32_t waitmask,
+                               sdio_eventset_t waitevents)
 {
   irqstate_t flags;
 
@@ -552,7 +555,7 @@ static void sam3u_enablewaitints(struct sam3u_dev_s *priv, uint32_t waitmask,
 }
 
 /****************************************************************************
- * Name: sam3u_disablewaitints
+ * Name: sam_disablewaitints
  *
  * Description:
  *   Disable HSMCI interrupts and save wakeup event.  Called
@@ -566,8 +569,8 @@ static void sam3u_enablewaitints(struct sam3u_dev_s *priv, uint32_t waitmask,
  *
  ****************************************************************************/
 
-static void sam3u_disablewaitints(struct sam3u_dev_s *priv,
-                                  sdio_eventset_t wkupevent)
+static void sam_disablewaitints(struct sam_dev_s *priv,
+                                sdio_eventset_t wkupevent)
 {
   irqstate_t flags;
 
@@ -584,7 +587,7 @@ static void sam3u_disablewaitints(struct sam3u_dev_s *priv,
 }
 
 /****************************************************************************
- * Name: sam3u_enablexfrints
+ * Name: sam_enablexfrints
  *
  * Description:
  *   Enable HSMCI interrupts needed to support the data transfer event
@@ -598,7 +601,7 @@ static void sam3u_disablewaitints(struct sam3u_dev_s *priv,
  *
  ****************************************************************************/
 
-static void sam3u_enablexfrints(struct sam3u_dev_s *priv, uint32_t xfrmask)
+static void sam_enablexfrints(struct sam_dev_s *priv, uint32_t xfrmask)
 {
   irqstate_t flags = irqsave();
   priv->xfrmask = xfrmask;
@@ -607,7 +610,7 @@ static void sam3u_enablexfrints(struct sam3u_dev_s *priv, uint32_t xfrmask)
 }
 
 /****************************************************************************
- * Name: sam3u_disablexfrints
+ * Name: sam_disablexfrints
  *
  * Description:
  *   Disable HSMCI interrupts needed to support the data transfer event
@@ -621,7 +624,7 @@ static void sam3u_enablexfrints(struct sam3u_dev_s *priv, uint32_t xfrmask)
  *
  ****************************************************************************/
 
-static void sam3u_disablexfrints(struct sam3u_dev_s *priv)
+static void sam_disablexfrints(struct sam_dev_s *priv)
 {
   irqstate_t flags = irqsave();
   priv->xfrmask = 0;
@@ -630,14 +633,14 @@ static void sam3u_disablexfrints(struct sam3u_dev_s *priv)
 }
 
 /****************************************************************************
- * Name: sam3u_disable
+ * Name: sam_disable
  *
  * Description:
  *   Disable the HSMCI
  *
  ****************************************************************************/
 
-static inline void sam3u_disable(void)
+static inline void sam_disable(void)
 {
   /* Disable the MCI peripheral clock */
 
@@ -653,14 +656,14 @@ static inline void sam3u_disable(void)
 }
 
 /****************************************************************************
- * Name: sam3u_enable
+ * Name: sam_enable
  *
  * Description:
  *   Enable the HSMCI
  *
  ****************************************************************************/
 
-static inline void sam3u_enable(void)
+static inline void sam_enable(void)
 {
   /* Enable the MCI peripheral clock */
 
@@ -676,7 +679,7 @@ static inline void sam3u_enable(void)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_hsmcisample
+ * Name: sam_hsmcisample
  *
  * Description:
  *   Sample HSMCI registers
@@ -684,7 +687,7 @@ static inline void sam3u_enable(void)
  ****************************************************************************/
 
 #if defined(CONFIG_HSMCI_XFRDEBUG) || defined(CONFIG_HSMCI_CMDDEBUG)
-static void sam3u_hsmcisample(struct sam3u_hsmciregs_s *regs)
+static void sam_hsmcisample(struct sam_hsmciregs_s *regs)
 {
   regs->mr    = getreg32(SAM_HSMCI_MR);
   regs->dtor  = getreg32(SAM_HSMCI_DTOR);
@@ -706,7 +709,7 @@ static void sam3u_hsmcisample(struct sam3u_hsmciregs_s *regs)
 #endif
 
 /****************************************************************************
- * Name: sam3u_hsmcidump
+ * Name: sam_hsmcidump
  *
  * Description:
  *   Dump one register sample
@@ -714,7 +717,7 @@ static void sam3u_hsmcisample(struct sam3u_hsmciregs_s *regs)
  ****************************************************************************/
 
 #if defined(CONFIG_HSMCI_XFRDEBUG) || defined(CONFIG_HSMCI_CMDDEBUG)
-static void sam3u_hsmcidump(struct sam3u_hsmciregs_s *regs, const char *msg)
+static void sam_hsmcidump(struct sam_hsmciregs_s *regs, const char *msg)
 {
   fdbg("HSMCI Registers: %s\n", msg);
   fdbg("     MR[%08x]: %08x\n", SAM_HSMCI_MR,    regs->mr);
@@ -737,7 +740,7 @@ static void sam3u_hsmcidump(struct sam3u_hsmciregs_s *regs, const char *msg)
 #endif
 
 /****************************************************************************
- * Name: sam3u_xfrsample
+ * Name: sam_xfrsample
  *
  * Description:
  *   Sample HSMCI/DMA registers
@@ -745,18 +748,18 @@ static void sam3u_hsmcidump(struct sam3u_hsmciregs_s *regs, const char *msg)
  ****************************************************************************/
 
 #ifdef CONFIG_HSMCI_XFRDEBUG
-static void sam3u_xfrsample(struct sam3u_dev_s *priv, int index)
+static void sam_xfrsample(struct sam_dev_s *priv, int index)
 {
-  struct sam3u_xfrregs_s *regs = &g_xfrsamples[index];
+  struct sam_xfrregs_s *regs = &g_xfrsamples[index];
 #ifdef CONFIG_DEBUG_DMA
-  sam3u_dmasample(priv->dma, &regs->dma);
+  sam_dmasample(priv->dma, &regs->dma);
 #endif
-  sam3u_hsmcisample(&regs->hsmci);
+  sam_hsmcisample(&regs->hsmci);
 }
 #endif
 
 /****************************************************************************
- * Name: sam3u_xfrsampleinit
+ * Name: sam_xfrsampleinit
  *
  * Description:
  *   Setup prior to collecting transfer samples
@@ -764,9 +767,9 @@ static void sam3u_xfrsample(struct sam3u_dev_s *priv, int index)
  ****************************************************************************/
 
 #ifdef CONFIG_HSMCI_XFRDEBUG
-static void sam3u_xfrsampleinit(void)
+static void sam_xfrsampleinit(void)
 {
-  memset(g_xfrsamples, 0xff, DEBUG_NDMASAMPLES * sizeof(struct sam3u_xfrregs_s));
+  memset(g_xfrsamples, 0xff, DEBUG_NDMASAMPLES * sizeof(struct sam_xfrregs_s));
 #ifdef CONFIG_HSMCI_CMDDEBUG
   g_xfrinitialized = true;
 #endif
@@ -774,7 +777,7 @@ static void sam3u_xfrsampleinit(void)
 #endif
 
 /****************************************************************************
- * Name: sam3u_xfrdumpone
+ * Name: sam_xfrdumpone
  *
  * Description:
  *   Dump one transfer register sample
@@ -782,18 +785,18 @@ static void sam3u_xfrsampleinit(void)
  ****************************************************************************/
 
 #ifdef CONFIG_HSMCI_XFRDEBUG
-static void sam3u_xfrdumpone(struct sam3u_dev_s *priv,
-                             struct sam3u_xfrregs_s *regs, const char *msg)
+static void sam_xfrdumpone(struct sam_dev_s *priv,
+                           struct sam_xfrregs_s *regs, const char *msg)
 {
 #ifdef CONFIG_DEBUG_DMA
-  sam3u_dmadump(priv->dma, &regs->dma, msg);
+  sam_dmadump(priv->dma, &regs->dma, msg);
 #endif
-  sam3u_hsmcidump(&regs->hsmci, msg);
+  sam_hsmcidump(&regs->hsmci, msg);
 }
 #endif
 
 /****************************************************************************
- * Name: sam3u_xfrdump
+ * Name: sam_xfrdump
  *
  * Description:
  *   Dump all transfer-related, sampled register data
@@ -801,20 +804,20 @@ static void sam3u_xfrdumpone(struct sam3u_dev_s *priv,
  ****************************************************************************/
 
 #ifdef CONFIG_HSMCI_XFRDEBUG
-static void  sam3u_xfrdump(struct sam3u_dev_s *priv)
+static void  sam_xfrdump(struct sam_dev_s *priv)
 {
 #ifdef CONFIG_HSMCI_CMDDEBUG
   if (g_xfrinitialized)
 #endif
     {
-      sam3u_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_BEFORE_SETUP], "Before setup");
+      sam_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_BEFORE_SETUP], "Before setup");
 #ifdef CONFIG_DEBUG_DMA
-      sam3u_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable");
+      sam_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable");
 #endif
-      sam3u_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_AFTER_SETUP], "After setup");
-      sam3u_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_END_TRANSFER], "End of transfer");
+      sam_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_AFTER_SETUP], "After setup");
+      sam_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_END_TRANSFER], "End of transfer");
 #ifdef CONFIG_DEBUG_DMA
-      sam3u_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_DMA_CALLBACK], "DMA Callback");
+      sam_xfrdumpone(priv, &g_xfrsamples[SAMPLENDX_DMA_CALLBACK], "DMA Callback");
 #endif
 #ifdef CONFIG_HSMCI_CMDDEBUG
       g_xfrinitialized = false;
@@ -824,7 +827,7 @@ static void  sam3u_xfrdump(struct sam3u_dev_s *priv)
 #endif
 
 /****************************************************************************
- * Name: sam3u_cmdsampleinit
+ * Name: sam_cmdsampleinit
  *
  * Description:
  *   Setup prior to collecting command/response samples
@@ -832,9 +835,9 @@ static void  sam3u_xfrdump(struct sam3u_dev_s *priv)
  ****************************************************************************/
 
 #ifdef CONFIG_HSMCI_CMDDEBUG
-static void sam3u_cmdsampleinit(void)
+static void sam_cmdsampleinit(void)
 {
-  memset(g_cmdsamples, 0xff, DEBUG_NCMDSAMPLES * sizeof(struct sam3u_hsmciregs_s));
+  memset(g_cmdsamples, 0xff, DEBUG_NCMDSAMPLES * sizeof(struct sam_hsmciregs_s));
 #ifdef CONFIG_HSMCI_XFRDEBUG
   g_cmdinitialized = true;
 #endif
@@ -842,7 +845,7 @@ static void sam3u_cmdsampleinit(void)
 #endif
 
 /****************************************************************************
- * Name: sam3u_cmdsample1 & 2
+ * Name: sam_cmdsample1 & 2
  *
  * Description:
  *   Sample command/response registers
@@ -850,20 +853,20 @@ static void sam3u_cmdsampleinit(void)
  ****************************************************************************/
 
 #ifdef CONFIG_HSMCI_CMDDEBUG
-static inline void sam3u_cmdsample1(int index)
+static inline void sam_cmdsample1(int index)
 {
-  sam3u_hsmcisample(&g_cmdsamples[index]);
+  sam_hsmcisample(&g_cmdsamples[index]);
 }
 
-static inline void sam3u_cmdsample2(int index, uint32_t sr)
+static inline void sam_cmdsample2(int index, uint32_t sr)
 {
-  sam3u_hsmcisample(&g_cmdsamples[index]);
+  sam_hsmcisample(&g_cmdsamples[index]);
   g_cmdsamples[index].sr = sr;
 }
 #endif
 
 /****************************************************************************
- * Name: sam3u_cmddump
+ * Name: sam_cmddump
  *
  * Description:
  *   Dump all comand/response register data
@@ -871,14 +874,14 @@ static inline void sam3u_cmdsample2(int index, uint32_t sr)
  ****************************************************************************/
 
 #ifdef CONFIG_HSMCI_CMDDEBUG
-static void sam3u_cmddump(void)
+static void sam_cmddump(void)
 {
 #ifdef CONFIG_HSMCI_XFRDEBUG
   if (g_cmdinitialized)
 #endif
     {
-      sam3u_hsmcidump(&g_cmdsamples[SAMPLENDX_AFTER_CMDR], "After command setup");
-      sam3u_hsmcidump(&g_cmdsamples[SAMPLENDX_AT_WAKEUP],  "After wakeup");
+      sam_hsmcidump(&g_cmdsamples[SAMPLENDX_AFTER_CMDR], "After command setup");
+      sam_hsmcidump(&g_cmdsamples[SAMPLENDX_AT_WAKEUP],  "After wakeup");
 #ifdef CONFIG_HSMCI_XFRDEBUG
       g_cmdinitialized = false;
 #endif
@@ -891,20 +894,20 @@ static void sam3u_cmddump(void)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_dmacallback
+ * Name: sam_dmacallback
  *
  * Description:
  *   Called when HSMCI DMA completes
  *
  ****************************************************************************/
 
-static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result)
+static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
 {
   /* We don't really do anything at the completion of DMA.  The termination
    * of the transfer is driven by the HSMCI interrupts.
    */
 
-  sam3u_xfrsample((struct sam3u_dev_s*)arg, SAMPLENDX_DMA_CALLBACK);
+  sam_xfrsample((struct sam_dev_s*)arg, SAMPLENDX_DMA_CALLBACK);
 }
 
 /****************************************************************************
@@ -912,7 +915,7 @@ static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_eventtimeout
+ * Name: sam_eventtimeout
  *
  * Description:
  *   The watchdog timeout setup when the event wait start has expired without
@@ -930,9 +933,9 @@ static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result)
  *
  ****************************************************************************/
 
-static void sam3u_eventtimeout(int argc, uint32_t arg)
+static void sam_eventtimeout(int argc, uint32_t arg)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s *)arg;
+  struct sam_dev_s *priv = (struct sam_dev_s *)arg;
 
   DEBUGASSERT(argc == 1 && priv != NULL);
   DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0);
@@ -943,13 +946,13 @@ static void sam3u_eventtimeout(int argc, uint32_t arg)
     {
       /* Yes.. wake up any waiting threads */
 
-      sam3u_endwait(priv, SDIOWAIT_TIMEOUT);
+      sam_endwait(priv, SDIOWAIT_TIMEOUT);
       flldbg("Timeout\n");
     }
 }
 
 /****************************************************************************
- * Name: sam3u_endwait
+ * Name: sam_endwait
  *
  * Description:
  *   Wake up a waiting thread if the waited-for event has occurred.
@@ -966,7 +969,7 @@ static void sam3u_eventtimeout(int argc, uint32_t arg)
  *
  ****************************************************************************/
 
-static void sam3u_endwait(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent)
+static void sam_endwait(struct sam_dev_s *priv, sdio_eventset_t wkupevent)
 {
   /* Cancel the watchdog timeout */
 
@@ -974,15 +977,15 @@ static void sam3u_endwait(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent)
 
   /* Disable event-related interrupts and save wakeup event */
 
-  sam3u_disablewaitints(priv, wkupevent);
+  sam_disablewaitints(priv, wkupevent);
 
   /* Wake up the waiting thread */
 
-  sam3u_givesem(priv);
+  sam_givesem(priv);
 }
 
 /****************************************************************************
- * Name: sam3u_endtransfer
+ * Name: sam_endtransfer
  *
  * Description:
  *   Terminate a transfer with the provided status.  This function is called
@@ -1001,26 +1004,27 @@ static void sam3u_endwait(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent)
  *
  ****************************************************************************/
 
-static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent)
+static void sam_endtransfer(struct sam_dev_s *priv,
+                            sdio_eventset_t wkupevent)
 {
   /* Disable all transfer related interrupts */
 
-  sam3u_disablexfrints(priv);
+  sam_disablexfrints(priv);
 
   /* No data transfer */
 
-  sam3u_notransfer(priv);
+  sam_notransfer(priv);
 
   /* DMA debug instrumentation */
 
-  sam3u_xfrsample(priv, SAMPLENDX_END_TRANSFER);
+  sam_xfrsample(priv, SAMPLENDX_END_TRANSFER);
 
   /* Make sure that the DMA is stopped (it will be stopped automatically
    * on normal transfers, but not necessarily when the transfer terminates
    * on an error condition.
    */
 
-  sam3u_dmastop(priv->dma);
+  sam_dmastop(priv->dma);
 
   /* Disable the DMA handshaking */
 
@@ -1032,16 +1036,16 @@ static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupeven
     {
       /* Yes.. wake up any waiting threads */
 
-      sam3u_endwait(priv, wkupevent);
+      sam_endwait(priv, wkupevent);
     }
 }
 
 /****************************************************************************
- * Name: sam3u_notransfer
+ * Name: sam_notransfer
  *
  * Description:
  *   Setup for no transfer.  This is the default setup that is overriddden
- *   by sam3u_dmarecvsetup or sam3u_dmasendsetup
+ *   by sam_dmarecvsetup or sam_dmasendsetup
  *
  * Input Parameters:
  *   priv   - An instance of the HSMCI device interface
@@ -1051,7 +1055,7 @@ static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupeven
  *
  ****************************************************************************/
 
-static void sam3u_notransfer(struct sam3u_dev_s *priv)
+static void sam_notransfer(struct sam_dev_s *priv)
 {
   uint32_t regval = getreg32(SAM_HSMCI_MR);
   regval &= ~(HSMCI_MR_RDPROOF | HSMCI_MR_WRPROOF | HSMCI_MR_BLKLEN_MASK);
@@ -1063,7 +1067,7 @@ static void sam3u_notransfer(struct sam3u_dev_s *priv)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_interrupt
+ * Name: sam_interrupt
  *
  * Description:
  *   HSMCI interrupt handler
@@ -1077,9 +1081,9 @@ static void sam3u_notransfer(struct sam3u_dev_s *priv)
  *
  ****************************************************************************/
 
-static int sam3u_interrupt(int irq, void *context)
+static int sam_interrupt(int irq, void *context)
 {
-  struct sam3u_dev_s *priv = &g_sdiodev;
+  struct sam_dev_s *priv = &g_sdiodev;
   uint32_t sr;
   uint32_t enabled;
   uint32_t pending;
@@ -1118,20 +1122,20 @@ static int sam3u_interrupt(int irq, void *context)
                 {
                   /* Yes.. Terminate with a timeout. */
 
-                  sam3u_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_TIMEOUT);
+                  sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_TIMEOUT);
                 }
               else
                 {
                   /* No..  Terminate with an I/O error. */
 
-                  sam3u_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR);
+                  sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR);
                 }
             }
           else
             {
               /* No.. Then the transfer must have completed successfully */
 
-              sam3u_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
+              sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
             }
         }
 
@@ -1147,7 +1151,7 @@ static int sam3u_interrupt(int irq, void *context)
 
           if ((pending & priv->cmdrmask) != 0)
             {
-              sam3u_cmdsample2(SAMPLENDX_AT_WAKEUP, sr);
+              sam_cmdsample2(SAMPLENDX_AT_WAKEUP, sr);
 
               /* Yes.. Did the Command-Response sequence end with an error? */
 
@@ -1185,7 +1189,7 @@ static int sam3u_interrupt(int irq, void *context)
                 {
                   /* Yes.. wake the thread up */
 
-                  sam3u_endwait(priv, wkupevent);
+                  sam_endwait(priv, wkupevent);
                 }
             }
         }
@@ -1198,7 +1202,7 @@ static int sam3u_interrupt(int irq, void *context)
  * SDIO Interface Methods
  ****************************************************************************/
 /****************************************************************************
- * Name: sam3u_reset
+ * Name: sam_reset
  *
  * Description:
  *   Reset the HSMCI controller.  Undo all setup and initialization.
@@ -1211,9 +1215,9 @@ static int sam3u_interrupt(int irq, void *context)
  *
  ****************************************************************************/
 
-static void sam3u_reset(FAR struct sdio_dev_s *dev)
+static void sam_reset(FAR struct sdio_dev_s *dev)
 {
-  FAR struct sam3u_dev_s *priv = (FAR struct sam3u_dev_s *)dev;
+  FAR struct sam_dev_s *priv = (FAR struct sam_dev_s *)dev;
   irqstate_t flags;
 
   /* Enable the MCI clock */
@@ -1240,7 +1244,7 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
 
   /* Set the Mode Register for ID mode frequency (probably 400KHz) */
 
-  sam3u_clock(dev, CLOCK_IDMODE);
+  sam_clock(dev, CLOCK_IDMODE);
 
   /* Set the SDCard Register */
 
@@ -1260,7 +1264,7 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
 
   /* No data transfer */
 
-  sam3u_notransfer(priv);
+  sam_notransfer(priv);
 
   /* Reset data */
 
@@ -1280,7 +1284,7 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
 }
 
 /****************************************************************************
- * Name: sam3u_status
+ * Name: sam_status
  *
  * Description:
  *   Get SDIO status.
@@ -1289,18 +1293,18 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
  *   dev   - Device-specific state data
  *
  * Returned Value:
- *   Returns a bitset of status values (see sam3u_status_* defines)
+ *   Returns a bitset of status values (see sam_status_* defines)
  *
  ****************************************************************************/
 
-static uint8_t sam3u_status(FAR struct sdio_dev_s *dev)
+static uint8_t sam_status(FAR struct sdio_dev_s *dev)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s *)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s *)dev;
   return priv->cdstatus;
 }
 
 /****************************************************************************
- * Name: sam3u_widebus
+ * Name: sam_widebus
  *
  * Description:
  *   Called after change in Bus width has been selected (via ACMD6).  Most
@@ -1316,9 +1320,9 @@ static uint8_t sam3u_status(FAR struct sdio_dev_s *dev)
  *
  ****************************************************************************/
 
-static void sam3u_widebus(FAR struct sdio_dev_s *dev, bool wide)
+static void sam_widebus(FAR struct sdio_dev_s *dev, bool wide)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s *)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s *)dev;
   uint32_t regval;
 
   /* Set 1-bit or 4-bit bus by configuring the SDCBUS field of the SDCR register */
@@ -1334,7 +1338,7 @@ static void sam3u_widebus(FAR struct sdio_dev_s *dev, bool wide)
 }
 
 /****************************************************************************
- * Name: sam3u_clock
+ * Name: sam_clock
  *
  * Description:
  *   Enable/disable SDIO clocking
@@ -1348,7 +1352,7 @@ static void sam3u_widebus(FAR struct sdio_dev_s *dev, bool wide)
  *
  ****************************************************************************/
 
-static void sam3u_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
+static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
 {
   uint32_t regval;
   bool enable = true;
@@ -1395,16 +1399,16 @@ static void sam3u_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
   putreg32(regval, SAM_HSMCI_MR);
   if (enable)
     {
-      sam3u_enable();
+      sam_enable();
     }
   else
     {
-      sam3u_disable();
+      sam_disable();
     }
 }
 
 /****************************************************************************
- * Name: sam3u_attach
+ * Name: sam_attach
  *
  * Description:
  *   Attach and prepare interrupts
@@ -1417,13 +1421,13 @@ static void sam3u_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
  *
  ****************************************************************************/
 
-static int sam3u_attach(FAR struct sdio_dev_s *dev)
+static int sam_attach(FAR struct sdio_dev_s *dev)
 {
   int ret;
 
   /* Attach the HSMCI interrupt handler */
 
-  ret = irq_attach(SAM_IRQ_HSMCI, sam3u_interrupt);
+  ret = irq_attach(SAM_IRQ_HSMCI, sam_interrupt);
   if (ret == OK)
     {
 
@@ -1449,7 +1453,7 @@ static int sam3u_attach(FAR struct sdio_dev_s *dev)
 }
 
 /****************************************************************************
- * Name: sam3u_sendcmd
+ * Name: sam_sendcmd
  *
  * Description:
  *   Send the SDIO command
@@ -1464,13 +1468,14 @@ static int sam3u_attach(FAR struct sdio_dev_s *dev)
  *
  ****************************************************************************/
 
-static int sam3u_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
+static int sam_sendcmd(FAR struct sdio_dev_s *dev,
+                       uint32_t cmd, uint32_t arg)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
   uint32_t regval;
   uint32_t cmdidx;
 
-  sam3u_cmdsampleinit();
+  sam_cmdsampleinit();
 
     /* Set the HSMCI Argument value */
 
@@ -1570,12 +1575,12 @@ static int sam3u_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
 
   fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
   putreg32(regval, SAM_HSMCI_CMDR);
-  sam3u_cmdsample1(SAMPLENDX_AFTER_CMDR);
+  sam_cmdsample1(SAMPLENDX_AFTER_CMDR);
   return OK;
 }
 
 /****************************************************************************
- * Name: sam3u_blocksetup
+ * Name: sam_blocksetup
  *
  * Description:
  *   Some hardward needs to be informed of the selected blocksize.
@@ -1589,8 +1594,8 @@ static int sam3u_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
  *
  ****************************************************************************/
 
-static void sam3u_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
-                             unsigned int nblocks)
+static void sam_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
+                           unsigned int nblocks)
 {
   uint32_t regval;
 
@@ -1613,7 +1618,7 @@ static void sam3u_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
 }
 
 /****************************************************************************
- * Name: sam3u_cancel
+ * Name: sam_cancel
  *
  * Description:
  *   Cancel the data transfer setup of HSMCI_RECVSETUP, HSMCI_SENDSETUP,
@@ -1629,18 +1634,18 @@ static void sam3u_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
  *
  ****************************************************************************/
 
-static int sam3u_cancel(FAR struct sdio_dev_s *dev)
+static int sam_cancel(FAR struct sdio_dev_s *dev)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
 
   /* Disable all transfer- and event- related interrupts */
 
-  sam3u_disablexfrints(priv);
-  sam3u_disablewaitints(priv, 0);
+  sam_disablexfrints(priv);
+  sam_disablewaitints(priv, 0);
 
   /* No data transfer */
 
-  sam3u_notransfer(priv);
+  sam_notransfer(priv);
 
   /* Clearing (most) pending interrupt status by reading the status register */
 
@@ -1655,7 +1660,7 @@ static int sam3u_cancel(FAR struct sdio_dev_s *dev)
    * on an error condition.
    */
 
-  sam3u_dmastop(priv->dma);
+  sam_dmastop(priv->dma);
 
   /* Disable the DMA handshaking */
 
@@ -1665,7 +1670,7 @@ static int sam3u_cancel(FAR struct sdio_dev_s *dev)
 }
 
 /****************************************************************************
- * Name: sam3u_waitresponse
+ * Name: sam_waitresponse
  *
  * Description:
  *   Poll-wait for the response to the last command to be ready.
@@ -1679,9 +1684,9 @@ static int sam3u_cancel(FAR struct sdio_dev_s *dev)
  *
  ****************************************************************************/
 
-static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
+static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
   uint32_t sr;
   int32_t  timeout;
 
@@ -1717,8 +1722,8 @@ static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
       sr = getreg32(SAM_HSMCI_SR);
       if ((sr & priv->cmdrmask) != 0)
         {
-          sam3u_cmdsample2(SAMPLENDX_AT_WAKEUP, sr);
-          sam3u_cmddump();
+          sam_cmdsample2(SAMPLENDX_AT_WAKEUP, sr);
+          sam_cmddump();
 
           /* Yes.. Did the Command-Response sequence end with an error? */
 
@@ -1764,7 +1769,7 @@ static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
 }
 
 /****************************************************************************
- * Name: sam3u_recvRx
+ * Name: sam_recvRx
  *
  * Description:
  *   Receive response to SDIO command.  Only the critical payload is
@@ -1785,9 +1790,10 @@ static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
  *
  ****************************************************************************/
 
-static int sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
+static int sam_recvshort(FAR struct sdio_dev_s *dev,
+                         uint32_t cmd, uint32_t *rshort)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
   int ret = OK;
 
   /* These responses could have CRC errors:
@@ -1871,9 +1877,9 @@ static int sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
   return ret;
 }
 
-static int sam3u_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4])
+static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4])
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
   int ret = OK;
 
  /* R2  CID, CSD register (136-bit)
@@ -1926,20 +1932,21 @@ static int sam3u_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
 
 /* MMC responses not supported */
 
-static int sam3u_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl)
+static int sam_recvnotimpl(FAR struct sdio_dev_s *dev,
+                           uint32_t cmd, uint32_t *rnotimpl)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
   priv->wkupevent = 0;
   return -ENOSYS;
 }
 
 /****************************************************************************
- * Name: sam3u_waitenable
+ * Name: sam_waitenable
  *
  * Description:
  *   Enable/disable of a set of SDIO wait events.  This is part of the
  *   the HSMCI_WAITEVENT sequence.  The set of to-be-waited-for events is
- *   configured before calling sam3u_eventwait.  This is done in this way
+ *   configured before calling sam_eventwait.  This is done in this way
  *   to help the driver to eliminate race conditions between the command
  *   setup and the subsequent events.
  *
@@ -1957,17 +1964,17 @@ static int sam3u_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
  *
  ****************************************************************************/
 
-static void sam3u_waitenable(FAR struct sdio_dev_s *dev,
-                             sdio_eventset_t eventset)
+static void sam_waitenable(FAR struct sdio_dev_s *dev,
+                           sdio_eventset_t eventset)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
   uint32_t waitmask;
 
   DEBUGASSERT(priv != NULL);
 
   /* Disable event-related interrupts */
 
-  sam3u_disablewaitints(priv, 0);
+  sam_disablewaitints(priv, 0);
 
   /* Select the interrupt mask that will give us the appropriate wakeup
    * interrupts.
@@ -1982,16 +1989,16 @@ static void sam3u_waitenable(FAR struct sdio_dev_s *dev,
   /* Enable event-related interrupts */
 
   (void)getreg32(SAM_HSMCI_SR);
-  sam3u_enablewaitints(priv, waitmask, eventset);
+  sam_enablewaitints(priv, waitmask, eventset);
 }
 
 /****************************************************************************
- * Name: sam3u_eventwait
+ * Name: sam_eventwait
  *
  * Description:
  *   Wait for one of the enabled events to occur (or a timeout).  Note that
- *   all events enabled by HSMCI_WAITEVENTS are disabled when sam3u_eventwait
- *   returns.  HSMCI_WAITEVENTS must be called again before sam3u_eventwait
+ *   all events enabled by HSMCI_WAITEVENTS are disabled when sam_eventwait
+ *   returns.  HSMCI_WAITEVENTS must be called again before sam_eventwait
  *   can be used again.
  *
  * Input Parameters:
@@ -2006,10 +2013,10 @@ static void sam3u_waitenable(FAR struct sdio_dev_s *dev,
  *
  ****************************************************************************/
 
-static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
-                                       uint32_t timeout)
+static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev,
+                                     uint32_t timeout)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
   sdio_eventset_t wkupevent = 0;
   int ret;
 
@@ -2037,7 +2044,7 @@ static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
       /* Start the watchdog timer */
 
       delay = (timeout + (MSEC_PER_TICK-1)) / MSEC_PER_TICK;
-      ret   = wd_start(priv->waitwdog, delay, (wdentry_t)sam3u_eventtimeout,
+      ret   = wd_start(priv->waitwdog, delay, (wdentry_t)sam_eventtimeout,
                        1, (uint32_t)priv);
       if (ret != OK)
         {
@@ -2046,7 +2053,7 @@ static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
     }
 
   /* Loop until the event (or the timeout occurs). Race conditions are avoided
-   * by calling sam3u_waitenable prior to triggering the logic that will cause
+   * by calling sam_waitenable prior to triggering the logic that will cause
    * the wait to terminate.  Under certain race conditions, the waited-for
    * may have already occurred before this function was called!
    */
@@ -2058,7 +2065,7 @@ static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
        * there will be no wait.
        */
 
-      sam3u_takesem(priv);
+      sam_takesem(priv);
       wkupevent = priv->wkupevent;
 
       /* Check if the event has occurred.  When the event has occurred, then
@@ -2075,18 +2082,18 @@ static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
         }
     }
 
-  sam3u_cmddump();
-  sam3u_xfrdump(priv);
+  sam_cmddump();
+  sam_xfrdump(priv);
   return wkupevent;
 }
 
 /****************************************************************************
- * Name: sam3u_callbackenable
+ * Name: sam_callbackenable
  *
  * Description:
  *   Enable/disable of a set of SDIO callback events.  This is part of the
  *   the SDIO callback sequence.  The set of events is configured to enabled
- *   callbacks to the function provided in sam3u_registercallback.
+ *   callbacks to the function provided in sam_registercallback.
  *
  *   Events are automatically disabled once the callback is performed and no
  *   further callback events will occur until they are again enabled by
@@ -2102,20 +2109,20 @@ static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
  *
  ****************************************************************************/
 
-static void sam3u_callbackenable(FAR struct sdio_dev_s *dev,
-                                 sdio_eventset_t eventset)
+static void sam_callbackenable(FAR struct sdio_dev_s *dev,
+                               sdio_eventset_t eventset)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
 
   fvdbg("eventset: %02x\n", eventset);
   DEBUGASSERT(priv != NULL);
 
   priv->cbevents = eventset;
-  sam3u_callback(priv);
+  sam_callback(priv);
 }
 
 /****************************************************************************
- * Name: sam3u_registercallback
+ * Name: sam_registercallback
  *
  * Description:
  *   Register a callback that that will be invoked on any media status
@@ -2136,10 +2143,10 @@ static void sam3u_callbackenable(FAR struct sdio_dev_s *dev,
  *
  ****************************************************************************/
 
-static int sam3u_registercallback(FAR struct sdio_dev_s *dev,
-                                  worker_t callback, void *arg)
+static int sam_registercallback(FAR struct sdio_dev_s *dev,
+                                worker_t callback, void *arg)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s*)dev;
 
   /* Disable callbacks and register this callback and is argument */
 
@@ -2153,7 +2160,7 @@ static int sam3u_registercallback(FAR struct sdio_dev_s *dev,
 }
 
 /****************************************************************************
- * Name: sam3u_dmasupported
+ * Name: sam_dmasupported
  *
  * Description:
  *   Return true if the hardware can support DMA
@@ -2167,14 +2174,14 @@ static int sam3u_registercallback(FAR struct sdio_dev_s *dev,
  ****************************************************************************/
 
 #ifdef CONFIG_SDIO_DMA
-static bool sam3u_dmasupported(FAR struct sdio_dev_s *dev)
+static bool sam_dmasupported(FAR struct sdio_dev_s *dev)
 {
   return true;
 }
 #endif
 
 /****************************************************************************
- * Name: sam3u_dmarecvsetup
+ * Name: sam_dmarecvsetup
  *
  * Description:
  *   Setup to perform a read DMA.  If the processor supports a data cache,
@@ -2192,38 +2199,38 @@ static bool sam3u_dmasupported(FAR struct sdio_dev_s *dev)
  *
  ****************************************************************************/
 
-static int sam3u_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
-                              size_t buflen)
+static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
+                          size_t buflen)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s *)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s *)dev;
 
   DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
   DEBUGASSERT(((uint32_t)buffer & 3) == 0);
 
   /* Setup register sampling */
 
-  sam3u_xfrsampleinit();
-  sam3u_xfrsample(priv, SAMPLENDX_BEFORE_SETUP);
+  sam_xfrsampleinit();
+  sam_xfrsample(priv, SAMPLENDX_BEFORE_SETUP);
 
   /* Configure the RX DMA */
 
-  sam3u_enablexfrints(priv, HSMCI_DMARECV_INTS);
-  sam3u_dmarxsetup(priv->dma, SAM_HSMCI_FIFO, (uint32_t)buffer, buflen);
+  sam_enablexfrints(priv, HSMCI_DMARECV_INTS);
+  sam_dmarxsetup(priv->dma, SAM_HSMCI_FIFO, (uint32_t)buffer, buflen);
 
   /* Enable DMA handshaking */
 
   putreg32(HSMCI_DMA_DMAEN, SAM_HSMCI_DMA);
-  sam3u_xfrsample(priv, SAMPLENDX_BEFORE_ENABLE);
+  sam_xfrsample(priv, SAMPLENDX_BEFORE_ENABLE);
 
   /* Start the DMA */
 
-  sam3u_dmastart(priv->dma, sam3u_dmacallback, priv);
-  sam3u_xfrsample(priv, SAMPLENDX_AFTER_SETUP);
+  sam_dmastart(priv->dma, sam_dmacallback, priv);
+  sam_xfrsample(priv, SAMPLENDX_AFTER_SETUP);
   return OK;
 }
 
 /****************************************************************************
- * Name: sam3u_dmasendsetup
+ * Name: sam_dmasendsetup
  *
  * Description:
  *   Setup to perform a write DMA.  If the processor supports a data cache,
@@ -2241,36 +2248,36 @@ static int sam3u_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
  *
  ****************************************************************************/
 
-static int sam3u_dmasendsetup(FAR struct sdio_dev_s *dev,
-                              FAR const uint8_t *buffer, size_t buflen)
+static int sam_dmasendsetup(FAR struct sdio_dev_s *dev,
+                          FAR const uint8_t *buffer, size_t buflen)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s *)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s *)dev;
 
   DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
   DEBUGASSERT(((uint32_t)buffer & 3) == 0);
 
   /* Setup register sampling */
 
-  sam3u_xfrsampleinit();
-  sam3u_xfrsample(priv, SAMPLENDX_BEFORE_SETUP);
+  sam_xfrsampleinit();
+  sam_xfrsample(priv, SAMPLENDX_BEFORE_SETUP);
 
   /* Configure the TX DMA */
 
-  sam3u_dmatxsetup(priv->dma, SAM_HSMCI_FIFO, (uint32_t)buffer, buflen);
+  sam_dmatxsetup(priv->dma, SAM_HSMCI_FIFO, (uint32_t)buffer, buflen);
 
   /* Enable DMA handshaking */
 
   putreg32(HSMCI_DMA_DMAEN, SAM_HSMCI_DMA);
-  sam3u_xfrsample(priv, SAMPLENDX_BEFORE_ENABLE);
+  sam_xfrsample(priv, SAMPLENDX_BEFORE_ENABLE);
 
   /* Start the DMA */
 
-  sam3u_dmastart(priv->dma, sam3u_dmacallback, priv);
-  sam3u_xfrsample(priv, SAMPLENDX_AFTER_SETUP);
+  sam_dmastart(priv->dma, sam_dmacallback, priv);
+  sam_xfrsample(priv, SAMPLENDX_AFTER_SETUP);
 
   /* Enable TX interrrupts */
 
-  sam3u_enablexfrints(priv, HSMCI_DMASEND_INTS);
+  sam_enablexfrints(priv, HSMCI_DMASEND_INTS);
   return OK;
 }
 
@@ -2278,7 +2285,7 @@ static int sam3u_dmasendsetup(FAR struct sdio_dev_s *dev,
  * Initialization/uninitialization/reset
  ****************************************************************************/
 /****************************************************************************
- * Name: sam3u_callback
+ * Name: sam_callback
  *
  * Description:
  *   Perform callback.
@@ -2290,9 +2297,9 @@ static int sam3u_dmasendsetup(FAR struct sdio_dev_s *dev,
  *
  ****************************************************************************/
 
-static void sam3u_callback(void *arg)
+static void sam_callback(void *arg)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s*)arg;
+  struct sam_dev_s *priv = (struct sam_dev_s*)arg;
 
   /* Is a callback registered? */
 
@@ -2377,7 +2384,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
 {
   /* There is only one slot */
 
-  struct sam3u_dev_s *priv = &g_sdiodev;
+  struct sam_dev_s *priv = &g_sdiodev;
 
   fdbg("slotno: %d\n", slotno);
 
@@ -2389,7 +2396,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
 
   /* Allocate a DMA channel.  A FIFO size of 8 is sufficient. */
 
-  priv->dma = sam3u_dmachannel(DMA_FLAGS);
+  priv->dma = sam_dmachannel(DMA_FLAGS);
   DEBUGASSERT(priv->dma);
 
   /* Configure GPIOs for 4-bit, wide-bus operation.  NOTE: (1) the chip is capable of
@@ -2397,23 +2404,23 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
    * GPIOs must be set up in board-specific logic.
    */
 
-  sam3u_configgpio(GPIO_MCI_DAT0);   /* Data 0 of Slot A */
-  sam3u_configgpio(GPIO_MCI_DAT1);   /* Data 1 of Slot A */
-  sam3u_configgpio(GPIO_MCI_DAT2);   /* Data 2 of Slot A */
-  sam3u_configgpio(GPIO_MCI_DAT3);   /* Data 3 of Slot A */
-  sam3u_configgpio(GPIO_MCI_CK);     /* SD clock */
-  sam3u_configgpio(GPIO_MCI_DA);     /* Command/Response */
+  sam_configgpio(GPIO_MCI_DAT0);   /* Data 0 of Slot A */
+  sam_configgpio(GPIO_MCI_DAT1);   /* Data 1 of Slot A */
+  sam_configgpio(GPIO_MCI_DAT2);   /* Data 2 of Slot A */
+  sam_configgpio(GPIO_MCI_DAT3);   /* Data 3 of Slot A */
+  sam_configgpio(GPIO_MCI_CK);     /* SD clock */
+  sam_configgpio(GPIO_MCI_DA);     /* Command/Response */
 
 #ifdef CONFIG_DEBUG_FS
-  sam3u_dumpgpio(GPIO_PORT_PIOA, "Pins: 3-8");
-  sam3u_dumpgpio(GPIO_PORT_PIOB, "Pins: 28-31");
+  sam_dumpgpio(GPIO_PORT_PIOA, "Pins: 3-8");
+  sam_dumpgpio(GPIO_PORT_PIOB, "Pins: 28-31");
 #endif
 
   /* Reset the card and assure that it is in the initial, unconfigured
    * state.
    */
 
-  sam3u_reset(&priv->dev);
+  sam_reset(&priv->dev);
   return &g_sdiodev.dev;
 }
 
@@ -2438,7 +2445,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
 
 void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s *)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s *)dev;
   uint8_t cdstatus;
   irqstate_t flags;
 
@@ -2454,14 +2461,16 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
     {
       priv->cdstatus &= ~SDIO_STATUS_PRESENT;
     }
+
   fvdbg("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
 
   /* Perform any requested callback if the status has changed */
 
   if (cdstatus != priv->cdstatus)
     {
-      sam3u_callback(priv);
+      sam_callback(priv);
     }
+
   irqrestore(flags);
 }
 
@@ -2483,7 +2492,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
 
 void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
 {
-  struct sam3u_dev_s *priv = (struct sam3u_dev_s *)dev;
+  struct sam_dev_s *priv = (struct sam_dev_s *)dev;
   irqstate_t flags;
 
   /* Update card status */
@@ -2497,6 +2506,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
     {
       priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
     }
+
   fvdbg("cdstatus: %02x\n", priv->cdstatus);
   irqrestore(flags);
 }
diff --git a/nuttx/arch/arm/src/sam3u/sam_hsmci.h b/nuttx/arch/arm/src/sam3u/sam_hsmci.h
new file mode 100644
index 000000000..299f94c72
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_hsmci.h
@@ -0,0 +1,143 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_hsmci.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_HSMCI_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_HSMCI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO for operation.
+ *
+ * Input Parameters:
+ *   slotno - Not used.
+ *
+ * Returned Values:
+ *   A reference to an SDIO interface structure.  NULL is returned on failures.
+ *
+ ****************************************************************************/
+
+struct sdio_dev_s; /* See include/nuttx/sdio.h */
+FAR struct sdio_dev_s *sdio_initialize(int slotno);
+
+/****************************************************************************
+ * Name: sdio_mediachange
+ *
+ * Description:
+ *   Called by board-specific logic -- posssible from an interrupt handler --
+ *   in order to signal to the driver that a card has been inserted or
+ *   removed from the slot
+ *
+ * Input Parameters:
+ *   dev        - An instance of the SDIO driver device state structure.
+ *   cardinslot - true is a card has been detected in the slot; false if a
+ *                card has been removed from the slot.  Only transitions
+ *                (inserted->removed or removed->inserted should be reported)
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
+
+/****************************************************************************
+ * Name: sdio_wrprotect
+ *
+ * Description:
+ *   Called by board-specific logic to report if the card in the slot is
+ *   mechanically write protected.
+ *
+ * Input Parameters:
+ *   dev       - An instance of the SDIO driver device state structure.
+ *   wrprotect - true is a card is writeprotected.
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_HSMCI_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam_irq.c
index a80f4a30e..083ad5ae1 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c
+++ b/nuttx/arch/arm/src/sam3u/sam_irq.c
@@ -1,6 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_irq.c
- * arch/arm/src/chip/sam3u_irq.c
+ * arch/arm/src/sam3u/sam_irq.c
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -52,7 +51,10 @@
 #include "up_arch.h"
 #include "os_internal.h"
 #include "up_internal.h"
-#include "sam3u_internal.h"
+
+#ifdef CONFIG_GPIO_IRQ
+#  include "sam_gpio.h"
+#endif
 
 /****************************************************************************
  * Definitions
@@ -87,7 +89,7 @@ volatile uint32_t *current_regs;
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_dumpnvic
+ * Name: sam_dumpnvic
  *
  * Description:
  *   Dump some interesting NVIC registers
@@ -95,7 +97,7 @@ volatile uint32_t *current_regs;
  ****************************************************************************/
 
 #if defined(SAM_IRQ_DEBUG) && defined (CONFIG_DEBUG)
-static void sam3u_dumpnvic(const char *msg, int irq)
+static void sam_dumpnvic(const char *msg, int irq)
 {
   irqstate_t flags;
 
@@ -121,12 +123,12 @@ static void sam3u_dumpnvic(const char *msg, int irq)
   irqrestore(flags);
 }
 #else
-#  define sam3u_dumpnvic(msg, irq)
+#  define sam_dumpnvic(msg, irq)
 #endif
 
 /****************************************************************************
- * Name: sam3u_nmi, sam3u_busfault, sam3u_usagefault, sam3u_pendsv,
- *       sam3u_dbgmonitor, sam3u_pendsv, sam3u_reserved
+ * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_dbgmonitor,
+ *       sam_pendsv, sam_reserved
  *
  * Description:
  *   Handlers for various execptions.  None are handled and all are fatal
@@ -136,7 +138,7 @@ static void sam3u_dumpnvic(const char *msg, int irq)
  ****************************************************************************/
 
 #ifdef CONFIG_DEBUG
-static int sam3u_nmi(int irq, FAR void *context)
+static int sam_nmi(int irq, FAR void *context)
 {
   (void)irqsave();
   dbg("PANIC!!! NMI received\n");
@@ -144,7 +146,7 @@ static int sam3u_nmi(int irq, FAR void *context)
   return 0;
 }
 
-static int sam3u_busfault(int irq, FAR void *context)
+static int sam_busfault(int irq, FAR void *context)
 {
   (void)irqsave();
   dbg("PANIC!!! Bus fault recived\n");
@@ -152,7 +154,7 @@ static int sam3u_busfault(int irq, FAR void *context)
   return 0;
 }
 
-static int sam3u_usagefault(int irq, FAR void *context)
+static int sam_usagefault(int irq, FAR void *context)
 {
   (void)irqsave();
   dbg("PANIC!!! Usage fault received\n");
@@ -160,7 +162,7 @@ static int sam3u_usagefault(int irq, FAR void *context)
   return 0;
 }
 
-static int sam3u_pendsv(int irq, FAR void *context)
+static int sam_pendsv(int irq, FAR void *context)
 {
   (void)irqsave();
   dbg("PANIC!!! PendSV received\n");
@@ -168,7 +170,7 @@ static int sam3u_pendsv(int irq, FAR void *context)
   return 0;
 }
 
-static int sam3u_dbgmonitor(int irq, FAR void *context)
+static int sam_dbgmonitor(int irq, FAR void *context)
 {
   (void)irqsave();
   dbg("PANIC!!! Debug Monitor receieved\n");
@@ -176,7 +178,7 @@ static int sam3u_dbgmonitor(int irq, FAR void *context)
   return 0;
 }
 
-static int sam3u_reserved(int irq, FAR void *context)
+static int sam_reserved(int irq, FAR void *context)
 {
   (void)irqsave();
   dbg("PANIC!!! Reserved interrupt\n");
@@ -186,7 +188,7 @@ static int sam3u_reserved(int irq, FAR void *context)
 #endif
 
 /****************************************************************************
- * Name: sam3u_prioritize_syscall
+ * Name: sam_prioritize_syscall
  *
  * Description:
  *   Set the priority of an exception.  This function may be needed
@@ -195,7 +197,7 @@ static int sam3u_reserved(int irq, FAR void *context)
  ****************************************************************************/
 
 #ifdef CONFIG_ARMV7M_USEBASEPRI
-static inline void sam3u_prioritize_syscall(int priority)
+static inline void sam_prioritize_syscall(int priority)
 {
   uint32_t regval;
 
@@ -209,7 +211,7 @@ static inline void sam3u_prioritize_syscall(int priority)
 #endif
 
 /****************************************************************************
- * Name: sam3u_irqinfo
+ * Name: sam_irqinfo
  *
  * Description:
  *   Given an IRQ number, provide the register and bit setting to enable or
@@ -217,7 +219,7 @@ static inline void sam3u_prioritize_syscall(int priority)
  *
  ****************************************************************************/
 
-static int sam3u_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
+static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
 {
   DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS);
 
@@ -290,7 +292,7 @@ void up_irqinitialize(void)
 #if defined(CONFIG_ARCH_RAMVECTORS)
   up_ramvec_initialize();
 #elif defined(CONFIG_STM32_DFU)
-  putreg32((uint32_t)sam3u_vectors, NVIC_VECTAB);
+  putreg32((uint32_t)sam_vectors, NVIC_VECTAB);
 #endif
 
   /* Set all interrrupts (and exceptions) to the default priority */
@@ -327,7 +329,7 @@ void up_irqinitialize(void)
 /* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
 #endif
 #ifdef CONFIG_ARMV7M_USEBASEPRI
-   sam3u_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
+   sam_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
 #endif
 
   /* If the MPU is enabled, then attach and enable the Memory Management
@@ -342,18 +344,18 @@ void up_irqinitialize(void)
   /* Attach all other processor exceptions (except reset and sys tick) */
 
 #ifdef CONFIG_DEBUG
-  irq_attach(SAM_IRQ_NMI, sam3u_nmi);
+  irq_attach(SAM_IRQ_NMI, sam_nmi);
 #ifndef CONFIG_ARMV7M_MPU
   irq_attach(SAM_IRQ_MEMFAULT, up_memfault);
 #endif
-  irq_attach(SAM_IRQ_BUSFAULT, sam3u_busfault);
-  irq_attach(SAM_IRQ_USAGEFAULT, sam3u_usagefault);
-  irq_attach(SAM_IRQ_PENDSV, sam3u_pendsv);
-  irq_attach(SAM_IRQ_DBGMONITOR, sam3u_dbgmonitor);
-  irq_attach(SAM_IRQ_RESERVED, sam3u_reserved);
+  irq_attach(SAM_IRQ_BUSFAULT, sam_busfault);
+  irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault);
+  irq_attach(SAM_IRQ_PENDSV, sam_pendsv);
+  irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor);
+  irq_attach(SAM_IRQ_RESERVED, sam_reserved);
 #endif
 
-  sam3u_dumpnvic("initial", SAM_IRQ_NIRQS);
+  sam_dumpnvic("initial", SAM_IRQ_NIRQS);
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
 
@@ -362,7 +364,7 @@ void up_irqinitialize(void)
    */
 
 #ifdef CONFIG_GPIO_IRQ
-  sam3u_gpioirqinitialize();
+  sam_gpioirqinitialize();
 #endif
 
   /* And finally, enable interrupts */
@@ -385,7 +387,7 @@ void up_disable_irq(int irq)
   uint32_t regval;
   uint32_t bit;
 
-  if (sam3u_irqinfo(irq, &regaddr, &bit) == 0)
+  if (sam_irqinfo(irq, &regaddr, &bit) == 0)
     {
       /* Clear the appropriate bit in the register to enable the interrupt */
 
@@ -398,10 +400,10 @@ void up_disable_irq(int irq)
     {
       /* Maybe it is a (derived) GPIO IRQ */
 
-      sam3u_gpioirqdisable(irq);
+      sam_gpioirqdisable(irq);
     }
 #endif
-  sam3u_dumpnvic("disable", irq);
+  sam_dumpnvic("disable", irq);
 }
 
 /****************************************************************************
@@ -418,7 +420,7 @@ void up_enable_irq(int irq)
   uint32_t regval;
   uint32_t bit;
 
-  if (sam3u_irqinfo(irq, &regaddr, &bit) == 0)
+  if (sam_irqinfo(irq, &regaddr, &bit) == 0)
     {
       /* Set the appropriate bit in the register to enable the interrupt */
 
@@ -431,10 +433,10 @@ void up_enable_irq(int irq)
     {
       /* Maybe it is a (derived) GPIO IRQ */
 
-      sam3u_gpioirqenable(irq);
+      sam_gpioirqenable(irq);
     }
 #endif
-  sam3u_dumpnvic("enable", irq);
+  sam_dumpnvic("enable", irq);
 }
 
 /****************************************************************************
@@ -500,7 +502,7 @@ int up_prioritize_irq(int irq, int priority)
   regval     |= (priority << shift);
   putreg32(regval, regaddr);
 
-  sam3u_dumpnvic("prioritize", irq);
+  sam_dumpnvic("prioritize", irq);
   return OK;
 }
 #endif
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_lowputc.c b/nuttx/arch/arm/src/sam3u/sam_lowputc.c
index 2f6747819..65e31fa47 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_lowputc.c
+++ b/nuttx/arch/arm/src/sam3u/sam_lowputc.c
@@ -1,5 +1,5 @@
 /**************************************************************************
- * arch/arm/src/sam3u/sam3u_lowputc.c
+ * arch/arm/src/sam3u/sam_lowputc.c
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -47,9 +47,11 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "sam3u_internal.h"
+#include "sam_gpio.h"
+#include "sam_lowputc.h"
 #include "chip/sam_pmc.h"
 #include "chip/sam_uart.h"
+#include "chip/sam_pinmap.h"
 
 /**************************************************************************
  * Private Definitions
@@ -228,7 +230,7 @@ void up_lowputc(char ch)
 }
 
 /**************************************************************************
- * Name: sam3u_lowsetup
+ * Name: sam_lowsetup
  *
  * Description:
  *   This performs basic initialization of the USART used for the serial
@@ -237,7 +239,7 @@ void up_lowputc(char ch)
  *
  **************************************************************************/
 
-void sam3u_lowsetup(void)
+void sam_lowsetup(void)
 {
   uint32_t regval;
 
@@ -264,44 +266,44 @@ void sam3u_lowsetup(void)
   /* Configure UART pins for all selected UART/USARTs */
 
 #ifdef CONFIG_SAM34_UART
-  (void)sam3u_configgpio(GPIO_UART_RXD);
-  (void)sam3u_configgpio(GPIO_UART_TXD);
+  (void)sam_configgpio(GPIO_UART_RXD);
+  (void)sam_configgpio(GPIO_UART_TXD);
 #endif
 #ifdef CONFIG_SAM34_USART0
-  (void)sam3u_configgpio(GPIO_USART0_RXD);
-  (void)sam3u_configgpio(GPIO_USART0_TXD);
-  (void)sam3u_configgpio(GPIO_USART0_CTS);
-  (void)sam3u_configgpio(GPIO_USART0_RTS);
+  (void)sam_configgpio(GPIO_USART0_RXD);
+  (void)sam_configgpio(GPIO_USART0_TXD);
+  (void)sam_configgpio(GPIO_USART0_CTS);
+  (void)sam_configgpio(GPIO_USART0_RTS);
 #endif
 #ifdef CONFIG_SAM34_USART1
-  (void)sam3u_configgpio(GPIO_USART1_RXD);
-  (void)sam3u_configgpio(GPIO_USART1_TXD);
-  (void)sam3u_configgpio(GPIO_USART1_CTS);
-  (void)sam3u_configgpio(GPIO_USART1_RTS);
+  (void)sam_configgpio(GPIO_USART1_RXD);
+  (void)sam_configgpio(GPIO_USART1_TXD);
+  (void)sam_configgpio(GPIO_USART1_CTS);
+  (void)sam_configgpio(GPIO_USART1_RTS);
 #endif
 #ifdef CONFIG_SAM34_USART2
-  (void)sam3u_configgpio(GPIO_USART2_RXD);
-  (void)sam3u_configgpio(GPIO_USART2_TXD);
-  (void)sam3u_configgpio(GPIO_USART2_CTS);
-  (void)sam3u_configgpio(GPIO_USART2_RTS);
+  (void)sam_configgpio(GPIO_USART2_RXD);
+  (void)sam_configgpio(GPIO_USART2_TXD);
+  (void)sam_configgpio(GPIO_USART2_CTS);
+  (void)sam_configgpio(GPIO_USART2_RTS);
 #endif
 #ifdef CONFIG_SAM34_USART3
-  (void)sam3u_configgpio(GPIO_USART3_RXD);
-  (void)sam3u_configgpio(GPIO_USART3_TXD);
-  (void)sam3u_configgpio(GPIO_USART3_CTS);
-  (void)sam3u_configgpio(GPIO_USART3_RTS);
+  (void)sam_configgpio(GPIO_USART3_RXD);
+  (void)sam_configgpio(GPIO_USART3_TXD);
+  (void)sam_configgpio(GPIO_USART3_CTS);
+  (void)sam_configgpio(GPIO_USART3_RTS);
 #endif
 
 #ifdef GPIO_CONSOLE_RXD
 #endif
 #ifdef GPIO_CONSOLE_TXD
-  (void)sam3u_configgpio(GPIO_CONSOLE_TXD);
+  (void)sam_configgpio(GPIO_CONSOLE_TXD);
 #endif
 #ifdef GPIO_CONSOLE_CTS
-  (void)sam3u_configgpio(GPIO_CONSOLE_CTS);
+  (void)sam_configgpio(GPIO_CONSOLE_CTS);
 #endif
 #ifdef GPIO_CONSOLE_RTS
-  (void)sam3u_configgpio(GPIO_CONSOLE_RTS);
+  (void)sam_configgpio(GPIO_CONSOLE_RTS);
 #endif
 
   /* Configure the console (only) */
diff --git a/nuttx/arch/arm/src/sam3u/sam_lowputc.h b/nuttx/arch/arm/src/sam3u/sam_lowputc.h
new file mode 100644
index 000000000..ffb033862
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_lowputc.h
@@ -0,0 +1,102 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_lowputc.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_LOWPUTC_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_LOWPUTC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: sam_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level initialization
+ *   including setup of the console UART.  This UART done early so that the serial
+ *   console is available for debugging very early in the boot sequence.
+ *
+ ************************************************************************************/
+
+void sam_lowsetup(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_LOWPUTC_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c b/nuttx/arch/arm/src/sam3u/sam_mpuinit.c
index 799dd9fab..3b49f9d97 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c
+++ b/nuttx/arch/arm/src/sam3u/sam_mpuinit.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/common/sam3u_mpuinit.c
+ * arch/arm/src/common/sam_mpuinit.c
  *
  *   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -44,6 +44,7 @@
 #include <nuttx/userspace.h>
 
 #include "mpu.h"
+#include "sam_mpuinit.h"
 
 #if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_ARMV7M_MPU)
 
@@ -72,7 +73,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_mpuinitialize
+ * Name: sam_mpuinitialize
  *
  * Description:
  *   Configure the MPU to permit user-space access to only restricted SAM3/4
@@ -80,7 +81,7 @@
  *
  ****************************************************************************/
 
-void sam3u_mpuinitialize(void)
+void sam_mpuinitialize(void)
 {
   uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
   uintptr_t dataend   = MAX(USERSPACE->us_dataend,   USERSPACE->us_bssend);
@@ -105,7 +106,7 @@ void sam3u_mpuinitialize(void)
 }
 
 /****************************************************************************
- * Name: sam3u_mpu_uheap
+ * Name: sam_mpu_uheap
  *
  * Description:
  *  Map the user-heap region.
@@ -114,7 +115,7 @@ void sam3u_mpuinitialize(void)
  *
  ****************************************************************************/
 
-void sam3u_mpu_uheap(uintptr_t start, size_t size)
+void sam_mpu_uheap(uintptr_t start, size_t size)
 {
   mpu_userintsram(start, size);
 }
diff --git a/nuttx/arch/arm/src/sam3u/sam_mpuinit.h b/nuttx/arch/arm/src/sam3u/sam_mpuinit.h
new file mode 100644
index 000000000..f2111bd26
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_mpuinit.h
@@ -0,0 +1,114 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_mpuinit.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_MPUINIT_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_MPUINIT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: sam_mpuinitialize
+ *
+ * Description:
+ *   Configure the MPU to permit user-space access to only unrestricted SAM3/4
+ *   resources.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NUTTX_KERNEL
+void sam_mpuinitialize(void);
+#else
+#  define sam_mpuinitialize()
+#endif
+
+/****************************************************************************
+ * Name: sam_mpu_uheap
+ *
+ * Description:
+ *  Map the user heap region.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NUTTX_KERNEL
+void sam_mpu_uheap(uintptr_t start, size_t size);
+#else
+#  define sam_mpu_uheap(start,size)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_MPUINIT_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_serial.c b/nuttx/arch/arm/src/sam3u/sam_serial.c
index 496630f49..deef640ea 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_serial.c
+++ b/nuttx/arch/arm/src/sam3u/sam_serial.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_serial.c
+ * arch/arm/src/sam3u/sam_serial.c
  *
  *   Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -55,12 +55,13 @@
 #include <arch/serial.h>
 #include <arch/board/board.h>
 
-#include "chip.h"
-#include "chip/sam_uart.h"
 #include "up_arch.h"
 #include "up_internal.h"
 #include "os_internal.h"
 
+#include "chip.h"
+#include "chip/sam_uart.h"
+
 /****************************************************************************
  * Definitions
  ****************************************************************************/
@@ -861,7 +862,7 @@ static int up_setup(struct uart_dev_s *dev)
   uint32_t regval;
 
   /* Note: The logic here depends on the fact that that the USART module
-   * was enabled and the pins were configured in sam3u_lowsetup().
+   * was enabled and the pins were configured in sam_lowsetup().
    */
 
   /* The shutdown method will put the UART in a known, disabled state */
@@ -1132,8 +1133,10 @@ static int up_interrupt(int irq, void *context)
 
 static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
   struct inode      *inode = filep->f_inode;
   struct uart_dev_s *dev   = inode->i_private;
+#endif
   int                ret    = OK;
 
   switch (cmd)
@@ -1330,7 +1333,7 @@ static bool up_txempty(struct uart_dev_s *dev)
 void up_earlyserialinit(void)
 {
   /* NOTE:  All GPIO configuration for the USARTs was performed in
-   * sam3u_lowsetup
+   * sam_lowsetup
    */
 
   /* Disable all USARTS */
@@ -1403,7 +1406,7 @@ int up_putc(int ch)
 {
 #ifdef HAVE_CONSOLE
   struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
-  uint16_t imr;
+  uint32_t imr;
 
   up_disableallints(priv, &imr);
 
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_spi.c b/nuttx/arch/arm/src/sam3u/sam_spi.c
index a3b4f6af6..c8ca05721 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_spi.c
+++ b/nuttx/arch/arm/src/sam3u/sam_spi.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_spi.c
+ * arch/arm/src/sam3u/sam_spi.c
  *
  *   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -55,9 +55,11 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "sam3u_internal.h"
+#include "sam_gpio.h"
+#include "sam_spi.h"
 #include "chip/sam_pmc.h"
 #include "chip/sam_spi.h"
+#include "chip/sam_pinmap.h"
 
 #ifdef CONFIG_SAM34_SPI
 
@@ -93,7 +95,7 @@
 /* The state of one chip select */
 
 #ifndef CONFIG_SPI_OWNBUS
-struct sam3u_chipselect_s
+struct sam_chipselect_s
 {
   uint32_t         frequency;  /* Requested clock frequency */
   uint32_t         actual;     /* Actual clock frequency */
@@ -104,12 +106,12 @@ struct sam3u_chipselect_s
 
 /* The overall state of the SPI interface */
 
-struct sam3u_spidev_s
+struct sam_spidev_s
 {
   struct spi_dev_s spidev;     /* Externally visible part of the SPI interface */
 #ifndef CONFIG_SPI_OWNBUS
   sem_t            exclsem;    /* Held while chip is selected for mutual exclusion */
-  struct sam3u_chipselect_s csstate[4];
+  struct sam_chipselect_s csstate[4];
 #endif
   uint8_t          cs;         /* Chip select number */
 };
@@ -127,7 +129,7 @@ static void spi_dumpregs(FAR const char *msg);
 #endif
 
 static inline void spi_flush(void);
-static inline uint32_t spi_cs2pcs(FAR struct sam3u_spidev_s *priv);
+static inline uint32_t spi_cs2pcs(FAR struct sam_spidev_s *priv);
 
 /* SPI methods */
 
@@ -164,9 +166,9 @@ static const struct spi_ops_s g_spiops =
   .setfrequency      = spi_setfrequency,
   .setmode           = spi_setmode,
   .setbits           = spi_setbits,
-  .status            = sam3u_spistatus,
+  .status            = sam_spistatus,
 #ifdef CONFIG_SPI_CMDDATA
-  .cmddata           = sam3u_spicmddata,
+  .cmddata           = sam_spicmddata,
 #endif
   .send              = spi_send,
 #ifdef CONFIG_SPI_EXCHANGE
@@ -180,7 +182,7 @@ static const struct spi_ops_s g_spiops =
 
 /* SPI device structure */
 
-static struct sam3u_spidev_s g_spidev =
+static struct sam_spidev_s g_spidev =
 {
   .spidev            = { &g_spiops },
 };
@@ -285,7 +287,7 @@ static inline void spi_flush(void)
  *
  ****************************************************************************/
 
-static inline uint32_t spi_cs2pcs(FAR struct sam3u_spidev_s *priv)
+static inline uint32_t spi_cs2pcs(FAR struct sam_spidev_s *priv)
 {
   return ((uint32_t)1 << (priv->cs)) - 1;
 }
@@ -314,7 +316,7 @@ static inline uint32_t spi_cs2pcs(FAR struct sam3u_spidev_s *priv)
 #ifndef CONFIG_SPI_OWNBUS
 static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
 {
-  FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
+  FAR struct sam_spidev_s *priv = (FAR struct sam_spidev_s *)dev;
 
   spivdbg("lock=%d\n", lock);
   if (lock)
@@ -357,7 +359,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
 
  static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
  {
-  FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
+  FAR struct sam_spidev_s *priv = (FAR struct sam_spidev_s *)dev;
   uint32_t regval;
 
   /* Are we selecting or de-selecting the device? */
@@ -371,7 +373,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
 
       /* Get the chip select number used with this SPI device */
 
-      priv->cs = sam3u_spicsnumber(devid);
+      priv->cs = sam_spicsnumber(devid);
       spivdbg("cs=%d\n", priv->cs);
       DEBUGASSERT(priv->cs >= 0 && priv->cs <= 3);
 
@@ -389,7 +391,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
       /* At this point, we expect the chip to have already been selected */
 
 #ifdef CONFIG_DEBUG
-      int cs = sam3u_spicsnumber(devid);
+      int cs = sam_spicsnumber(devid);
       DEBUGASSERT(priv->cs == cs);
 #endif
 
@@ -402,7 +404,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
    * pins may be programmed by the board specific logic in one of two
    * different ways.  First, the pins may be programmed as SPI peripherals.
    * In that case, the pins are completely controlled by the SPI driver.
-   * This sam3u_spiselect method still needs to be provided, but it may
+   * This sam_spiselect method still needs to be provided, but it may
    * be only a stub.
    *
    * An alternative way to program the PIO chip select pins is as normal
@@ -412,7 +414,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
    * same as the NPCS pin normal associated with the chip select number.
    */
 
-  sam3u_spiselect(devid, selected);
+  sam_spiselect(devid, selected);
  }
 
 /****************************************************************************
@@ -432,7 +434,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
 
 static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
 {
-  FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
+  FAR struct sam_spidev_s *priv = (FAR struct sam_spidev_s *)dev;
   uint32_t actual;
   uint32_t scbr;
   uint32_t dlybs;
@@ -543,7 +545,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
 
 static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
 {
-  FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
+  FAR struct sam_spidev_s *priv = (FAR struct sam_spidev_s *)dev;
   uint32_t regval;
   uint32_t regaddr;
 
@@ -612,7 +614,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
 
 static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
 {
-  FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
+  FAR struct sam_spidev_s *priv = (FAR struct sam_spidev_s *)dev;
   uint32_t regaddr;
   uint32_t regval;
 
@@ -709,7 +711,7 @@ static void  spi_exchange(FAR struct spi_dev_s *dev,
                           FAR const void *txbuffer, FAR void *rxbuffer,
                           size_t nwords)
 {
-  FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)dev;
+  FAR struct sam_spidev_s *priv = (FAR struct sam_spidev_s *)dev;
   FAR uint8_t *rxptr = (FAR uint8_t*)rxbuffer;
   FAR uint8_t *txptr = (FAR uint8_t*)txbuffer;
   uint32_t pcs;
@@ -882,7 +884,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
 
 FAR struct spi_dev_s *up_spiinitialize(int port)
 {
-  FAR struct sam3u_spidev_s *priv = &g_spidev;
+  FAR struct sam_spidev_s *priv = &g_spidev;
   irqstate_t flags;
   uint32_t regval;
 
@@ -909,9 +911,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
    * must be configured by board-specific logic.
    */
 
-  sam3u_configgpio(GPIO_SPI0_MISO);
-  sam3u_configgpio(GPIO_SPI0_MOSI);
-  sam3u_configgpio(GPIO_SPI0_SPCK);
+  sam_configgpio(GPIO_SPI0_MISO);
+  sam_configgpio(GPIO_SPI0_MOSI);
+  sam_configgpio(GPIO_SPI0_SPCK);
 
   /* Disable SPI clocking */
 
diff --git a/nuttx/arch/arm/src/sam3u/sam_spi.h b/nuttx/arch/arm/src/sam3u/sam_spi.h
new file mode 100644
index 000000000..32fb39387
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_spi.h
@@ -0,0 +1,226 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_spi.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_SPI_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name:  sam_spicsnumber, sam_spiselect, sam_spistatus, and sam_spicmddata
+ *
+ * Description:
+ *   These external functions must be provided by board-specific logic.  They
+ *   include:
+ *
+ *   o sam_spicsnumber and sam_spiselect which are helper functions to
+ *     manage the board-specific aspects of the unique SAM3/4 chip select
+ *     architecture.
+ *   o sam_spistatus and sam_spicmddata:  Implementations of the status
+ *     and cmddata methods of the SPI interface defined by struct spi_ops_
+ *     (see include/nuttx/spi.h). All other methods including
+ *     up_spiinitialize()) are provided by common SAM3/4 logic.
+ *
+ *  To use this common SPI logic on your board:
+ *
+ *   1. Provide logic in sam_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide sam_spicsnumber(), sam_spiselect() and sam_spistatus()
+ *      functions in your board-specific logic.  These functions will perform
+ *      chip selection and status operations using GPIOs in the way your board
+ *      is configured.
+ *   2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
+ *      sam_spicmddata() functions in your board-specific logic.  This
+ *      function will perform cmd/data selection operations using GPIOs in
+ *      the way your board is configured.
+ *   3. Add a call to up_spiinitialize() in your low level application
+ *      initialization logic
+ *   4. The handle returned by up_spiinitialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAM34_SPI
+struct spi_dev_s;
+enum spi_dev_e;
+
+/****************************************************************************
+ * Name: sam_spicsnumber
+ *
+ * Description:
+ *   The SAM3/4 has 4 CS registers for controlling device features.  This
+ *   function must be provided by board-specific code.  Given a logical device
+ *   ID, this function returns a number from 0 to 3 that identifies one of
+ *   these SAM3/4 CS resources.
+ *
+ *   If CONFIG_SPI_OWNBUS is not defined and the GPIO is controlled by
+ *   sam_spiselect, then the same CS register may be used to control
+ *   multiple devices.
+ *
+ * Input Parameters:
+ *   dev - SPI device info
+ *   devid - Identifies the (logical) device
+ *
+ * Returned Values:
+ *   On success, a CS number from 0 to 3 is returned; A negated errno may
+ *   be returned on a failure.
+ *
+ ****************************************************************************/
+
+int sam_spicsnumber(enum spi_dev_e devid);
+
+/****************************************************************************
+ * Name: sam_spiselect
+ *
+ * Description:
+ *   PIO chip select pins may be programmed by the board specific logic in
+ *   one of two different ways.  First, the pins may be programmed as SPI
+ *   peripherals.  In that case, the pins are completely controlled by the
+ *   SPI driver.  This method still needs to be provided, but it may be only
+ *   a stub.
+ *
+ *   An alternative way to program the PIO chip select pins is as a normal
+ *   GPIO output.  In that case, the automatic control of the CS pins is
+ *   bypassed and this function must provide control of the chip select.
+ *   NOTE:  In this case, the GPIO output pin does *not* have to be the
+ *   same as the NPCS pin normal associated with the chip select number.
+ *
+ * Input Parameters:
+ *   dev - SPI device info
+ *   devid - Identifies the (logical) device
+ *   selected - TRUE:Select the device, FALSE:De-select the device
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void sam_spiselect(enum spi_dev_e devid, bool selected);
+
+/****************************************************************************
+ * Name: sam_spistatus
+ *
+ * Description:
+ *   Return status information associated with the SPI device.
+ *
+ * Input Parameters:
+ *   dev - SPI device info
+ *   devid - Identifies the (logical) device
+ *
+ * Returned Values:
+ *   Bit-encoded SPI status (see include/nuttx/spi.h.
+ *
+ ****************************************************************************/
+
+uint8_t sam_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+
+/****************************************************************************
+ * Name: sam_spicmddata
+ *
+ * Description:
+ *   Some SPI devices require an additional control to determine if the SPI
+ *   data being sent is a command or is data.  If CONFIG_SPI_CMDDATA then
+ *   this function will be called to different be command and data transfers.
+ *
+ *   This is often needed, for example, by LCD drivers.  Some LCD hardware
+ *   may be configured to use 9-bit data transfers with the 9th bit
+ *   indicating command or data.  That same hardware may be configurable,
+ *   instead, to use 8-bit data but to require an additional, board-
+ *   specific GPIO control to distinguish command and data.  This function
+ *   would be needed in that latter case.
+ *
+ * Input Parameters:
+ *   dev - SPI device info
+ *   devid - Identifies the (logical) device
+ *
+ * Returned Values:
+ *   Zero on success; a negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CMDDATA
+int sam_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#endif
+#endif /* CONFIG_SAM34_SPI */
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_SPI_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_start.c b/nuttx/arch/arm/src/sam3u/sam_start.c
index dceb65ab2..c5a7d1783 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_start.c
+++ b/nuttx/arch/arm/src/sam3u/sam_start.c
@@ -1,8 +1,7 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_start.c
- * arch/arm/src/chip/sam3u_start.c
+ * arch/arm/src/sam3u/sam_start.c
  *
- *   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -50,7 +49,9 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "sam3u_internal.h"
+#include "sam_clockconfig.h"
+#include "sam_lowputc.h"
+#include "sam_userspace.h"
 
 /****************************************************************************
  * Private Definitions
@@ -101,8 +102,8 @@ void __start(void)
 
   /* Configure the uart so that we can get debug output as soon as possible */
 
-  sam3u_clockconfig();
-  sam3u_lowsetup();
+  sam_clockconfig();
+  sam_lowsetup();
   showprogress('A');
 
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
@@ -141,13 +142,13 @@ void __start(void)
    */
 
 #ifdef CONFIG_NUTTX_KERNEL
-  sam3u_userspace();
+  sam_userspace();
   showprogress('E');
 #endif
 
   /* Initialize onboard resources */
 
-  sam3u_boardinitialize();
+  sam_boardinitialize();
   showprogress('F');
 
   /* Then start NuttX */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_timerisr.c b/nuttx/arch/arm/src/sam3u/sam_timerisr.c
index cddd1cd05..828ec1e73 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_timerisr.c
+++ b/nuttx/arch/arm/src/sam3u/sam_timerisr.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_timerisr.c
+ * arch/arm/src/sam3u/sam_timerisr.c
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -51,7 +51,6 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "sam3u_internal.h"
 
 /****************************************************************************
  * Definitions
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_userspace.c b/nuttx/arch/arm/src/sam3u/sam_userspace.c
index 1450e27a9..4e90435ae 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_userspace.c
+++ b/nuttx/arch/arm/src/sam3u/sam_userspace.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sam3u/sam3u_userspace.c
+ * arch/arm/src/sam3u/sam_userspace.c
  *
  *   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -44,7 +44,7 @@
 
 #include <nuttx/userspace.h>
 
-#include "sam3u_internal.h"
+#include "sam_userspace.h"
 
 #ifdef CONFIG_NUTTX_KERNEL
 
@@ -65,7 +65,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: sam3u_userspace
+ * Name: sam_userspace
  *
  * Description:
  *   For the case of the separate user-/kernel-space build, perform whatever
@@ -75,7 +75,7 @@
  *
  ****************************************************************************/
 
-void sam3u_userspace(void)
+void sam_userspace(void)
 {
   uint8_t *src;
   uint8_t *dest;
@@ -111,7 +111,7 @@ void sam3u_userspace(void)
 
   /* Configure the MPU to permit user-space access to its FLASH and RAM */
 
-  sam3u_mpuinitialize();
+  sam_mpuinitialize();
 }
 
 #endif /* CONFIG_NUTTX_KERNEL */
diff --git a/nuttx/arch/arm/src/sam3u/sam_userspace.h b/nuttx/arch/arm/src/sam3u/sam_userspace.h
new file mode 100644
index 000000000..93ca9d278
--- /dev/null
+++ b/nuttx/arch/arm/src/sam3u/sam_userspace.h
@@ -0,0 +1,105 @@
+/************************************************************************************
+ * arch/arm/src/sam3u/sam_userspace.h
+ *
+ *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM3U_SAM_USERSPACE_H
+#define __ARCH_ARM_SRC_SAM3U_SAM_USERSPACE_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "up_internal.h"
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: sam_userspace
+ *
+ * Description:
+ *   For the case of the separate user-/kernel-space build, perform whatever
+ *   platform specific initialization of the user memory is required.
+ *   Normally this just means initializing the user space .data and .bss
+ *   segments.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NUTTX_KERNEL
+void sam_userspace(void);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAM3U_SAM_USERSPACE_H */
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S b/nuttx/arch/arm/src/sam3u/sam_vectors.S
index c50637dca..7ff50553e 100644
--- a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S
+++ b/nuttx/arch/arm/src/sam3u/sam_vectors.S
@@ -1,6 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam3u/sam3u_vectors.S
- * arch/arm/src/chip/sam3u_vectors.S
+ * arch/arm/src/sam3u/sam_vectors.S
  *
  *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -73,7 +72,7 @@
 
 	.syntax		unified
 	.thumb
-	.file		"sam3u_vectors.S"
+	.file		"sam_vectors.S"
 
 /************************************************************************************************
  * Macros
@@ -89,7 +88,7 @@
 	.thumb_func
 \label:
 	mov		r0, #\irqno
-	b		sam3u_common
+	b		sam_common
 	.endm
 
 /************************************************************************************************
@@ -99,10 +98,10 @@
 	.section	.vectors, "ax"
 	.code		16
 	.align		2
-	.globl		sam3u_vectors
-	.type		sam3u_vectors, function
+	.globl		sam_vectors
+	.type		sam_vectors, function
 
-sam3u_vectors:
+sam_vectors:
 
 /* Processor Exceptions */
 
@@ -125,36 +124,18 @@ sam3u_vectors:
 
 /* External Interrupts */
 
-	.word	sam_supc		/* Vector 16+0:  Supply Controller */
-	.word	sam_rstc		/* Vector 16+1:  Reset Controller */
-	.word	sam_rtc			/* Vector 16+2:  Real Time Clock */
-	.word	sam_rtt			/* Vector 16+3:  Real Time Timer */
-	.word	sam_wdt			/* Vector 16+4:  Watchdog Timer */
-	.word	sam_pmc			/* Vector 16+5:  Power Management Controller */
-	.word	sam_eefc0		/* Vector 16+6:  Enhanced Embedded Flash Controller 0 */
-	.word	sam_eefc1		/* Vector 16+7:  Enhanced Embedded Flash Controller 1 */
-	.word	sam_uart		/* Vector 16+8:  Universal Asynchronous Receiver Transmitter */
-	.word	sam_smc			/* Vector 16+9:  Static Memory Controller */
-	.word	sam_pioa		/* Vector 16+10: Parallel I/O Controller A */
-	.word	sam_piob		/* Vector 16+11: Parallel I/O Controller B */
-	.word	sam_pioc		/* Vector 16+12: Parallel I/O Controller C */
-	.word	sam_usart0		/* Vector 16+13: USART 0 */
-	.word	sam_usart1		/* Vector 16+14: USART 1 */
-	.word	sam_usart2		/* Vector 16+15: USART 2 */
-	.word	sam_usart3		/* Vector 16+16: USART 3 */
-	.word	sam_hsmci		/* Vector 16+17: High Speed Multimedia Card Interface */
-	.word	sam_twi0		/* Vector 16+18: Two-Wire Interface 0 */
-	.word	sam_twi1		/* Vector 16+19: Two-Wire Interface 1 */
-	.word	sam_spi			/* Vector 16+20: Serial Peripheral Interface */
-	.word	sam_ssc			/* Vector 16+21: Synchronous Serial Controller */
-	.word	sam_tc0			/* Vector 16+22: Timer Counter 0 */
-	.word	sam_tc1			/* Vector 16+23: Timer Counter 1 */
-	.word	sam_tc2			/* Vector 16+24: Timer Counter 2 */
-	.word	sam_pwm			/* Vector 16+25: Pulse Width Modulation Controller */
-	.word	sam_adc12b		/* Vector 16+26: 12-bit ADC Controller */
-	.word	sam_adc			/* Vector 16+27: 10-bit ADC Controller */
-	.word	sam_dmac		/* Vector 16+28: DMA Controller */
-	.word	sam_udphs		/* Vector 16+29: USB Device High Speed */
+#undef VECTOR
+#define VECTOR(l,i) .word l
+
+#undef UNUSED
+#define UNUSED(i) .word stm32_reserved
+
+#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#  include "chip/sam3u_vectors.h"
+#else
+#  Unrecognized SAM architecture
+#endif
+
 	.size	sam_vectors, .-sam_vectors
 
 /************************************************************************************************
@@ -176,36 +157,17 @@ handlers:
 	HANDLER	sam_pendsv, SAM_IRQ_PENDSV			/* Vector 14: Penable system service request */
 	HANDLER	sam_systick, SAM_IRQ_SYSTICK		/* Vector 15: System tick */
 
-	HANDLER	sam_supc, SAM_IRQ_SUPC				/* Vector 16+0:  Supply Controller */
-	HANDLER	sam_rstc, SAM_IRQ_RSTC				/* Vector 16+1:  Reset Controller */
-	HANDLER	sam_rtc, SAM_IRQ_RTC				/* Vector 16+2:  Real Time Clock */
-	HANDLER	sam_rtt, SAM_IRQ_RTT				/* Vector 16+3:  Real Time Timer */
-	HANDLER	sam_wdt, SAM_IRQ_WDT				/* Vector 16+4:  Watchdog Timer */
-	HANDLER	sam_pmc, SAM_IRQ_PMC				/* Vector 16+5:  Power Management Controller */
-	HANDLER	sam_eefc0, SAM_IRQ_EEFC0			/* Vector 16+6:  Enhanced Embedded Flash Controller 0 */
-	HANDLER	sam_eefc1, SAM_IRQ_EEFC1			/* Vector 16+7:  Enhanced Embedded Flash Controller 1 */
-	HANDLER	sam_uart, SAM_IRQ_UART				/* Vector 16+8:  Universal Asynchronous Receiver Transmitter */
-	HANDLER	sam_smc, SAM_IRQ_SMC				/* Vector 16+9:  Static Memory Controller */
-	HANDLER	sam_pioa, SAM_IRQ_PIOA				/* Vector 16+10: Parallel I/O Controller A */
-	HANDLER	sam_piob, SAM_IRQ_PIOB				/* Vector 16+11: Parallel I/O Controller B */
-	HANDLER	sam_pioc, SAM_IRQ_PIOC				/* Vector 16+12: Parallel I/O Controller C */
-	HANDLER	sam_usart0, SAM_IRQ_USART0			/* Vector 16+13: USART 0 */
-	HANDLER	sam_usart1, SAM_IRQ_USART1			/* Vector 16+14: USART 1 */
-	HANDLER	sam_usart2, SAM_IRQ_USART2			/* Vector 16+15: USART 2 */
-	HANDLER	sam_usart3, SAM_IRQ_USART3			/* Vector 16+16: USART 3 */
-	HANDLER	sam_hsmci, SAM_IRQ_HSMCI			/* Vector 16+17: High Speed Multimedia Card Interface */
-	HANDLER	sam_twi0, SAM_IRQ_TWI0				/* Vector 16+18: Two-Wire Interface 0 */
-	HANDLER	sam_twi1, SAM_IRQ_TWI1				/* Vector 16+19: Two-Wire Interface 1 */
-	HANDLER	sam_spi, SAM_IRQ_SPI				/* Vector 16+20: Serial Peripheral Interface */
-	HANDLER	sam_ssc, SAM_IRQ_SSC				/* Vector 16+21: Synchronous Serial Controller */
-	HANDLER	sam_tc0, SAM_IRQ_TC0				/* Vector 16+22: Timer Counter 0 */
-	HANDLER	sam_tc1, SAM_IRQ_TC1				/* Vector 16+23: Timer Counter 1 */
-	HANDLER	sam_tc2, SAM_IRQ_TC2				/* Vector 16+24: Timer Counter 2 */
-	HANDLER	sam_pwm, SAM_IRQ_PWM				/* Vector 16+25: Pulse Width Modulation Controller */
-	HANDLER	sam_adc12b, SAM_IRQ_ADC12B			/* Vector 16+26: 12-bit ADC Controller */
-	HANDLER	sam_adc, SAM_IRQ_ADC				/* Vector 16+27: 10-bit ADC Controller */
-	HANDLER	sam_dmac, SAM_IRQ_DMAC				/* Vector 16+28: DMA Controller */
-	HANDLER	sam_udphs, SAM_IRQ_UDPHS			/* Vector 16+29: USB Device High Speed */
+#undef VECTOR
+#define VECTOR(l,i) HANDLER l, i
+
+#undef UNUSED
+#define UNUSED(i)
+
+#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#  include "chip/sam3u_vectors.h"
+#else
+#  Unrecognized SAM architecture
+#endif
 
 /* Common IRQ handling logic.  On entry here, the return stack is on either
  * the PSP or the MSP and looks like the following:
@@ -225,7 +187,7 @@ handlers:
  *      We are in handler mode and the current SP is the MSP
  */
 
-sam3u_common:
+sam_common:
 
 	/* Complete the context save */