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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-22 16:08:21 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-22 16:08:21 +0000 |
| commit | 84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a (patch) | |
| tree | fd3d96de23b5b5c7021565041f59e7d8c7b69b8b /nuttx/arch/arm/src/stm32/chip/stm32_adc.h | |
| parent | 1c87f4d5e59da4337f5372c191a860916f593794 (diff) | |
| download | px4-nuttx-84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a.tar.gz px4-nuttx-84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a.tar.bz2 px4-nuttx-84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a.zip | |
Working toward clean STM3240xx build
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4119 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/stm32/chip/stm32_adc.h')
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_adc.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_adc.h b/nuttx/arch/arm/src/stm32/chip/stm32_adc.h index c8e9f8163..5893ae625 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_adc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_adc.h @@ -503,21 +503,21 @@ #ifdef CONFIG_STM32_STM32F40XX # define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ # define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT) -# define ADC_CCR_MULTI_NON (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ +# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ -# define ADC_CCR_MULTI_ MASK (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_ MASK (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ MASK (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ -# define ADC_CCR_MULTI_ MASK (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ +# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ -# define ADC_CCR_MULTI_ MASK (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_ MASK (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ MASK (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ -# define ADC_CCR_MULTI_ MASK (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ +# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ /* Bits 5-7: Reserved, must be kept at reset value. */ # define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ # define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) |